WO2007011012A1

WO2007011012A1 - Power amplification device

Info

Publication number: WO2007011012A1
Application number: PCT/JP2006/314452
Authority: WO
Inventors: Minoru Yoshida; Hiroyuki Ishihara
Original assignee: Pioneer Corporation
Priority date: 2005-07-21
Filing date: 2006-07-21
Publication date: 2007-01-25
Also published as: JP4688225B2; JPWO2007011012A1

Abstract

There is provided a small-size D class power amplification device capable of preventing nonlinear distortion generated when a switching process is executed and being applied to high frequency. The D class power amplification device (100) calculates an error signal between a PWM signal before a switching process is executed and the PWM signal after the switching process is executed and generates a clock signal varying clock frequency according to the change of the calculated error signal. In accordance with the generated clock signal, a pulse width modulation is executed for the PCM signal.

Description

Power amplifier

Technical field

[0001] The present invention belongs to a technical field of a power amplifying apparatus that performs nonlinear distortion correction.

Background art

[0002] In recent years, there has been a demand for a specification that can reproduce 5.1 channels in a stereo system that integrates speakers, amplifiers, CD players, etc., called mini-components. On the other hand, mini-components are required to be miniaturized due to design problems, and miniaturization of each circuit is required. Especially, the amplifying device, especially the case is large and heavy. There is a demand for miniaturization of power amplification devices that tend to be.

Recently, due to the demand for downsizing of such a power amplifying device, for example, a signal input to a power amplifying device such as a PCM (Pulse Code Modulation) signal is applied to pulse width modulation (PWM). The signal is amplified after being converted to a digitally modulated signal by performing modulation processing such as pulse density modulation (PDM) and output to the analog signal via a low-pass filter. Power amplifiers using Class D power amplification are becoming popular.

[0004] A power amplifying apparatus using this class D power amplifying method (hereinafter referred to as "class D power amplifying apparatus").

) Theoretically because the signal is amplified by turning on and off the switching elements in the output stage of the amplifying part located in front of the low-pass filter based on the digital modulation signal generated based on the input signal. 100% power efficiency can be obtained, and this high efficiency can reduce the size of the power amplifier.

[0005] Conventionally, as a power amplifying apparatus using such a class D power amplifying method, an apparatus that adjusts the edge width of a pulse signal input based on a reference signal to correct nonlinear distortion is known. Are known.

[0006] Specifically, this power amplifying device corrects nonlinear distortion in the switching element. In order to achieve this, a predetermined trapezoidal wave signal is generated as a reference signal, the edge width of the input pulse signal is adjusted by changing the slice level, and negative feedback control is performed! /, (For example, Patent Document 1).

Patent Document 1: Special Table 2001—517393 (International Publication W098Z44626 Pamphlet)

Disclosure of the invention

Problems to be solved by the invention

[0007] However, in the conventional class D power amplifier, in order to accurately correct the edge width adjustment of the pulse signal, it is necessary to generate a highly accurate trapezoidal wave signal as a reference signal. In order to generate the high-accuracy trapezoidal wave signal, the scale of the generation circuit becomes large, which may affect the miniaturization of the power amplifying device.

[0008] Further, in this class D power amplifying device, the edge width is adjusted based on the slice level, and therefore depends on the slope of the edge in the generated trapezoidal wave. Therefore, this class D power amplifying device ensures a sufficient amount of correction for edge width correction because the slope of the edge becomes steep when the clock frequency becomes high, and the generated trapezoidal wave becomes close to a rectangular wave. I can't.

[0009] The present invention solves an example of the above-mentioned problem by accurately preventing nonlinear distortion that occurs when switching processing is performed, and is applicable to high frequencies and can be downsized. It is to provide a class D power amplifier.

Means for solving the problem

[0010] In order to solve the above-described problem, the invention according to claim 1 is a class D power amplifying device that performs pulse modulation on a sound signal, amplifies the pulse modulated sound signal, and outputs the amplified signal to a speaker A receiving means for receiving a sound signal that is a digital signal; a first generating means for pulse-modulating the received sound signal to generate a pulse width modulated signal; and a power supply voltage according to the generated pulse width modulated signal. A second generation means for amplifying the signal level of the pulse width modulation signal to generate a loud sound signal, a detection means for detecting an error between the generated pulse width modulation signal and the loud sound signal, Generating means for generating a clock signal formed at a clock frequency that varies in accordance with the detected error signal. The first generation means generates the received sound signal force and the pulse width modulation signal based on the clock signal generated by the generation means.

Brief Description of Drawings

FIG. 1 is a block diagram showing a configuration in a first embodiment of a class D power amplifier according to the present application.

FIG. 2 is a graph showing a clock frequency range of a clock signal generated by a second clock signal generation unit corresponding to a detected error signal voltage value in the first embodiment.

FIG. 3 is a diagram showing signal waveforms at various parts when an error signal is larger than “0” in the generation process of the second clock signal of the first embodiment.

FIG. 4 is a diagram showing signal waveforms at various parts when an error signal is smaller than “0” in the generation process of the second clock signal of the first embodiment.

FIG. 5 is a timing chart in each part when an error signal is larger than “0” in the pulse width modulation operation of the first exemplary embodiment.

FIG. 6 is a timing chart in each part when the error signal is smaller than “0” in the pulse width modulation operation of the first exemplary embodiment.

FIG. 7 is another example of the block diagram showing the configuration of the first embodiment of the class D power amplifier according to the present application.

FIG. 8 is another example of a graph showing the clock frequency range of the clock signal generated by the second clock signal generation unit corresponding to the voltage value of the detected error signal in the first embodiment.

FIG. 9 is a block diagram showing a configuration in a second embodiment of a class D power amplifier according to the present application.

FIG. 10 is a diagram showing signal waveforms at various parts when an error signal is larger than “0” in the generation process of the second clock signal of the second embodiment.

FIG. 11 is a diagram showing signal waveforms at various parts when an error signal is smaller than “0” in the generation process of the second clock signal of the second embodiment.

FIG. 12 is a timing chart in each part when an error signal is larger than “0” in the pulse width modulation operation of the second exemplary embodiment. 13] FIG. 13 is a timing chart in 1--each o section when the error signal is smaller than “0” in the pulse width modulation operation of the second embodiment.

Yes

14] Another example of the block diagram showing the configuration of the second embodiment of the class D power amplifier according to the present application.

[15] FIG. 15 is a block diagram showing a configuration in a third embodiment of a class D power amplifier according to the present application.

16] FIG. 16 is a diagram illustrating an example of signal waveforms in the asynchronous circuit according to the third embodiment. 17] Another example of a block diagram showing the configuration of the third embodiment of the class D power amplifier according to the present application.

Explanation of symbols

200, 300… Class D power amplifier

101… Oversampling processor

102… Noise shaving circuit

103… 1st clock signal generator

104, 211… Nota

105, 311, 312… Output controller

106, 210… PCM / PWM converter

107… Switching amplifier circuit

108… 1st LPF

109… Amplifier

110… 2nd LPF

111… Error signal calculator

112… integrator

113… Voltage detector

114… Limiter circuit

115… 2nd clock signal generator

116… Waveform shaping circuit

310… Asynchronous circuit SP… Speaker

BEST MODE FOR CARRYING OUT THE INVENTION

Next, embodiments suitable for the present application will be described with reference to the drawings.

In the embodiment described below, a PCM signal read from a recording medium recorded as a digital signal such as a CD (Compact Disc) is input, and the signal of the input PCM signal is input. This is an embodiment in which the class D power amplifying apparatus of the present application is applied to a class D amplifying apparatus that amplifies the level and outputs it to a speaker. The following description is also applicable to a class D power amplifying apparatus that uses a lch class D power amplifying apparatus, a stereo, a 5. lch or a 7. lch multi-channel speaker.

[First Embodiment]

First, a first embodiment of a class D power amplifying apparatus will be described with reference to FIGS.

First, the configuration of the class D power amplifying apparatus in the present embodiment will be described using FIG. 1 and FIG. FIG. 1 is a block diagram showing the configuration of the class D power amplifying apparatus of this embodiment, and FIG. 2 shows the second clock signal generator corresponding to the voltage value of the detected error signal in this embodiment. 5 is a graph showing a clock frequency range of a clock signal generated in response. Also, in the following explanation, an application example in the single sided PWM method is explained.

[0017] The class D power amplifying apparatus 100 of this embodiment performs pulse width modulation on a PCM signal input based on a predetermined clock signal, and generates a PWM signal. The power supply voltage is switched according to the PWM signal (hereinafter referred to as “switching process”), and the PWM signal with the amplified signal level is output to the speaker.

In particular, the class D power amplifying apparatus 100 of the present embodiment calculates an error signal between the PWM signal before the switching process and the PWM signal after the switching process are performed as described later. A clock signal whose clock frequency changes according to the change in the calculated error signal is generated. The class D power amplifying apparatus 100 generates the generated clock in order to correct the nonlinear distortion that occurs when the switching process is performed. Based on the signal, pulse width modulation is applied to the PCM signal.

This class D power amplifying apparatus 100 includes an oversampling processing unit 101 and a noise shaving circuit 102 for performing over-sampling processing and noise-shaping pink processing as preprocessing on an input PCM signal, A first clock signal generation unit 103 that generates a clock signal (hereinafter referred to as a “first clock signal”) for operating the processing unit 101 and the noise shaving circuit 102, and a preprocessed PCM signal are temporarily stored. , The output control unit 105 that controls the output of the PCM signal stored in the buffer 104, and the PCMZPWM conversion unit 106 that generates a PWM signal by performing pulse width modulation on the output-controlled PCM signal. And have.

[0020] In addition, the class D power amplifying apparatus 100 performs switching processing based on the generated PWM signal, and a switching amplification circuit 107 that amplifies the signal level of the PWM signal by k times, and a signal level The first low-pass filter (hereinafter referred to as “first LPF”) 108 that filters the amplified PWM signal to generate an amplified signal, and an amplifier 109 that multiplies the signal level of the expanded signal by lZk. , A second low-pass filter (hereinafter referred to as “second LPF”) 110 that performs the same filtering process as the first low-pass filter on the PWM signal output from the PCMZPWM converter 106, and a loudspeaker multiplied by lZk And an error signal calculation unit 111 for calculating an error signal between the signal and the PWM signal output from the second low-pass filter.

Furthermore, this class D power amplifying apparatus 100 converts the calculated error signal into a DC voltage (DC), that is, an integrator 112 that performs averaging, and a voltage value of the error signal converted into a DC voltage. A voltage detector 113 for detecting, a limiter circuit 114 for performing a limiter process on the detected voltage value, and a clock signal whose clock frequency changes in accordance with a change in the limiter-processed voltage value (hereinafter referred to as “second clock”). A second clock signal generation unit 115 that generates a signal “)” and a waveform shaping circuit 116 that shapes the waveform of the generated second clock signal.

[0022] Note that, for example, the buffer 104 of the present embodiment constitutes the reception means, the first generation means, and the storage means of the present invention, and the output control unit 105 includes the first generation means and the control means of the present invention. Constitute. Further, the PCMZPWM converter 106 of the present embodiment constitutes the first generation means and pulse width modulation signal generation means of the present invention, and the switching amplifier circuit 107 This constitutes a clear second generation means. Further, for example, the error signal calculation unit 111 of the present embodiment constitutes the detection means of the present invention, and the second clock signal generation unit 115 constitutes the generation means of the present invention.

[0023] The PCM signal is input to the oversampling processing unit 101 via the input terminal T. The oversampling processing unit 101 generates a first clock signal generated by the first clock signal generation unit 103. Based on one clock signal, an oversampling process is performed on the input PCM signal, and the PCM signal subjected to the oversampling process is output to the noise shaving circuit 102.

For example, the oversampling processing unit 101 of the present embodiment executes a process of sampling an input PCM signal, such as 4 times or 8 times, at a sampling frequency that is a predetermined multiple of the sampling frequency of the PCM signal. It is like that.

[0025] An oversampled PCM signal is input to the noise shaving circuit 102, and the noise shaving circuit 102 receives the first clock signal generated by the first clock signal generator 103. Based on this, the noise PC pink processing is performed to reduce the input PCM signal power quantization bit number to a predetermined bit number (N bits) and shift the quantization noise to a high frequency band. Also, the noise shaving circuit 102 writes the PCM signal that has been subjected to the noise shaving pink process into the buffer 104.

[0026] The first clock signal generation unit 103 generates a first clock signal based on a predetermined clock frequency, and the oversampling processing unit 101 and the noise shaving circuit 102 generate the generated first clock signal. And output to the buffer 104.

[0027] The noffer 104 has a predetermined storage capacity, and can temporarily store a PCM signal that has been subjected to oversampling processing and noise shear pink processing. Further, in this buffer 104, input / output timing control is performed independently, and PCM signal writing and reading are performed. The time difference due to the difference is absorbed. [0028] Specifically, the PCM signals output from the noise shaving circuit 102 are sequentially written in the buffer 104 based on the first clock signal. As described later, under the control of the control unit 105, the stored PCM signal is output to the PCMZPWM conversion unit 106 based on a predetermined timing, that is, a clock signal generated based on the second clock signal. It has become.

Note that the write rate in the buffer 104 is constant. In addition, the storage capacity of the nother 104 of this embodiment is preferably a capacity capable of absorbing a time length equal to or greater than the switching frequency fluctuation width in the switching amplifier circuit 107 described later.

[0030] The output control section 105 has a frequency divider for the second clock signal output from the waveform shaping circuit 116 (NZ2 ^N) times, the period of the second clock signal input (NZ2 ^N) The PCM signal stored in the PCMZPWM conversion unit 106 is output from the notch 104 based on the second clock signal multiplied by (NZ2 ^N ).

“N” indicates the number of bits of the PCM signal output from the noise shaving circuit 102. In this embodiment, since the time resolution of the PCMZPWM converter 106 is (2 ^N ) times that of the PCM signal, (N / 2 ^N) of the second clock signal used in the PCM / PWM converter 106 described later. ) Read out at double timing!

[0032] The PCMZPWM converter 106 is configured to receive a PCM signal read at a predetermined timing and subjected to a predetermined pre-processing. Based on the clock signal, the input PCM signal is subjected to pulse width modulation, and a PWM signal is generated and output to the switching amplifier circuit 107 and the second LPF 110.

Specifically, in the present embodiment, the second clock signal is changed based on the error signal, and the PCMZPWM converter 106 is input based on the changed second clock signal. In addition, the pulse width modulation is applied to PCM signals.

The switching amplifier circuit 107 is input with a pulse width modulated PWM signal. The switching amplifier circuit 107 is, for example, a MOS (Metal Oxide Semiconductor) transistor, which is a field effect transistor (hereinafter referred to as “FET: Field Effect”). TransistorJ is called. ) FET and DC power supply for applying drive voltage to drive the speaker, perform predetermined control such as switching control of the input PWM signal, and increase the signal level of the PWM signal k times In other words, the signal is amplified to a predetermined signal level. The switching amplifier circuit 107 outputs the amplified PWM signal to the first LPF 108.

In the present embodiment, the switching amplifier circuit 107 may use a bipolar transistor instead of the FET.

[0036] A PWM signal amplified to a predetermined level is input to the first LPF 108. The first LPF 108 is high in response to the PWM signal input to remove high-frequency noise. The loudspeaker signal is generated by performing the band cut-off process, and the generated loudspeaker signal is output to the speaker and the amplifier 109.

[0037] Amplified signal generated by the first LPF 108 is input to the amplifier 109, and this amplifier 109 calculates one signal when calculating an error signal, that is, a PCM / PWM converter. In order to achieve consistency with the PWM signal output from 106, the signal level of the input loudspeak signal is amplified (lZk) times, and the loudspeak signal whose signal level is amplified (lZk) times is an error signal. It will be output to the calculation unit 111!

[0038] The PWM signal output from the PCMZPWM converter 106 is input to the second LPF 110, and this second LPF 110 receives the other signal, that is, the loudspeaker signal when calculating the error signal. The high-frequency cutoff processing similar to that of the first LP F108 is performed on the input PWM signal for consistency, and the signal subjected to the high-frequency cutoff processing is output to the error signal calculation unit 111. Yes.

[0039] The error signal calculation unit 111 receives a loudspeaker signal whose signal level is multiplied by (lZk) and a signal from which the second LPF 110 force is also output. An error signal is calculated on the basis of each of the signals, and the calculated error signal is output to the integrator 112.

[0040] Specifically, the error signal calculation unit 111 of the present embodiment is composed of a subtracter, and the loudness signal power with the signal level multiplied by (lZk) is also subtracted from the signal output from the second LPF 110, resulting in an error. A difference signal is generated! / Speak. [0041] The error signal generated by the error signal generation unit is input to the integrator 112. The integrator 112 performs an integration operation on the input error signal to obtain a DC voltage. Digitization (DC digitization), that is, the inputted error signal is averaged and output to the voltage detection unit 113 and the limiter circuit 114.

[0042] For example, the integrator 112 has a low and low-pass time constant that is equal to or less than the sampling period (F) of the oversampled PCM signal shown in (Equation 1) and satisfies (Equation 2).

PWM

It consists of filters. In the following equation, Fs indicates the sampling frequency of the PCM signal.

[0043] (Equation 1)

F = Fs X Oversampling number (1)

PWM

[0044] (Number 2)

τ ≥ l / (Fs X oversampling number X (2 ^Ν —1)) ··· (Equation 2)

The voltage detection unit 113 is configured to receive an error signal whose DC value has been input by the integrator 112. The voltage detection unit 113 detects and detects the voltage value of the input error signal. The output of the limiter circuit 114 is controlled based on the voltage value!

The limiter circuit 114 is supplied with the averaged error signal output from the integrator 112 and the voltage value output from the voltage detection unit 113. Is an upper limit voltage value (hereinafter, referred to as “upper limit voltage value”) determined based on the voltage value detected by the voltage detection unit 113, and a predetermined lower limit voltage value (hereinafter, “ When the following voltage value is input from the integrator 112 as an error signal, the upper limit voltage value or the lower limit voltage value is output.

In this embodiment, as will be described later, the variation range of the clock frequency in the clock signal generated by the second clock signal generation unit 115 is determined in advance, and belongs to this variation range. Based on the voltage value detected by the voltage detector 113, the upper and lower thresholds in the limiter circuit 114 are appropriately determined so as to generate a clock signal formed at the clock frequency. .

[0047] The limiter circuit 114 may limit the input error signal based on a predetermined upper limit voltage value and lower limit voltage value and output a predetermined voltage value. Good. In this case, the voltage detection unit 113 described above is not necessary.

[0048] The voltage value output from the limiter circuit 114 is input to the second clock signal generation unit 115. The second clock signal generation unit 115 is generated by the PCMZPWM conversion unit 106. In order to expand and contract the pulse width of the PWM signal, a predetermined clock frequency is generated according to the input voltage value, and the second clock signal formed at the generated clock frequency is sent to the waveform shaping circuit 116. It is designed to output.

Specifically, the second clock signal generator 115 generates a clock signal formed at a clock frequency belonging to a predetermined frequency range in advance by the limiter circuit 114 at the upper limit voltage value and the lower limit voltage value. I'm going to let you go.

For example, as shown in FIG. 2, the second clock signal generator 115 generates a clock frequency within a frequency range from a lower limit frequency F11 to an upper limit frequency F12, When the voltage value is “0” or more, the generated clock frequency is increased. When the voltage value in the error signal is “0” or less, the generated clock frequency is decreased.

[0051] Further, for example, in the present embodiment, the second clock signal generation unit 115 generates the clock frequency within the fluctuation range having the center frequency Fc calculated as in (Expression 3) based on (Expression 1). Is starting to occur. However, N in (Equation 3) indicates the number of output bits in the noise shaving circuit 102.

[0052] (Equation 3)

Fc = FX (2 ^N )

PWM

The upper limit frequency F12 is a pulse width force of the PWM signal modulated based on the second clock signal formed at the clock frequency F12 in order to prevent malfunction in the switching amplifier circuit 107. The clock frequency F12 is set in advance so that it is larger than the minimum pulse width that can be used by the device! In addition, the lower limit frequency F11 is a frequency axis target for the center frequency fc so that the deviation between the center frequency fc, which is the center during operation, and the upper limit frequency fl2, ie, I fl2-fc I or more is satisfied. Come to predetermine like! By configuring the second clock signal in this way, a highly stable configuration is possible. [0053] The waveform shaping circuit 116 is supplied with the second clock signal generated by the second clock signal generator 115, and the waveform shaping circuit 116 receives the input second clock. The signal waveform is converted from a sine wave to a rectangular wave, and the second clock signal converted to the rectangular wave is output to the PCMZPWM converter 106 and the output controller 105.

Next, the generation process of the second clock signal and the operation of the pulse width modulation in this embodiment will be described with reference to FIGS.

FIG. 3 is a diagram showing signal waveforms at various portions when the error signal is larger than “0” in the generation process of the second clock signal of the present embodiment, and FIG. 4 is a diagram of the first embodiment of the present embodiment. FIG. 5 is a diagram showing signal waveforms in respective parts when an error signal is smaller than “0” during the generation process of the two clock signals.

FIG. 5 is a timing chart in each part when the error signal is larger than “0” in the pulse width modulation operation of the present embodiment. FIG. 6 shows the nors width modulation of the present embodiment. 6 is a timing chart in each part when the error signal is smaller than “0”.

[0057] In the following description, it is assumed that the reproduction signal amplified in the class D power amplifier 100 is input as a PCM signal having a 4-bit PCM value of "0101", and the error signal is larger than "0". If it is smaller than “0”, the case will be described separately.

[0058] Further, the number of output bits in the noise shaving circuit 102 is 4 bits, and the clock frequency of the first clock signal is 4 Hz. As described above, the number of PWM steps is “16” from each of the conditions, and the center frequency of the clock frequency of the second clock signal is 16 Hz.

In the present embodiment, when the reproduction signal shown in FIG. 3 (a) is loudened, if the amplification factor in the switching amplifier circuit 107 is “1”, a predetermined value in each part such as the switching amplifier is given. Based on the processing, the loudspeaker signal containing the noise component shown in Fig. 3 (b) is output to the speaker.

In this case, when the error signal calculation unit 111 detects the error signal (> “0”) shown in FIG. 3 (c), the integrator 112 detects the error signal shown in FIG. The limiter circuit 114 outputs the signal shown in (d), and the limiter circuit 114 is based on the upper limit voltage value and the lower limit voltage value determined as described above. Outputs the signal shown in Fig. 3 (e). Then, the second clock signal generation unit 115 generates a sine wave clock signal with a variable clock frequency as shown in FIG. 3 (f) based on the signal shown in FIG. Output to the shaping circuit 116. The waveform shaping circuit 116 shapes the sine wave clock signal into a rectangular wave as described above.

[0061] When error signal calculation section 111 detects the error signal ("0") shown in Fig. 4 (a), integrator 112 shows the error signal shown in Fig. 4 (b) based on the error signal. The limiter circuit 114 outputs a signal shown in FIG. 4 (c) based on the upper limit voltage value and the lower limit voltage value determined as described above. Then, the second clock signal generation unit 115 generates a sine wave clock signal with a variable clock frequency, as shown in FIG. 4 (d), based on the signal in FIG. Output to the shaping circuit 116. The waveform shaping circuit 116 shapes the sine wave clock signal into a rectangular wave as described above.

On the other hand, as described above, a 4-bit PCM signal having a PCM value of “0101” is input to the input terminal, and oversampling processing and noise are performed based on the first clock signal shown in FIG. When the shaving process is performed, the PCM signal shown in FIG.

[0063] Then, as described above, the PCM signal written to the notch 104 is generated based on the calculated error signal (> "O"), and the clock frequency shown in FIG. When the variable (NZ2 N) multiplied second clock signal is used to read out from PC 104 as the PCM signal shown in Fig. 5 (d), the read PCM signal is shown in Fig. 5 (e). Based on the second clock signal with variable clock frequency shown in Fig. 5, it is converted to the PWM signal shown in Fig. 5 (f).

[0064] Further, as described above, the PCM signal written to the nother 104 is generated based on the calculated error signal (<"0"), and the clock frequency shown in Fig. 6 (a) is variable. When the second clock signal multiplied by (NZ2 ^N ) is used to read out from PC 104 as the PCM signal shown in Fig. 6 (b), the read PCM signal is shown in Fig. 6 (c). Based on the second clock signal with variable clock frequency, it is converted to the PWM signal shown in Fig. 6 (d).

In this way, in this embodiment, the clock frequency of the second clock signal can be varied based on the error signal! Therefore, the second clock signal with the variable clock frequency can be changed. Output control from the buffer 104 and PCMZPWM conversion based on the The pulse width of the PWM signal amplified by the pushing amplifier circuit 107 can be varied. For this reason, in this embodiment, nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107, that is, nonlinear distortion that occurs due to switching of the DC power supply in the switching amplifier circuit 107. In addition to being able to prevent distortion accurately, it is also possible to reduce the circuit scale that requires a dedicated circuit with high accuracy to make the pulse width of the PWM signal variable. In the present embodiment, since the clock frequency of the second clock signal varies, the generation of high frequency noise based on the clock frequency can be reduced.

[0066] As described above, the class D power amplifying apparatus 100 of the present embodiment is a class D power amplifying apparatus 100 that performs pulse modulation on a PCM signal, amplifies the pulse modulated PWM signal, and outputs the amplified PWM signal to a speaker. A buffer 104 that receives a PCM signal, which is a digital signal, a PCMZPWM converter 106 that generates a PWM signal by pulse-modulating the received PCM signal, and a power supply voltage that is switched according to the generated PWM signal. A switching amplifier circuit 107 that amplifies the signal level of the signal to generate a loud sound signal, an error signal calculation unit 111 that detects an error between the generated PWM signal and the loud sound signal, and a detected error signal. A second clock signal generation unit 115 for generating a second clock signal formed at a clock frequency that varies with the second clock signal generation unit 1 15. Clock signal Ru has been, a configuration for generating a PCM signal power PWM signal received based on.

With this configuration, the class D power amplifying apparatus 100 according to the present embodiment generates the second clock signal formed at the clock frequency that changes according to the detected error signal, and the generated second clock signal is generated. Using the clock signal, the received PCM signal power also generates a PWM signal.

Therefore, the class D power amplifying apparatus 100 of the present embodiment can also generate a PWM signal from the received PCM signal power using the generated second clock signal, and is amplified by the switching amplifier circuit 107. Since the PWM signal pulse width can be varied, nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107, that is, switching the DC power supply on and off in the switching amplifier circuit 107. As a result, the nonlinear distortion generated by the It is possible to reduce the circuit scale and the dedicated circuit with high accuracy required to make the width of the circuit variable.

[0069] Since the clock frequency of the second clock signal fluctuates in the class D power amplifying device 100 of the present embodiment, generation of high frequency noise such as unnecessary radiation based on the clock frequency can be reduced. It becomes an EMI countermeasure (Electro Magnetic Interference) taka when receiving radio waves close to the high-frequency noise, for example, broadcast waves of 500 kHz to 1600 kHz.

[0070] Also, in the class D power amplifying apparatus 100 of the present embodiment, the error signal calculation unit 111 is generated when the amplified signal is generated by smoothing the PWM signal whose signal level is amplified. Since the error from the loudspeaker signal is detected while smoothing the PWM signal, the second clock signal can be generated accurately, so that the pulse width modulation must be accurately performed on the PCM signal. The switching amplifier circuit 107 can accurately prevent nonlinear distortion caused by switching the DC power supply on and off.

In addition, the class D power amplifying apparatus 100 of the present embodiment has an integrator 112 that calculates the average value of the detected error signal, and is formed at a different clock frequency according to the calculated average value. The second clock signal can be generated.

[0072] With this configuration, the class D power amplifying apparatus 100 of the present embodiment can accurately generate the second clock signal, the overshoot that the waveform temporarily exceeds the specified level, and the waveform that is the specified level. This can prevent tracking of waveform distortion components such as undershoot that temporarily falls below, so that pulse width modulation can be performed accurately on the PCM signal. Nonlinear distortion caused by switching off can be accurately prevented.

In addition, since the class D power amplifying apparatus 100 of the present embodiment generates the second clock signal belonging to the frequency range determined in advance by the limiter circuit 114, the second clock signal can be generated stably. It is possible to accurately perform pulse width modulation on PCM signals.

[0074] In this embodiment, the error signal calculation unit performs smoothing processing by the second LPF 110 on the (lZk) -multiplied sound signal and the PWM signal output from the PCMZ PWM conversion unit 106. As shown in Fig. 7, the error signal is calculated based on the signal that has been subjected to the processing. However, as shown in Fig. 7, the PWM signal amplified by the switching amplifier circuit 107 multiplied by (lZk) and the PCMZ PWM converter 106 The error signal may be calculated based on the PWM signal output from. In this case, similar to the above, each signal input to the error signal can be matched, so that the same effect as described above can be obtained.

Further, in this embodiment, the first clock signal having the same clock frequency is used for the oversampling processing unit 101 and the noise-shaping circuit. You can use different clock signals.

In the present embodiment, a limiter circuit 114 is provided, and the voltage value detected by the voltage detection unit 113 is input to the second clock signal generation unit 115 based on the upper limit voltage value and the lower limit voltage value. The power to control the voltage value is not provided, the limiter circuit 114 is not provided, and the detected voltage value is held and input to the second clock signal generator 115 as shown in FIG. You can do it!

[0077] In this embodiment, the single sided PWM method is described as an example of the PWM modulation method. However, N in (Expression 1) to (Expression 3) is replaced with (N + 1). It is also possible to apply to the double sided PWM method by setting the frequency division ratio in the output control unit 105 to NZ (2 ^{(N + 1)} ).

Further, in the present embodiment, the force applied to the single-ended configuration, that is, the binary PWM modulation may be applied to the ternary PWM modulation. In this case, if the configuration of the present embodiment is applied to each PWM signal.

[0079] Further, the oversampling processing unit 101 and the noise shaving circuit 102 of the present embodiment operate based on the first clock signal generated by the first clock signal generation unit 103. Each oversampling processing unit 101 and noise shaping circuit 102 should be provided with a frequency dividing circuit so that it operates based on the divided first clock signal.

[0080] [Second Embodiment]

Next, a second embodiment of the class D power amplifying device will be described with reference to FIGS.

In this embodiment, the PCM signal stored in the buffer in the first embodiment is clocked. Instead of generating a PWM signal based on a second clock signal whose clock frequency is multiplied by a predetermined frequency, a PWM signal is generated with a clock signal having a predetermined clock frequency, written to the buffer, and the second clock signal is generated. The feature is that the written PWM signal is read based on the signal. The other points are the same as in the first embodiment, and the same members are denoted by the same reference numerals and the description thereof is omitted. In the following description, an application example in the Single Sided P WM method will be described.

First, the configuration of the class D power amplifying device in the present embodiment will be described with reference to FIG.

Note that FIG. 9 is a block diagram showing a configuration of the class D power amplifying apparatus of the present embodiment.

As shown in FIG. 9, this class D power amplifying apparatus 200 performs pulse width modulation on the oversampling processing unit 101 and noise shaving circuit 102 and the noise-shaved PCM signal to generate a PWM signal. PCMZPWM conversion unit 210 that generates the first clock signal generation unit 103 that generates the first clock signal for operating the oversampling processing unit 101, the noise shaving circuit 102, and the PCMZPWM conversion unit 210. And a buffer 211 for temporarily storing the PWM signal.

In addition, as in the first embodiment, this class D power amplifying apparatus 200 includes a switching amplification circuit 107, a first LPF 108, an amplifier 109, a second LPF 110, an error signal calculation unit 111, an integrator 112, a voltage detection unit 113, a limiter circuit 114, a second clock signal generation unit 115, and a waveform shaping circuit 116.

[0086] For example, the buffer 211 of this embodiment constitutes a receiving means, a first generating means, a storage means, and a control means of the present invention. Further, the PCMZPWM converter 210 of the present embodiment constitutes the receiving means, the first generating means and the pulse width modulation signal generating means of the present invention, and the amplifier circuit constitutes the second generating means of the present invention. Further, for example, the error signal calculation unit 111 of the present embodiment constitutes the detection means of the present invention, and the second clock signal generation unit 115 constitutes the generation means of the present invention.

[0087] The PCMZPWM converter 210 is configured to receive the PCM signal that has been subjected to the predetermined preprocessing output from the noise shaving circuit 102, and the PCMZPWM converter 210 receives the first clock signal. Based on the pulse width for the input PCM signal Modulation is performed, and a PWM signal is generated and output to the buffer 211.

[0088] The nother 211 has a predetermined storage capacity, and can temporarily store a PCM signal that has been subjected to oversampling processing and noise shear pink processing.

Further, in this buffer 211, the input / output timing control is performed independently, and the PWM signal is written and read out. Due to the difference in timing and read timing, the pulse width of the PWM signal that is memorized is changed.

Specifically, the buffer 211 sequentially writes the PWM signals output from the PCMZPWM converter 210 based on the first clock signal. The buffer 211 has a predetermined value. Based on the timing, that is, based on the second clock signal output from the output control circuit 116, the stored PWM signal is output to the switching amplifier circuit 107 and the second LPF 110 based on the second clock signal. ing.

Note that the write rate in the buffer 211 is constant. The first clock signal generator 103 has the same configuration as that of the first embodiment except that the first clock signal is output to the PCMZPWM converter 210.

FIG. 10 is a diagram showing signal waveforms at various parts when the error signal is larger than “0” in the generation process of the second clock signal of the present embodiment, and FIG. FIG. 7 is a diagram showing signal waveforms in various parts when an error signal is smaller than “0” during the process of generating a two-clock signal.

FIG. 12 is a timing chart in each part when the error signal is larger than “0” in the pulse width modulation operation of the present embodiment. FIG. 13 shows the pulse width modulation of the present embodiment. In operation, this is a timing chart in each part when the error signal is smaller than “0”.

[0095] In the following description, as in the first embodiment, the reproduction signal power bit amplified by the class D power amplifier 109 is input as a PCM signal having a PCM value of "0101" with bit The case where the error signal is larger than “0” and smaller than “0” will be described separately.

[0096] Further, the number of output bits in the noise shaving circuit 102 is 4 bits, and the clock frequency of the first clock signal is 2.5 Hz. As described above, the number of PWM steps is “16” from each of the conditions, and the center frequency of the clock frequency of the second clock signal is 10 Hz.

In the present embodiment, when the reproduction signal similar to that in the first embodiment is amplified, if the amplification factor in the switching amplifier circuit 107 is “1”, predetermined processing in each unit such as the switching amplifier unit is performed. Based on the above, a loudspeaker signal including a noise component is output to the speaker as in the first embodiment.

In this case, when the error signal calculation unit 111 detects the error signal (> “0”) shown in FIG. 10 (&), the integrator 112 generates the error signal shown in FIG. 10 (b) based on the error signal. The limiter circuit 114 outputs the signal shown in FIG. 10 (c) based on the determined upper limit voltage value and lower limit voltage value, as in the first embodiment. Then, the second clock signal generation unit 115 generates a sine wave clock signal with a variable clock frequency based on the signal of FIG. 10 (c), and generates a waveform shaping circuit. Output to 116. Note that the waveform shaping circuit 116 shapes the sine wave clock signal into a rectangular wave as described above.

[0099] When error signal calculation section 111 detects the error signal ("0") shown in Fig. 11 (a), integrator 112 shows the error signal shown in Fig. 11 (b) based on the error signal. The limiter circuit 114 outputs a signal shown in FIG. 11 (c) based on the upper limit voltage value and the lower limit voltage value determined as described above. Then, the second clock signal generation unit 115 generates a sine wave clock signal whose clock frequency is variable based on the signal of FIG. 11 (c), and generates a waveform shaping circuit. Output to 116. The waveform shaping circuit 116 shapes the sine wave clock signal into a rectangular wave as described above.

On the other hand, as in the first embodiment, a 4-bit PCM signal having a PCM value of “0101” is input to the input terminal, and the PWM signal is based on the first clock signal shown in FIG. Is generated, the PWM signal shown in FIG.

[0101] The PWM signal written to the buffer 211 is generated based on the calculated error signal (>"0"), as in the first embodiment, and the clock frequency shown in Fig. 12 (c). Have When the second clock signal is read from the buffer 211, the PWM signal shown in FIG.

[0102] Further, the PWM signal written to the buffer 211 is generated based on the calculated error signal (<0>) as in the first embodiment, and the clock frequency shown in FIG. When the second clock signal is read from the buffer 211, the PWM signal shown in FIG. 12 (d) is output to the switching amplifier circuit 107.

As described above, according to the present embodiment, the clock frequency of the second clock signal can be varied based on the error signal! Therefore, the pulse width of the PWM signal output from the buffer 211 can be changed. It can be made variable. Therefore, in this embodiment, as in the first embodiment, nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107, that is, the DC power supply is turned on and off in the switching amplifier circuit 107. Non-linear distortion caused by switching can be accurately prevented, and the accuracy for making the pulse width of the PWM signal variable is high! No dedicated circuit is required, and the circuit scale can be reduced. . In the present embodiment, since the clock frequency of the second clock signal varies, generation of high frequency noise based on the clock frequency can also be reduced.

As described above, the class D power amplifying apparatus 200 of the present embodiment is a class D power amplifying apparatus 200 that performs pulse modulation on a PCM signal, amplifies the pulse modulated PWM signal, and outputs the amplified PWM signal to a speaker. which receives the PCM signal is a digital signal, the received PCM signal pulse-modulated, ¹ \ ^^ [signal to generate a 1 ^ 1 ^ 7? ¹ \ ^^ [converting unit 210 Oyobi buffer 211 Switching amplifier circuit 107 that switches the power supply voltage according to the generated PWM signal, amplifies the signal level of the PWM signal to generate a loud sound signal, and detects an error between the generated PWM signal and the loud sound signal. An error signal calculation unit 111, and a second clock signal generation unit 115 that generates a second clock signal formed at a clock frequency that changes according to the detected error signal, and a PCM / PWM conversion unit 210. And the buffer 211 generates a second clock signal. Based on the second clock signal generated by the section 115 Te, and has a configuration for generating a received PCM signal Kakara PWM signal.

[0105] With this configuration, the class D power amplifying device 200 of the present embodiment is similar to that of the first embodiment. A second clock signal is generated with a clock frequency that changes according to the detected error signal, and a PWM signal is generated from the PCM signal using the generated second clock signal.

Therefore, the class D power amplifying apparatus 200 of the present embodiment can generate a PWM signal using the generated second clock signal as well as the received PCM signal power, and is amplified by the switching amplifier circuit 107. Since the PWM signal pulse width can be varied, nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107, that is, switching the DC power supply on and off in the switching amplifier circuit 107. In addition to accurately preventing non-linear distortion caused by this, a dedicated circuit with high accuracy for making the pulse width of the PWM signal variable is also reduced, and the circuit scale required is also reduced.

[0107] Since the clock frequency of the second clock signal fluctuates in the class D power amplifying apparatus 200 of the present embodiment, generation of high-frequency noise such as unnecessary radiation based on the clock frequency can be reduced. EMI countermeasures are also effective when receiving radio broadcasts close to the high-frequency noise, for example, broadcast waves of 500 kHz to 1600 kHz.

In the present embodiment, the error signal calculation unit is based on the (lZk) -magnified loudspeaker signal and the signal that has been subjected to the smoothing process in the second LPF 110 in the PWM signal output from the buffer 211. As shown in FIG. 14, the error signal is calculated based on the PWM signal output from the PWM signal buffer 211 amplified by the switching amplifier circuit 107 multiplied by (lZk). An error signal may be calculated. In this case, similar to the above, each signal input to the error signal can be matched, so that the same effect as described above can be obtained.

Further, in this embodiment, the first sampling signal having the same clock frequency is used for the oversampling processing unit 101 and the noise-shaping circuit. However, as long as synchronization can be obtained in each unit. You can use different clock signals.

Further, in the present embodiment, a limiter circuit 114 is provided, and is input to the second clock signal generation unit 115 based on the upper limit voltage value and the lower limit voltage value with respect to the voltage value detected by the voltage detection unit 113. The force that controls the voltage value Instead of providing it, keep the detected voltage value and input it to the second clock signal generator 115.

[Oil 1] In this embodiment, the power applied to the single-ended configuration, that is, the binary PWM modulation may be applied to the ternary PWM modulation. In this case, if the configuration of the present embodiment is applied to each PWM signal.

In addition, the oversampling processing unit 101 and the noise shaving circuit 102 according to the present embodiment operate based on the first clock signal generated by the first clock signal generation unit 103. In each oversampling processing unit 101 and noise shaping circuit 102, a frequency dividing circuit may be provided to operate based on the frequency-divided first clock signal. In particular, in the present embodiment, the first clock signal is used when signal processing of the PCM signal and the PWM signal is performed, so that a frequency dividing circuit is required. However, in this case, when the single sided PWM method is used as the PWM modulation method, the division ratio in (Equation 1) to (Equation 3) of the first embodiment is used, and the Doubly Sided PWM method is used as the PWM modulation method. When N is used, the frequency division ratio obtained by replacing N in (Equation 1) to (Equation 3) with (N + 1), that is, N / (2 ^{(N + 1)} ) is used.

[Third Embodiment]

Next, a third embodiment of the class D power amplifying device will be described with reference to FIGS.

[0114] The present embodiment is characterized in that an asynchronous circuit is used instead of the buffer in the first embodiment, and the other points are the same as in the first embodiment, and the same reference numerals are used for the same members. The description is omitted.

[0115] First, the configuration of the class D power amplifying device in the present embodiment will be described with reference to FIGS. 15 and 16. FIG. FIG. 15 is a block diagram showing the configuration of the class D power amplifier of this embodiment, and FIG. 16 is a diagram showing an example of signal waveforms in the asynchronous circuit of this embodiment. In the following description, application examples in the single sided PWM method will be described.

As shown in FIG. 15, the class D power amplifying apparatus 300 is preprocessed with an oversampling processing unit 101, a noise shaving circuit 102, and a first clock signal generating unit 103. The PCM signal timing and pulse width, the asynchronous circuit 310, the output control unit 311 for controlling the asynchronous circuit 310 timing, and the same 1 ^ 7? ¹ \ ^^ [conversion unit 312 .

Also, this class D power amplifying apparatus 300 includes a switching amplification circuit 107, a first LPF 108, an amplifier 109, a second LPF 110, an error signal calculation unit 111, an integrator, as in the first embodiment. 112, a voltage detection unit 113, a limiter circuit 114, a second clock signal generation unit 115, and a waveform shaping circuit 116.

As in the first embodiment, the output control unit 311 has a frequency dividing circuit that multiplies the second clock signal output from the waveform shaping circuit 116 by (N / 2 ^N ), and the first clock signal If, multiplies the second clock signal input (NZ2 ^N), and the (NZ2 ^N) multiplied by a second clock signal, based on, and controls the asynchronous circuit 310.

Asynchronous circuit 310 is constituted by, for example, a D (Delay) flip-flop or a latch, and as shown in FIG. 16, the PCM output from noise shaving circuit 102 under the control of output control unit 311. The signal is synchronized again and output to the PCMZPWM converter 312.

Note that FIG. 16 shows that the width of the input PCM signal, the first clock signal, the output PCM signal, and the second clock signal multiplied by (NZ2 ^N ) are different in the switching cycle of the asynchronous circuit 310. Is shown. However, MSB (Most Significan Digit) indicates the most significant bit, and LSB (Least Significant Bit) indicates the least significant bit. Further, the write rate in the asynchronous circuit 310 is constant.

[0121] As described above, the class D power amplifying apparatus 300 of the present embodiment is a class D power amplifying apparatus 300 that performs pulse modulation on the PCM signal, amplifies the pulse modulated PWM signal, and outputs the amplified PWM signal to the speaker. Asynchronous circuit 310 that receives the PCM signal, which is a digital signal, and ¹ \ ^ [ ¹ ^^^ [conversion unit 312 that generates a 1 \ ^ [signal by pulse-modulating the received PCM signal The switching amplifier circuit 107 that switches the power supply voltage according to the generated PWM signal, amplifies the signal level of the PWM signal to generate a loud sound signal, and calculates an error signal that detects an error between the generated PWM signal and the loud sound signal 111 and a second clock for generating a second clock signal formed at a clock frequency that varies according to the detected error signal. Lock signal generator 115, and PCMZPWM converter 312 receives a PCM signal from the received PCM signal based on the second clock signal generated by second clock signal generator 115. It has a configuration to generate.

[0122] With this configuration, the class D power amplifying apparatus 300 according to the present embodiment, as in the first embodiment, generates the second clock signal formed at the clock frequency that changes according to the detected error signal. Generate a PWM signal from the received PCM signal using the generated second clock signal.

Therefore, the class D power amplifying apparatus 300 of the present embodiment can generate a PWM signal using the generated second clock signal, and the received PCM signal power can be amplified by the switching amplifier circuit 107. Since the PWM signal pulse width can be varied, nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107, that is, switching the DC power supply on and off in the switching amplifier circuit 107. In addition to accurately preventing non-linear distortion caused by this, a dedicated circuit with high accuracy for making the pulse width of the PWM signal variable is also reduced, and the circuit scale required is also reduced.

[0124] Since the class D power amplifying apparatus 300 of the present embodiment varies the clock frequency of the second clock signal, generation of high frequency noise such as unwanted radiation based on the clock frequency can be reduced. EMI countermeasures are also effective when receiving radio broadcasts close to the high-frequency noise, for example, broadcast waves of 500 kHz to 1600 kHz.

[0125] In this embodiment, the error signal calculation unit converts the sound signal multiplied by (lZk) and the signal smoothed by the second LPF 110 in the PWM signal output from the PCMZ PWM conversion unit 312. The error signal is calculated based on the PWM signal amplified by the switching amplifier circuit 107 multiplied by (lZk) and the PWM signal output from the PCMZ PWM converter 312 as shown in FIG. The error signal may be calculated based on the above. In this case, similar to the above, each signal input to the error signal can be matched, so that the same effect as described above can be obtained.

Further, in this embodiment, the first clock signal having the same clock frequency is used for the oversampling processing unit 101 and the noise shaping circuit. If it can be synchronized, use different clock signals.

In the present embodiment, a limiter circuit 114 is provided, and the voltage value detected by the voltage detection unit 113 is input to the second clock signal generation unit 115 based on the upper limit voltage value and the lower limit voltage value. The force to control the voltage value to be controlled is not provided, and the second clock signal generation unit 115 is made to hold the detected voltage value as in the first embodiment without providing the limiter circuit 114. You can enter it!

In this embodiment, the single sided PWM method is described as an example of the PWM modulation method. However, as in the first embodiment, N in (Expression 1) to (Expression 3) is set to (N + Instead of 1), it is also possible to apply the double sided PWM method by setting the frequency division ratio in the output control unit 311 of this embodiment to NZ (2 ^{(N + 1)} ).

Further, in the present embodiment, the power applied to the single-ended configuration, that is, the binary PWM modulation may be applied to the ternary PWM modulation. In this case, if the configuration of the present embodiment is applied to each PWM signal.

[0130] Further, the oversampling processing unit 101 and the noise shaving circuit 102 of the present embodiment operate based on the first clock signal generated by the first clock signal generation unit 103. Each oversampling processing unit 101 and noise shaping circuit 102 should be provided with a frequency dividing circuit so that it operates based on the divided first clock signal.

Claims

The scope of the claims

[1] A class D power amplifying apparatus that pulse-modulates a sound signal, amplifies the pulse-modulated sound signal, and outputs the amplified sound signal to a speaker.

Receiving means for receiving a sound signal which is a digital signal;

First generation means for pulse-modulating the received sound signal to generate a pulse width modulation signal, and switching the power supply voltage according to the generated pulse width modulation signal, and amplifying the signal level of the pulse width modulation signal A second generation means for generating a loud signal;

Detecting means for detecting an error between the generated pulse width modulation signal and the loud sound signal; and generating means for generating a clock signal formed at a clock frequency that changes in accordance with the detected error signal;

With

The class D power amplifying apparatus, wherein the first generation means generates the received sound signal force and the pulse width modulation signal based on the clock signal generated by the generation means.

[2] In the class D power amplifying device according to claim 1,

The first generation means performs pulse width modulation on the received sound signal based on the clock signal generated by the generation means, and generates the pulse width modulation signal. apparatus.

[3] In the class D power amplifying device according to claim 2,

The first generation means comprises:

Storage means for temporarily storing the received sound signal;

Control means for performing output control for outputting the stored sound signal based on the clock signal generated by the generating means;

A pulse width modulation signal generating means for performing pulse width modulation on the output-controlled sound signal and generating the pulse width modulation signal based on the clock signal generated by the generating means;

A class D power amplifying apparatus, further comprising:

[4] In the class D power amplifying device according to claim 1,

The first generation means comprises:

A pulse width modulation signal generating means for pulse-modulating the received sound signal based on a predetermined reference signal to generate a pulse width modulation signal;

Storage means for temporarily storing the generated pulse width modulation signal, and based on the clock signal generated by the generation means, output control of the stored pulse width modulation signal, Control means for outputting to the second generating means and the detecting means;

A class D power amplifying apparatus characterized by comprising:

[5] In the class D power amplifying device according to any one of claims 1 to 4,

When the second generating means generates the loudspeaker signal by smoothing the pulse width modulated signal with the signal level amplified,

The class D power amplifier, wherein the detection means detects an error from the loudspeaker signal while smoothing the generated pulse width modulation signal.

[6] In the class D power amplifying device according to any one of claims 1 to 5,

The class D power amplifier characterized in that the generating means calculates an average value of the detected error signal and generates a clock signal formed at a clock frequency that changes in accordance with the calculated average value.

[7] The class D power amplifying device according to any one of claims 1 to 6, wherein the generating means generates a clock signal belonging to a predetermined frequency range. Power amplifier.