WO2006102833A1 - Procede et appareil de partage et de synthese de signaux - Google Patents

Procede et appareil de partage et de synthese de signaux Download PDF

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Publication number
WO2006102833A1
WO2006102833A1 PCT/CN2006/000505 CN2006000505W WO2006102833A1 WO 2006102833 A1 WO2006102833 A1 WO 2006102833A1 CN 2006000505 W CN2006000505 W CN 2006000505W WO 2006102833 A1 WO2006102833 A1 WO 2006102833A1
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Prior art keywords
frame
signal
data
frames
signals
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PCT/CN2006/000505
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English (en)
French (fr)
Inventor
Xin Xiao
Shimin Zou
Zhiqing Yu
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Huawei Technologies Co., Ltd.
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Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to ES06722157.2T priority Critical patent/ES2491893T3/es
Priority to EP06722157.2A priority patent/EP1865632B1/en
Publication of WO2006102833A1 publication Critical patent/WO2006102833A1/zh
Priority to US11/863,683 priority patent/US8059684B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process

Definitions

  • the present invention relates to an asynchronous signal processing technique, and more particularly to a method and apparatus for implementing asynchronous signal splitting, and a method and apparatus for combining signals. Background of the invention
  • OTH Optical Transport System
  • SDH Synchronous Digital Hierarchy
  • Sonet Synchronous Optical Network
  • ITU-T International Telecommunication Union Standards Department
  • OPUk optical payload unit
  • OTTUGk tributary unit group
  • the first row (row) of columns 1 to 14 is the reserved area of frame delimitation (FA) and OTUk overhead (OH, Overhead), and the 2 ⁇ 4 behavior of ODUk of the 1st to 14th columns,
  • the remaining 15th to 3824th columns are OPUk areas occupying a total of 4 x 3810 bytes.
  • the 1 ⁇ 6 bytes of the ODUk frame are fixed frame bytes.
  • the ODUk can be converted to OTUk by mapping, and the mapping structure of ODUk to OTUk is shown in Figure 2.
  • the OTUk frame is obtained by padding the FA and OTUk overhead in the reserved area and adding the 3825 to 4080 columns (4 X 256 bytes), and filling the OTUk forward error correction (FEC) coding (RS), thereby obtaining an OTUk frame.
  • FEC forward error correction
  • RS forward error correction
  • X 4080 15296 bytes, where 1 to 6 bytes of the OTUk frame are fixed frame bytes.
  • OTUk (k 1, 2, 3), as three levels of transmission signals, the rates are: OTU1: 255/238 x 2.48832 Gbps - 2.66605714285714 Gbps;
  • existing signal transmission and crossover techniques often fail to support ODU2/OTU2, ODU3/OTU3 Serial transmission of contour rate signals, for example:
  • the current commercial high-capacity asynchronous electrical cross-network port speed is generally only 3.6 Gbps, and can only support the scheduling function of the ODU1 serial signal.
  • the rate is 10 Gbps. Generally, it needs to be split into 4 bit-bit wide parallel signals. For the OTU3/ODU3 signals, the rate is 40 Gbps. Generally, it needs to be split into 16-bit wide parallel signals.
  • the split parallel signal also needs to consider framing processing to ensure the normal framing alignment of the sink, and merge and recover the source signal.
  • FIG. 3 is a schematic diagram of splitting the frame structure of the OTU2 in the optical transport network.
  • the slanted line filling part is a frame header area, and the OTU2 frame is generally split into four channels in the order of bytes. 1 channel is 1 ⁇ 4080 bytes, the second channel is 4081 ⁇ 8160 bytes, the third channel is 8161 ⁇ 12240 bytes, and the 4th channel is 12241 ⁇ 16320 bytes.
  • the entire frame header area will fall to the first channel, so that the framing alignment of the sink end cannot be achieved, and the source signal cannot be recovered.
  • each frame can be split into several channels (a number of blocks) in an integer.
  • the frame size is F bytes
  • the number of channels is C
  • the number of blocks per channel is B
  • the size of the block is S bytes (must be larger than the frame area size)
  • this method requires a frame size.
  • the header area is 6 bytes, so the block split size should be a minimum of 6 bytes.
  • the main object of the present invention is to provide a signal splitting in an optical transport network.
  • the method realizes splitting of high-speed signals of various levels of OTN to low-level rate signals.
  • the method for asynchronous signal splitting includes: the asynchronous signals to be split are respectively buffered in units of data frames in the order of frames, and each time n frames are filled, the n is The data frames are respectively sent in parallel through n channels, and at the same time, the n-frame data of the asynchronous signal to be split is buffered; wherein, n is a multiple of the difference between the rate levels before and after the splitting.
  • the buffering process of the data frame of the splitting method further includes: synchronizing the storage frequency of each data frame with the associated asynchronous signal clock of the to-be-split signal; and the sending process of the data frame further includes: The parallel transmission frequency of the n data frames is one-nth of the frequency of the data frame storage.
  • the method for buffering the data frame in the splitting method is: setting two sets of caches for each group, and storing one data frame for each cache; and respectively, the asynchronous signals to be split are in units of data frames, respectively, in the order of frames Write a set of caches, once a set of caches are stored, jump to another set of caches for storage, and at the same time, the data frames in a set of caches that are full are read out in parallel through n channels, and written Interleaving with the readout operation.
  • a second object of the present invention is to provide an asynchronous signal splitting apparatus that splits various levels of high speed signals within the OTN system into low level rate signals.
  • the apparatus for splitting an asynchronous signal provided by the present invention based on the second object includes:
  • a write address generation module for controlling a write operation of each of the first-in first-out memories
  • a read address generation module for controlling a read operation of each of the first-in first-out memories
  • a frequency dividing module configured to reduce the frequency of the input clock signal to 1/n of the original frequency and output the same; Where n is a multiple of the difference between the rate levels before and after the splitting; the write address generation module generates a write address and a write enable according to the frequency of the input clock signal, and inputs each of the first-in first-out memories separately, and controls the input data according to The order of the frames is sequentially serially written into a set of first-in first-out memories; at the same time, the clock signal is reduced to 1/n of the original frequency by the n-divide module, and then input to the read address generating module, and the read address and the read enable are respectively input to Each first-in first-out memory controls another set of first-in first-out memories to simultaneously output the stored data in parallel; two sets of first-in first-out memories are interleaved to perform the above operations.
  • the splitting device further includes: a search frame module for performing a frame search process on the input signal;
  • the input signal enters the search frame module, and after performing the frame search process, the output frame signal and the associated asynchronous signal clock are input to the write address generation module.
  • the associated clock signal is simultaneously input to the n-divide module, and after being output by the n-divide module, is input to the read address generating module together with the frame signal.
  • the three objects of the present invention provide a method of combining signals by combining multiple low speed signals into one high speed signal.
  • a method of merging signals based on three purposes including:
  • n parallel signals to be combined are respectively buffered in units of data frames in the order of frames, and after the n signals are filled one frame, the buffered n signal data frames are sequentially serially framed.
  • the buffering process of the data frame of the merging method further includes: controlling a frequency of storing the each data frame to be synchronized with a reference clock of the signal to be combined;
  • the issuing process of the data frame further includes: controlling the read frequency of each data frame stored to be n times the frequency of the data frame storage.
  • the method of caching the data frame of the merging method is: setting two sets of caches for each group of n, each The cache stores one data frame; the n parallel signals to be merged are written into a set of buffers in the order of frames in units of data frames, and each time a set of buffers is stored, the jump is performed to another set of buffers. At the same time, the data frames in a set of buffers that are full are sequentially read out in frames, and the write and read operations are interleaved.
  • a fourth object of the present invention is to provide a signal combining apparatus for combining multiple low speed signals into one high speed signal.
  • a signal merging apparatus includes: 2n first-in first-out memories, which are divided into two groups of n each, and each memory stores one frame of data at a time;
  • a write address generation module for controlling a write operation of each of the first-in first-out memories
  • a read address generation module for controlling a read operation of each of the first-in first-out memories
  • a frequency multiplication module configured to reduce the frequency of the input clock signal by n times the original frequency and output the same
  • n is a multiple of the difference between the rate levels before and after the splitting; the write address generation module generates a write address and write permission according to the frequency of the input clock signal, and inputs each of the first-in first-out memories, the control input
  • the n-channel data is simultaneously written in parallel to a set of first-in first-out memories in the order of frames; at the same time, the clock signal is reduced to n times of the original frequency by the n-multiplied module, and then input to the read address generating module to generate a read address and read permission.
  • Each input is input to each first-in first-out memory, and another set of first-in first-out memory is controlled to sequentially output the stored data in sequence; two sets of first-in first-out memories are interleaved to perform the above operations.
  • the merging device further comprises: a frame alignment unit, configured to perform frame search on each signal separately, find a frame start position of each of the n signals, and align the frame start positions of the n signals to the same frame phase. And outputting n-way aligned data to the 2n first-in first-out memories, and outputting reference frame signals to the write address generation module and the read address generation module.
  • the merging device further includes:
  • the interface unit is configured to perform clock data recovery on the input n asynchronous signals transmitted through the backplane or the cable, and the recovered n clocks select one of the clocks as the reference clock and the parallel data signals to be aligned are sent to the
  • the frame alignment unit is described; the reference clock is output to the write address generation module and the read address generation module after being output by the n-multiplication module.
  • the method and apparatus for signal splitting in the optical transport network splits the frame as a basic unit when performing signal splitting, and the frame header area of each frame is completely saved. Down, there is no need to make adjustments during the splitting process, which greatly simplifies the splitting operation. At the same time, there is no requirement for the number of bytes included in each frame, so that various signals in the optical transport network can be split.
  • the present invention also provides a method and a device for merging signals in an optical transport network. The low-speed signals are combined in a frame as a basic unit, and the frame header area of each frame is completely saved, which greatly complicates the operation of signal combining. And there is no need to limit the number of bytes per frame of the combined signal. BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram showing a frame structure of an ODUk signal in an optical transport network
  • FIG. 2 is a schematic diagram of a mapping structure of an ODUk to an OTUk in an optical transport network
  • FIG. 3 is a schematic diagram of splitting a frame structure of an OTU2 in an optical transport network
  • FIG. 4 is a schematic structural view of an ODU2 splitting device according to a preferred embodiment of the present invention
  • FIG. 5 is a schematic structural view of an ODU3 splitting device according to a preferred embodiment of the present invention
  • FIG. 8 is a block diagram showing the structure of an ODU3 merging apparatus according to a preferred embodiment of the present invention
  • FIG. 8 is a structural block diagram of a merging apparatus including an interface unit and a framing alignment unit according to a preferred embodiment of the present invention
  • 9 is a schematic structural diagram of an interface unit of an ODU2 merging apparatus according to the present invention
  • FIG. 10 is a schematic structural diagram of a framing alignment unit of an ODU2 merging apparatus according to the present invention
  • FIG. 11 is a timing chart of a frame alignment process of a framing alignment unit according to the present invention. Mode for carrying out the invention
  • splitting the signal in units of frames and buffering the high-speed signals in the order of frames.
  • n frames are full, the data of the n frames is sent in parallel, and the above-mentioned execution is repeated. The process continues until the high speed signal is completely split into the desired low speed signal.
  • n is a multiple of the difference in rate levels between the high speed signal and the low speed signal.
  • the ODU2 signal is serially buffered. After 4 frames are stored, the 4 frames of data are sent in parallel, and at the same time, the data frame behind the buffer is buffered. After the frame is sent in parallel, the above operation is repeated, so that one serial serial ODU2 is successfully split into four parallel signals, which can also be called four channel parallel signals. Since the four signals are combined to form a complete ODU2, the present invention uses ODU2[3:0] to represent the four ODU1 rate level parallel signals obtained after the ODU2 split for convenience of the following description. In this process, since the frame is used as the basic unit for splitting, the frame header area of each frame is completely saved, and no adjustment is needed during the splitting process, so that the splitting operation is greatly simplified, and each frame is simultaneously The number of bytes included is not required.
  • the present invention uses OTU2[3:0] to represent the parallel signals of the four OTU1 rate levels obtained after the OTU2 split.
  • the present invention uses ODU3[15:0]/OTU3[15:0] to represent the parallel signals of 16 ODU1/OTU1 rate levels obtained after the ODU3/OTU3 split; if splitting is required Signals of the ODU2/OTU2 rate level are sent in parallel after each 4 frames are filled; the rest of the process is completely similar to the processing of the ODU2/OTU2 signal.
  • the structure of the ODU2 splitting apparatus of the preferred embodiment of the present invention is as shown in FIG. 4, including: a frame search module, a write address generation module, a read address generation module, a 4-way frequency module, and eight first-in first-out modules.
  • the divide-by-4 module is used to reduce the frequency of the input clock signal to 1/4 of the original frequency;
  • the write address generation module is used to control the write frequency of each FIFO write pointer;
  • the read address generation module is used to control each FIFO read pointer read frequency;
  • 8 FIFOs are divided into two groups, each of which is a group, each FIFO can store one ODU2 frame data.
  • the device splitting the ODU2 signal specifically includes:
  • the input ODU2 asynchronous signal has an asynchronous signal clock CLK along with the path, and the frame signal FP is obtained after the frame search process is performed by the search frame module. This process is a mature existing technology and will not be described again.
  • the write address and write permission generation rules are as follows: The FIFO write address is cyclically changed, so that the ODU2 data is sequentially written into each FIFO according to the frame; the write enable signal is rotated in turn, so that the four FIFOs of the first group are written and then jumped to Another set of FIFOs.
  • the corresponding FIFOs in the two groups in FIG. 4 share a set of write address W_Addr lines to receive write address signals, that is, FIFO-1 and FIFO-5, FIFO-2 and FIFO-6, FIFO-3 and FIFO-7 FIFO-4 and FIFO-8 are shared by one group, which can be used for trunking, and of course for each FIFO. Both provide a set of write address W-Addr lines.
  • the clock Clk is also input to the divide-by-4 module, and the output signal divided by the divide-by-4 module and the frame signal FP are respectively input to the Clk and FP terminals of the read address generation module, where the asynchronous signal clock is used to control the FIFO.
  • the read frequency, the frame signal FP is used to control the read start address of the FIFO, the read address generation module generates the read address R_Addr according to the input Clk and FP, and the read enable RE1, RE2, and the read address R_Addr respectively enter each FIFO.
  • R-Addr Read allows RE1 to input the first group of first-in first-out memory FIFO-1, FIFO-2, FIFO-3, FIFO-4, RE2 input second group first-in first-out memory FIFO-5, FIFO-6, FIFO — 7, FIFO—8, which controls the readout of each FIFO.
  • the read address and read enable generation rules are: The read address is cyclically changed, and the read enable signals RE1 and RE2 are alternately valid, so that the data in the two sets of FIFOs are alternately read out in parallel, wherein the corresponding FIFOs in the two groups share one in FIG.
  • the group read address R_Addr line that is, FIFO-1 and FIFO-5, FIFO-2 and FIFO-6, FIFO-3 and FIFO-7, FIFO-4 and FIF0-8 are shared by one group. Of course, it can also be set to Not shared.
  • the generated read address signal needs to ensure that a set of FIFOs currently performing the read operation is staggered from a set of FIFOs currently performing the write operation, and the ping-pong mode is read and written, that is, during the period of writing FIF0_1 to FIF0_4, the read FIFO-5 to FIFO — 8; Write FIFO — 5 to FIFO — 8 when reading FIFO — 1 to FIFO — 4.
  • the read frequency of the FIFO is 1/4 of the write frequency.
  • 0DU2 data is sequentially written to FIF0-1, FIFO-2, FIFO-3 and FIFO-4, each FIFO stores one frame of data; FIFO-1 to FIFO-4 are written to one frame and jump to FIFO-5. FIFO-6, FIF0-7 and FIFO-8 are written in the same order.
  • the read pointer starts to read data from FIF0-1, FIF0__2, FIFO-3 and FIF0-4 simultaneously, forming low-speed parallel data.
  • the read rate is 1/4 of the 0DU2 rate, so the read and write operations alternate, that is, the 0DU2 signal is completed to the parallel signal ODU2[3:0 ] (ODU1 rate level signal) conversion.
  • the ODU2[3:0] signal obtained after the split is still a framing signal, including the FA Area; data delay is 4 times ODU2 signal period.
  • the case of the OTU2 signal is basically the same as that of the ODU2, except that each FIFO of the OTU splitting unit needs to store one frame of data of the OTU2.
  • FIG. 5 shows the structure of the ODU3 splitting device according to the preferred embodiment of the present invention. Schematic, the difference is that 32 FIFOs need to be set in the splitting device, each 16 as a group, and a 16-divide module for reducing the frequency of the input signal to the original frequency 1/16, the write address generation module And the read address generation module controls the reading and writing of the 32 FIFOs, respectively.
  • the structure of the splitting device for other signal processing can also be deduced by those skilled in the art.
  • the present invention also provides a method for merging signals, comprising: buffering data of n-way aligned parallel low-speed signals by frame, sequentially reading in frame order at n times the rate of depositing The buffered data is taken, and the frame header area is determined according to the aligned frame phase, and is combined into a high-speed signal and serially issued.
  • the phase of the n low-speed signal frames before the combination is usually not the same, in this case, it is generally necessary to increase the alignment process of the signals before performing the above-mentioned combining process, including: clocking and data recovery for the n parallel signals.
  • the n-channel clock and data signal wherein a clock recovery in any way as a reference clock signal of these n-channel data frame search, find their way n frame start position data signal, a frame of data signals from n channels
  • the start position is aligned to the same frame phase according to the frame start position of a certain data signal, and a reference frame signal is generated.
  • the specific merge process includes: clock and data recovery for the n-channel parallel signal ODU2[3:0], and the recovered 4
  • the road clock and the data signal use one of the clocks as a reference clock to perform frame search on the four data signals, and find the starting position of each of the four data signals, and the four paths are
  • the frame start position of the data signal is aligned to the same frame phase, and a reference frame signal is generated, and the output 4-way aligned data and the reference frame signal are written into the memory buffer in parallel with the frame, and then 4 times of the write operation.
  • the rate is read sequentially in frame order, and the ODU2 data is recovered.
  • the above operation is repeatedly performed by the ping-pong read/write method, thereby restoring the parallel low-speed signal ODU2[3:0] to the ODU2 signal.
  • FIG. 6 is a schematic structural diagram of an ODU2 merging device in which ODU2[3:0] is merged into an ODU2 signal, and includes: a write address generation module, a read address generation module, a 4 ⁇ frequency module, and 8 first-in first-out memories FIFO_l, FIFO. — 2, FIFO — 3, FIFO — 4, FIFO — 5, FIFO — 6, FIFO — 7 and FIFO — 8. Eight of the FIFOs are divided into two groups, and each FIFO stores one frame of data.
  • the write address generation module generates a write address W_Addr and a write enable signal WE1, WE2 of each FIFO according to the received reference clock and the reference frame signal, where the role of the reference clock is to control the write frequency of the FIFO, and the role of the reference frame signal is to control
  • the write start address of the FIFO the generation rule is: FIFO write address W_Addr cyclic change, WE1 and WE2 alternately valid; in the first reference clock cycle, WE1 is valid, write address W_Addr points to the first group of FIFOs, so that the aligned ODU2 [ 3:0] Parallel data ODU2[0] to ODU2[3] are written in parallel to the first group of FIFOs; WE2 is valid at the next reference clock cycle, write address W_Addr points to the second group of FIFOs, aligned parallel data ODU2 [0] to ODU2[3] begins writing to the second set of FIFOs.
  • the corresponding FIFOs in the two groups can share a set of write address lines, that is, FIFO-1 and FIFO-5, FIFO-2 and FIF0_6, FIFO-3 and FIF0-7, FIFO-4 and FIFO-8 are shared by one.
  • write rate is the reference clock rate.
  • the 4th frequency clock signal outputted by the reference clock signal after the 4th frequency multiplication module enters the read address generation module together with the reference frame signal, and generates the read address R_Addr and the read enable signals RE1, RE2, RE3, RE4, RE5 of each FIFO, RE6, RE7, RE8, where the reference clock is used to control the read frequency of the FIFO, and the role of the reference frame signal is to control the read start of the FIFO.
  • the generation rule is: FIFO read address cyclic change, read enable signal is valid, for example: In the first 1/4 reference clock cycle, RE5 is valid, the read address points to FIFO-5, and the data frame in FIFO_5 is read.
  • the data in FIFO-5 to FIF08 are serially read out; then the first 1/4 cycle of another reference clock cycle, the read address points to FIFO-1.
  • the data frame in FIFO-1 is read out; thus, after the end of the first reference clock cycle, the data in FIFO-1 to FIF04 are sequentially read out in series.
  • the data in FIFO-1 to FIF08 is continuously read out serially.
  • the corresponding FIFOs in the two groups can share a set of read address R-Addr lines, namely FIFO-1 and FIFO-5, FIFO-2 and FIFO-6, FIFO-3 and FIFO-7, FIFO-4 and FIFO- 8 pairs of two share a group.
  • the data in the FIFO is read out serially, and the set of FIFOs currently being read is staggered from the set of FIFOs currently being written.
  • the write pointer of the FIFO is written in parallel to the FIFO-1, FIFO-2, FIFO-3, and FIFO-4, and then written to the FIFO in parallel.
  • the write rate is Reference clock rate;
  • the read pointer begins to read data sequentially from FIFO-1, FIFO-2, FIFO-3, and FIFO-4 at a read rate four times the reference clock. This cycle continues, thus completing the conversion of the 4-channel 0DU2 parallel signal ODU2[ 3 :0] (2.5Gbps level signal) to one 0DU2 signal.
  • the structure of the 0DU3 merging device that combines ODU3[15:0] into the 0DU3 signal is shown in Figure ,.
  • the difference from the merging device for the 0DU2 signal is that 32 FIFOs are set in the 0DU3 merging device, and each 16 is a group.
  • the 4 multiplier module is replaced with a 16 ⁇ multiplier for increasing the frequency of the input signal to 16 times the original frequency, and the write address generation module and the read address generation module respectively control the reading and writing of the 32 FIFOs.
  • the ODU3 combining device works in a completely similar manner to the 0DU2 signal combining device. Used to combine OTU3[15:0] into a 0TU3 signal
  • the structure of the OTU3 merging device is also identical to the structure shown in FIG.
  • the structure of the merging device for other signal processing can also be deduced by those skilled in the art.
  • the merging device Since the frame phases of the normally input n low speed signals are not synchronized, the merging device is usually used in conjunction with the device for framing alignment.
  • FIG. 8 Taking the processing of the ODU2[3:0] signal as an example, as shown in FIG. 8, further setting is performed before the merging apparatus shown in FIG. 6 or FIG. 7: an interface unit and a fixed frame alignment unit.
  • the interface unit and the framing unit are used for clock recovery of asynchronous signals and clock selection and framing alignment processing, respectively.
  • the composition of the device for processing other signals is exactly the same as that shown in Figure 7, and the signal processing can be similar.
  • the 4-channel ODU2[3:0] to be merged enters the interface unit, and the interface unit performs clock data recovery on the input 4-way parallel signal, and inputs the restored 4-channel clock and data signals to the fixed frame alignment unit, and according to the clock.
  • Select ⁇ Air signal to select one of the clocks as the reference clock to send to the fixed frame alignment unit and the ODU2 merge device.
  • the frame alignment unit performs frame search for each signal separately, finds the frame start position of each of the four signals, and aligns the start positions of the four signals to the same frame phase, and outputs 4-way aligned data and reference.
  • the frame signal is combined with the ODU2 device.
  • the ODU2 merging device is internally provided with two sets of FIFOs, four in each group, and each FIFO stores one frame of data.
  • the ODU2[3:0] parallel data is sequentially written into the set of FIFOs in parallel with the reference frame using the low-speed clock, and the alignment process is performed; at the same time, the frame rate is sequentially performed at a rate of 4 times the write operation.
  • Another group of FIFOs reads data and sends out, and the two sets of FIFOs use ping-pong reading and writing to prevent read and write conflicts.
  • the ODU2 data is obtained; the data is advanced by 4 times the ODU1 signal period.
  • CDRs clock data recovery modules
  • ODU2[3:0] parallel signals ODU2[0], 0DU2[1]
  • the CDR clock signals have the same clock source, and one of the CD clocks can be selected as the read clock of the frame alignment FIFO to complete the ODU2 [ 3:0]
  • the frame alignment of the data compensates for the delay difference caused by the 4-way signal undergoing cross-scheduling and transmission.
  • the interface unit for the OTU2 signal is exactly the same as that shown in Figure 9.
  • the structure of the interface unit for the ODU3/OTU3 signal is similar to that shown in Figure 9, except that the number of CDRs is 16 and a sixteen-selector is used. .
  • the structure of the interface unit for other signal processing can also be deduced by those skilled in the art.
  • the structure of the framing alignment unit is shown in Fig. 10. It includes: 4 search frame modules, 4 FIFOs and corresponding write address generation modules, and a frame phase alignment module and a read address generation module.
  • the ⁇ phase of each signal is respectively output to the frame phase alignment module and the write address generation module of each FIFO; the write address generation module further receives the corresponding clock signal, and generates the write address to be output to the corresponding FIFO respectively;
  • the frame phase alignment module Aligning the frame phase of each signal to a suitable position according to the received reference clock, generating a reference frame signal output to the read address generation module and the subsequent ODU2 merging device; the read address generation module receiving the reference frame signal and the reference clock to generate a read
  • the address is output to each FIFO; each FIFO is cyclically read and written by the read/write address, and all four signals are aligned to the same frame phase.
  • the frame phase is a frame signal that is searched out by one of the four channels, that is, an internal automatic frame alignment operation. Since the clock frequency of the read and write addresses is the same, the FIFO will not overflow or be empty in the case of a suitable read/write address difference. The difference between the read and write addresses is determined by the frame phase alignment module and is related to the size of the FIFO.
  • the framing alignment unit for the OTU2 signal is identical to that shown in Figure 10; the structure of the framing alignment unit for the ODU3/OTU3 signal is similar to that shown in Figure 10, except that the frame search module, FIFO, and corresponding write address are used. The number of generated modules is 16 and 16 selectors are used. The structure of the framing alignment unit for other signal processing can also be deduced by those skilled in the art.

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Description

信号拆分合并的方法及装置
技术领域
本发明涉及一种异步信号的处理技术， 特別是指一种实现异步信号 拆分的方法和装置， 以及对信号进行合并的方法及装置。 发明背景
光传送体系 (OTH)技术是在同步数字体系 (SDH) /同步光网络 ( Sonet )之后的新一代传送体制。 为了实现 OTH中的数据传输， 国际 电信联盟标准部 （ITU-T) G.709建议定义了光数据单元（ODUk)作为 连接信号，光传送单元（ OTUk)作为传送信号，以及光净荷单元（ OPUk)、 支路单元组（ ODTUGk )等信号 , 用以实现不同的功能,其中 k= 1,2,3。
ODUk的帧结构参见图 1所示， 共 4 x 3824 = 16320字节 （byte)。 第 1 ~ 14列 （ Column )的第 1行（ Row )为帧定界（ FA )和 OTUk开销 ( OH， Overhead )的保留区， 第 1 ~ 14列的第 2 ~ 4行为 ODUk的开销 区， 其余的第 15〜3824列为 OPUk区共占 4 x 3810字节。 其中 ODUk帧 的 1~6字节为定帧字节。
ODUk通过映射可以转化为 OTUk, ODUk到 OTUk的映射结构参 见图 2所示。 通过在保留区中填充 FA和 OTUk开销， 并增加第 3825至 4080列（4 X 256字节），在其中填充 OTUk的前向纠错（FEC )编码（RS ), 从而得到 OTUk帧， 共 4 X 4080 = 15296字节， 其中 OTUk帧的 1 ~ 6字 节为定帧字节。
ODUk (k = 1,2,3)作为三种级别的连接信号， 速率分别为： ODU1: 239/238 x 2.48832 Gbps = 2.498775126 Gbps;
ODU2: 239/237 x 9.95328 Gbps = 10.037273924 Gbps; ODU3: 239/236 x 39.81312 Gbps = 40.319218983 Gbps。
即， ODUk (k= 1, 2, 3 )的速率满足: 239/ ( 239 - k) x "N阶同步 传送模块（STM-N)"。
OTUk (k= 1,2,3), 作为三种级別的传送信号, 速率分別为： OTU1： 255/238 x 2.48832 Gbps - 2.66605714285714 Gbps;
OTU2: 255/237 x 9.95328 Gbps = 10.7092253164557 Gbps;
OTU3: 255/236 x 39.81312 Gbps = 43.018413559322 Gbps。
即， OTUk (k= 1,2,3)的速率满足： 255/ (239- k) x "STM-N"„ 然而， 现有的信号传送和交叉技术往往无法支持 ODU2/OTU2、 ODU3/OTU3 等高速率信号的串行传送， 例如： 当前业界商用成熟的大 容量异步电交叉网片端口速率一般只达到 3.6Gbps， 只能支持 ODU1 串 行信号的调度功能。
对于 OTU2/ODU2信号，速率为 lOGbps级别，一般需要拆分成 4bit 位宽的并行信号； 对于 OTU3/ODU3信号， 速率为 40Gbps级别， 一般 需要拆分成 16bit位宽的并行信号。 拆分后的并行信号还需要考虑成帧 处理， 保证宿端的正常定帧对齐， 合并恢复出源信号。
现有技术的拆分方法是对 OTN的帧结构以 16字节 /块拆分成 4路通 道后传送。 参见图 3所示， 图 3为光传送网中 OTU2的帧结构拆分示意 图， 图中斜线填充部分为帧头区， 一般是将 OTU2帧直接按字节的顺序 拆分成 4路， 第 1路为 1~ 4080字节， 第 2路为 4081 ~ 8160字节， 第 3 路为 8161~ 12240字节，第 4路为 12241 ~ 16320字节。参见图 3a所示， 整个帧头区域将会落到第 1个通道， 这样无法实现宿端的定帧对齐， 也 就无法合并恢复出源信号。 为了解决这个问题， 在拆分后的第 2、 3、 4 帧起始位置， 调整通道顺序， 使帧头能够分別落到第 2、 3、 4通道， 参 见图 3b所示。 如此保证每个通道都具有用于定帧的帧头区域， 从而保 证宿端的定帧对齐合并正常进行。
这种拆分方法要求每帧能够整数的拆分成若干个通道（若干块组 成）。 以一帧大小来计算， 帧大小为 F字节， 通道数为 C, 每通道含的 块数 B, 块的大小为 S字节 （要大于帧区域大小）， 有： F = C x B x S。
因此， 这种方法对于帧大小有要求， 对于 OTN帧结构 ODU/OTU 信号， 帧头区域为 6字节， 所以块拆分的大小最小应为 6字节。
例如： 对于以上 OTU2帧结构， 由于 OTU2帧大小为 16320字节， 拆分成 4通道（ lOGbps速率级别， 4个通道方便处理）， 这样， 16320 = 16字节 /块 4通道 X 255 , 即每帧拆分到每个通道后有 255块。
对于 ODU2帧结构， 扩展出上述的帧头区域（斜线区域 6字节）， ODU2帧大小为 15296字节， 15296 = 16字节 /块 x 4通道 x 239, 即每帧 拆分到每个通道后有 239块。
而对于 OTU3结构， 大小 16320字节， 拆分成 16通道， 16320 = 16 字节 /块 X 16通道 X 63.75, 即每帧拆分到每个通道后有 63.75块， 非整 数， 无法拆分。
对于 ODU3结构， 大小 15296字节， 拆分成 16通道， 15296 = 16 字节 /块 X 16通道 X 59.75, 即每帧拆分到每个通道后有 59.75块， 非整 数， 也无法拆分。
从上面所述可以看出， 由于现有技术的信号拆分方法对 OTN 系统 中的一些帧结构无法适用， 造成 OTN 系统信号处理能力的不完善， 对 于 OTN的系统来说是一个缺陷， 很多场合， 例如： 多种信号的统一传 输、 统一调度， 该系统的许多功能都难以实现。 发明内容
有鉴于此， 本发明的主要目的在于提供一种光传送网中信号的拆分 方法， 实现 OTN各种级别高速信号向低级别速率信号的拆分。
基于上述目的本发明提供的一种异步信号拆分的方法， 包括： 将待拆分的异步信号以数据帧为单位， 按帧的顺序分别进行緩存 , 每当存满 n帧后， 将该 n个数据帧分别通过 n个通道并行发出， 与此同 时緩存待拆分的异步信号后续的 n帧数据； 其中， n为拆分前与拆分后 信号之间速率级别相差的倍数。
该拆分方法所述数据帧的緩存过程进一步包括： 将所述每个数据帧 的存入频率与所述待拆分信号的随路异步信号时钟同步； 所述数据帧的 发出过程进一步包括： 将所述 n个数据帧的并行发出频率为所述数据帧 存入频率的 n分之一。
该拆分方法所述数据帧的緩存方法为： 设置两組緩存每組 n个， 每 个緩存存储一个数据帧； 将所述待拆分的异步信号以数据帧为单位， 按 帧的顺序分别写入一组緩存， 每当存满一组緩存后， 跳转到另一组緩存 进行存储， 与此同时将存满的一组緩存中的数据帧分别通过 n个通道并 行读出， 写入和读出动作交错重复进行。
本发明的第二个目的提供一种异步信号的拆分装置， 将 OTN 系统 内部各种级別的高速信号拆分为低级別速率信号。
基于第二个目的本发明提供的一种异步信号的拆分装置， 包括：
2n个先入先出存储器， 分为两组， 每組 n个， 每个存储器一次存储 一帧的数据；
写地址产生模块， 用于控制每个所迷先入先出存储器的写入操作； 读地址产生模块， 用于控制每个所迷先入先出存储器的读出操作； 以及
n分频模块， 用于将输入时钟信号的频率降低为原频率的 1/n后输 出； 其中， n为拆分前与拆分后信号之间速率级别相差的倍数； 写地址产生模块根据输入时钟信号的频率， 产生写地址和写允许分 别输入每个先入先出存储器 , 控制输入数据按帧的顺序依次串行写入一 组先入先出存储器；同时所述时钟信号经 n分频模块降低为原频率的 1/n 后输入至读地址产生模块， 产生读地址和读允许分别输入至每个先入先 出存储器， 控制另一组先入先出存储器将所存储的数据同时并行输出； 两组先入先出存储器交错执行上述操作。
该拆分装置进一步包括： 用于对输入信号进行搜帧处理的搜帧模 块；
输入信号进入搜帧模块， 进行搜帧处理后， 输出帧信号和所述的随 路异步信号时钟输入至所迷的写地址产生模块。
所述的随路时钟信号同时输入至 n分频模块， 经 n分频模块输出后 与所述的帧信号一起输入至所述的读地址产生模块。
本发明的笫三个目的提供一种信号的合并方法， 将多路低速信号合 并为一路高速信号。
基于笫三个目的所提供的一种信号的合并方法， 包括：
将待合并的 n路并行信号以数据帧为单位， 按帧的顺序分别同时进 行緩存， 并在该 n路信号各存满一帧后， 对所緩存的 n路信号数据帧依 次按帧串行输出； 其中， n为合并后与拆分前信号之间速率级别相差的 倍数。
该合并方法所述数据帧的緩存过程进一步包括： 控制所述每个数据 帧的存入频率与所述待合并信号的参考时钟同步；
所述数据帧的发出过程进一步包括： 控制对存入的每个数据帧的读 出频率为所述数据帧存入频率的 n倍。
该合并方法所漆数据帧的緩存方法为： 设置两組緩存每組 n个， 每 个緩存存储一个数据帧； 将待合并的 n路并行信号以数据帧为单位， 按 帧的顺序分别同时写入一组緩存， 每当存满一组緩存后， 跳转到另一組 緩存进行存储， 与此同时将存满的一组緩存中的数据帧依次按帧串行读 出， 写入和读出动作交错进行。
本发明的第四个目的是提供一种信号的合并装置， 将多路低速信号 合并为一路高速信号。
基于本发明的第四个目的所提供的一种信号的合并装置， 包括： 2n个先入先出存储器， 分为两组， 每组 n个， 每个存储器一次存储 一帧的数据；
写地址产生模块， 用于控制每个所述先入先出存储器的写入操作; 读地址产生模块， 用于控制每个所述先入先出存储器的读出操作； 以及
n倍频模块， 用于将输入时钟信号的频率降^ ^为原频率的 n倍后输 出；
其中， n为拆分前与拆分后信号之间速率级别相差的倍数； 写地址产生模块 ^艮据输入时钟信号的频率， 产生写地址和写允许分 别输入每个先入先出存储器， 控制输入的 n路数据按帧的顺序同时并行 写入一组先入先出存储器； 同时所述时钟信号经 n倍频模块降低为原频 率的 n倍后输入至读地址产生模块， 产生读地址和读允许分别输入至每 个先入先出存储器， 控制另一组先入先出存储器将所存储的数据依次串 行输出； 两组先入先出存储器交错执行上述操作。
该合并装置进一步包括： 定帧对齐单元， 用于对每路信号分别进行 帧搜索， 找到 n路信号各自的帧起始位置， 将 n路信号的帧起始位置都 对齐到相同的帧相位上， 输出 n路对齐的数据至所述 2n个先入先出存 储器， 并输出参考帧信号至所述写地址产生模块和读地址产生模块。 该合并装置进一步包括：
接口单元， 用于对输入的经过背板或者电缆等方式传送的 n路异步 信号进行时钟数据恢复， 恢复后的 n路时钟选出其中一路时钟作为参考 时钟和待对齐的并行数据信号发送至所述的定帧对齐单元； 所述的参考 时钟经 n倍频模块输出后输入至所述写地址产生模块和读地址产生模 块。
从上面所述可以看出， 本发明提供的光传送网中信号拆分的方法和 装置， 在进行信号拆分时， 以帧为基本单位进行拆分， 每帧的帧头区域 被完整的保存下来， 无需在拆分过程中再进行调整， 使拆分操作大为简 化， 同时对每帧包含的字节数也没有要求， 实现对光传送网中的各种信 号都能够进行拆分。 同时， 本发明还提供了光传送网中信号合并的方法 和装置， 对低速信号以帧为基本单位进行合并， 每帧的帧头区域被完整 的保存下来， 大大筒化了信号合并的操作， 并且对待合并信号每帧的字 节数无需进行限制。 附图简要说明
图 1为光传送网中 ODUk信号的帧结构示意图；
图 2为光传送网中 ODUk到 OTUk的映射结构示意图；
图 3为光传送网中 OTU2的帧结构拆分示意图；
图 4为本发明较佳实施例的 ODU2拆分装置的结构示意图； 图 5为本发明较佳实施例的 ODU3拆分装置的结构示意图； 图 6为本发明较佳实施例的 ODU2合并装置的结构示意图； 图 Ί为本发明较佳实施例的 ODU3合并装置的结构示意图； 图 8为本发明较佳实施例中包含有接口单元和定帧对齐单元的合并 装置的结构框图； 图 9为本发明 ODU2合并装置的接口单元的结构示意图； 图 10为本发明 ODU2合并装置的定帧对齐单元的结构示意图； 图 11为本发明定帧对齐单元帧对齐过程的时序图。 实施本发明的方式
下面结合附图及具体实施例对本发明再作进一步详细的说明。 本发明拆分方法的核心思想为： 以帧为单位对信号进行拆分， 对高 速信号按帧的顺序进行緩存， 每当存满 n帧后， 将该 n帧的数据并行发 出， 重复执行上述过程直至将高速信号完全拆分成所需的低速信号。 其 中， n为高速信号与低速信号之间速率级别相差的倍数。
以下以 OTN中的应用为例进行详细说明。 以将 ODU2信号拆分为 ODU1速率级别的信号为例， ODU2信号串行进行緩存， 存满 4帧后， 将这 4帧数据并行发出， 与此同时， 緩存后面的数据帧， 待存满 4帧后 并行发出， 如此反复执行上述操作， 这样就将一路串行的 ODU2成功地 拆分成了 4路并行信号， 也可称为 4个通道并行信号。 由于这 4路信号 组合在一起才能构成完整的 ODU2, 因此为了下文描述方便， 本发明用 ODU2[3:0]代表 ODU2拆分后得到的 4个 ODU1速率级别的并行信号。 在这一过程中由于以帧为基本单位进行拆分， 每帧的帧头区域被完整的 保存下来， 无需在拆分过程中再进行调整， 使拆分操作大为筒化， 同时 对每帧包含的字节数没有要求。
对于 OTU2信号， 如果需将其拆分为 OTU1速率级别的信号， 则也 采用上述拆分过程。 本发明用 OTU2[3:0]代表 OTU2拆分后得到的 4个 OTU1速率级别的并行信号。
对于 ODU3/OTU3信号， 如果需要拆分为 ODU1/OTU1速率级别的 信号， 则在每次存满 16帧后， 并行发出， 拆分成 16路 ODU1/OTU1速 率级别的信号， 为了下文描述方便， 本发明用 ODU3[15:0]/OTU3[15:0] 代表 ODU3/OTU3拆分后得到的 16个 ODU1/OTU1速率级别的并行信 号； 如果需要拆分为 ODU2/OTU2速率级别的信号， 则在每次存满 4帧 后， 并行发出; 其余过程与 ODU2/OTU2信号的处理完全类似。
基于上述方法，本发明较佳实施例的 ODU2拆分装置的结构参见图 4所示， 包括： 搜帧模块、 写地址产生模块， 读地址产生模块， 4分频 模块、 以及 8个先入先出存储器 FIFO— 1、 FIFO— 2、 FIFO— 3、 FIFO— 4、 FIFO— 5、 FIFO—6、 FIFO_7 FIFO一 8。 其中， 4分频模块用于将输入时钟 信号的频率降低为原有频率的 1/4; 写地址产生模块用于控制每个 FIFO 写指针的写入频率; 读地址产生模块用于控制每个 FIFO读指针的读出 频率； 8个 FIFO共分为两组， 每 4个为一組， 每个 FIFO可存储一个 ODU2帧的数据。
该装置对 ODU2信号的拆分过程具体包括:
输入的 ODU2异步信号具有随路的异步信号时钟 CLK,经搜帧模块 进行搜帧处理后得到帧信号 FP,这一过程是成熟的现有技术，不再赘述。 随路异步信号时钟 Clk与帧信号 FP—起进入写地址产生模块， 这里随 路异步信号时钟用于控制 FIFO的写频率， 帧信号 FP用于控制 FIFO的 写起始地址，写地址产生模块根据输入的 Clk和 FP产生写地址 W— Addr 和写允许 WEi ( i=l , 2......8 ), 分别进入每个 FIFO的 W— Addr和 WE 端， 控制 FIFO的写入。 所述写地址和写允许的产生规则为： FIFO写地 址循环变化， 使 ODU2数据按帧依次写入各个 FIFO; 写允许信号轮流 有效， 使写满第一组的 4个 FIFO后再跳转到另一组 FIFO。 其中， 在图 4中两组中对应的 FIFO共用一组写地址 W_ Addr线来接收写地址信号， 即 FIFO— 1与 FIFO— 5、 FIFO— 2与 FIFO— 6、 FIFO— 3与 FIFO— 7、 FIFO— 4 与 FIFO— 8两两共用一組， 从而可以筒化布线， 当然也允许为每个 FIFO 都提供一組写地址 W—Addr线。
时钟 Clk还输入至 4分频模块， 经 4分频模块分频后的输出信号与 帧信号 FP—起分别输入至读地址产生模块的 Clk和 FP端，这里随路异 步信号时钟用于控制 FIFO的读频率， 帧信号 FP用于控制 FIFO的读起 始地址，读地址产生模块根据输入的 Clk和 FP产生读地址 R— Addr以及 读允许 RE1、 RE2, 读地址 R— Addr分别进入每个 FIFO的 R— Addr; 读 允许 RE1输入第一组先入先出存储器 FIFO— 1、 FIFO— 2、 FIFO— 3、 FIFO— 4 , RE2输入第二组先入先出存储器 FIFO— 5、 FIFO— 6、 FIFO— 7、 FIFO—8, 分别控制各 FIFO的读出。 读地址和读允许的产生规则是: 读地址循环 变化， 读允许信号 RE1和 RE2交替有效， 使两组 FIFO中的数据交替并 行读出， 其中， 在图 4 中两组中对应的 FIFO共用一组读地址 R_Addr 线，即 FIFO—1与 FIFO— 5、FIFO—2与 FIFO— 6、FIFO—3与 FIFO—7、FIFO—4 与 FIF0—8两两共用一組， 当然， 也可设置为不共用。 另外， 产生的读 地址信号需要保证当前进行读出操作的一組 FIFO与当前进行写入操作 的一组 FIFO错开， 进行乒乓方式的读写， 即写 FIF0_1至 FIF0_4的期 间，读 FIFO— 5至 FIFO— 8;写 FIFO— 5至 FIFO— 8时，读 FIFO— 1至 FIFO— 4。 其中， 可以看出， FIFO的读出频率是写入频率的 1/4。
0DU2数据顺序写入 FIF0—1、 FIFO— 2、 FIFO— 3和 FIFO— 4, 每个 FIFO存储一帧数据； FIFO— 1至 FIFO— 4都写入一帧过后，跳转到 FIFO— 5、 FIFO— 6、 FIF0—7和 FIFO一 8同样的顺序写入， 与此同时， 读指针开始从 FIF0—1、 FIF0__2、 FIFO— 3和 FIF0—4中同时并行读出数据， 形成低速的 并行数据 ODU2[0]、ODU2[1]、ODU2[2]和 ODU2[3]输出，读速率为 0DU2 速率的 1/4 , 如此读写动作交替， 即完成了 0DU2 信号到并行信号 ODU2[3:0] ( ODU1速率级别信号） 的转换。
如此， 拆分后得到的 ODU2[3:0]信号依然为成帧信号， 包含有 FA 区域； 数据延迟为 4倍 ODU2信号周期。
对于 OTU2信号的情况与 ODU2的基本相同， 只是 OTU拆分单元 的每个 FIFO—x需要存储 OTU2的一帧数据。
对于需拆分为 ODU1/OTU1速率级别信号的 ODU3/OTU3信号， 与 上述 ODU2信号的拆分装置完全类似， 参见图 5所示， 图 5为本发明较 佳实施例的 ODU3拆分装置的结构示意图， 所不同的是需在拆分装置中 设置 32个 FIFO，每 16个作为一组， 以及用于将输入信号的频率降低为 原有频率 1/16的 16分频模块， 写地址产生模块和读地址产生模块分别 控制该 32个 FIFO的读写。 用于其它信号处理的拆分装置的结构， 本领 域技术人员也完全可以依此类推。
与上述拆分方法相对应, 本发明还提出了一种信号的合并方法, 包 括： 将 n路对齐的并行低速信号的数据按帧进行緩存， 以 n倍于存入的 速率按帧顺序依次读取所緩存的数据 , 根据对齐后的帧相位确定帧头区 域， 合并为高速信号后串行发出。
由于通常合并前的 n路低速信号帧相位并不是相同的，这种情况下， 一般还需要在进行上述合并过程之前， 增加对这些信号的对齐过程包 括： 对 n路并行信号进行时钟和数据恢复， 将恢复后的 n路时钟和数据 信号以其中的任意一路时钟作为参考时钟对这 n路数据信号进行帧搜 索， 找到 n路数据信号各自的帧起始位置， 将 n路数据信号的帧起始位 置按照某路数据信号的帧起始位置， 对齐到相同的帧相位上， 生成参考 帧信号， 具体实现可参见下文对图 10的描述。
以经上述拆分方法后得到的 ODU2[3:0]合并为 ODU2的过程为例， 具体合并过程包括： 对 n路并行信号 ODU2[3:0]进行时钟和数据恢复， 将恢复后的 4路时钟和数据信号以其中的一路时钟作为参考时钟对这 4 路数据信号进行帧搜索， 找到 4路数据信号各自的帧起始位置， 将 4路 数据信号的帧起始位置都对齐到相同的帧相位上， 并生成参考帧信号， 将输出 4路对齐的数据和参考帧信号一起按帧并行写入存储器緩存， 然 后，以 4倍于写操作的速率按帧顺序依次读取数据，恢复出 ODU2数据。 如此， 采用乒乓读写方式反复执行上述操作， 从而将并行的低速信号 ODU2[3:0]恢复为 ODU2信号。
基于上述合并方法， 本发明的低速信号合并装置， 参见图 6所示。 图 6是以 ODU2[3:0]合并为 ODU2信号为例的 ODU2合并装置结构 示意图， 包括： 写地址产生模块、 读地址产生模块、 4倍频模块、 以及 8个先入先出存储器 FIFO_l、 FIFO— 2、 FIFO— 3、 FIFO— 4、 FIFO— 5、 FIFO— 6、 FIFO— 7和 FIFO— 8。其中 8个 FIFO分为两组，每个 FIFO存储一帧数据。
写地址产生模块根据接收的参考时钟和参考帧信号，产生各个 FIFO 的写地址 W— Addr和写允许信号 WE1、 WE2,这里参考时钟的作用是控 制 FIFO的写频率， 参考帧信号的作用是控制 FIFO的写起始地址, 产生 规则是： FIFO写地址 W_Addr循环变化， WE1和 WE2交替有效； 在第 一个参考时钟周期中， WE1有效， 写地址 W_Addr指向第一组 FIFO, 使对齐的 ODU2[3:0]并行数据 ODU2[0]至 ODU2[3]并行写入第一组 FIFO; 在下一个参考时钟周期来临时， WE2有效， 写地址 W— Addr指 向第二组 FIFO, 对齐的并行数据 ODU2[0]至 ODU2[3]开始写入第二組 FIFO。 其中， 两组中对应的 FIFO可共用一組写地址线， 即 FIFO— 1与 FIFO— 5、 FIFO— 2与 FIF0_6、 FIFO—3与 FIF0—7、 FIFO— 4与 FIFO— 8两 两共用一组， 写速率为参考时钟速率。
参考时钟信号经 4倍频模块后输出的 4倍频时钟信号与参考帧信号 一起进入读地址产生模块，产生各个 FIFO的读地址 R— Addr和读允许信 号 RE1、 RE2、 RE3、 RE4、 RE5、 RE6、 RE7、 RE8, 这里参考时钟的 作用是控制 FIFO的读频率，参考帧信号的作用是控制 FIFO的读起始地 址， 产生规则为： FIFO读地址循环变化， 读允许信号轮流有效， 例如： 在第一个 1/4参考时钟周期， RE5有效，读地址指向 FIFO一 5 ,将 FIFO_5 中的数据帧读出，如此，在第一个参考时钟周期结束后， FIFO— 5至 FIF08 中的数据都依次被串行读出；然后另一参考时钟周期的第一个 1/4周期， 读地址指向 FIFO— 1 , 将 FIFO— 1中的数据帧读出； 如此， 在第一个参考 时钟周期结束后， FIFO— 1至 FIF04中的数据都依次被串行读出。 从而 使读完第一组的 4个 FIFO后再跳转到另一组 FIF0， FIFO— 1至 FIF08 中的数据不断被串行读出。 其中， 两組中对应的 FIFO可共用一组读地 址 R— Addr线， 即 FIFO— 1与 FIFO— 5、 FIFO— 2与 FIFO— 6、 FIFO— 3与 FIFO— 7、 FIFO— 4与 FIFO— 8两两共用一组。 FIFO中的数据被串行读出， 并且当前正在读的一组 FIFO与当前正写的一组 FIFO错开。
这样， FIFO的写指针并行分别写入 FIFO— 1、 FIFO— 2、 FIFO— 3和 FIFO— 4, 然后再并行写入 FIFO— 5、 FIFO一 6、 FIFO一 7和 FIFO— 8， 写速 率为参考时钟速率; 此时， 读指针开始从 FIFO— 1、 FIFO— 2、 FIFO— 3和 FIFO— 4顺序读出数据， 读速率为参考时钟的 4倍频。 如此不断循环， 从 而完成了 4路 0DU2并行信号 ODU2[3:0] ( 2.5Gbps级别信号）到一路 0DU2信号的转换。
OTU2[3:0]合并为 0TU2信号的 0TU2合并装置结构与图 6所示完 全一致。
将 ODU3[15:0]合并为 0DU3信号的 0DU3合并装置结构参见图 Ί 所示，与用于 0DU2信号的合并装置所不同的只是在 0DU3合并装置中 设置 32个 FIFO, 每 16个为一组， 4倍频模块替换为用于将输入信号的 频率提高为原有频率 16倍的 16倍频^ ^莫块， 写地址产生模块和读地址产 生模块分别控制该 32个 FIFO的读写。 ODU3合并装置的工作方式与 0DU2信号合并装置完全类似。用于将 OTU3[15:0]合并为 0TU3信号的 OTU3合并装置结构与图 7所示的结构也完全相同。 用于其它信号处理 的合并装置的结构， 本领域技术人员也完全可以依此类推。
由于通常输入的 n路低速信号的帧相位不同步， 因此， 合并装置通 常与用于定帧对齐的装置配合使用。
以 ODU2[3:0]信号的处理为例， 参见图 8所示， 在图 6或图 7所示 的合并装置前进一步设置： 接口单元、 定帧对齐单元。 接口单元和定帧 对齐单元分别用于异步信号的时钟恢复及时钟选择和定帧对齐处理。 处 理其它信号的装置组成与图 7所示的完全一样， 信号处理过程也可以此 类推。
待合并的 4路 ODU2[3 :0]进入接口单元中， 接口单元对输入的 4路 并行信号进行时钟数据恢复， 将恢复后的 4路时钟和数据信号输入至定 帧对齐单元， 并根据时钟选择 ^空制信号选择其中一路时钟作为参考时钟 分别发送至定帧对齐单元和 ODU2合并装置。
定帧对齐单元对每路信号分别进行帧搜索 , 找到 4路信号各自的帧 起始位置， 将 4路信号的帧起始位置都对齐到相同的帧相位上， 输出 4 路对齐的数据和参考帧信号至 ODU2合并装置。
ODU2合并装置内部设置有两组 FIFO, 每组 4个， 每个 FIFO存储 一帧数据。 对齐之后的 ODU2[3:0]并行数据与参考帧一起按帧使用低速 时钟并行写入其中的一組 FIFO, 进行对齐处理； 与此同时， 以 4倍于写 操作的速率按帧顺序依次从另一组 FIFO中读取数据并发出， 两组 FIFO 采用乒乓读写方式防止读写冲突。 最后得到 ODU2数据； 数据提前为 4 倍 ODU1信号周期。
其中的接口单元结构参见图 9所示， 包括： 4个时钟数据恢复模块 ( CDR ) 和四选一的选择器， ODU2[3:0]的各路并行信号 ODU2[0]、 0DU2[1]、 ODU2[2]和 ODU2[3]分别进入 4个 CDR恢复出数据 0DU2[n] 和对应的时钟信号 ODU2[n] Clk并输出， 其中 n = 0, 1， 2， 3； 恢复出的 4 路时钟信号 ODU2[n] Clk同时进入四选一选择器， 根据时钟选择控制信 号选择一路时钟输出， 作为参考时钟。 其中， 由于 ODU2[3:0]信号是由 同一 ODU2信号拆分而成的， 因此 CDR时钟信号具有相同的时钟源， 可选择其中一路 CD 时钟作为定帧对齐 FIFO 的读时钟， 以完成 ODU2[3:0]数据的定帧对齐， 弥补了 4路信号经过交叉调度及传送过程 中产生的延迟差异。
用于 OTU2 信号的接口单元与图 9 所示完全相同； 对用于 ODU3/OTU3信号的接口单元的结构也图 9所示类似，只是 CDR的数量 为 16个， 并采用十六选一选择器。 用于其它信号处理的接口单元的结 构， 本领域技术人员也完全可以依此类推。
定帧对齐单元结构参见图 10所示， 包括： 4个搜帧模块、 4个 FIFO 和相应的写地址产生模块、 以及一个帧相位对齐模块和一个读地址产生 模块。
经 CDR恢复后的各路数据 ODU2[n] ( n = 0, 1, 2, 3 )和时钟 0DU2[n] Clk ( n = 0, 1, 2, 3 )首先分别进入搜帧模块进行搜帧，搜索出各路信号的 桢相位分别输出给帧相位对齐模块和各 FIFO的写地址产生模块； 写地 址产生模块还接收对应的时钟信号， 产生写地址分别输出至对应的 FIFO; 帧相位对齐模块根据接收的参考时钟将各信号的帧相位对齐到一 个合适的位置， 生成参考帧信号输出给读地址产生模块以及后面的 ODU2合并装置；读地址产生模块接收所述参考帧信号和参考时钟生成 读地址输出给各 FIFO;各 FIFO在读写地址的作用下循环进行读写操作， 将 4路信号都对齐到相同的帧相位上。 其中， 此帧相位是 4路中某一路 信号搜帧出来的帧信号， 即内部自动帧对齐操作。 由于读写地址的时钟 频率是相同的， 在合适的读写地址差异情况下， FIFO不会溢出或为空。 其中读写地址差异由帧相位对齐模块决定， 与 FIFO的大小相关。
参见图 11所示， 为帧对齐过程的时序图。 由于每个 FIFO的大小是 有限制的， 所以各个帧信号的最大偏差不能超过 FIFO的大小范围， 对 齐后的参考帧信号相位应位于最落后的帧相位后一定量延迟的位置， 但 不能超过 FIFO的范围， 即该参考帧信号的相位应落在图 11中所示实线 框区 i或内。
用于 OTU2信号的定帧对齐单元与图 10 所示完全相同； 对用于 ODU3/OTU3信号的定帧对齐单元的结构也图 10所示类似，只是其中搜 帧模块、 FIFO和相应的写地址产生模块的数量为 16个，并采用 16选一 选择器。 用于其它信号处理的定帧对齐单元的结构， 本领域技术人员也 完全可以依此类推。
以上所述仅为本发明的较佳实施例而已， 并不用以限制本发明， 凡 在本发明的精神和原则之内， 所作的任何修改、 等同替换、 改进等， 均 应包含在本发明的保护范围之内。

Claims

权利要求书
1、 一种异步信号的拆分方法， 其特征在于， 包括：
将待拆分的异步信号以数据帧为单位， 按帧的顺序分别进行緩存， 每当存满 n帧后， 将该 n个数据帧分别通过 n个通道并行发出， 与此同 时緩存待拆分的异步信号后续的 n帧数据； 其中， n为拆分前与拆分后 信号之间速率级別相差的倍数。
2、 根据权利要求 1 所述的方法， 其特征在于， 所述数据帧的緩存 过程进一步包括： 将所述每个数据帧的存入频率与所述待拆分信号的随 路异步信号时钟同步；
所述数据帧的发出过程进一步包括： 将所述 n个数据帧的并行发出 频率为所述数据帧存入频率的 n分之一。
3、 根据权利要求 1或 2所述的方法， 其特征在于， 所述数据帧的 緩存方法为: 设置两组緩存每组 n个， 每个緩存存储一个数据帧； 将所 述待拆分的异步信号以数据帧为单位 , 按帧的顺序分别写入一组緩存， 每当存满一组緩存后， 跳转到另一组緩存进行存储， 与此同时将存满的 一组緩存中的数据帧分别通过 n个通道并行读出， 写入和读出动作交错 重复进行。
4、 一种异步信号的拆分装置， 其特征在于， 包括：
2n个先入先出存储器， 分为两组， 每组 n个， 每个存储器一次存储 一帧的数据；
写地址产生模块 , 用于控制每个所述先入先出存储器的写入操作； 读地址产生模块， 用于控制每个所述先入先出存储器的读出操作； 以及
n分频模块， 用于将输入时钟信号的频率降低为原频率的 1/n后输 出；
其中， n为拆分前与拆分后信号之间速率级别相差的倍数； 写地址产生模块根据输入时钟信号的频率, 产生写地址和写允许分 别输入每个先入先出存储器， 控制输入数据按帧的顺序依次串行写入一 组先入先出存储器；同时所述时钟信号经 n分频模块降低为原频率的 1/n 后输入至读地址产生模块， 产生读地址和读允许分别输入至每个先入先 出存储器， 控制另一组先入先出存储器将所存储的数据同时并行输出； 两组先入先出存储器交错执行上述操作。
5、 根据权利要求 4所述的装置， 其特征在于， 该装置进一步包括： 用于对输入信号进行搜帧处理的搜帧模块;
输入信号进入搜帧模块， 进行搜帧处理后， 输出帧信号和所述的随 路异步信号时钟输入至所述的写地址产生模块。
所述的随路时钟信号同时输入至 n分频模块 , 经 n分频模块输出后 与所述的帧信号一起输入至所述的读地址产生模块。
6、 一种信号的合并方法， 其特征在于， 包括：
将待合并的 n路并行信号以数据帧为单位， 按帧的顺序分别同时进 行緩存， 并在该 n路信号各存满一帧后, 对所緩存的 n路信号数据帧依 次按帧串行输出； 其中， n为合并后与拆分前信号之间速率级别相差的 倍数。
7、 根据权利要求 6 所述的方法， 其特征在于， 所述数据帧的緩存 过程进一步包括： 控制所述每个数据帧的存入频率与所述待合并信号的 参考时钟同步；
所述数据帧的发出过程进一步包括： 控制对存入的每个数据帧的读 出频率为所述数据帧存入频率的 n倍。
8、 根据权利要求 6或 7所述的方法， 其特征在于， 所述数据帧的 緩存方法为： 设置两组緩存每组 n个， 每个緩存存储一个数据帧； 将待 合并的 n路并行信号以数据帧为单位， 按帧的顺序分别同时写入一组緩 存， 每当存满一组緩存后, 跳转到另一组緩存进行存储， 与此同时将存 满的一组緩存中的数据帧依次按帧串行读出， 写入和读出动作交错进 行。
9、 一种信号的合并装置， 其特征在于， 包括：
2n个先入先出存储器， 分为两组， 每組 n个， 每个存储器一次存储 一帧的数据；
写地址产生模块， 用于控制每个所述先入先出存储器的写入操作； 读地址产生模块, 用于控制每个所述先入先出存储器的读出操作； 以及
n倍频模块， 用于将输入时钟信号的频率降低为原频率的 n倍后输 出；
其中， n为拆分前与拆分后信号之间速率级别相差的倍数;
写地址产生模块根据输入时钟信号的频率， 产生写地址和写允许分 别输入每个先入先出存储器， 控制输入的 n路数据按帧的顺序同时并行 写入一组先入先出存储器； 同时所述时钟信号经 n倍频模块降低为原频 率的 n倍后输入至读地址产生模块， 产生读地址和读允许分别输入至每 个先入先出存储器， 控制另一组先入先出存储器将所存储的数据依次串 行输出； 两组先入先出存储器交错执行上述操作。
10、根据权利要求 9所述的装置， 其特征在于， 该装置进一步包括： 定帧对齐单元， 用于对每路信号分别进行帧搜索， 找到 n路信号各自的 帧起始位置， 将 n路信号的帧起始位置都对齐到相同的帧相位上， 输出 n路对齐的数据至所述 2n个先入先出存储器,并输出参考帧信号至所述 写地址产生模块和读地址产生模块。
11、 才 据权利要求 10 所述的装置， 其特征在于， 该装置进一步包 括：
接口单元， 用于对输入的经过背板或者电缆等方式传送的 n路异步 信号进行时钟数据恢复， 恢复后的 n路时钟选出其中一路时钟作为参考 时钟和待对齐的并行数据信号发送至所述的定帧对齐单元；
所述的参考时钟经 n倍频模块输出后输入至所述写地址产生模块和 读地址产生模块。
PCT/CN2006/000505 2005-04-01 2006-03-24 Procede et appareil de partage et de synthese de signaux WO2006102833A1 (fr)

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