WO2006101769A2 - Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom - Google Patents

Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom Download PDF

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Publication number
WO2006101769A2
WO2006101769A2 PCT/US2006/008543 US2006008543W WO2006101769A2 WO 2006101769 A2 WO2006101769 A2 WO 2006101769A2 US 2006008543 W US2006008543 W US 2006008543W WO 2006101769 A2 WO2006101769 A2 WO 2006101769A2
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Prior art keywords
wafer structure
layer
substrate
patterned
aluminum
Prior art date
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PCT/US2006/008543
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French (fr)
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WO2006101769A3 (en
Inventor
Steven S. Nasiri
Anthony Francis Flannery, Jr.
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Invesense Inc.
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Filing date
Publication date
Application filed by Invesense Inc. filed Critical Invesense Inc.
Priority to CNA2006800155345A priority Critical patent/CN101171665A/en
Priority to KR1020077023947A priority patent/KR100934291B1/en
Priority to EP06737697.0A priority patent/EP1859475B8/en
Priority to EP17161696.4A priority patent/EP3208231B1/en
Publication of WO2006101769A2 publication Critical patent/WO2006101769A2/en
Publication of WO2006101769A3 publication Critical patent/WO2006101769A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/02—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating by means of a press ; Diffusion bonding
    • B23K20/023—Thermo-compression bonding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0315—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/012—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being separate parts in the same package
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/033—Thermal bonding
    • B81C2203/035—Soldering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/038—Bonding techniques not provided for in B81C2203/031 - B81C2203/037
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0785—Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
    • B81C2203/0792—Forming interconnections between the electronic processing unit and the micromechanical structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/828—Bonding techniques

Definitions

  • the present invention relates generally to wafer bonding and more particularly to a method and system of bonding in a wafer packaging environment.
  • MEMS technology has been under steady development for some time, and as a result various MEMS devices have been considered and demonstrated for several applications.
  • MEMS technology is an attractive approach for providing inertial sensors, such as accelerometers for measuring linear acceleration and gyroscopes for measuring angular velocity.
  • a MEMS inertial sensor typically includes a proof mass which is flexibly attached to the rest of the device. Relative motion between the proof mass and the rest of the device is driven by actuators and/or sensed by sensors in various ways, depending on the detailed device design.
  • Other MEMS applications include optical applications such as movable mirrors, and RF applications such as RF switches and resonators.
  • MEMS fabrication technology is typically based on processing planar silicon wafers, it is useful to classify MEMS devices according to whether the actuation and/or sensing performed in an inertial sensor (or other application) is in-plane or out of plane (i.e., vertical). More specifically, a device is "in-plane” if all of its sensing and/or actuation is in-plane, otherwise it is “vertical”. Thus MEMS devices are undergoing steady development, despite fabrication difficulties that tend to increase.
  • hybrid integration where elements of a MEMS assembly are individually assembled to form the desired vertical structure. For example, attachment of a spacer to a substrate, followed by attachment of a deformable diaphragm to the spacer, provides a vertical MEMS structure having a spacing between diaphragm and substrate controlled by the spacer.
  • US patent 6,426,687 provides further information on this approach.
  • CMOS compatible wafer-wafer bonding is very desirable for wafer-level- packaging. Its use has been demonstrated in a variety of different technologies.
  • RTV RTV, and others have been spun on and used to form permanent bonds between wafers.
  • Frit glass is typically screen printed on the cover wafers and reflowed to form a patterned glass interface for subsequent wafer-wafer bonding. Frit glass has a typical melting point near 500°C and can be remelted post wafer-wafer aligned bond in a special temperature chamber with a controlled environment.
  • the primary use of glass frit is to provide for the cover substrate and a hermetic sealed cavity for the MEMS. Frit glass technology has been utilized in the MEMS industry for many decades.
  • frit glass does not provide for electrical interconnection between the MEMS and cover, to achieve a hermetic seal interface, minimum of 400 micron seal ring width is required which makes small MEMS devices, such as resonators and optical devices, much larger than otherwise.
  • frit glass screen printed is inherently a thick film process with tens of microns in thickness and several microns of nonuniformity.
  • CMOS compatible eutectic bonding has been demonstrated with indium-gold, solder-gold, gold-gold, etc.
  • all of these prior art systems require the addition of non-standard layers, such as plating of lead, indium, gold, etc., to be added to the CMOS wafer.
  • non-standard layers such as plating of lead, indium, gold, etc.
  • MEMS and CMOS substrates can be very beneficial and provide for an all new generation of MEMS devices with much added functionality, smart electronics, smaller size, and lower cost. Finally, it is important to provide a lead free alloy based upon environmental considerations. Accordingly, what is needed is a system and method for providing wafer bonding that overcomes the above-identified problems. The system and method should be easily implemented, cost effective and adaptable to existing bonding processes. The present invention addresses such a need.
  • An aluminum- germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as a standard foundry CMOS process;
  • this process can provide for high density electrical interconnect; and (7) this process is highly controllable and provides for the smallest gap between two substrates. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.
  • Figure 1 is a flow chart of a method for fabrication of a wafer level package in accordance with the present invention.
  • Figures 2A and 2B are cross sectional and top views of a first embodiment of an assembly in accordance with the present invention.
  • Figures 3 A and 3B are cross sectional and top views of a second embodiment of an assembly in accordance with the present invention.
  • Figure 4 illustrates an exemplary bonding profile to achieve a proper Al/Ge bond.
  • the present invention relates generally to wafer bonding and more particularly to a method and system of bonding utilizing aluminum and germanium in a wafer-level- packaging of MEMS devices with electrical substrate interconnect environment.
  • the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
  • Figure 1 is a flow chart of a method of fabrication of a wafer level package in accordance with the present invention. The method comprises providing a MEMS structure including a substantially germanium top layer, via step 12, and providing a CMOS structure including a substantially aluminum top layer, via step 14. Finally, the method comprises bonding the top layer of the MEMS structure with the top layer of the
  • CMOS structure via step 16.
  • Figures 2A and 2B are cross sectional and top views of a first embodiment of an assembly 100 in accordance with the present invention.
  • a standard foundry CMOS wafer 104 which includes aluminum is bonded to a MEMS substrate 102 which includes germanium to provide an aluminum/germanium (Al/Ge) bond 110.
  • a cavity 106 is within the substrate 104.
  • the CMOS substrate wafer 104 can be any substrate with patterned aluminum shown in Figure 2B that is designed to interface with the MEMS substrate 102 to make for a complete functioning product.
  • a plurality of aluminum contacts 116 are on the top of the CMOS substrate 104 which are coupled to bond pads 105 by interconnect 107. Vias 107 are provided in both the bond pads 105 and the aluminum contacts 116 to allow for electrical connection thereto.
  • the substrate 104 can comprise only a collection of metal layers and interconnects for providing for an electrical interconnection to the MEMS layers.
  • the substrate 102 includes a MEMS feature 108 to complement the MEMS layers on the MEMS substrates 104, such as corresponding cavity 106.
  • a gap control standoff 110 is provided to provide a precise separation of the MEMS substrate 102 from the CMOS substrate 104. The gap control standoff 110 provides a seal ring 1 V 2 for the device.
  • Figures 3 A and 3B are cross sectional and top views of a second embodiment of an assembly in accordance with the present invention.
  • the assembly 200 includes many of the same elements as assembly 100 of Figure 2 and those elements have the same reference numerals. Additionally, the assembly 200 has via contacts 202 through the MEMS substrate 102 'and the gap control standoff 110' to provide electric feedthrough of signals.
  • the MEMS substrate 102 can be a silicon wafer or combination of silicon wafers assembled with all the MEMS features and functionalities including any type of preprocessed features.
  • the MEMS substrate on which the germanium has been patterned is a silicon substrate doped with boron to a conductivity of 0.006-0.02 ⁇ cm. This p+ doping forms an ohmic contact with the aluminum-germanium eutectic mix following the bond.
  • the top metal layer of the foundry CMOS wafer is a ratio mix of 97.5:2:.5 Al:Si:Cu and is 700 nm thick and is on a planarized oxide layer using CMP which is the standard processing step for most CMOS processes of 0.5 urn or lower geometries.
  • the bonding layers on the MEMS are 500 nm of germanium deposited in a standard vacuum sputter deposition system which is properly patterned to match the corresponding aluminum patterned for bonding.
  • the bonding is performed in a commercially available wafer bonder such as that supplied by Electronic Visions Group, Inc., or Suss Microtec, Inc.
  • the equipment should meet the following standards and have the following capabilities: (1) temperature control of both the top and the bottom chuck to nominally 450° C; (2) ambient pressure control to sub-tor; (3) ambient gas control (via a purge line); (4) plumbed with 4-3-5 percent forming gas; and (5) the capability of applying a uniform force across the wafer pair of a minimum of 3000N.
  • the wafers are pre cleaned and then aligned prior to bonding in a compatible alignment tool.
  • both the CMOS wafer and the MEMS wafer are cleaned prior to bonding. Both wafers are assumed to be free of any photoresist or other extraneous materials from previous processing steps.
  • the wafers are cleaned by: (1) a 1. 30 second dip in deionized water, (2) a 1.30 second dip in 50:1 HF; (3) a dump rinse; and (4) a standard spin-rinse-dry process.
  • the bonding pair is aligned in an Electronic Visions 620 wafer- wafer aligner. Separation flags are inserted to maintain separation of the bonded pair prior to bonding.
  • Bonding The aligned pair is transferred to an Electronic Visions 501 bonder.
  • the purge line of this machine has been plumbed with forming gas.
  • the bonding is complete and requires no further processing.
  • An example of an exemplary bonding temperature profile for achieving the proper Al/Ge bond is shown in Figure 4.
  • Alternative embodiments include, for example, (1) the utilization of different materials on top of the germanium to protect it during subsequent MEMS processing; (2) the employment of different pre-bond cleaning methods; (3) the bond may be performed unaligned; (4) the bond may be performed without patterning the aluminum and/or the germanium; (5) the CMOS wafer may be bonded without any additional processing other than the pre-bond clean; (6) the aluminum-germanium bond may be configured so as not to create a hermetic seal; (7) utilization of a substrate other than a MEMS wafer (such as a simple cover wafer); (8) the MEMS substrate may comprise something other than a gyroscope (such as a pressure sensor or accelerometer); (9) the aluminum of the standard
  • CMOS wafer may comprise different formulations of standard aluminum (2% silicon, 2% silicon/1% copper, etc.)
  • a specific temperature profile can be utilized; (11) a forming gas can be used to deoxidize the contact surfaces; (12) aluminum can be utilized as the standard metalization used for IC fabrication; (13) aluminum substrate can be kept below a predetermined temperature to prevent complete leaching of aluminum and germanium alloy from the oxide on the substrate; (14) the bonding can be performed using controlled ambient such as forming gas; (15) the bonding can be performed using low pressure bonding force or high pressure bonding force as assistance for/in order to assist in breaking of the aluminum oxide to initiate the interaction; (16) two wafers can be pre- aligned prior to bonding process; (17) a special cleaning solution can be utilized to clean the oxide from both surfaces; (18) the bonding surfaces can be cleaned by sputter etching; (19) a thin layer of TiW can be utilized to protect the bonding surface during
  • the germanium can be deposited on a non-conductive layer (such as dilicon dioxide) to create an insulating contact.
  • the germanium can be deposited on a semiconductor substrate that has been doped such that the resulting contact between the aluminum of the substrate and the MEMS is rectifying. This substrate can be a silicon substrate with n-type doping to 0.02- 0.05 ⁇ -cm.
  • the germanium can be deposited on a semiconductor substrate that has been doped such that the resulting contact between the aluminum of the substrate and the
  • MEMS is ohmic.
  • An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as a standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of bonding between a first MEMS substrate (102) including at least one pattern substantially germanium layer and a secon CMOS substrate (104) including at least one patterned substantially aluminum layer through an aluminum-germanium bond (110) to create a robust electrical and mechanical contact.

Description

METHOD OF FABRICATION OF AI/GE BONDING IN A WAFER PACKAGING ENVIRONMENT AND A PRODUCT PRODUCED THEREFROM
FIELD OF THE INVENTION
The present invention relates generally to wafer bonding and more particularly to a method and system of bonding in a wafer packaging environment.
RELATED APPLICATIONS
U.S. patent application, serial Nr. 10/690,224, entitled "X-Y Axis Dual-Mass Tuning Fork Gyroscope with Vertically Integrated Electronics and Wafer-Scale Hermetic Packaging," filed October 20, 2003.
U.S. patent application, serial Nr. 10/691,472, entitled "Method of Making an X- Y Axis Dual-Mass Tuning Fork Gyroscope with Vertically Integrated Electronics and
Wafer-Scale Hermetic Packaging," filed October 20, 2003.
U.S. patent application, serial Nr. 10/770,838, entitled "Vertically Integrated MEMS Structure," filed February 2, 2004.
U.S. patent application, serial Nr. 10/771,135, entitled "Vertical Integration of a MEMS Structure with Electronics in a Hermetically Sealed Cavity," filed February 2,
2004.
BACKGROUND OF THE INVENTION
MEMS technology has been under steady development for some time, and as a result various MEMS devices have been considered and demonstrated for several applications. MEMS technology is an attractive approach for providing inertial sensors, such as accelerometers for measuring linear acceleration and gyroscopes for measuring angular velocity. A MEMS inertial sensor typically includes a proof mass which is flexibly attached to the rest of the device. Relative motion between the proof mass and the rest of the device is driven by actuators and/or sensed by sensors in various ways, depending on the detailed device design. Other MEMS applications include optical applications such as movable mirrors, and RF applications such as RF switches and resonators.
Since MEMS fabrication technology is typically based on processing planar silicon wafers, it is useful to classify MEMS devices according to whether the actuation and/or sensing performed in an inertial sensor (or other application) is in-plane or out of plane (i.e., vertical). More specifically, a device is "in-plane" if all of its sensing and/or actuation is in-plane, otherwise it is "vertical". Thus MEMS devices are undergoing steady development, despite fabrication difficulties that tend to increase.
One approach which has been used to fabricate vertical MEMS devices is hybrid integration, where elements of a MEMS assembly are individually assembled to form the desired vertical structure. For example, attachment of a spacer to a substrate, followed by attachment of a deformable diaphragm to the spacer, provides a vertical MEMS structure having a spacing between diaphragm and substrate controlled by the spacer. US patent 6,426,687 provides further information on this approach. Although hybrid integration can provide vertical MEMS devices, the cost tends to be high, since manual processing steps are usually required, and because hybrid integration is typically performed on single devices. Therefore, there is a need for reduced cost integrated MEMS devices that is unmet in the prior art.
CMOS compatible wafer-wafer bonding is very desirable for wafer-level- packaging. Its use has been demonstrated in a variety of different technologies.
However, most of these processes have been limited to providing protection of a sensitive feature from post process handling, such as sawing, die bonding, testing, package, etc.
The need for a robust wafer level integration that can allow for simultaneous wafer-level-packaging and electrical interconnect is very high and can open up a multitude of new smaller, low-cost and feature rich MEMS products. The following describes conventional methods for bonding and their problems.
Organic or Adhesive Based Methods Materials such as Benzocyclobutene (BCB), polyamide, photo resists, patternable
RTV, and others have been spun on and used to form permanent bonds between wafers.
These materials have disadvantages in that because they are organic, they tend to outgas and so are unsuitable for forming hermetic enclosures, and also they are susceptible to solvents, or moistures which can lead to problems with long term reliability and drift of a device's performance. Additionally, they are insulating materials and so are incapable of forming a conductive path between two substrates.
One popular method of making wafer- wafer bonding is by use of frit glass. Frit glass is typically screen printed on the cover wafers and reflowed to form a patterned glass interface for subsequent wafer-wafer bonding. Frit glass has a typical melting point near 500°C and can be remelted post wafer-wafer aligned bond in a special temperature chamber with a controlled environment. The primary use of glass frit is to provide for the cover substrate and a hermetic sealed cavity for the MEMS. Frit glass technology has been utilized in the MEMS industry for many decades. Several major drawbacks are that frit glass does not provide for electrical interconnection between the MEMS and cover, to achieve a hermetic seal interface, minimum of 400 micron seal ring width is required which makes small MEMS devices, such as resonators and optical devices, much larger than otherwise. Also, frit glass screen printed is inherently a thick film process with tens of microns in thickness and several microns of nonuniformity.
Metal-metal bonding
CMOS compatible eutectic bonding has been demonstrated with indium-gold, solder-gold, gold-gold, etc. In order to bond a CMOS wafer, all of these prior art systems require the addition of non-standard layers, such as plating of lead, indium, gold, etc., to be added to the CMOS wafer. Although these processes are capable of doing/creating? hermetic seals and electrical interface, achieving fine features, small gaps and water uniformity are/is very challenging and will result in yield losses.
There are many MEMS device applications that require an electro-mechanical interface between the CMOS substrate and the MEMS substrates that are in micron gaps and require submicron uniformity. Most plating processes require under-layer barrier metalization with tens of microns thickness, and uniformity across the wafer is measured in microns. Hence it is not possible to specify one or two micron gap controls between the MEMS and CMOS substrates using this bonding methodology. The ability to make high density and reliable electrical contacts between the
MEMS and CMOS substrates can be very beneficial and provide for an all new generation of MEMS devices with much added functionality, smart electronics, smaller size, and lower cost. Finally, it is important to provide a lead free alloy based upon environmental considerations. Accordingly, what is needed is a system and method for providing wafer bonding that overcomes the above-identified problems. The system and method should be easily implemented, cost effective and adaptable to existing bonding processes. The present invention addresses such a need. SUMMARY OF THE INVENTION
A method of bonding two substrates to create a robust electrical and mechanical contact by using aluminum and germanium eutectic alloys is disclosed. An aluminum- germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as a standard foundry CMOS process;
(5) this process is compatible with completely fabricated CMOS wafers as post process;
(6) this process can provide for high density electrical interconnect; and (7) this process is highly controllable and provides for the smallest gap between two substrates. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a flow chart of a method for fabrication of a wafer level package in accordance with the present invention.
Figures 2A and 2B are cross sectional and top views of a first embodiment of an assembly in accordance with the present invention.
Figures 3 A and 3B are cross sectional and top views of a second embodiment of an assembly in accordance with the present invention.
Figure 4 illustrates an exemplary bonding profile to achieve a proper Al/Ge bond.
DETAILED DESCRIPTION
The present invention relates generally to wafer bonding and more particularly to a method and system of bonding utilizing aluminum and germanium in a wafer-level- packaging of MEMS devices with electrical substrate interconnect environment. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein. Figure 1 is a flow chart of a method of fabrication of a wafer level package in accordance with the present invention. The method comprises providing a MEMS structure including a substantially germanium top layer, via step 12, and providing a CMOS structure including a substantially aluminum top layer, via step 14. Finally, the method comprises bonding the top layer of the MEMS structure with the top layer of the
CMOS structure, via step 16.
The following describes a preferred embodiment in accordance with the present invention. Figures 2A and 2B are cross sectional and top views of a first embodiment of an assembly 100 in accordance with the present invention. Referring to the embodiment shown in Figure 2A5 a standard foundry CMOS wafer 104 which includes aluminum is bonded to a MEMS substrate 102 which includes germanium to provide an aluminum/germanium (Al/Ge) bond 110. In this embodiment, a cavity 106 is within the substrate 104. The CMOS substrate wafer 104 can be any substrate with patterned aluminum shown in Figure 2B that is designed to interface with the MEMS substrate 102 to make for a complete functioning product. In addition, a plurality of aluminum contacts 116 are on the top of the CMOS substrate 104 which are coupled to bond pads 105 by interconnect 107. Vias 107 are provided in both the bond pads 105 and the aluminum contacts 116 to allow for electrical connection thereto. As an example, the substrate 104 can comprise only a collection of metal layers and interconnects for providing for an electrical interconnection to the MEMS layers. Furthermore, the substrate 102 includes a MEMS feature 108 to complement the MEMS layers on the MEMS substrates 104, such as corresponding cavity 106. A gap control standoff 110 is provided to provide a precise separation of the MEMS substrate 102 from the CMOS substrate 104. The gap control standoff 110 provides a seal ring 1 V 2 for the device. Figures 3 A and 3B are cross sectional and top views of a second embodiment of an assembly in accordance with the present invention. The assembly 200 includes many of the same elements as assembly 100 of Figure 2 and those elements have the same reference numerals. Additionally, the assembly 200 has via contacts 202 through the MEMS substrate 102 'and the gap control standoff 110' to provide electric feedthrough of signals.
Another important feature of the substrate 104 is the availability of the multilayer metalization standard in CMOS foundries with chemical-mechanical-polishing of the oxide to make for a very planar metalized layer suitable for forming Al/Ge eutectic alloy with a germanium presence on the MEMS layer. The MEMS substrate 102 can be a silicon wafer or combination of silicon wafers assembled with all the MEMS features and functionalities including any type of preprocessed features.
In the preferred embodiment, the MEMS substrate on which the germanium has been patterned is a silicon substrate doped with boron to a conductivity of 0.006-0.02Ω cm. This p+ doping forms an ohmic contact with the aluminum-germanium eutectic mix following the bond.
To describe the bonding layers in more detail refer now to the following.
Bonding layers
In a preferred embodiment, the top metal layer of the foundry CMOS wafer is a ratio mix of 97.5:2:.5 Al:Si:Cu and is 700 nm thick and is on a planarized oxide layer using CMP which is the standard processing step for most CMOS processes of 0.5 urn or lower geometries. In a preferred embodiment, the bonding layers on the MEMS are 500 nm of germanium deposited in a standard vacuum sputter deposition system which is properly patterned to match the corresponding aluminum patterned for bonding.
Below is an example of the preferred embodiment of the equipment and process in accordance with the present invention.
Required Equipment
The bonding is performed in a commercially available wafer bonder such as that supplied by Electronic Visions Group, Inc., or Suss Microtec, Inc. The equipment should meet the following standards and have the following capabilities: (1) temperature control of both the top and the bottom chuck to nominally 450° C; (2) ambient pressure control to sub-tor; (3) ambient gas control (via a purge line); (4) plumbed with 4-3-5 percent forming gas; and (5) the capability of applying a uniform force across the wafer pair of a minimum of 3000N.
In the preferred embodiment, the wafers are pre cleaned and then aligned prior to bonding in a compatible alignment tool.
Pre-bond Cleaning
In the preferred embodiment, both the CMOS wafer and the MEMS wafer are cleaned prior to bonding. Both wafers are assumed to be free of any photoresist or other extraneous materials from previous processing steps. The wafers are cleaned by: (1) a 1. 30 second dip in deionized water, (2) a 1.30 second dip in 50:1 HF; (3) a dump rinse; and (4) a standard spin-rinse-dry process.
Alignment
The bonding pair is aligned in an Electronic Visions 620 wafer- wafer aligner. Separation flags are inserted to maintain separation of the bonded pair prior to bonding.
Bonding The aligned pair is transferred to an Electronic Visions 501 bonder. The purge line of this machine has been plumbed with forming gas. Following the cool down period of the bonding recipe, the bonding is complete and requires no further processing. An example of an exemplary bonding temperature profile for achieving the proper Al/Ge bond is shown in Figure 4.
Description of Various and Alternate Embodiments
Alternative embodiments include, for example, (1) the utilization of different materials on top of the germanium to protect it during subsequent MEMS processing; (2) the employment of different pre-bond cleaning methods; (3) the bond may be performed unaligned; (4) the bond may be performed without patterning the aluminum and/or the germanium; (5) the CMOS wafer may be bonded without any additional processing other than the pre-bond clean; (6) the aluminum-germanium bond may be configured so as not to create a hermetic seal; (7) utilization of a substrate other than a MEMS wafer (such as a simple cover wafer); (8) the MEMS substrate may comprise something other than a gyroscope (such as a pressure sensor or accelerometer); (9) the aluminum of the standard
CMOS wafer may comprise different formulations of standard aluminum (2% silicon, 2% silicon/1% copper, etc.)
In addition, (10) a specific temperature profile can be utilized; (11) a forming gas can be used to deoxidize the contact surfaces; (12) aluminum can be utilized as the standard metalization used for IC fabrication; (13) aluminum substrate can be kept below a predetermined temperature to prevent complete leaching of aluminum and germanium alloy from the oxide on the substrate; (14) the bonding can be performed using controlled ambient such as forming gas; (15) the bonding can be performed using low pressure bonding force or high pressure bonding force as assistance for/in order to assist in breaking of the aluminum oxide to initiate the interaction; (16) two wafers can be pre- aligned prior to bonding process; (17) a special cleaning solution can be utilized to clean the oxide from both surfaces; (18) the bonding surfaces can be cleaned by sputter etching; (19) a thin layer of TiW can be utilized to protect the bonding surface during
MEMS processing; (20) including pre bond cleaning using plasma and/or other insitu cleaning techniques, in addition to a more concentrated forming gas and higher force bond; (21) The germanium can be deposited on a non-conductive layer (such as dilicon dioxide) to create an insulating contact. The germanium can be deposited on a semiconductor substrate that has been doped such that the resulting contact between the aluminum of the substrate and the MEMS is rectifying. This substrate can be a silicon substrate with n-type doping to 0.02- 0.05 Ω-cm.
The germanium can be deposited on a semiconductor substrate that has been doped such that the resulting contact between the aluminum of the substrate and the
MEMS is ohmic.
A method and structure of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as a standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer. Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims

CLAIMSWhat is claimed is:
1. A wafer structure comprising: a first substrate including at least one MEMS feature, the first substrate including at least one patterned substantially germanium layer; and a second substrate, the second substrate including at least one patterned substantially aluminum layer and one electrical contact; wherein the at least one patterned substantially germanium layer is bonded to the at least one patterned aluminum layer to create a robust electrical and mechanical contact.
2. The wafer structure of claim 1 wherein the first and/or the second substrates comprise silicon substrates or multi layer of silicon substrates.
3. The wafer structure of claim 1 wherein the first and/or second substrates can be any of GaAs, InPh, SiGe substrates.
4. The wafer structure of claim 1 wherein the first and/or second substrates comprise glass substrates or glass multi layer structures.
5. The wafer structure of claim 1 wherein MEMS structures are included in the substrate.
6. The wafer structure of claim 1 wherein integrated circuits are incorporated on the substrate.
7. The wafer structure of claim 6 wherein the integrated circuit has multilayer metalization with a CMP (chemical and mechanical polishing) process of the oxide layer to allow for electrical under pass feed-through and planar metal to provide for a hermetic seal.
8. The wafer structure of claim 1 wherein contact pads are located outside the hermetic sealing ring.
9. The wafer structure of claim 1 wherein the at least one patterned substantially germanium layer and the at least one patterned aluminum layer are bonded to provide a hermetic seal.
10. The wafer structure of claim 1 wherein the at least one electrical contact comprises a plurality of electrical contacts.
11. The wafer structure of claim 1 wherein the bond is Al & Ge eutectic composition.
12. A wafer structure comprising: a first substrate including at least one MEMS feature, the first substrate including at least one patterned substantially germanium layer and at least one via for electric feed-through; and a second substrate, the second substrate including at least one patterned substantially aluminum layer and one electrical contact; wherein the at least one patterned substantially germanium layer with the at least one via is bonded to the at least one patterned aluminum to create a robust electrical and mechanical contact.
13. The wafer structure of claim 12 wherein the first and/or the second substrates comprise silicon substrates or multi layer of silicon substrates.
14. The wafer structure of claim 12 wherein the first and/or second substrates comprise glass substrates or glass multi layer structures.
15. The wafer structure of claim 12 wherein the first and/or second substrates can be any of GaAs, InPh, SiGe substrates.
16. The wafer structure of claim 12 wherein MEMS structures are included in the substrate.
17. The wafer structure of claim 12 wherein integrated circuits are incorporated on the substrate.
18. The wafer structure of claim 17 wherein the integrated circuit has multilayer metalization with a CMP (chemical and mechanical polishing) process of the oxide layer to allow for electrical under pass feed-through and planar metal to provide for a hermetic seal.
19. The wafer structure of claim 12 wherein contact pads are outside the seat ring.
20. The wafer structure of claim 12 wherein the at least one patterned substantially germanium layer and the at least one patterned aluminum layer are bonded to provide a hermetic seal.
21. The wafer structure of claim 12 wherein the at least one electrical contact comprises a plurality of electrical contacts.
22. The wafer structure of claim 12 wherein the bond is Al/Ge eutectic composition.
23. A wafer structure comprising: a first substrate including at least one MEMS feature, the first substrate including at least one patterned substantially germanium layer deposited over patterned etched standoff with precise height; and a second substrate, the second substrate including at least one patterned substantially aluminum layer and one electrical contact; wherein the at least one patterned substantially germanium layer over the precise standoffs is bonded to the at least one patterned aluminum to create a robust electrical and mechanical contact, wherein a specific and precise gap is created and maintained between the first and second substrates.
24. A method for providing a wafer structure comprising the steps of: providing a first substrate including at least one MEMS feature, the first substrate including at least one patterned substantially germanium layer; and providing a second substrate, the second substrate including at least one patterned substantially aluminum layer and one electrical contact; wherein the at least one patterned substantially germanium layer is bonded to the at least one patterned aluminum to create a robust electrical and mechanical contact.
25. The method of claim 24 wherein a specific temperature and time profile is used to provide the bond.
26. The method of claim 24 wherein a forming gas is used to deoxidize the contact surfaces of aluminum and germanium.
27. The method of claim 24 wherein aluminum is the standard metaiization used for IC fabrication.
28. The method of claim 24 wherein the second substrate is kept below a predetermined temperature to prevent complete leaching of aluminum from the oxide surface on the second substrate.
29. The method of claim 24 wherein the bonding is performed using controlled ambient such as forming gas.
30. The method of claim 24 wherein the bonding is performed using low pressure bonding force.
31. The method of claim 24 wherein two wafers have been pre-aligned prior to bonding process.
32. The method of claim 24 wherein special cleaning solution is used to clean the oxide from both surfaces.
33. The method of claim 24 wherein the bonding surfaces are cleaned by sputter etching.
34. The method of claim 24 wherein a thin layer of TiW is used to protect the bonding surface during MEMS processing.
35. The method of claim 24 where a doped cover layer is chosen so that the nature of the electrical contact is ohmic.
36. The method of claim 24 wherein the doping of the cover layer is chosen so that the nature of the electrical contact is rectifying.
37. The method of claim 24 wherein a dielectric layer is deposited on the cover layer so that the nature of the electrical contact is insulating.
38. The method of claim 24 wherein the at least one patterned substantially germanium layer comprises approximately 500nm of germanium and an approximate ratio mix of 97.5:2:.5 of A1:SI:CU and is approximately 700 nm thick.
PCT/US2006/008543 2005-03-18 2006-03-09 Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom WO2006101769A2 (en)

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EP06737697.0A EP1859475B8 (en) 2005-03-18 2006-03-09 Method of fabrication of al/ge bonding in a wafer packaging environment and a product produced therefrom
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