WO2006100951A1 - Circuit et procede de commande de dispositif d’affichage - Google Patents

Circuit et procede de commande de dispositif d’affichage Download PDF

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Publication number
WO2006100951A1
WO2006100951A1 PCT/JP2006/304897 JP2006304897W WO2006100951A1 WO 2006100951 A1 WO2006100951 A1 WO 2006100951A1 JP 2006304897 W JP2006304897 W JP 2006304897W WO 2006100951 A1 WO2006100951 A1 WO 2006100951A1
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WIPO (PCT)
Prior art keywords
signal
image
output
data
pixel
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PCT/JP2006/304897
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English (en)
Japanese (ja)
Inventor
Hidetaka Mizumaki
Yasuhiro Hirayama
Shuji Uemura
Hideki Yakushigawa
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Sharp Kabushiki Kaisha
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Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2006100951A1 publication Critical patent/WO2006100951A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present invention relates to a matrix display device such as an active matrix liquid crystal display device, and more particularly to a drive circuit for driving data signal lines in such a display device.
  • liquid crystal display devices that provide stereoscopic display by causing binocular parallax to a user have been provided.
  • a parallax barrier is provided on the liquid crystal panel to display different images for two viewpoints corresponding to the left and right eyes.
  • DV liquid crystal display device a liquid crystal display device that displays different images for two users.
  • a display image seen from the right side and a display image seen from the left side can be made different. Therefore, for example, this DV liquid crystal display device can be installed in a car to display different images for the driver and passengers in the passenger seat, or installed at a counter such as a bank to display different images for customers and staff. It can be displayed.
  • FIG. 30 (A) is a plan view schematically showing the arrangement of the pixel formation portions (hereinafter referred to as “pixel arrangement”) for forming the pixels of the image to be displayed in the DV liquid crystal display device
  • FIG. FIG. 30 is a cross-sectional view schematically showing the pixel arrangement (FIG. 30A is a cross-sectional view taken along the line YY in FIG. 30B).
  • each pixel constituting an image to be displayed is composed of an R (red) subpixel, a G (green) subpixel, and a B (blue) subpixel.
  • an R (red) pixel forming portion also referred to as “R subpixel”
  • a G (green) pixel forming portion also referred to as “G subpixel”.
  • a B (blue) pixel formation portion also referred to as “B sub-pixel”.
  • the DV liquid crystal display device has a large number of elements arranged in a matrix.
  • the pixel array which has a pixel forming power, includes a column in which R subpixels are arranged, a column in which G subpixels are arranged, and a row in which B subpixels are arranged, and R subpixels arranged every other column and Three subpixels consisting of the G subpixel and the B subpixel form one pixel in the image to be displayed (the DV liquid crystal display device has two images to be displayed and one of them).
  • the parallax barrier 84b As shown in FIG. 30B, the light emitted from each sub-pixel 90 is selectively blocked, and each sub-pixel 90 Of the light emitted from the DV liquid crystal display device, only the light that passes through the slit 84s formed in the parallax barrier 84b is emitted from the DV liquid crystal display device. That is, light is emitted only in the ranges indicated by ⁇ b and ⁇ g in FIG.
  • the user located on the left side in front of the display surface of the DV liquid crystal display device has the third B subpixel from the left among the four subpixels shown in the figure.
  • the first subpixel group composed of subpixels selected every other column is for the user (viewpoint) located on the left side.
  • a second pixel group that forms an image to be displayed and has a sub-pixel power other than the first sub-pixel group (which is also a pixel power selected every other column) is a user (viewpoint) located on the right side.
  • the display image when viewed from the left side is different from the display image when viewed from the right side.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2004-206089
  • Patent Document 2 Japanese Unexamined Patent Publication No. 2004-287406
  • Patent Document 3 Japanese Unexamined Patent Publication No. 62-278591
  • a dual view display device such as a DV liquid crystal display device
  • two images to be displayed respectively in two regions where viewpoints can be arranged typically Is a format of input data that represents a left image that is displayed when viewed from the left and a right image that is displayed when viewed from the right.
  • Two types of input formats are possible as shown in Fig. 5 (A) and Fig. 5 (B).
  • the input format shown in Fig. 5 (A) is a format in which the left image data DaL and the right image data DaR are input simultaneously as two digital image signals (hereinafter referred to as "DV2 simultaneous input format"). Is simply called “simultaneous input format").
  • the input format shown in Fig. 5 (B) is input as a single signal indicating combined image data, which is image data in a format in which left image data DaL and right image data DaR are arranged in the horizontal direction (display row direction).
  • Format that is, the data for one line of the left image and the data for one line of the right image are alternately input (hereinafter referred to as “DV display mapping input format” or “alternate input format”).
  • DV display mapping input format or “alternate input format”.
  • the binocular parallax is generated by the parallax barrier as described above, so that a three-dimensional display is obtained.
  • the 3D liquid crystal display device that performs the display.
  • the sub-pixel 70 is arranged so that the horizontal direction (row direction) is the longitudinal direction, and each pixel constituting the color image is arranged in the vertical direction (column A configuration (hereinafter referred to as “horizontal pixel arrangement configuration”) in which three subpixels 70, which are adjacent to each other in the direction (R), G subpixel, and B subpixel, are also proposed (for example, FIG. (See 7 (b)).
  • the parallax barrier is smaller than the above configuration in which the sub-pixels are arranged so that the vertical direction is the longitudinal direction (hereinafter referred to as “vertically long pixel arrangement configuration”). Since the distance dl between 54b and the sub-pixel 70 can be made relatively large, reflection of the left and right images can be prevented without requiring high processing accuracy.
  • a DV liquid crystal display device having a horizontally long pixel arrangement configuration requires a data driver that outputs a drive signal in a format corresponding to the pixel arrangement configuration, and data used in a DV liquid crystal display device having a vertically long pixel arrangement configuration.
  • the driver cannot be used as it is.
  • the IC is dedicated to a DV liquid crystal display with a horizontally long pixel arrangement, and a DV liquid crystal display or SV liquid crystal with a vertically long pixel arrangement. It cannot be used with display devices.
  • the present invention has been made to solve the above-described problem, and is a data signal line drive circuit having flexibility in display data input format and Z or drive signal output format in a matrix display device.
  • the purpose is to provide.
  • a first aspect of the present invention includes a plurality of data signal lines extending in the column direction, a plurality of scanning signal lines intersecting with the plurality of data signal lines and extending in the row direction, and the plurality of data signal lines. And a plurality of sub-pixel forming portions arranged in a matrix corresponding to the intersections of the plurality of scanning signal lines, and each sub-pixel forming portion selects a scanning signal line passing through the corresponding intersection.
  • a predetermined number of input terminal groups for receiving an image signal representing the image as a serial signal in units of pixels or sub-pixels, and an image signal input from the input terminal group.
  • a predetermined number of output terminal groups for outputting as serial signals in units of units or sub-pixels, and input from each input terminal group of the predetermined number of input terminal groups based on a first control signal to which an external force is also applied.
  • a first connection switching circuit for switching an output terminal group to output an image signal to be output among the predetermined number of output terminal groups;
  • a serial-parallel converter that is provided corresponding to each output terminal group of the predetermined number of output terminal groups, and that inputs an image signal output from the corresponding output terminal group as a serial signal and outputs it as a parallel signal;
  • a data signal generation circuit for generating the plurality of data signals based on the parallel signals to be output.
  • a second aspect of the present invention is the first aspect of the present invention.
  • the plurality of sub-pixel forming units includes a first sub-pixel forming unit group for forming a first image displayed for a first predetermined region where a viewpoint can be arranged, and a first sub-pixel forming unit capable of arranging a viewpoint.
  • the predetermined number of input terminal groups includes a first input terminal group for receiving an image signal representing the first or second image, and a second input terminal for receiving the image signal representing the second image.
  • Input terminal group
  • the predetermined number of output terminal groups are input from a first output terminal group for outputting an image signal input from the first input terminal group and from the first or second input terminal group.
  • the first connection switching circuit includes a first output terminal group and an output terminal group to which an image signal to be input is output as the first output terminal group based on the first control signal.
  • the second output terminal group is switched between two output terminal groups, and the second input terminal group force is switched to determine whether or not to output the input image signal to the second output terminal group force.
  • a third aspect of the present invention is the first aspect of the present invention.
  • the data signal generation circuit includes:
  • each serial-parallel converter The parallel signal output from each serial-parallel converter is converted into the image by each serial-parallel converter.
  • a holding circuit for holding and outputting until the next serial signal representing pixels in one row is input and output as a parallel signal;
  • a second connection switching circuit for sequentially selecting and outputting signals constituting the same pixel signal group having a signal power corresponding to data
  • a signal generation / output circuit that generates and outputs the plurality of data signals based on a signal output from the second connection switching circuit.
  • a fourth aspect of the present invention is the third aspect of the present invention.
  • the second connection switching circuit is
  • the signals constituting the same pixel signal group are sequentially selected and output based on the first predetermined signal
  • the second control signal is a second predetermined signal
  • all signals constituting the same pixel signal group are selected and output simultaneously.
  • a fifth aspect of the present invention provides a plurality of data signal lines extending in the column direction, a plurality of scanning signal lines intersecting with the plurality of data signal lines and extending in the row direction, and the plurality of data signal lines. And a plurality of subpixel forming portions arranged in a matrix corresponding to the intersections of the plurality of scanning signal lines, and each subpixel forming portion selects a scanning signal line passing through the corresponding intersection.
  • a holding circuit for holding an image signal corresponding to the sub-pixel data for at least one row of the image
  • the sub-pixels Based on the second control signal to which an external force is also applied, out of the image signals held in the holding circuit, the sub-pixels to be taken in by a predetermined number of sub-pixel forming units forming each of the pixels for at least one row
  • a second connection switching circuit for selecting and outputting any or all of the same pixel signal group consisting of signals corresponding to data;
  • the plurality of data signals are generated based on a signal output from the second connection switching circuit.
  • a data signal generation circuit to be configured,
  • the second connection switching circuit is
  • the signals constituting the same pixel signal group are sequentially selected and output based on the first predetermined signal
  • the second control signal is a second predetermined signal
  • all signals constituting the same pixel signal group are selected and output simultaneously.
  • a sixth aspect of the present invention is a display device, comprising a drive circuit according to any one of the first to fifth aspects of the present invention.
  • the seventh aspect of the present invention is the first image displayed for the first predetermined area where the viewpoint can be arranged and the second image displayed for the second predetermined area where the viewpoint can be arranged.
  • the first operation mode for driving the first display device that forms the first and second images to be different from the second image, and the same for the first and second predetermined regions A driving circuit having a second operation mode for driving the second display device that forms the same image so that the image is displayed,
  • Each of the first and second display devices is a display device
  • a plurality of data signal lines extending in the column direction
  • a plurality of scanning signal lines that intersect the plurality of data signal lines and extend in the row direction; and a plurality of sub signal lines arranged in a matrix corresponding to the intersections of the plurality of data signal lines and the plurality of scanning signal lines, respectively.
  • a pixel forming portion
  • Each sub-pixel forming unit in the first and second display devices takes in a signal on the corresponding data signal line as sub-pixel data when a scanning signal line passing through the corresponding intersection is selected,
  • the plurality of subpixel forming portions of the first display device include a first subpixel forming portion group for forming the first image and a second subpixel forming portion for forming the second image.
  • the first sub-pixel forming unit group and the second sub-pixel forming unit group are alternately arranged in a line,
  • the plurality of sub-pixel forming units of the second display device form the same image, and the driving circuit generates a plurality of data signals representing images to be displayed, and Including a data signal line driving circuit for applying to the data signal line;
  • the data signal line driving circuit includes:
  • a first input terminal group for receiving the first image or the image signal representing the same image as a serial signal in pixel units or sub-pixel units, and the image signal representing the second image as pixel units or sub-pixels.
  • a second input terminal group for receiving as a serial signal in pixel units,
  • an image signal representing the first image input from the first input terminal group is applied to a data signal line corresponding to the first sub-pixel forming unit group.
  • a power data signal and to apply to the data signal line corresponding to the second sub-pixel forming unit group based on the image signal representing the second image input to the second input terminal group force Generate a data signal,
  • a data signal to be applied to the plurality of data signal lines of the second display device is generated based on an image signal representing the same image input from the first input terminal group. It is characterized by doing.
  • the eighth aspect of the present invention is the seventh aspect of the present invention.
  • the data signal line driving circuit includes:
  • the first and second input terminal groups and a predetermined number of output terminal groups for outputting image signals input from the first and second input terminal groups as pixel-unit or sub-pixel unit serial signals; Output image signals input from the input terminal groups of the first and second input terminal groups according to whether the operation mode of the drive circuit is the first operation mode or the second operation mode.
  • a connection switching circuit for switching an output terminal group to be switched between the predetermined number of output terminal groups;
  • a serial-parallel converter that is provided corresponding to each output terminal group of the predetermined number of output terminal groups, and that inputs an image signal output from the corresponding output terminal group as a serial signal and outputs it as a parallel signal;
  • a data signal generation circuit for generating the plurality of data signals based on the parallel signals to be output
  • the connection switching circuit is In the first operation mode, a data signal corresponding to the first sub-pixel forming unit group based on a parallel signal output from a serial parallel transformation to which an image signal representing the first image is input.
  • a data signal to be applied to the line is generated by the data signal generation circuit, and based on the parallel signal output from the serial / parallel transformation to which the image signal representing the second image is input, the first signal is generated.
  • the first and second input terminal groups and the predetermined number of output terminal groups so that the data signal to be applied to the data signal lines corresponding to the two sub-pixel forming unit groups is generated by the data signal generation circuit.
  • a data signal to be applied to the plurality of data signal lines in the second display device based on the normal signal output from each series-parallel conversion is the data signal generation circuit.
  • the first input terminal group and the predetermined number of output terminal groups are connected to each other as generated by the above.
  • a ninth aspect of the present invention there are provided a plurality of data signal lines extending in the column direction, a plurality of scanning signal lines intersecting with the plurality of data signal lines and extending in the row direction, the plurality of data signal lines, and the plurality of data signals lines.
  • a plurality of sub-pixel forming portions arranged in a matrix corresponding to each of the intersections with the scanning signal lines, and each sub-pixel forming portion is selected when a scanning signal line passing through the corresponding intersection is selected.
  • a display device that captures a signal on a data signal line corresponding to a subpixel data as a drive method for applying a plurality of data signals representing an image to be displayed to the plurality of data signal lines,
  • a predetermined number of input terminal groups for receiving image signals representing the image as serial signals in pixel units or sub-pixel units, and image signals input from the input terminal groups as serial signals in pixel units or sub-pixel units
  • the first connection switching circuit having a predetermined number of output terminal groups for output as a first input signal
  • the first connection switching circuit is input from each input terminal group of the predetermined number of input terminal groups based on a first control signal given by an external force.
  • the plurality of data signals based on the parallel signal output in the serial-parallel conversion step. And a data signal generation step of generating a signal.
  • a tenth aspect of the present invention is the ninth aspect of the present invention.
  • the plurality of sub-pixel forming units includes a first sub-pixel forming unit group for forming a first image displayed for a first predetermined region where a viewpoint can be arranged, and a first sub-pixel forming unit capable of arranging a viewpoint.
  • the predetermined number of input terminal groups includes a first input terminal group for receiving an image signal representing the first or second image, and a second input terminal for receiving the image signal representing the second image.
  • Input terminal group
  • the predetermined number of output terminal groups are input from a first output terminal group for outputting an image signal input from the first input terminal group and from the first or second input terminal group.
  • the first input terminal group force is an output terminal group to which an input image signal is to be output, the first output terminal group and the second output terminal group.
  • the output terminal group is switched between and whether the image signal input from the second input terminal group outputs the second output terminal group force or not is switched.
  • An eleventh aspect of the present invention is the ninth aspect of the present invention.
  • the data signal generation step includes
  • the parallel signal output in the serial-parallel conversion step is held and output until the next serial signal representing one row of pixels in the image is input and output as a parallel signal in the serial-parallel conversion step. Holding step;
  • sub-pixel data to be taken in by a predetermined number of sub-pixel forming units forming each of the pixels for one row of the signals output as parallel signals in the holding step
  • a second connection switching step for sequentially selecting and outputting signals constituting the same pixel signal group having a signal power equivalent to
  • a twelfth aspect of the present invention is the eleventh aspect of the present invention.
  • the second connection switching step includes:
  • the method includes selecting and simultaneously outputting all signals constituting the same pixel signal group.
  • a thirteenth aspect of the present invention provides a plurality of data signal lines extending in the column direction, a plurality of scanning signal lines intersecting with the plurality of data signal lines and extending in the row direction, and the plurality of data signals.
  • a plurality of sub-pixel forming portions arranged in a matrix corresponding to the intersections of the lines and the plurality of scanning signal lines, and each sub-pixel forming portion selects a scanning signal line passing through the corresponding intersection.
  • the sub-pixel data to be taken in by a predetermined number of sub-pixel forming units that form each of the pixels for the one row of the image signal is held in the holding step!
  • a data signal generating step for generating the plurality of data signals based on the signal output in the second connection switching step
  • the second connection switching step includes:
  • the second control signal is a first predetermined signal
  • the control signal is the second predetermined signal
  • the method includes selecting and simultaneously outputting all signals constituting the same pixel signal group.
  • a predetermined number of output terminal groups in the first connection switching circuit A data signal to be applied to the data signal line of the display panel is generated on the basis of the normal signal that is also output corresponding to each of the series and parallel transformations. Then, based on the first control signal given from the outside, each input terminal group of the predetermined number of input terminal groups is switched between the predetermined number of output terminal groups. Can be replaced. Therefore, by setting or switching the first control signal, an image signal input from each input terminal group as a signal (display data) representing an image to be displayed is displayed in any appropriate series-parallel manner according to the input format. Can be input to the converter. Therefore, it is possible to input display data of various input formats without separately preparing an interface circuit and appropriately drive the data signal lines of the display panel.
  • the signal of the first image displayed for the first predetermined area where the viewpoint can be arranged and the second predetermined area where the viewpoint can be arranged When two image signals, the second image signal displayed at the same time, are input simultaneously (in the case of DV2 simultaneous input format), the first connection switching circuit sets the first control signal.
  • the first input terminal group force The first image signal input to the first output terminal group force is output to the corresponding series-parallel variable ⁇ and the second input terminal group force is input to the second input terminal group force.
  • the image signal of can be output to the second output terminal group force and given to the corresponding series-parallel variable.
  • the first control signal When the first image signal is also input to the first input terminal group force by switching the setting, the first image signal is output to the first output terminal force and applied to the corresponding series-parallel change.
  • the second input image group force is input to the second image signal, the second image signal can also be output to the corresponding series-parallel variable by outputting the second output terminal force.
  • This corresponds to sub-pixel data to be taken in by a predetermined number of sub-pixel forming portions that form
  • the signals constituting the same pixel signal group consisting of the signals are sequentially selected and output, and the data signal to be applied to the data signal line is generated based on the sequentially selected signals.
  • a predetermined number of sub-pixel forming portions for example, three sub-pixel forming portions having R sub-pixel, G sub-pixel, and B sub-pixel force) for forming one pixel of an image to be displayed are arranged in the column direction and are the same
  • the data signal lines in a display panel configured to be connected to the data signal lines for example, a DV liquid crystal panel having a horizontally long pixel arrangement
  • the same pixel signal group is configured based on the first predetermined signal.
  • the signals are sequentially selected and output, and the second control signal is the second predetermined signal, all signals constituting the same pixel signal group are selected and output simultaneously. Therefore, by setting or switching the second control signal, the output format of the data signal can be changed to an independent output format for the same pixel signal group, or a time-division output format.
  • the data signal line of the display panel can be appropriately driven regardless of the arrangement configuration or the horizontally long pixel arrangement configuration.
  • the first subpixel formation is performed based on the image signal representing the first image input from the first input terminal group.
  • a data signal to be applied to the data signal line corresponding to the group of pixels is generated, and the second subpixel formation unit group is generated based on the image signal representing the second image input from the second input terminal group.
  • a data signal to be applied to the corresponding data signal line is generated, and in the second operation mode, the first and second predetermined regions are applied based on the image signal input from the first input terminal group.
  • Data signals to be applied to the plurality of data signal lines of the second display device that displays the same image are generated.
  • the data signal line is connected to both the first display device such as a DV liquid crystal display device and the second display device such as an SV liquid crystal display device.
  • a driving circuit that can be used for driving can be provided.
  • FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing an equivalent circuit of one sub-pixel forming unit in the first embodiment.
  • FIG. 3 is a cross-sectional view for explaining the structure of the liquid crystal panel in the first embodiment.
  • FIG. 4 is a plan view (A) and a cross-sectional view (B) schematically showing a configuration for realizing dual view display in the first embodiment.
  • FIG. 5 is a diagram (A, B) showing a format of input data represented by an image signal to be supplied to the data driver in the first embodiment.
  • FIG. 6 is a block diagram showing a configuration example of a data driver in the first embodiment.
  • FIG. 7A is a diagram showing a truth table showing the operation of the input-side selector in the data driver according to the above configuration example
  • FIG. 7B is a diagram showing a truth table showing the operation of the output-side selector.
  • FIG. 8 is a timing chart (A to C) for explaining the operation of the input side selector in the data driver according to the above configuration example.
  • FIG. 9 is a timing chart (A to F) for explaining the operation of the output side selector for time division output in the data driver according to the above configuration example.
  • FIG. 10 is a timing chart (A to G) for explaining the operation (mainly on the input side) of the data driver according to the above configuration example in the two-system simultaneous input mode.
  • FIG. 11 is a timing chart (A to I) for explaining the operation (mainly on the output side) of the data driver according to the above configuration example in the two-system simultaneous input mode.
  • FIG. 12 is a timing chart (A to F) for explaining the operation (mainly on the input side) in the display mapping input mode of the data driver according to the above configuration example.
  • FIG. 13 is a block diagram showing a first modification of the data driver in the first embodiment.
  • FIG. 14 is a block diagram showing a second modification of the data driver in the first embodiment.
  • FIG. 15 is a diagram showing a truth table showing the operation of the output side selector in the second modified example.
  • FIG. 17 is a block diagram showing a configuration of a data driver for liquid crystal display according to a second embodiment of the present invention.
  • FIG. 19 is a timing chart (A to E) for explaining the operation of the input side selector in the data driver according to the second embodiment.
  • FIG. 20 is a timing chart (A to E) for explaining the operation of the output-side selector in the independent output mode in the data driver according to the second embodiment.
  • FIG. 22 is a timing chart for explaining the operation (mainly on the input side) of the data driver according to the second embodiment in the simultaneous input mode when driving a DV liquid crystal panel having a vertically long pixel arrangement configuration (A) ⁇ F).
  • FIG. 23 is a timing chart for explaining the operation (mainly on the output side) in the independent output mode of the data driver according to the second embodiment when driving a DV liquid crystal panel having a vertically long pixel arrangement configuration. ⁇ I).
  • FIG. 24 is a timing chart for explaining the operation (mainly on the input side) in the display mapping input mode of the data driver according to the second embodiment when driving a DV liquid crystal panel having a vertically long pixel arrangement configuration. ⁇ F).
  • FIG. 25 is a timing chart for explaining the operation (mainly on the input side) in the simultaneous input mode of the data driver according to the second embodiment when driving a DV liquid crystal panel having a horizontally long pixel arrangement configuration. ⁇ F).
  • FIG.26 Second implementation when driving a DV LCD panel with a horizontally long pixel configuration 6 is a timing chart (A to F) for explaining the operation (mainly on the input side) in the display mapping input mode of the data driver according to the embodiment.
  • FIG. 27 is a timing chart for explaining the operation (mainly on the input side) in the normal display input mode of the data driver according to the second embodiment when driving an SV liquid crystal panel with a vertically or horizontally long pixel arrangement configuration. (A to F).
  • FIG. 28 is a timing chart for explaining the operation (mainly on the output side) in the independent output mode of the data driver according to the second embodiment when driving an SV liquid crystal panel having a vertically long pixel arrangement configuration. ⁇ I).
  • FIG. 29 is a timing chart for explaining the operation (mainly on the output side) in the time division output mode of the data driver according to the second embodiment when driving an SV liquid crystal panel having a horizontally long pixel arrangement configuration. ⁇ I).
  • FIG. 30 is a diagram (A to C) showing a pixel arrangement of a conventional dual view liquid crystal display device. Explanation of symbols
  • TFT Thin film transistor
  • FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to the first embodiment of the present invention.
  • This liquid crystal display device is different from each other in two areas where viewpoints can be arranged.
  • Display device that is, a DV (dual view) liquid crystal display device that can display different images when looking at a predetermined angle force tilted left or right on the display screen.
  • the display control circuit 200 includes a data driver 300 as a data signal line driving circuit, a gate driver 400 as a scanning signal line driving circuit, and an active matrix liquid crystal panel 600.
  • the image displayed when looking at the left force toward the display screen is called “left image”, and the image displayed when looking at the right force is called “right image” t t.
  • a liquid crystal panel 600 as a display unit in the liquid crystal display device includes image data Dvl for displaying a left image and image data for displaying a right image from a predetermined external video source (CPU or the like). Dv2 and a control signal TS for controlling the operation timing are received. Note that the original image for displaying the left image and the right image on the liquid crystal panel 600 is displayed in the horizontal direction so that it is displayed correctly by being displayed only in the odd or even columns in the display column of the liquid crystal panel 600. It is assumed that it has been compressed (halved) in the (display line direction). For example, when the display screen is composed of 640 columns and 480 rows, the original image for displaying the left image and the right image is composed of 320 columns and 480 rows.
  • the liquid crystal panel 600 includes three scanning signal lines Lg that are three times the number of horizontal scanning lines m (3m) in the image represented by the image data Dvl and Dv2, and the 3m scanning signal lines Lg. 2n data signal lines Ls intersecting with each other, and 3m x 2n subpixels formed corresponding to the intersections of these 3m scanning signal lines Lg and 2n data signal lines Ls, respectively Part Ps (l, l) to Ps (3m, 2n). Further, the liquid crystal panel 600 is provided in common to the pixel electrodes included in the sub-pixel forming portions Ps (l, l) to Ps (3m, 2n), and is opposed to the pixel electrodes with the liquid crystal layer interposed therebetween. Are provided with a common electrode.
  • 3m ⁇ 2n sub-pixel forming portions Ps (l, l) to Ps (3m, 2n) in the liquid crystal panel 600 are adjacent to the extending direction of the data signal line Ls, that is, the column direction.
  • the R subpixel, the G subpixel, and the B subpixel are arranged in a matrix in units of three subpixel formation portions, and the color image to be displayed on the liquid crystal panel 600 by the three subpixel formation portions.
  • Each pixel of the left image represented by the image data Dvl and the right image represented by the image data Dv2 (hereinafter referred to as one pixel of the image to be displayed).
  • the corresponding three sub-pixel forming portions are indicated by “pixel forming portion” t ⁇ and the symbol “Pix”).
  • the display control circuit 200 receives the image data Dvl, Dv2 and the timing control signal TS sent from the outside, and converts the image signals corresponding to the image data Dvl, Dv2 respectively to the digital image signal DV1, DV1.
  • Data start pulse signal DSP, data clock signal DCK, latch strobe signal LS, gate start pulse signal GS P, and gate to output as DV2 and control the timing of displaying images on LCD panel 600 Outputs various signals including clock signal GCK.
  • the digital image signals DV1, DV2, the data start pulse signal DSP, the data clock signal DCK, and the latch strobe signal LS are data.
  • the gate start pulse signal GSP and the gate clock signal GCK are supplied to the driver 300, and are supplied to the gate dryer OO.
  • the display control circuit 200 generates a polarity switching control signal for AC drive of the liquid crystal panel 600 based on the clock signal and the like, and this is used as the data driver 300 and a common electrode drive circuit (not shown). Supply. Since the polarity switching signal and the AC driving based on the polarity switching signal are not directly related to the present invention, the description thereof will be omitted below.
  • the data driver 300 generates an analog voltage for driving the liquid crystal panel 600 based on the digital image signals DV1, DV2, the data clock signal DCK, the data start pulse signal DSP, the latch strobe signal LS, and the like. Signals D (l), D (2),..., D (2n) are generated and applied to 2n data signal lines Ls in the liquid crystal panel 600, respectively.
  • the gate dry 400 is applied to each scanning signal line to sequentially select the scanning signal lines in the liquid crystal panel 600 by 1Z3 horizontal scanning period. Generates scanning signals G (l), G (2), G (3), ..., G (3m) to be generated, and active scans to select each of all scanning signal lines in turn. The application of the ⁇ signal to each scanning signal line is repeated with one vertical scanning period as a cycle.
  • the data signals D (1) to D (2n) based on the digital image signals DV1 and DV2 are applied to the data signal line Ls, and the scanning signals G (1) to G (3m) is applied to the scanning signal line Lg.
  • a common voltage signal is applied to the common electrode by a common electrode drive circuit (not shown).
  • the liquid crystal panel 600 changes the light transmittance by applying a voltage corresponding to the digital image signal DV1, DV2 to the liquid crystal layer, and receives the image data Dvl, Dv2 received from the external video source
  • the left and right images represented by are displayed. Depending on the viewing angle of the display screen, one of these images appears clearly bright and the other appears dark or completely invisible.
  • the liquid crystal panel 600 includes 2n data signal lines Ls connected to the data driver 300 and 3m scanning signal lines Lg connected to the gate driver 400, and the 2n data signal lines Ls and 3m
  • the scanning signal lines Lg are arranged in a grid pattern so that each data signal line Ls and each scanning signal line Lg intersect each other. Then, 3m ⁇ 2n sub-pixel forming portions Ps (1, l) to Ps (3m, 2n) are provided corresponding to the intersections of the 2n data signal lines and the 3m scanning signal lines Lg, respectively. ing.
  • each pixel of the color image to be displayed by the liquid crystal panel 600 is in the column direction (the data signal line extends).
  • 3m x 2n sub-pixel forming parts Ps (l in the liquid crystal panel 600 are formed by a pixel forming part Pix consisting of three sub-pixel forming parts of R sub-pixel, G sub-pixel and B sub-pixel adjacent to each other in the direction).
  • , l) to Ps (3m, 2n) are arranged in a matrix with these three subpixel formation units as units (see Fig. 1).
  • each sub-pixel forming portion Ps (i, j) has a source terminal connected to the data signal line Ls that passes through the corresponding intersection and a scanning signal that passes through the corresponding intersection.
  • Thin film transistor with gate terminal connected to line Lg hereinafter referred to as ⁇ TFT 10
  • the pixel electrode Ep connected to the drain terminal of the TFT 10
  • the common electrode (also referred to as “counter electrode”) Ec provided and the pixel electrode Ep provided in common to the 3m ⁇ 2n sub-pixel formation portions Ps (l, l) to Ps (3m, 2 ⁇ )
  • the common electrode Ec and not shown !, color filters, various optical compensation films (polarizing plates, etc. ) Is a CF substrate.
  • the liquid crystal capacitance Clc formed by the pixel electrode Ep, the common electrode Ec, and the liquid crystal layer sandwiched between them constitutes a pixel capacitance for holding a voltage corresponding to sub-pixel data.
  • an auxiliary capacitor is provided in parallel with the liquid crystal capacitor Clc, which should surely hold the voltage in the pixel capacitor.
  • the auxiliary capacitor is not directly related to the present invention, its description and illustration are omitted.
  • FIG. 3 is a cross-sectional view schematically showing the structure of the liquid crystal panel 600 as described above.
  • the liquid crystal panel 600 includes a pair of transparent insulating substrates, a TFT substrate 66 and a CF substrate 56, and a liquid crystal layer 60 sandwiched between the TFT substrate 66 and the CF substrate 56.
  • the viewpoint (eyepoint) should be placed in front ( Display the image represented by the above image data Dvl and Dv2
  • Polarizing plates 68 and 55 are attached to the outer surfaces of the TFT substrate 66 and the CF substrate 56 in the liquid crystal panel 600 (the main surface opposite to the side where the liquid crystal layer 60 is disposed), respectively.
  • the data signal lines Ls and And the scanning signal line Lg On the inner surface of the TFT substrate 66 (the main surface on the side where the liquid crystal layer 60 is disposed), the TFT circuit section 64 including the TFT 10 of each of the sub-pixel forming sections Ps (l, l) to Ps (3m, 2n) and the pixel electrode Ep, are formed on the inner surface of the CF substrate 56.
  • a color filter 58 configured to correspond to the arrangement shown in FIG.
  • a transparent parallax barrier substrate 52 is disposed outside the CF substrate 56, and the parallax barrier layer 54 including the parallax barrier 54b is formed on the inner surface of the parallax barrier substrate 52 with a light-shielding metal or It is formed from greaves.
  • the parallax barrier layer 54 has a slit 54s, and selectively blocks light that passes through the TFT substrate 66, the liquid crystal layer 60, the CF substrate 56, and the like from the knock light and moves forward.
  • a parallax is generated for an image formed by the sub-pixel forming portions Ps (l, l) to Ps (3 m, 2n) realized by the liquid crystal layer 60, the color filter 58, and the like. That is, the parallax barrier layer 54 has a parallax on the image formed by the sub-pixel forming portions Ps (l, l) to Ps (3m, 2n) so that different images are displayed for at least two viewpoints. It functions as a parallax generator that generates
  • FIG. 4 schematically shows the configuration of the liquid crystal panel 600 as described above.
  • FIG. 4A is a plan view showing the configuration for a dual-view display (hereinafter abbreviated as “DV display”).
  • FIG. 4B is a cross-sectional view showing a configuration for DV display, and corresponds to a cross-sectional view taken along line XX in FIG. 4A.
  • FIG. 4 (A) and FIG. 4 (B) the configuration and operation for realizing DV display in the present embodiment will be described.
  • Ps (l, l) to Ps (3m, 2n) realized by the TFT circuit portion 64, the liquid crystal layer 60, the color filter 58, etc. without distinction.
  • each subpixel 70 is any of the R subpixel, the G subpixel, and the B subpixel.
  • the subpixel 70 with “R1” is an R subpixel for forming the left image
  • the subpixel 70 with “Gr” is the G subpixel for forming the right image.
  • each sub-pixel 70 is arranged such that its longitudinal direction is the row direction (direction in which the scanning signal line Lg extends),
  • the sub-pixel forming portions Ps (l, 1) to Ps (3m, 2n) the sub-pixels 70 constituting each column are only sub-pixels for forming one of the left image and the right image. Consists of. Then, a column composed of only sub-pixels for forming the left image and a column composed of only the sub-pixels for forming the right image are alternately arranged.
  • the parallax barrier layer 54 has slits 54 s extending in the direction perpendicular to the longitudinal direction of each sub-pixel 70, that is, the column direction (direction in which the data signal line Ls extends), and one slit 54 s for every two columns of the sub-pixel 70.
  • the distance dl between the parallax barrier 54b and the sub-pixel 70 corresponds to the distance between the color filter 58 and the parallax barrier 54b shown in FIG.
  • each subpixel 70 is arranged so that its longitudinal direction is the row direction (horizontal pixel arrangement configuration), and the slit 54s in the parallax barrier layer 54 is perpendicular to the longitudinal direction of each subpixel.
  • the slit 84s extends in parallel to the longitudinal direction of each subpixel 90 even if the distance dl between the parallax nolia 54b and the subpixel 70 is increased, the left and right images are projected. It is hard to produce. Therefore, according to the above configuration, the left and right images are reflected without requiring high processing accuracy. Can be prevented.
  • the distance d2 between the viewing barrier 84b and the subpixel 90 is about 50 ⁇ , whereas the thickness of the glass as the CF substrate 56 is about 700.
  • special processing such as polishing of the glass substrate is required when manufacturing a conventional DV liquid crystal panel.
  • the above-described configuration in the present embodiment in addition to not requiring high machining accuracy as high as conventional, such special work is unnecessary and reduced, so that the manufacturing cost is suppressed. be able to.
  • the number of scanning signal lines Lg is three times that of the conventional vertical pixel arrangement (Fig. 30).
  • the number of data signal lines Ls is 1Z3 in the case of the conventional vertically long pixel arrangement configuration. It can be.
  • the data driver 300 in this embodiment needs to generate data signals D (1) to D (2n) so as to enable DV display (dual view display) according to the configuration of the liquid crystal panel 600. .
  • DV display dual view display
  • FIGS. 5A and 5B show the format of input data represented by a digital image signal to be supplied to the data driver 300.
  • FIG. 5A the left image data DaL and the right image data DaR are simultaneously supplied to the display control circuit 200 as image data Dvl and Dv2, and the image data
  • the digital image signal DV1 which is the signal of the left image represented by Dv 1 and the digital image signal DV2 which is the signal of the right image represented by image data Dv2 are simultaneously input to the data driver 300 (hereinafter this input format is referred to as “ DV2 simultaneous input format ”).
  • this input format is referred to as “ DV2 simultaneous input format ”).
  • image data in a format in which the left image data DaL and the right image data DaR are arranged in the row direction (horizontal direction) (hereinafter referred to as “combined image data” t, ), And an image signal represented by the combined image data may be input to the data driver 300 (hereinafter, this input format is referred to as “DV display mapping input format”).
  • This combined image data is a matrix of m rows 2 X 3n columns 2 x 3 x m x n sub-pixel data power image data arranged in a format, where the first half of each row consists of sub-pixel data representing the left image and the second half consists of sub-pixel data representing the right image .
  • the DV display mapping input type such 2 ⁇ 3 ⁇ m ⁇ n sub-pixel data are sequentially input to the data driver 300 as one digital image signal DV.
  • the left image data DaL and the right image data DaR are data with the same contents
  • the normal display that is not DV display is used regardless of whether the input format is DV2 simultaneous input format or DV display mapping input format. (The same image is displayed for any viewpoint in front of the display screen).
  • FIG. 6 is a block diagram showing a configuration example of a data driver 300 that can support both the DV2 system simultaneous input format and the DV display mapping input format.
  • the data driver 300 includes an input side selector 302 as a first connection switching circuit and six line memories functioning as a serial-parallel converter, that is, a left image red line memory. 304R1, left line green line memory 304G1, left line blue line memory 304B 1, right line red line memory 304Rr, right line green line memory 304Gr and right line blue line memory 304Br, and sub-line for one display line
  • a latch circuit 306 as a holding means for holding a signal indicating pixel data
  • an output side selector 308 as a second connection switching circuit
  • a DZA conversion circuit 310 a DZA conversion circuit 310
  • an output buffer 312 are provided.
  • the digital image signal DV1 representing the left image is the red input signal R—Lin for the left image, the green input signal G—Lin, and the blue input signal B—Lin.
  • the red input signal R—Rin, the green input signal G—Rin, and the blue input signal B—Rin for the right image are input from the display control circuit 200 to the input side selector 302, respectively.
  • the input side selection control signal Sa is given from the display control circuit 200 to the input side selector 302 as a control signal for selecting the input format, and the output side selection control is used as a control signal for switching the output signal in a time division manner.
  • Signals Sb and Sc are supplied from the display control circuit 200 to the output side selector 308.
  • the latch strobe signal LS is supplied from the display control circuit 200 to the latch circuit 306, and a plurality of reference voltages are supplied to the DZA conversion circuit 310 as well as a reference voltage generating circuit power (not shown).
  • the input side selection control signal Sa is also given to the above line memos U304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br. Also serves as an in-memory enable signal.
  • the input-side selector 302 includes the first input terminal group for inputting the input signals R—Lin, G—Lin, and B—Lin that constitute the digital image signal DV1 representing the left image.
  • the first output terminal group 1Y1, 1Y2, 1Y3 for outputting image signals to the line memory 304R1, 304G1, 304B1 for the left image and the image signals to the line memories 304Rr, 30 4Gr, 304Br for the right image, respectively.
  • the second output terminal groups 1Y4, 1Y5, and 1Y6 are respectively provided for outputting.
  • FIG. 7A shows a truth table showing the operation of the input side selector 302. This figure 7
  • the input side selector 302 uses the first and second input terminal groups A1 to F1 as the first image signals as they are. And output from the second output terminal group 1Y1 to 1Y6.
  • the input-side selector 302 sends the image signals given to the first input terminal groups A1 to C1 to the second output terminal groups 1Y4 to: The second input terminal group D1 to F1 is not used.
  • "X" indicates that the output signal is indefinite or invalid.
  • the input side selector 302 receives a signal representing the left image and the right image in the DV2 system simultaneous input format (hereinafter, the operation mode at this time is referred to as "two systems simultaneous input mode").
  • the input side selection control signal Sa as shown in Fig. 8 (B) is given and signals representing the left image and the right image are received in the DV display mapping format (hereinafter, the operation mode at this time is displayed as ⁇ Display In the “mapping input mode”, an input side selection control signal Sa as shown in FIG.
  • the input-side selector 302 operates in the two-system simultaneous input mode, and therefore, the input-side selection control signal Sa as shown in FIG. Given by.
  • the output side selector 308 has 2n block power (2n is the number of data signal lines Ls), and each block receives digital signals A2, B2, and C2 corresponding to three sub-pixel data. According to the truth table shown in (B), select one of those signals A2, B2, C2 Output as the Y signal. Therefore, when the output-side selector 308 receives the output-side selection control signals Sb and Sc as shown in FIG. 9B, the digital image signal input from the latch circuit 306 is shown in FIG. 9C. In this way, the output side selection control signals Sb and Sc are output in a time-sharing manner according to switching.
  • the switching order of the output side selection control signals Sb and Sc for the time division output corresponds to the horizontally long pixel arrangement configuration shown in FIGS.
  • the output side selection control signals Sb and Sc are switched every 1Z3 period of each horizontal scanning period, and the switching timing is gated as shown in FIGS. 9 (D) to 9 (F). This is synchronized with the selection of the scanning signal line Lg by the dryino O 0.
  • the input-side selector 302 is supplied with the input-side selection control signal Sa shown in FIG. 10 (A) and two digital image signals DV1, DV2 representing the left image and the right image.
  • the input side selector 302 receives the digital image signal R—Lin, G—Lin, B—Lin, R—Rin, G as shown in FIG.
  • FIGS. 10C and 10D show the input when the digital image signal corresponding to the second line of the image to be displayed (the left image and the right image) is input to the input side selector 302.
  • the line memo U304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br holds the digital image signal corresponding to the first line of the image to be displayed. .
  • Line memos U304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br are digital image signals R-Lin, G-Lin, B_Lin, R- Rin, G—Rin, B—Rin are output in parallel for each line of the image to be displayed.
  • the three line memories 304R1, 304G1, and 304B1 input digital image signals representing the left image serially in units of pixels and output them in parallel for each row of the left image.
  • the other three line memories 304Rr, 304Gr, and 304Br input the digital image signal representing the right image serially in pixel units, one line at a time for the right image. It functions as the second series-parallel variable that outputs in parallel.
  • the latch circuit 306 receives the digital image signal for one line output from the line memories 304R1, 304 Gl, 304B1, 304Rr, 304Gr, and 304Br to the normal output, and the latch shown in FIG. Latching based on the strobe signal LS, the digital image signal for one row is output as shown in Fig. 10 (F) and Fig. 10 (G) (Fig. 10 (F) and Fig. 10 (G) are output) This shows the digital image signal output to each of the blocks I and II of the side selector 308).
  • the latch circuit 306 is connected to three sub-pixel forming portions (R sub-pixel, G sub-pixel, and B sub-pixel) for forming one pixel of an image to be displayed during one horizontal scanning period.
  • R sub-pixel, G sub-pixel, and B sub-pixel sub-pixel forming portions
  • a digital image signal for one row is input from the latch circuit 306 to the output-side selector 308 (FIGS. 11D and 11E), and FIG. Output side selection control signals Sb and Sc shown in FIG.
  • the values of the output side selection control signals Sb, Sc are switched every 1Z3 horizontal scanning period in each horizontal scanning period.
  • the output-side selector 308 should capture the three sub-pixel forming portions (R sub-pixel, G sub-pixel and B sub-pixel) that form each pixel in one row of the image to be displayed (left image and right image).
  • the signal Y is output in a time division manner in one horizontal scanning period (1H period) (FIG. 11 (F) and FIG. 11 (G) are output side selectors).
  • the digital image signals respectively output from the blocks I and II of FIG. The order in this time-division output corresponds to the horizontally long pixel arrangement configuration shown in FIGS.
  • the output side selector 308 performs the sequential selection of the scanning signal line Lg in the liquid crystal panel 600. In conjunction with this, the output signal is switched between the same pixel signal group.
  • the eight conversion circuit 310 converts the digital image signal Y output from the output side selector 308 (each block thereof) into an analog voltage signal based on a plurality of reference voltages supplied from a reference voltage generation circuit (not shown). Convert.
  • the analog voltage signal thus obtained is output from the data driver 300 as data signals D (1) to D (2n) for one row via an output buffer 312 configured by a voltage hollow or the like as impedance conversion means. It is output as shown in Fig. 11 (H) and Fig. 11 (1).
  • the DZA conversion circuit 310 and the output buffer 312 constitute a signal generation output circuit that generates and outputs a data signal D (j) based on the digital image signal Y from the output side selector 308.
  • the signal generation output circuit constitutes a signal generation circuit for the data signal together with the latch circuit 306 and the output side selector 308.
  • the liquid crystal non-channel 600 ⁇ ! /, And the data signal line Ls connected to the sub-pixel forming portion where each pixel of the left image is to be formed are connected to the same pixel signal group xRy. — L, xGy_L, xBy—L
  • the data signal is applied in a time-sharing manner, and the same pixel signal group xRy—R is connected to the data signal line Ls connected to the sub-pixel forming part that should form each pixel of the right image.
  • the TFT 10 becomes conductive, and the data passes through the intersection corresponding to the sub-pixel formation portion P s (i, j).
  • the data signal D (j) of the signal line Ls is captured as subpixel data, and a voltage corresponding to the subpixel data is held in the pixel capacitor Clc.
  • the light transmittance of the liquid crystal layer is controlled based on the subpixel data taken into each subpixel formation portion Ps (i, j), and this is combined with the action of the parallax barrier layer 54 as the parallax generation portion.
  • dual view display is realized.
  • the input-side selector 302 is supplied with the input-side selection control signal Sa shown in FIG. 12 (A), and the left image data DaL and the right image data as shown in FIG. 5 (B).
  • One digital image signal DV corresponding to combined image data in the form of DaR arranged in the row direction is input terminal group Al, Bl, C1 as digital image signals R_Lin, G_Lin, B_Lin shown in Fig. 12 (B) Power is input serially in ij pixel units.
  • the input-side selector 302 in the first half of each horizontal scanning period, digital image signals xR y_L, xGy_L, xBy— L is output from the first output terminal group 1Y1 ⁇ : LY3 is supplied to the line memories 304R1, 304G1, 304B1, respectively, and in the second half of each horizontal scanning period, digital image signals representing the right image xRy—R, xGy_R, xBy—R are output from the second output terminal group 1 Y4 ⁇ : LY6, respectively, and supplied to the line memories 304Rr, 304Gr, 304Br.
  • the line memories 304R1, 304G1, 304B1 capture and hold the digital image signal supplied from the input side selector 302 in the first half of each horizontal scanning period
  • the line memories 304Rr, 304Gr, 304Br In the second half of the scanning period, the digital image signal supplied from the input side selector 302 is captured and held.
  • FIGS. 12B and 12C show the signals on the input side and the output side when the digital image signal corresponding to the second line of the image to be displayed is input to the input side selector 302.
  • the line memo U304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br is the image to be displayed Holds the digital image signal corresponding to the first line.
  • “X” indicates an invalid or indefinite signal value.
  • the digital image signals xRy—L, xGy_L, and xBy—L representing the left image are line memories 304R1, 304G1, 304B1, and the right image, each of which is ij pixel-powered.
  • Digital image signals xRy— R, xGy_R, xBy— R are serially input in units of subpixels, and line memories 304Rr, 304Gr, 304Br output these image signals in parallel for each row of the image to be displayed. To do.
  • the three line memories 304R1, 304G1, and 304B1 input digital image signals representing the left image serially in units of pixels and correspond to one row of the left image.
  • the other three line memories 304Rr, 304 Gr, and 304Br function as the first series-parallel variable ⁇ output to the parallel, and input the digital image signal representing the right image serially in pixel units. It functions as the second series-parallel variation that outputs the image one line at a time in parallel.
  • the latch circuit 306 receives one line of digital image signals output from the line memory 304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br force to the NORENORE. Based on the latch strobe signal LS shown in 12 (D), the digital image signal for one row is output as shown in FIGS. 12 (E) and 12 (F).
  • the output side selector 308, the DZ A conversion circuit 310, and the output buffer 312 operate in the same manner as in the two-system simultaneous input mode described above (see FIG. 11), and the same data signal D (1) to D (2n) is output from the data driver 300.
  • the data signal line Ls connected to the sub-pixel forming portion where each pixel of the left image is to be formed is time-divided into the same pixel signal group xRy—L, xGy_L, xBy—L.
  • the data signal is applied to the data signal line Ls connected to the sub-pixel forming part where each pixel of the right image is to be formed, and the data signal is applied to the same pixel signal group xRy—R, xGy_R, xBy—R in a time division manner.
  • the horizontal pixel arrangement configuration is higher than the conventional vertical pixel arrangement configuration and can prevent the left and right images from being reflected without requiring processing accuracy.
  • the number of scanning signal lines is three times as many as the number of display rows.
  • the conventional vertical pixel arrangement configuration (Fig. 30) is required.
  • the number of scanning signal lines Lg is three times as large as that of the liquid crystal panel 600.
  • the three sub-pixel forming portions are connected to the same data signal line Ls (FIG. 1).
  • a data signal is applied to the data signal line Ls connected to the sub-pixel forming portion that should form each pixel of the left image in a time division manner for the same pixel signal group xRy—L, xGy_L, xBy—L.
  • the input data format is the DV2 system simultaneous input format (FIG. 5 (A)) and the DV display.
  • the DV display LCD panel 600 (with a horizontal pixel arrangement with a reduced number of data signal lines to suppress a decrease in aperture ratio) Data signal line Ls) can be driven.
  • the output-side selector 308 for time-division output for the same pixel signal group is arranged in front of the DZA conversion circuit 310.
  • the output-side selector The 308b may be constituted by an analog switch or the like, and may be arranged at the subsequent stage of the DZA conversion circuit 310 as shown in FIG.
  • the configuration in which the output side selector 308 is arranged in front of the DZA conversion circuit 310 has the advantage that the scale of the DZA conversion circuit can be reduced.
  • the block has only one terminal that outputs a signal Y selected from the same pixel signal group A2, B2, and C2. Instead, the block has an output selector 308 as shown in FIG. Each block may output three signals Yl, Y2, Y3 from three output terminals. In this case, as shown in Fig. 16 (F) and Fig. 16 (G), the three signals Yl, Y2, Y3 from the three output terminals of each block in the output side selector 308 are the same signal.
  • the three output terminals in the data driver 300 correspond to one data signal line Ls in the liquid crystal panel 600, and the three signals Rj, Gj, Bj as the data signal D (j) are substantially the same signal. It is. Therefore, the three output terminals from which the signals Rj, Gj, and Bj are output are connected to one data signal line (jth data signal line) Ls in the liquid crystal panel 600. As a result, it is possible to improve reliability by providing redundancy in the connection between the data signal line Ls and the data driver 300 in the liquid crystal panel 600.
  • the input side selector 302 is connected to the first output terminal group 1Y1 to: LY3 and the second output terminal group 1Y4 to which the digital image signals input from the first input terminal groups A1 to C1 are to be output.
  • the data driver 300 can also be used as a data driver in a normal SV liquid crystal display device with a vertically long pixel arrangement (in this case, input The second input terminal group D1 to F1 of the side selector 302 is not used).
  • a configuration in which the parallax barrier layer 54 as a parallax generation unit is arranged on the front side of the liquid crystal panel 600, that is, a front parallax barrier method is adopted (FIG. 3).
  • a rear parallax barrier method (see, for example, FIG. 4 of Patent Document 1) may be employed.
  • the liquid crystal display device is a so-called driver (full) monolithic type or partial driver monolithic type in which all or part of various drive circuits and the like are integrally formed on a glass substrate together with a pixel circuit. It may be a liquid crystal display device. Also, above In the embodiment, the liquid crystal panel in which the pixel electrode and the counter electrode are formed on different substrates has been described as an example. However, these electrode structures are not limited to the same substrate, for example, the IPS On Plane Switching) method. Further, a pixel electrode and a counter electrode may be formed. Furthermore, the present invention is not limited to a liquid crystal display device, but can be applied to an active matrix type DV display device other than a liquid crystal display device.
  • a DV display device that displays different images for two users is taken as an example, but binocular parallax is given to one user based on the same principle.
  • the present invention is also applicable to a display device that generates a three-dimensional display by generating the above.
  • a display device other than a DV display device when a pixel of a color image is formed by an R subpixel, a G subpixel, and a B subpixel which are in a horizontally long pixel arrangement configuration and are adjacent in the column direction. If so, the present invention can be applied.
  • the data driver according to this embodiment can be used not only for driving a liquid crystal panel of a DV liquid crystal display device (hereinafter referred to as “DV liquid crystal panel”), but also for an SV liquid crystal display device. It can also be used to drive a liquid crystal panel (hereinafter referred to as “SV liquid crystal panel”).
  • the expressions “left image” and “right image” are the two images that should be displayed on the DV liquid crystal display panel when driving the DV liquid crystal panel, as in the first embodiment. Means.
  • the expressions “two-line simultaneous input mode” and “display mapping input mode” are also used in the same meaning as in the first embodiment, and the SV LCD panel is driven.
  • the operation mode when the data driver receives the image signal in the input format is called ⁇ normal display mode '' .
  • ⁇ normal display mode '' the operation mode when the data driver receives the image signal in the input format (general input format for normal display, not DV display)
  • ⁇ normal display mode '' the operation mode when the data driver receives the image signal in the input format
  • ⁇ normal display mode '' the operation mode when the data driver receives the image signal in the input format
  • ⁇ normal display mode '' the operation mode when the data driver receives the image signal in the input format
  • ⁇ normal display mode '' the operation mode when the data driver receive
  • FIG. 17 is a block diagram showing the configuration of the data driver according to this embodiment.
  • This data driver is basically the same as the configuration shown in FIG. 14 as the configuration example of the data driver 300 in the first embodiment, and therefore, the same reference numerals are assigned to the same or corresponding parts.
  • other components and signals in the liquid crystal display device to which the data driver according to the present embodiment should be used are also referred to as “display control circuit 200” or “digital image signal DV1 or DV2,” for example.
  • display control circuit 200 or “digital image signal DV1 or DV2,” for example.
  • the data driver includes an input-side selector 302 as a first connection switching circuit and six line memories functioning as a series-parallel shift, that is, a left image red line.
  • a latch circuit 306 as a holding means for holding a signal indicating sub-pixel data, an output side selector 308 as a second connection switching circuit, an eight-eight conversion circuit 310, and an output buffer 312 are provided. .
  • the digital image signal DV1 representing the left image is a red input signal R-Lin for the left image, a green input signal G-Lin, and a blue input signal B-Lin
  • the digital image signal DV1 representing the right image is
  • the red input signal R—Rin, green input signal G—Rin, and blue input signal B—Rin of the right image are input from the display control circuit 200 to the input side selector 302, respectively.
  • the input side selection control signals SI and S2 are given from the display control circuit 200 to the input side selector 302 as control signals for selecting the input format, and control for enabling time-division switching of the output signals is possible.
  • Output side selection control signals S3 and S4 are given from the display control circuit 200 to the output side selector 308 as signals. Further, the latch strobe signal LS is supplied from the display control circuit 200 to the latch circuit 306, and a plurality of reference voltages (not shown) are supplied to the DZA conversion circuit 310.
  • the input side selection control signals SI and S2 are also provided with the above line memos U304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br, and also serve as enable signals for these line memories.
  • the input-side selector 302 is a first input for inputting the input signals R—Lin, G—Lin, and B—Lin that constitute the digital image signal DV1 representing the left image.
  • Terminal group Al, Bl, CI and second input terminal group Dl, El, F for inputting the input signals R — Rin, G— Rin, B— Rin that constitute the digital image signal DV2 representing the right image, respectively 1 and the first output terminal group 1Y1, 1Y2, 1Y3 for outputting image signals to the line memories 304R1, 304G1, 304B1 for the left image and the line memories 304Rr, 30 4Gr, 304Br for the right image, respectively.
  • a second output terminal group 1Y4, 1Y5, 1Y6 for outputting image signals is provided.
  • FIG. 18A shows a truth table showing the operation of the input side selector 302.
  • the input side selector 302 receives the second image signals given to the first input terminal groups A1 to C1, respectively. Output terminal group 1Y4 to 1Y6, and the second input terminal group D1 to F1 are not used.
  • “X” indicates that the output signal is indefinite or invalid.
  • the input-side selector 302 receives a signal representing the left image and the right image in a DV2 system simultaneous input format (see FIG. 30).
  • the input side selection control signals SI and S2 shown in Fig. 19 (B) are given, and the signals representing the left and right images are displayed in DV display mapping format.
  • input side selection control signals SI and S2 shown in Fig. 19 (C) are given.
  • the input side selection control signals SI and S2 shown in FIG. 19D are given.
  • the input side selection control signals SI and S2 shown in Fig. 19 (E) are given.
  • the output side selector 308 also has 2n blocking power (2n is the number of data signal lines Ls), and each block has three input terminals and three output terminals. Each block receives the digital signals A2, B2, and C2 corresponding to the three subpixel data, and the true signals shown in FIG. According to the reasoning table, select the medium power of the signals A2, B2, and C2 for the signals to be output from the three output terminals, and output the three output terminal forces as digital signals Yl, Y2, and Y3. .
  • the output side selector 308 When driving a liquid crystal panel with a vertically long pixel arrangement (whether to drive either a DV liquid crystal panel or an SV liquid crystal panel), the output side selector 308 includes the output side selector 308 shown in FIGS. ), The output side selection control signals S3 and S4 shown in Fig. 20 (B) are given so that the three signals Yl, Y2 and Y3 are output independently from each block.
  • the operation mode in which three signals Yl, Y2, and Y3 are output independently for each block force is called “independent output mode”).
  • the output side selector 308 is shown in FIGS. 21 (C) to 21 (E).
  • the signals Yl, Y2, Y3 output from each block are the same and can be switched sequentially between the three signals A2, B2, C2, that is, the three signals A2, B2, C2
  • Output side selection control signals S3 and S4 shown in Fig. 21 (B) are given so that the signals are output in a time-sharing manner within one horizontal scanning period (hereinafter, signals Yl output from each block in this way).
  • signals Y2 and Y3 are the same, and the operation mode that can be switched sequentially between the above three signals A2, B2, and C2 is called “time division output mode”.
  • each of the three signals Rj, Bj, Gj is output as the same data signal D (j), and each data signal D (j) is the above three signals.
  • This signal corresponds to the time-division output of A2, B2, and C2.
  • the output side selection control signals S3 and S4 are switched every 1Z3 period of each horizontal scanning period as shown in FIG. 21B, and the timing of the switching is the scanning signal line Lg by the gate driver 400. Is synchronized with the selection.
  • connection by signal wiring between the line memories 304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br and the latch circuit 30 6 is as follows. It is different from the embodiment. That is, in this embodiment, a sub-pixel forming unit (any one of the R sub-pixel, G sub-pixel, and B sub-pixel) that forms the left image pixel corresponding to the vertically long pixel arrangement configuration shown in FIG. 30 in the DV liquid crystal panel.
  • Signal corresponding to the data to be captured (X Ry_L, xGy_L, xBy—
  • the input-side selector 302 is provided with the input-side selection control signals SI and S2 shown in FIG. 22 (A), and two digital image signals DV1 and DV2 representing the left image and the right image are shown in FIG.
  • Digital image signals R-Lin, G-Lin, B-Lin, R_Rin, G-Rin, B-Rin shown in (B) are serially input in units of sub-pixels.
  • the input side selector 302 receives the control signal and the image signal as shown in FIG.
  • the digital image signal R—Lin, G—Lin, B—Lin, R—Rin, G — Rin, B— Rin is output terminal group 1Y1 ⁇ : LY6 force is also output and supplied to line memories 304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br, respectively.
  • 22B and 22C show the input side when the digital image signal corresponding to the second line of the image to be displayed (the left image and the right image) is input to the input side selector 302.
  • the line memo U304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br holds the digital image signal corresponding to the first line of the image to be displayed. .
  • the line memos U304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br are digital image signals R-Lin, G-Lin, B_Lin, R- Rin, G—Rin, B—Rin are output in parallel for each line of the image to be displayed. That is, the three line memories 304R1, 304G1, and 304B1 function as a first serial / parallel converter that serially inputs a digital image signal representing the left image in units of pixels and outputs the left image in parallel for each row.
  • the other three line memories 304Rr, 304Gr, and 304 Br input the digital image signal representing the right image serially in pixel units and output the right image in parallel for each row of the right image.
  • the line memories 304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br and the latch circuit 306 are connected as shown in FIG. 17 as described above. For this reason, the latch circuit 306 receives the digital image signals for one line of the left image and the right image output from the line memories 304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br force to the NORENORE, and FIG. Latch strobe signal LS shown in Fig. 22 (E) and Fig. 22 (F). To) alternately. 22E and 22F show digital image signals to be input from the latch circuit 306 to the blocks I and II of the output side selector 308, respectively. In this way, the latch circuit 306 holds the three digital image signals to be input to each block of the output side selector 308 for one horizontal scanning period and outputs them as signals A2, B2, and C2.
  • the output side selector 308 receives the digital image signal for one row of the left and right images from the latch circuit 306 as described above (FIGS. 23D and 23E) and FIG. Output side selection control signals S3 and S4 shown in (C) are given.
  • the signals A2, B2, and C2 input to the respective blocks of the latch circuit 306 are output as signals Yl, Y2, and Y3 as they are and input to the D ZA conversion circuit 310.
  • the input-side selector 302 is provided with the input-side selection control signals SI and S2 shown in FIG. 24 (A), and the left image data DaL and the right image data DaR as shown in FIG. 5 (B).
  • One system of digital image signals DV corresponding to combined image data arranged in the row direction is converted into digital image signals R-Lin, G-Lin, B-Lin shown in Fig. 24 (B). , Input serially from C1 in sub-pixel units.
  • the input-side selector 302 in the first half of each horizontal scanning period, digital image signals xR y_L, xGy_L, xBy— L is output from the first output terminal group 1Y1 ⁇ : LY3 is supplied to the line memories 304R1, 304G1, 304B1, respectively, and in the second half of each horizontal scanning period, digital image signals representing the right image xRy—R, xGy_R, xBy—R are output from the second output terminal group 1 Y4 ⁇ : LY6, respectively, and supplied to the line memories 304Rr, 304Gr, 304Br.
  • the line memories 304R1, 304G1, 304B1 capture and hold the digital image signal supplied from the input side selector 302 in the first half of each horizontal scanning period
  • the line memories 304Rr, 304Gr, 304Br In the second half of the scanning period, the digital image signal supplied from the input side selector 302 is captured and held.
  • FIGS. 24B and 24C show the signals on the input side and the output side when the digital image signal corresponding to the second line of the image to be displayed is input to the input side selector 302.
  • the line memos U304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br hold the digital image signal corresponding to the first line of the image to be displayed.
  • “X” indicates an invalid or indefinite signal value (the same applies to the other figures mentioned below).
  • the digital image signals xRy—L, xGy_L, and xBy—L representing the left image are line memory 304R1, 304G1, 304B1, and the right image, each of which is manually input to cylinole in ij pixels.
  • Digital image signals xRy—R, xGy_R, xBy—R The line memories 304Rr, 304Gr, and 304Br that are serially input in order output those image signals in parallel for each line of the left and right images to be displayed.
  • the three line memories 304R1, 304G1, and 304B1 input digital image signals representing the left image serially in units of pixels, and one line for the left image.
  • the other three line memories 304Rr, 304Gr, and 304Br function as the first series-parallel variable to be output to the normal, and digital image signals representing the right image are serially input in units of pixels to output the right image. It functions as a second series-parallel variable that outputs in parallel one line at a time.
  • the latch circuit 306 receives the digital image signal for one line of the left and right images output to the NORENORE from the line memo U304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br force, Latching is performed based on the latch strobe signal LS shown in FIG. 24 (D), and the digital image signal for one row is output as shown in FIGS. 24 (E) and 24 (F).
  • the output side selector 308, the DZ A conversion circuit 310, and the output buffer 312 operate in the same manner as in the two-system simultaneous input mode described above (see FIG. 23), and the image signal power for one line of the left and right images
  • the input-side selector 302 is provided with the input-side selection control signals SI and S2 shown in FIG. 25A, and two digital image signals DV1 and DV2 representing the left image and the right image are shown in FIG.
  • Digital image signals R-Lin, G-Lin, B-Lin, R_Rin, G-Rin, B-Rin shown in (B) are serially input in units of sub-pixels.
  • the input-side selector 302 receives the control signal and the image signal as shown in FIG.
  • 25 (C) according to the truth table shown in FIG. 18 (A).
  • B_L in, R Rin, G Rin, B Rin are output from the output terminal groups 1Y1 to 1Y6 respectively.
  • 25 (B) and 25 (C) show the input side when the digital image signal corresponding to the second line of the image to be displayed (the left image and the right image) is input to the input side selector 302 and The signals on the output side are shown.
  • the line memories 304R1, 304G1, 304 Bl, 304Rr, 304Gr, and 304Br hold the digital image signal corresponding to the first line of the image to be displayed.
  • Line memos U304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br are digital image signals R-Lin, G-Lin, B_Lin, R_Rin, which are serially input in units of sub-pixels in this way.
  • G_Rin, B 1 Rin is output to the parallel line for one line of the left and right image to be displayed. That is, unlike the case of driving a liquid crystal panel having a vertically long pixel arrangement, the three line memories 304G1, 304Rr, and 304Br input digital image signals representing the left image serially in units of pixels, and one line of the left image.
  • the other three line memories 304R1, 304B1, and 304Gr function as the first serial-to-parallel variation that outputs the data in parallel, and input the digital image signal representing the right image serially in units of pixels. It functions as the second series-parallel transformation that outputs to the normal by one line.
  • the line memories 304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br and the latch circuit 306 are connected as shown in FIG. 17 as described above.
  • the latch circuit 306 receives the digital image signals for one row of the left image and the right image output from the line memories 304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br force to the NORENORE, and FIG. Is latched based on the latch strobe signal LS shown in FIG. 25, and the digital image signals for the corresponding one row of the left image and the right image are output as shown in FIGS. 25 (E) and 25 (F).
  • the signals xRy—R, xGy_R, and xBy—R corresponding to the data to be taken in by the three subpixel forming sections (R subpixel, G subpixel, and B subpixel) that form the pixel are on the output side of the latch circuit 306. They will be lined up alternately. In each block, the latch circuit 306 holds such a digital image signal for one horizontal scanning period and outputs it as signals A2, B2, and C2.
  • the digital image signal for the above-mentioned one row of the left and right images is input from the latch circuit 306 to the output side selector 308 (FIGS. 16D and 16E) and FIG. 21B.
  • Output side selection control signals S3 and S4 shown in Fig. 6 are given.
  • the values of the output side selection control signals S3 and S4 (a combination of the value of the signal S3 and the value of the signal S4) are switched every 1Z3 horizontal scanning period in each horizontal scanning period.
  • the output-side selector 308 has three sub-pixel forming portions (R sub-pixel, G sub-pixel, and B sub-pixel) that form each pixel in one row of the image to be displayed (left image and right image).
  • the output side selection control signals S3 and S4 are switched in synchronization with the selection of the scanning signal line Lg by the gate driver 400.
  • the signal output from the output side selector 308 in this way is converted into an analog voltage signal by the DZA conversion circuit.
  • the analog voltage signal thus obtained is output from the data driver as data signals 0 (1) to 0 (211) for one row of the left and right images via the output buffer 312. That is, each of the three signals Rj, Bj, Gj is output from the data driver as the same data signal D (j), and each data signal D (j) is the above three signals A2, B2, C2 (same pixel signal) Group)). Therefore, the DV liquid crystal panel can be driven by applying such a data signal to a data signal line of a DV liquid crystal panel (FIGS. 1 and 4) having a horizontally long pixel arrangement.
  • the input-side selector 302 is provided with the input-side selection control signals SI and S2 shown in FIG. 26 (B), and the left image data DaL and the right image data DaR as shown in FIG. 5 (B).
  • One digital image signal DV is serially input in units of subpixels from the input terminal group Al, Bl, C1 as digital image signals R-Lin, G-Lin, B-Lin shown in Fig. 26 (B) .
  • the input-side selector 302 receives the control signal and the image signal in accordance with the truth table of FIG. 18A, and in the first half of each horizontal scanning period, Digital image signals xRy— L, xGy_L, xBy—L representing the left image are respectively output from the output terminal groups 1Y2, 1Y4, 1Y6 and supplied to the line memories 304G1, 304Rr, 304Br, respectively, and the latter half of each horizontal scanning period.
  • digital image signals xRy—R, xGy_R, and xBy—R representing the right image are output from the output terminal groups 1Y1, 1Y3, and 1Y5, respectively, and supplied to the line memories 304R1, 304B1, and 304Gd, respectively.
  • the line memories 304G1, 304Rr, 304Br capture and hold the digital image signal supplied from the input side selector 302 in the first half of each horizontal scanning period
  • the line memories 304R1, 304B1, 304Gr In the second half of the horizontal scanning period, the digital image signal supplied from the input side selector 302 is captured and held.
  • 26B and 26C show the signals on the input side and the output side when the digital image signal corresponding to the second line of the image to be displayed is input to the input side selector 302.
  • the line memories 304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br hold digital image signals corresponding to the first line of the image to be displayed.
  • the digital image signals xRy—L, xGy_L, and xBy—L representing the left image are represented by line memories 304G1, 304Rr, 304B, and the right image, each of which is manually input to ij pixels.
  • Line memory 304R1, 304B1, and 304Gr that input digital image signals xRy—R, xGy_R, and xBy—R serially in units of sub-pixels in parallel for each row of left and right images to be displayed.
  • the three line memories 304G1, 304Rr, and 304Br serialize the digital image signal representing the left image in units of pixels.
  • the other three line memories 304R1, 304B1, and 304Gr use the digital image signal that represents the right image as a pixel. It functions as a second serial-to-parallel converter that inputs serially in units and outputs in parallel each row of the right image. Therefore, this display mapping input mode [Even if this is the case, the latch circuit 306, or the line memory 304R1, 304G1, 304B1, 304Rr, 304Rr, 304Gr, 304Br digital image signal for one row of left and right images output in parallel. Is received and latched based on the latch strobe signal LS shown in FIG. 26 (D), and the digital image signal for one row is output as shown in FIGS. 26 (E) and 26 (F). .
  • the output side selector 308 receives a digital image signal for one row of the left and right images from the latch circuit 306 as described above (FIGS. 16D and 16E), and FIG. Output side selection control signals S3 and S4 shown in (B) are given. Therefore, the output-side selector 308 performs one horizontal scanning as shown in FIGS. 16 (F) and 16 (G) in the same manner as in operation example 3 above. Output as signals Yl, Y2, Y3 in time division (1H period). However, these signals Yl, Y2, Y3 are the same signal.
  • the signal output from the output side selector 308 in this way is converted into an analog voltage signal by the DZA conversion circuit, and these analog voltage signals are passed through the output buffer 312 to one line of the left and right images.
  • Minute data signals D (l) to D (2n) are output from the data driver. That is, each of the three signals Rj, Bj, Gj is output as the same data signal D (j) as a data driver, and each data signal D (j) is output from the above three signals A2, B2, C2 (same pixel signal). Group)). Therefore, the DV liquid crystal panel can be driven by applying such a data signal to the data signal line of the DV liquid crystal panel (FIGS. 1 and 4) having a horizontally long pixel arrangement configuration.
  • the input-side selector 302 is provided with the input-side selection control signals S1 and S2 shown in FIG. 27 (A), and one digital image signal shown in FIG. , Serially input from C1 in sub-pixel units. At this time, a signal equivalent to one pixel.
  • the input side selection control signals SI, S2 (combination of the value of signal SI and the value of signal S2) are switched.
  • the input-side selector 302 receives odd numbers in these horizontal scanning periods as shown in FIG. 27 (C) according to the truth table of FIG. 18 (A).
  • Signals xRy, xGy, xBy (y is an odd number) corresponding to the eye pixel are respectively output from the output terminal groups 1Y2, 1Y4, 1Y6 and supplied to the line memories 304G1, 304Rr, 304Br, respectively.
  • the signals xRy, xGy, and xBy (y is an even number) corresponding to are output from the output terminal groups 1Y1, 1Y3, and 1Y5, and supplied to the line memories 304R1, 304B1, and 304Gr, respectively.
  • the line memories 304G1, 304Rr, and 304Br capture and hold the digital image signal supplied from the input-side selector 302 during the period corresponding to the odd-numbered pixels in each horizontal scanning period.
  • 304R1, 304B1, and 304Gr capture and hold a digital image signal supplied from the input-side selector 302 in a period corresponding to an even-numbered pixel in each horizontal scanning period.
  • FIGS. 27B and 27C show the signals on the input side and the output side when the digital image signal corresponding to the second line of the image to be displayed is input to the input-side selector 302.
  • the line memories 304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br hold the digital image signal corresponding to the first line of the display smooth image.
  • the line memories 304G1, 304Rr in which the image signals xRy, xGy, xBy (y is an odd number) corresponding to the odd-numbered pixels in each row of the image to be displayed are serially input in units of sub-pixels.
  • the line memories 304R1, 304B1, and 304Gr that serially input 304B and image signals xRy, xGy, and xBy (y is an even number) corresponding to even-numbered pixels in each row of the image to be displayed These image signals are output in parallel for each line of the image to be displayed.
  • the three line memories 304G1, 304Rr, and 304Br input digital image signals representing the odd-numbered pixels in each row of the image to be displayed serially in units of pixels, and apply them to the odd-numbered pixels in one row of the image.
  • the other three line memories 304R1, 304B1, and 304Gr function as the first series-parallel variable ⁇ that outputs the corresponding amount in parallel, and represent the even-numbered pixels in each row of the image to be displayed.
  • the image signal is input serially in pixel units, and the even-numbered image in one row of the image is displayed. It functions as a second serial-to-parallel converter that outputs in parallel the amount corresponding to the element.
  • the latch circuit 306 receives a digital image signal for one line in which the line memories 304R1, 304G1, 304B1, 304Rr, 304 Gr, and 304Br are also output in parallel.
  • the latch strobe signal shown in FIG. Latching is performed based on LS, and the digital image signal for one row is output as shown in FIGS. 27 (E) and 27 (F).
  • a digital image signal for one row of the above image is input to the output-side selector 308 from the latch circuit 306 (FIGS. 28D and 28E), as shown in FIG.
  • Output side selection control signals S3 and S4 are provided. Accordingly, the output side selector 308 outputs signals Yl, Y2, Y3 as shown in FIGS. 28 (F) and 28 (G) from each block.
  • the signal output from the output-side selector 308 in this way is converted into an analog voltage signal by the DZA conversion circuit, and these analog voltage signals are output to the image to be displayed via the output buffer 312.
  • the input-side selector 302 is provided with the input-side selection control signals S1 and S2 shown in FIG. 27 (A), and one digital image signal shown in FIG. , Serially input from C1 in sub-pixel units. Therefore, in this case, as in the above operation example 5, the latch circuit 306 receives the signals to be input to each block of the output side selector 308 as shown in FIG. 29 (D) and FIG. 29 (E) (FIG. 27 (E) And digital image signals A2, B2, C2 as shown in Fig. 27 (F)) are output.
  • the digital image signals A2, B2, and C2 are input to each block of the output side selector 308 (FIGS. 29D and 29E), and the output side shown in FIG. 29C.
  • Selection control signals S3 and S4 are provided.
  • the values of the output side selection control signals S3 and S4 (the combination of the signal S3 value and the signal S4 value) are switched every 1Z3 horizontal scanning period in each horizontal scanning period.
  • each block of the output-side selector 308 should take in three subpixel forming portions (R subpixel, G subpixel, and B subpixel) that form each pixel in one row of the image to be displayed.
  • the same pixel signal group xRy, xGy, xBy corresponding to the data is sequentially output every 1/3 horizontal scanning period. That is, the signals constituting the same pixel signal group are output as signals Yl, Y2, Y3 by time division in one horizontal scanning period as shown in FIGS. 29 (F) and 29 (G). However, these signals Yl, Y2, Y3 are the same signal.
  • the signal output from the output-side selector 308 in this way is converted into an analog voltage signal by the DZA conversion circuit, and these analog voltage signals are output via the output buffer 312 to the image to be displayed.
  • One row of data signals D (1) to D (2n) are output from the data driver. That is, each of the three signals Rj, Bj, Gj is output from the data driver as the same data signal D (j), and each data signal D (j) is the above three signals A2, B2, C2 (same pixel signal) Group)). Therefore, the DV liquid crystal panel can be driven by applying such a data signal to the data signal line of the SV liquid crystal panel having the horizontally long pixel arrangement configuration.
  • the three line memories corresponding to the three primary colors of the color image display are set as one set, and the left and right sides are compatible with the DV liquid crystal panel.
  • Two sets of line memories (total of 6 line memories) 304Rl to 304Br that can be associated with images are provided, and each of the 6 line memories 304R1 to 304Br represents an image to be displayed. It functions as a series-parallel transformation that inputs image data in units of subpixels and outputs them in parallel.
  • a digital image signal serially given to the data driver as image data (display data) representing an image to be displayed is a signal line connection between the six line memories 304Rl to 304Br and the latch circuit 306.
  • the output signals A2, B2, and C2 from the latch circuit 30 6 are the pixel arrangement configuration of the liquid crystal panel to be driven (vertical image).
  • Data signal format (independent output format or time-division output format) output from the data dryer by switching the output-side selection control signals S3 and S4 according to the basic configuration or horizontal pixel configuration) Can be changed by the output side selector 308 (see Fig. 18 (B) ⁇ Fig. 20, Fig. 21).
  • an output format corresponding to various liquid crystal panels such as a DV liquid crystal panel or an SV liquid crystal panel having a vertically long pixel arrangement structure or a horizontally long pixel arrangement structure without separately preparing an interface circuit.
  • the drive signal (data signal) can be output with the same, and the input format of the image signal representing the image to be displayed is the same as the DV2 simultaneous input format, DV display mapping input format, and normal display input format. Either can be supported.
  • the configuration shown in FIG. 17 and FIG. 18 for the second embodiment is an example, and even if the input format or output format that can be supported is more limited than the above embodiment, the input format or output format is not limited. If the degree of freedom can be secured within the required range for each type, For example, while ensuring flexibility in the input format (providing a connection switching circuit such as the input side selector 302), the liquid crystal panel to be driven is limited to a DV liquid crystal panel having a horizontally long pixel arrangement configuration. Also good. This reduces the degree of freedom with respect to the compatible input / output formats, but simplifies the configuration of the data driver (for example, the configuration of the output side selector 308 to the output buffer 312 shown in FIG. 6).
  • the input formats that can be supported are fixed, and for the liquid crystal panel to be driven, either the vertical pixel arrangement configuration or the horizontal pixel arrangement configuration (independent output format or time division output format)
  • a connection switching circuit such as the output side selector 308 may be provided only on the output side so that it can be supported.
  • the data driver of the liquid crystal panel has been described as an example.
  • the present invention is not limited to this, and the display panel in a matrix type display device other than the liquid crystal display device is not limited thereto.
  • the present invention is also applicable to the data side driving circuit.
  • the present invention relates to a matrix display device such as an active matrix liquid crystal display device.
  • a matrix display device such as an active matrix liquid crystal display device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

La présente invention concerne un procédé permettant d’adapter le format d’entrée et/ou le format de sortie d’un circuit de commande de données pour un dispositif d’affichage matriciel. Un circuit de commande de données possède deux jeux de mémoires de ligne (340RI-340Br) correspondant à des images dissymétriques respectives à afficher sur un écran à cristaux liquides DV, chaque jeu comprenant trois mémoires de ligne correspondant aux trois couleurs primaires de l’affichage couleur. Ces mémoires de ligne servent de convertisseur série/parallèle pour le circuit de commande de l’écran. Un signal d’image à appliquer au circuit est fourni à l’une des six mémoires de ligne en fonction du format d’entrée d’un sélecteur d’entrée (302). Un sélecteur de sortie (308) sert à commuter les sélections des signaux de sortie (A2, B2, C2) que doit produire un circuit de verrouillage (306) via ces mémoires de ligne, d’où modification du format de sortie du circuit de commande selon un agencement de pixels de l’écran. La présente invention est applicable aux circuits de commande de données de divers types de dispositifs d’affichage présentant différents agencements de pixels.
PCT/JP2006/304897 2005-03-22 2006-03-13 Circuit et procede de commande de dispositif d’affichage WO2006100951A1 (fr)

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JP2005082277 2005-03-22

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007163719A (ja) * 2005-12-13 2007-06-28 Renesas Technology Corp データプロセッサ
WO2007110993A1 (fr) * 2006-03-24 2007-10-04 Sharp Kabushiki Kaisha Convertisseur de format de signal et procédé de conversion de format de signal destinés à une utilisation avec un appareil d'affichage matriciel

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JPH07152338A (ja) * 1994-09-05 1995-06-16 Hitachi Ltd 表示駆動装置
JPH07248467A (ja) * 1994-03-08 1995-09-26 Sharp Corp ３次元情報入力装置及び３次元情報再生装置
JPH07318858A (ja) * 1994-05-20 1995-12-08 Sharp Corp ３次元情報再生装置
JPH09205661A (ja) * 1996-01-26 1997-08-05 Sharp Corp 視点補正自動立体表示装置
JP2003022057A (ja) * 2001-07-09 2003-01-24 Alps Electric Co Ltd 画像信号駆動回路および画像信号駆動回路を備えた表示装置
JP2003066921A (ja) * 2001-08-28 2003-03-05 Sharp Corp 駆動装置およびそれを備えている表示モジュール
JP2004120058A (ja) * 2002-09-24 2004-04-15 Sharp Corp ２ｄ（２次元）及び３ｄ（３次元）表示機能を備える電子機器
JP2005010304A (ja) * 2003-06-17 2005-01-13 Sea Phone Co Ltd 表示装置、該表示装置の制御方法および制御用プログラム
JP2006030512A (ja) * 2004-07-15 2006-02-02 Nec Corp 液晶表示装置、携帯機器及び液晶表示装置の駆動方法

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Publication number Priority date Publication date Assignee Title
JPH07248467A (ja) * 1994-03-08 1995-09-26 Sharp Corp ３次元情報入力装置及び３次元情報再生装置
JPH07318858A (ja) * 1994-05-20 1995-12-08 Sharp Corp ３次元情報再生装置
JPH07152338A (ja) * 1994-09-05 1995-06-16 Hitachi Ltd 表示駆動装置
JPH09205661A (ja) * 1996-01-26 1997-08-05 Sharp Corp 視点補正自動立体表示装置
JP2003022057A (ja) * 2001-07-09 2003-01-24 Alps Electric Co Ltd 画像信号駆動回路および画像信号駆動回路を備えた表示装置
JP2003066921A (ja) * 2001-08-28 2003-03-05 Sharp Corp 駆動装置およびそれを備えている表示モジュール
JP2004120058A (ja) * 2002-09-24 2004-04-15 Sharp Corp ２ｄ（２次元）及び３ｄ（３次元）表示機能を備える電子機器
JP2005010304A (ja) * 2003-06-17 2005-01-13 Sea Phone Co Ltd 表示装置、該表示装置の制御方法および制御用プログラム
JP2006030512A (ja) * 2004-07-15 2006-02-02 Nec Corp 液晶表示装置、携帯機器及び液晶表示装置の駆動方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007163719A (ja) * 2005-12-13 2007-06-28 Renesas Technology Corp データプロセッサ
WO2007110993A1 (fr) * 2006-03-24 2007-10-04 Sharp Kabushiki Kaisha Convertisseur de format de signal et procédé de conversion de format de signal destinés à une utilisation avec un appareil d'affichage matriciel

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