WO2006082817A1

WO2006082817A1 - Capacitor and wiring board incorporating same

Info

Publication number: WO2006082817A1
Application number: PCT/JP2006/301587
Authority: WO
Inventors: Yasuhiro Ishii; Tooru Mori; Akinobu Shibuya; Shintaro Yamamichi; Kazuhiro Baba; Hidenori Kawahara
Original assignee: Nec Corporation
Priority date: 2005-02-04
Filing date: 2006-01-31
Publication date: 2006-08-10
Also published as: JP5061895B2; JPWO2006082817A1

Abstract

A lower electrode is provided on a substrate composed of a resin, a dielectric film composed of an oxide having a perovskite structure is provided on a part of a region on the lower electrode, and an upper electrode is provided on the dielectric film. An insulating layer composed of a resin is provided on the substrate so as to cover the lower electrode, the dielectric film and the upper electrode. A slit-shaped hole is formed on a part of a region of the lower electrode, excluding a region directly under the dielectric film. At a bottom section of the hole, the insulating layer is brought into direct contact with the substrate, and the substrate and the insulating layer are firmly bonded. Thus a capacitor having strong adhesion among the substrate, the lower electrode, the dielectric film and the upper electrode is provided.

Description

Specification

Capacitor and wiring board incorporating the capacitor

Technical field

TECHNICAL FIELD [0001] The present invention relates to a capacitor that can be mounted on a wiring board and a wiring board that incorporates the capacitor.

Background art

[0002] Recently, in order to improve the performance of electronic devices, market demands for high-density mounting of passive components are increasing. To meet these requirements, the size of passive components has been reduced from 1005 size (vertical 1. Omm, horizontal 0.5 mm) to 0603 size (vertical 0.6 mm, horizontal 0.3 mm). I'm following a course. Recently, there is also a tendency to develop passive components of 0402 size (vertical is 0.4 mm, horizontal is 0.2 mm).

On the other hand, however, there is a recognition that further downsizing of the chip size is difficult in terms of technology and on the mounting machine side. Against this background, a technology that reduces the board area by incorporating passive components in an electric circuit board has attracted attention. In particular, a capacitor is one of the most frequently used components that make up an electronic circuit. Therefore, if the capacitor can be built in an electronic circuit board, a particularly large effect can be expected in reducing the board area. Among them, a capacitor using a dielectric having a high dielectric constant is attracting attention as a capacitor that can be built in an electronic circuit board in recent years because the capacitor per unit area is high and the capacitor element can be made thinner than a chip component. ing.

[0004] When a rigid substrate such as a silicon substrate or a glass substrate is used as a substrate for such a capacitor, the rigid substrate is excellent in surface flatness and heat resistance, but is thin and thin. Then, there is a problem that handling after processing and thinning becomes difficult. On the other hand, a flexible substrate such as a resin substrate has a problem of low heat resistance, but can be easily thinned and grounded, and is suitable as a capacitor substrate.

[0005] A number of technologies related to capacitors using flexible substrates have been proposed. For example, Patent Document 1 (Japanese Patent Laid-Open No. 7-22725) discloses a ceramic or resin. A technique for forming a capacitor on the surface of an insulating substrate is disclosed. Patent Document 2 (Japanese Patent Laid-Open No. 2000-357631) discloses a technique for forming a capacitor on a flexible substrate via a metal oxide adhesive film and a metal adhesive film. Further, in Patent Document 3 (Japanese Patent Laid-Open No. 2004-56097), in a capacitor in which a lower electrode, a dielectric thin film, and an upper electrode are laminated in this order on a flexible substrate, the lower electrode is attached to an adhesive layer, A technique for laminating an elastic layer and an oxidation-resistant layer in this order is disclosed.

[0006] Several techniques have been proposed for a printed circuit board or a resin wiring board with a built-in capacitor. For example, Patent Document 4 (Japanese Patent Laid-Open No. 2000-277922) and Patent Document 5 (Japanese Patent Laid-Open No. 2001-77539) disclose techniques for using an insulating layer constituting a multilayer substrate as a dielectric layer of a capacitor. ing. Patent Document 6 (Japanese Patent Publication No. 2001-160672) discloses a technique for forming a capacitor with a thick film. Further, in Patent Document 7 (Japanese Patent Laid-Open No. 2002-100533), a lower electrode is formed on an organic multilayer substrate, a valve metal film is formed on the lower electrode, and an anode oxidation treatment is performed on the valve metal film. Thus, a technique for forming an anodic oxide film and forming an upper electrode on the anodic oxide film is disclosed. According to the anodic oxidation method, the dielectric thin film can be formed at a low temperature, so that the dielectric thin film can be formed on a resin substrate such as a printed circuit board.

[0007] Patent Document 1: Japanese Patent Laid-Open No. 7-22725

Patent Document 2: JP 2000-357631 A

Patent Document 3: Japanese Patent Application Laid-Open No. 2004-56097

Patent Document 4: Japanese Patent Laid-Open No. 2000-277922

Patent Document 5: Japanese Patent Laid-Open No. 2001-77539

Patent Document 6: Japanese Unexamined Patent Publication No. 2001-160672

Patent Document 7: Japanese Patent Laid-Open No. 2002-100533

Disclosure of the invention

Problems to be solved by the invention

[0008] However, the conventional techniques described above have the following problems. In order to increase the capacitance of the capacitor built in the printed wiring board, 1) reduce the thickness of the dielectric film, 2) increase the relative dielectric constant of the dielectric film, and 3) increase the capacitance of the capacitor. Effective electrode area It is effective to increase the size. However, when the capacitance of the capacitor is increased by these methods, there is a problem that the adhesion between the substrate, the lower electrode, the dielectric film, and the upper electrode is lowered. Hereinafter, this problem will be described in detail.

[0009] Regarding the above 1), in the case of a so-called thick film capacitor using a thick dielectric film, the unevenness of the surface becomes large in the manufacturing process, so the adhesion between the dielectric film and the upper electrode is It is relatively good. However, if the dielectric film is thinned in order to increase the capacitance of the capacitor and to reduce the thickness of the capacitor and the printed wiring board in which the capacitor is built, the surface of the dielectric film becomes flat, and the dielectric film Adhesion between the electrode and the upper electrode decreases.

[0010] With regard to 2) above, in order to improve the relative dielectric constant of the dielectric film, barium titanate having a relative dielectric constant exceeding 100 at room temperature by a method such as sputtering, CVD, or sol-gel. A thin film made of (BaTiO 3) or lead zirconate titanate (Pb (Zr, Ti) 0) is formed.

3 3

It is effective. However, in order to form such a dielectric film, it is necessary to form a metal film having excellent surface flatness as a lower electrode serving as a base, and such a metal film is formed by sputtering. There is a need. However, although the metal film formed by the sputtering method has a flat surface, the residual stress at the time of film formation remains after the film formation, and the adhesion strength between the base flexible substrate becomes low.

[0011] When a conductive paste is supplied onto a substrate by screen printing and the conductive paste is dried and baked to form a lower electrode, the flatness of the surface of the lower electrode becomes low. For this reason, it is difficult to form a dielectric thin film having a thickness of submicron on the lower electrode, and it is therefore difficult to obtain a capacitor having a high capacitance density. Further, in a method in which a valve metal film is formed on the lower electrode, an anodized film is formed by subjecting the valve metal film to anodization, and this anodized film is used as a dielectric thin film, Since the dielectric constant of the dielectric film is 100 or less, the capacitance of the capacitor cannot be increased sufficiently.

For the above 3), if the effective electrode area is increased in order to increase the capacitance value of the capacitor, the adhesion between the substrate, the lower electrode, the dielectric film, and the upper electrode may be insufficient. This is an extremely serious issue. For this reason, the adhesion of a large-capacity capacitor with a large effective area It is difficult to improve to the extent that it can withstand the external force applied in the process of incorporating the capacitor in the printed wiring board.

[0013] As described above, when the capacitance value of the capacitor is increased, the adhesion of the capacitor is lowered. In particular, in a capacitor formed on a flexible substrate, an interface between a substrate made of a resin and a lower electrode made of metal force, an interface between a lower electrode made of metal force and a dielectric film made of metal oxide, a metal oxide There are multiple interfaces of dissimilar materials, such as the interface between the dielectric film made of a metal and the upper electrode made of metal. Further, when such a capacitor is incorporated in a printed wiring board, an external force is applied to the capacitor even during this incorporation process. For this reason, it is extremely difficult to increase the adhesion strength at each interface in the capacitor to such an extent that it can withstand the process of embedding in the printed circuit board.

[0014] The present invention has been made in view of a serious problem, and in a capacitor built in a wiring board, the adhesion strength among the substrate, the lower electrode, the dielectric film, and the upper electrode constituting the capacitor. An object of the present invention is to provide a capacitor and a printed wiring board incorporating the capacitor.

Means for solving the problem

A capacitor according to the present invention includes a substrate, a lower electrode formed on the substrate, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film. An insulating layer formed of a material that is in close contact with the substrate so as to cover the laminated body including the lower electrode, the dielectric film, and the upper electrode, and a part of the laminated body is removed, The insulating layer is in contact with the substrate at the removed portion of the stacked body.

Another capacitor according to the present invention includes a substrate made of a resin, a lower electrode formed on the substrate, a dielectric film formed on a part of the lower electrode, and the dielectric An upper electrode formed on the film, and a resin insulating layer provided on the substrate so as to cover the lower electrode, the dielectric film, and the stacked body having the upper electrode force, A hole penetrating the laminate is formed in a part of the laminate, the insulating layer is embedded in the hole, and the insulating layer is in contact with the substrate at the bottom of the hole. Features. [0017] In the present invention, since the substrate and the insulating layer are both formed by grease, the adhesion strength between the substrate and the insulating layer is high. A hole is formed in the laminate, and the insulating layer is in contact with the substrate at the bottom of the hole, so that the insulating layer is firmly bonded to the substrate at this portion. As a result, the lower electrode, the dielectric film, and the upper electrode are sandwiched between the substrate and the insulating layer bonded to each other, so that the adhesion between the substrate, the lower electrode, the dielectric film, and the upper electrode is good. It is.

[0018] Further, the hole may be formed in a part of a region where the lower electrode, the dielectric film, and the upper electrode are stacked in the stacked body. As a result, since the dielectric film and the upper electrode are disposed in the vicinity of the joint between the substrate and the insulating layer, the adhesion between the substrate, the lower electrode, the dielectric film and the upper electrode is further improved. .

At this time, the lower electrode, the dielectric film, and the upper electrode are each divided into a plurality of portions by the holes, and adjacent portions of the lower electrode are connected to each other. The adjacent portions of the upper electrode are preferably connected to each other. The holes may be formed in a lattice shape when viewed from a direction perpendicular to the surface of the substrate, and the shape of each part of the lower electrode, the dielectric film, and the upper electrode may be rectangular. The holes may be formed such that at least one of the portions of the lower electrode, the dielectric film, and the upper electrode has a hexagonal shape, and each of the portions may have a honeycomb shape. Arranged in !!

[0020] A wiring board according to the present invention includes a core substrate and the capacitor provided on at least one surface of the core substrate. As a result, even after the process of incorporating the capacitor into the wiring board, interfacial delamination does not occur between the substrate, the lower electrode, the dielectric film, and the upper electrode in the capacitor.

In addition, the wiring board according to the present invention has an insulating film provided so as to cover the capacitor, and a surface wiring provided on the surface of the insulating film, and the lower electrode of the capacitor is the Preferably, the capacitor is connected to a part of the surface wiring, and the upper electrode of the capacitor is connected to another part of the surface wiring that is insulated from the part.

[0022] At this time, the wiring board according to the present invention has an inner layer wiring provided in a region where the capacitor is not provided between the core substrate and the insulating film, and the lower electrode. A first conductor layer connected to a part of the inner layer wiring, and a second conductor layer connecting the upper electrode to the other part of the inner layer wiring insulated from the part. A first through hole and a second through hole are respectively formed in a part of the region immediately above the part and the other part of the inner layer wiring in the film, and the lower electrode includes the first conductor layer, A part of the inner layer wiring is connected to a part of the surface wiring through the first through-hole, and the upper electrode includes the second conductor layer, another part of the inner layer wiring, the It is preferable to be connected to the other part of the surface wiring via the second through hole. As a result, since the first and second through holes are arranged in the region except for the region directly above the capacitor, the capacitor is not damaged when the first and second through holes are formed.

The invention's effect

[0023] According to the present invention, the insulating layer is firmly bonded to the substrate at the bottom of the hole formed in the multilayer body, and thus the adhesion strength between the substrate, the lower electrode, the dielectric film, and the upper electrode is high. A capacitor can be obtained.

Brief Description of Drawings

FIG. 1 (a) is a plan view showing a capacitor according to a first embodiment of the present invention, and (b) is a cross-sectional view taken along the line AA ′ shown in (a).

[FIG. 2] (a) is a plan view showing a printed wiring board according to a comparative example outside the scope of the present invention, and (b) is a cross-sectional view taken along line BB ′ shown in (a).

FIG. 3 (a) is a plan view showing a capacitor according to a second embodiment of the present invention, and (b) is a cross-sectional view taken along the line CC ′ shown in (a).

FIG. 4 (a) is a plan view showing a capacitor according to a third embodiment of the present invention, and (b) is (a

It is sectional drawing by DD 'line shown to).

FIG. 5 is a cross-sectional view taken along line EE ′ shown in FIG. 4 (a).

[FIG. 6] (a) to (c) are plan views showing a capacitor according to a fourth embodiment of the present invention for each layer.

FIGS. 7A to 7C are plan views showing capacitors according to the present embodiment for each layer.

FIG. 8 (a) is a plan view showing the capacitor according to the present embodiment for each layer, and FIG. It is sectional drawing by the FF 'line shown.

[FIG. 9] (a) to (c) are plan views showing a method of manufacturing a capacitor according to the present embodiment in the order of steps.

FIG. 10 (a) is a plan view showing a capacitor according to a modification of the fourth embodiment, and FIG. 10 (b) is a cross-sectional view taken along line GG ′ shown in FIG.

[FIG. 11] (a) to (c) are plan views showing a method of manufacturing a capacitor according to this modification in the order of steps.

[FIG. 12] (a) to (c) are plan views showing the method of manufacturing a capacitor according to this modification in the order of the steps, and show the next step of FIG. 11 (c).

FIG. 13 is a cross-sectional view showing a printed wiring board according to a fifth embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a printed wiring board according to a sixth embodiment of the present invention.

Explanation of symbols

1; substrate

2; Bottom electrode

2a, 2b; rectangular area

2c; hexagonal region

3; Dielectric film

4; upper electrode

5; insulation layer

6; Hall

7a, 7b; opening

8; Laminate

9; Interlayer insulation film

10a, 10b, 10c, 10d; opening

11, 13; thick film electrode

12; Thin film electrode

12c; part

14, 15; Bridge part 20; Capacitor

21; Core substrate

22; Inner layer wiring

23; adhesive layer

24; Prepreda

25; Surface wiring

26a, 26b; via

27; Cu plating layer

28; Through-through hole

29; Plating electrode

31, 34;

32; Plating electrode

33; Inner layer pad

35; Plating electrode

36, 37; paste layer

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, the first embodiment of the present invention will be described. FIG. 1A is a plan view showing the capacitor according to the present embodiment, and FIG. 1B is a cross-sectional view taken along the line AA ′ shown in FIG. As shown in FIGS. 1 (a) and (b), the capacitor according to the present embodiment is provided with a substrate 1 made of resin and having a thickness of, for example, 10 to 60 / ζπι, for example, 20 to 50 m. It has been. On the substrate 1, a lower electrode 2 made of a metal or an alloy is provided. When viewed from a direction perpendicular to the surface of the substrate 1 (hereinafter referred to as a plan view), the shape of the lower electrode 2 is rectangular. Further, a dielectric film 3 made of an inorganic material, for example, an oxide having a bottom bumskite structure, is provided in a part of the region on the lower electrode 2. On the dielectric film 3, metal or An upper electrode 4 made of an alloy is provided. In plan view, the dielectric film 3 and the upper electrode 4 are rectangular. A laminated body 8 is constituted by the lower electrode 2, the dielectric film 3 and the upper electrode 4. [0027] An insulating layer 5 is provided so as to cover the laminated body 8. The insulating layer 5 is for protecting the lower electrode 2, the dielectric film 3 and the upper electrode 4, and is formed of a resin having good adhesion to the substrate 1. Two openings 7a and 7b are formed in regions of the insulating layer 5 that are separated from each other. The opening 7a is formed in a part of the region directly above the lower electrode 2 and excluding the region directly above the dielectric film 3, and the lower electrode 2 is exposed at the bottom of the opening 7a. The opening 7b is formed in a part of the region directly above the upper electrode 4, and the upper electrode 4 is exposed at the bottom of the opening 7b. In plan view, the shapes of the openings 7a and 7b are rectangular, the longitudinal directions thereof are the same as each other, and the openings 7a and 7b are along the direction (short direction) perpendicular to the longitudinal direction. Are arranged. A voltage is applied from the external circuit between the lower electrode 2 and the upper electrode 4 through the openings 7a and 7b. At this time, the dielectric film 3 functions as a capacitive insulating film.

[0028] In a region where the dielectric film 3 and the upper electrode 4 in the laminated body 8 are arranged, a part of the region excluding the region immediately below the dielectric film 3 in the lower electrode 2 is formed in a slit-like hole. 6 is formed. In plan view, the hole 6 is formed at a position opposite to the opening 7b when viewed from the opening 7a, and the longitudinal direction of the hole 6 is the same as the longitudinal direction of the openings 7a and 7b. In the hole 6, the lower electrode 2 is not provided, and the substrate 1 is exposed. In addition, since the dielectric film 3 and the upper electrode 4 are not provided on the hole 6, the insulating layer 5 is embedded in the hole 6. Therefore, the insulating layer 5 is in direct contact with the substrate 1 at the bottom of the hole 6. In a plan view, the ratio of the area of the hole 6 to the total area of the lower electrode 2, that is, the area including the hole 6 is, for example, 1 to 25%, for example, 5 to 10%.

[0029] The larger the ratio of the area of the hole 6 to the total area of the lower electrode 2, the stronger the adhesion strength between the insulating layer 5 and the substrate 1, but on the other hand, the total area of the capacitor is increased. There is a disadvantage that. When the total area of the lower electrode 2 in plan view, that is, the ratio of the area of the hole 6 to the area of the lower electrode 2 including the hole 6 is less than 1%, the above-described substrate 1, lower electrode 2, and dielectric film The effect of improving the adhesion at the interface between 3 and the upper electrode 4 is small. On the other hand, if the ratio exceeds 25%, the total area of the capacitor becomes too large and the capacitance density decreases. Therefore, the ratio is preferably 1 to 25%, more preferably 5 to 10%. Next, the effect of this embodiment will be described. The substrate 1 and the insulating layer 5 are both made of resin, and the adhesion strength between the substrate 1 and the insulating layer 5 is high. For this reason, the substrate 1 and the insulating layer 5 are firmly bonded to each other in the hole 6, and the laminated body including the lower electrode 2, the dielectric film 3 and the upper electrode 4 is bonded to the substrate 1 and the insulating layer 5. Is sandwiched between. Thus, between the substrate 1 and the lower electrode 2, between the lower electrode 2 and the dielectric film 3, between the dielectric film 3 and the upper electrode 4, and between the upper electrode 4 and the insulating layer 5. The adhesion strength can be increased.

That is, in the present embodiment, a hole 6 penetrating a part of the lower electrode 2 is formed, and the substrate 1 that is a flexible substrate and the insulating layer 5 made of resin are directly connected through the hole 6. It is attached. As a result, it is possible to improve the adhesion of each interface without providing a special adhesion layer at the interface existing in plural in the capacitor by utilizing the high adhesion between the substrate 1 and the insulating layer 5. Therefore, the capacitor according to the present embodiment can withstand the external force applied in the process of incorporating the capacitor in the printed board. For this reason, it is possible to prevent the occurrence of an open defect due to the separation of the capacitor interface, which has been caused by the external force accompanying the deformation of the substrate in the process of incorporating the printed circuit board. As a result, a highly reliable printed wiring board with a built-in capacitor can be provided. In addition, since an adhesion layer for improving the adhesion of the capacitor is unnecessary, it is possible to prevent a decrease in electrostatic capacity due to the adhesion layer, and it is possible to incorporate a large-capacity capacitor in the printed wiring board. is there.

In the present embodiment, since the dielectric film 3 is formed of an oxide having a bottom bskite structure, the capacitance value is high.

FIG. 2 (a) is a plan view showing a capacitor according to a comparative example that is out of the range force of the present invention, and FIG. 2 (b) is a cross-sectional view taken along line BB ′ shown in FIG. 2 (a). As shown in FIG. 2, no hole is formed in the laminate 8 in this comparative example. Therefore, the insulating layer 5 is bonded to the substrate 1 only at the periphery of the stacked body 8. Therefore, compared with the first embodiment described above, the adhesion strength between the substrate 1 and the insulating layer 5 is weak. As a result, the substrate 1 and the lower electrode 2 and the lower electrode 2 and the dielectric film are reduced. 3, adhesion strength between the dielectric film 3 and the upper electrode 4, and between the upper electrode 4 and the insulating layer 5 are also low.

[0034] In the first embodiment described above, an example in which only one hole 6 is formed is shown. However, the present invention is not limited to this, and a plurality of holes 6 may be formed. In the present embodiment, an example in which the lower electrode 2 is formed of a single layer film has been shown. However, the present invention is not limited to this, and the deformation of the substrate 1 after the formation of the dielectric film 3 is suppressed. In addition, the lower electrode 2 is formed of a three-layer film in which an adhesive conductive material layer, a highly elastic conductive material layer and an oxidation-resistant conductive material layer are laminated in order from the substrate 1 side, or four or more layers including this three-layer film. Form with a multilayer film.

[0035] Next, a second embodiment of the present invention will be described. FIG. 3A is a plan view showing the capacitor according to this embodiment, and FIG. 3B is a cross-sectional view taken along the line CC ′ shown in FIG. In FIGS. 3 (a) and (b), the same components as those shown in FIGS. 1 (a) and (b) are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIGS. 3 (a) and 3 (b), in the capacitor 20 according to the present embodiment, the lower electrode 2 is provided on the substrate 1, and a partial region on the lower electrode 2 is provided. A dielectric film 3 is provided, and an upper electrode 4 is provided on the dielectric film 3. In the lower electrode 2, one hole 6 is formed in the same manner as in the first embodiment.

Then, an interlayer insulating film 9 made of an insulating material, for example, photosensitive polyimide is provided so as to cover the lower electrode 2, the dielectric film 3 and the upper electrode 4. In the interlayer insulating film 9, three openings 10a, 10b and 10c are formed. The opening 10a is formed in a part of the region directly above the lower electrode 2 and not provided with the dielectric film 3, and the opening 10b is formed in the hole 6 and in the region immediately above it. The opening 10c is formed immediately above the upper electrode 4. In plan view, the openings 10a to 10c are arranged in a line in this order.

[0038] A thick film electrode 11 made of, for example, Cu or Au force is provided inside and directly above the opening 10a, and is connected to the lower electrode 2 at the bottom of the opening 10a. In addition, a thin film electrode 12 made of, for example, Cu, Au, or Ni is provided in the opening 10c and directly above, and is connected to the upper electrode 4 at the bottom of the opening 10c. The thin film electrode 12 extends on the interlayer insulating film 9 from the region directly above the opening 10c in a direction away from the opening 10b. Furthermore, a thick film electrode 13 made of, for example, Cu or Au is provided in a part of the region on the interlayer insulating film 9 except for the region directly above the upper electrode 4, and is in contact with the extending portion of the thin film electrode 12. It has been continued. The force that the lower electrode 2 is also provided in the region immediately below the thick film electrode 13 The portion of the lower electrode 2 that is disposed immediately below the thick film electrode 13 is disposed in the region immediately below the upper electrode 4 in the lower electrode 2. It is insulated from the part. The thin film electrode 12 and the thick film electrode 13 are insulated from the lower electrode 2 by the interlayer insulating film 9.

In addition, an insulating layer 5 is provided so as to cover the laminated body 8, the interlayer insulating film 9, the thick film electrode 11, the thin film electrode 12, and the thick film electrode 13 provided on the substrate 1. The insulating layer 5 is formed of a resin having good adhesion to the substrate 1. An insulating layer 5 is buried inside the opening 10b formed in the interlayer insulating film 9, and is in direct contact with the substrate 1 at the bottom of the opening 10b, that is, at the bottom of the hole 6. Thus, the substrate 1 is firmly bonded to the insulating layer 5 in the hole 6.

[0040] The insulating layer 5 has two openings 7a and 7b. The opening 7a is formed immediately above the thick film electrode 11, and the thick film electrode 11 is exposed at the bottom. Further, the opening 7b is formed in the region immediately above the thick film electrode 13, and the thick film electrode 13 is exposed at the bottom. As a result, the thick film electrode 11 passes through the insulating layer 5 and the opening 10a of the interlayer insulating film 9 and is connected to the lower electrode 2, and the thick film electrode 13 passes through the insulating layer 5. The thin film electrode 12 is connected to the upper electrode 4 through the opening 10 c of the interlayer insulating film 9. The thick film electrodes 11 and 13 connect the lower electrode 2 and the upper electrode 4 to an external circuit (not shown). Then, a voltage is applied between the lower electrode 2 and the upper electrode 4 from the external circuit via the thick film electrodes 11 and 13. Other configurations in the present embodiment are the same as those in the first embodiment described above.

The thin film electrode 12 as described above connects the upper electrode 4 to the thick film electrode 13. Further, the interlayer insulating film 9 ensures insulation between the upper electrode 4 and the lower electrode 2 of the capacitor and insulation between the upper electrode 4, the thin film electrode 12, the thick film electrode 13 and the lower electrode 2. It is for doing. Note that the interlayer insulating film 9 may be formed of an inorganic material.

In the present embodiment, since the thick film electrodes 11 and 13 are provided, the connection reliability with the external circuit is high. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

Next, a third embodiment of the present invention will be described. Fig. 4 (a) shows the key according to this embodiment. FIG. 5B is a cross-sectional view taken along line DD ′ shown in FIG. 5A, and FIG. 5 is a cross-sectional view taken along line EE ′ shown in FIG. 4A. In FIGS. 4 (a) and (b) and FIG. 5, the same components as those shown in FIGS. 3 (a) and (b) are denoted by the same reference numerals, and detailed description thereof is omitted. To do.

[0044] As shown in FIGS. 4 (a) and 4 (b) and FIG. 5, the capacitor according to the present embodiment has holes 6 in the lower electrode 2 in the multilayer body 8 as compared with the second embodiment described above. The dielectric film 3 and the upper electrode 4 are formed in the laminated region, and the holes 6 are formed in a lattice shape, for example, a cross shape in a plan view. The body film 3, the upper electrode 4 and the thin film electrode 12 are each divided into four parts, but are different.

[0045] Hereinafter, this will be described in more detail. The lower electrode 2 is divided into three regions along the direction from the region immediately below the thick film electrode 11 to the region immediately below the thick film electrode 13. In the lower electrode 2, the dielectric film 3 and the upper electrode 4 are not provided above the region including the region immediately below the thick film electrode 11, and this region is connected to the thick film electrode 11. In addition, the dielectric film 3 and the upper electrode 4 are not provided above the region of the lower electrode 2 including the region immediately below the thick film electrode 13, and this region is separated from the other two regions. Yes.

A dielectric film 3 and an upper electrode 4 are provided above the region of the lower electrode 2 disposed between the two regions described above. This region is continuous with the region including the region immediately below the thick film electrode 11 described above. This area is divided into four parts by a cross-shaped hole 6. In plan view, the shape of each part is a rectangle. Between the crossing portion and the outer end portion of the cross-shaped hole 6 and between each portion, there is a bridge portion 14 that extends each partial force of the lower electrode 2 and connects adjacent portions. As a result, the four portions of the lower electrode 2 are connected to each other via the bridge portion 14 at the crossing portion and the outer end portion. In addition, the dielectric film 3 and the upper electrode 4 are divided into four parts by the cross-shaped holes 6, respectively, and the parts are not connected to each other. In plan view, the dielectric film 3 and the upper electrode 4 are rectangular.

[0047] Furthermore, the thin film electrode 12 is provided in a region including a region immediately above the dielectric film 3 and the upper electrode 4, and is divided into four parts by a cross-shaped hole 6, but between each part and Between the thick film electrode 13, a bridge portion 15 in which each partial force extends is provided. Bridge part 15 is arranged in a region immediately above the bridge portion 14 provided between the portions of the lower electrode 2 in the bridge portion 14. Thereby, each part of the thin film electrode 12 is connected to the thick film electrode 13 via the bridge part 15. Therefore, the portions of the upper electrode 4 connected to the portions of the thin film electrode 12 are also connected to each other and to the thick film electrode 13. Other configurations in the present embodiment are the same as those in the second embodiment described above.

In the present embodiment, since the hole 6 is formed in a region where the lower electrode 2, the dielectric film 3 and the upper electrode 4 are stacked in the stacked body 8, the substrate 1 and the insulating layer 5 A lower electrode 2, a dielectric film 3, and an upper electrode 4 are disposed in the vicinity of the coupling portion. For this reason, the adhesion between the substrate lower electrode 2, the dielectric film 3, and the upper electrode 4 is further improved as compared with the second embodiment described above. Further, since the hole 6 is formed in a cross shape, the lower electrode 2, the dielectric film 3, and the upper electrode 4 are each divided into four portions having a relatively small area. As a result, between the substrate 1 and the lower electrode 2, between the lower electrode 2 and the dielectric film 3, between the dielectric film 3 and the upper electrode 4, and between the upper electrode 4 and the insulating layer 5. The adhesion of the material becomes stable and good.

[0049] In addition, when the substrate 1 is bent in the longitudinal direction of the opening 7a and the short direction perpendicular to the opening 7a, the stress applied to the stacked body 8 can be relaxed. High resistance to direction curvature.

[0050] Furthermore, by connecting the portions of the lower electrode 2 and the upper electrode 4 to each other, a plurality of units comprising the portions of the lower electrode 2, the dielectric film 3, and the upper electrode 4 divided by the holes 6 are provided. Can be integrated and used as a single capacitor. For this reason, the capacitance value of the capacitor is not greatly reduced as compared with the case where the hole 6 is not formed. The effects other than those described above in the present embodiment are the same as those in the second embodiment described above.

In the present embodiment, the shape force of the hole 6 is shown as an example of a cross having two slit-like partial forces orthogonal to each other in plan view, but the present invention is not limited to this. The shape of the hole 6 may be a lattice shape having a plurality of slit-like partial forces that are orthogonal to each other in plan view. In the present specification, a cross-shaped slit is an example of a lattice-shaped slit.

[0052] Next, a fourth embodiment of the present invention will be described. Fig. 6 (a) to (c), Fig. 7 (a) to (c) and FIG. 8 (a) are plan views showing the capacitor according to the present embodiment for each layer in the order of lower layer side force, and FIG. 8 (b) is taken along the line FF ′ shown in FIG. 8 (a). It is sectional drawing. In Fig. 6 (a) No to (c), Fig. 7 (a) to (c) and Fig. 8 (a) and (b), the same components as shown in Fig. 3 (a) and (b) are used. The same reference numerals are given to the constituent elements, and detailed description thereof will be omitted.

As shown in FIG. 6 (a), the lower electrode 2 is formed on the substrate 1. In plan view, the lower electrode 2 is patterned in the shape described below. That is, the lower electrode 2 includes two rectangular areas 2a and 2b and three hexagonal areas 2c arranged between the rectangular area 2a and the rectangular area 2b. Further, the lower electrode 2 includes a bridge portion 14 that connects between the rectangular region 2a and the one hexagonal region 2c closest to the rectangular region 2a and between the three hexagonal regions 2c. Thus, the rectangular region 2a and the hexagonal region 2c are connected to each other, and the rectangular region 2b is insulated from the rectangular region 2a and the hexagonal region 2c.

Further, as shown in FIG. 6B, a dielectric film 3 is formed on the hexagonal region 2 c of the lower electrode 2. That is, the dielectric film 3 is divided into three hexagonal regions that are regular hexagons in plan view. Furthermore, as shown in FIG. 6C, an upper electrode 4 is formed on the dielectric film 3. That is, the upper electrode 4 is divided into three hexagonal regions that are regular hexagons in plan view. A laminated body 8 is formed by the lower electrode 2, the dielectric film 3 and the upper electrode 4. Thereby, the laminate 8 is divided into three units having a regular hexagonal shape in plan view.

Furthermore, as shown in FIG. 7A, an interlayer insulating film 9 is formed on the substrate 1 so as to cover the stacked body 8. Openings 10a to lOd are formed in the interlayer insulating film 9. One opening 10a is formed in the region directly above the rectangular region 2a of the lower electrode 2, and the shape thereof is rectangular in plan view. In the opening 10a, the rectangular region 2a of the lower electrode 2 is exposed. The opening 10b has one location directly above the region surrounded by the three hexagonal regions 2c, and one location directly above the region surrounded by the two hexagonal regions 2c and the rectangular region 2b. It is formed and its shape reflects the shape of the region. In the opening 10b, the substrate 1 is exposed. The opening 10b corresponds to the hole 6 in the first to third embodiments described above. A total of three openings 10c are formed in the region immediately above the three hexagonal regions 2c, that is, the region directly above the upper electrode 4, and the shape thereof is circular in plan view. Open The upper electrode 4 is exposed at the mouth portion 10c. One opening 10d is formed in a region immediately above the rectangular region 2b of the lower electrode 2, and the shape thereof is rectangular in plan view. In the opening 10d, the rectangular region 2b of the lower electrode 2 is exposed! /.

Furthermore, as shown in FIG. 7B, a thin film electrode 12 is formed on the interlayer insulating film 9. The shape of the thin film electrode 12 is almost the same as the shape of the lower electrode 2 in plan view. The force is just above the bridge portion 14 (see FIG. 6 (a)) that connects the hexagonal region 2c of the lower electrode 2 to the rectangular region 2a. The thin film electrode 12 is not formed in the region. For this reason, the portion 12c of the thin film electrode 12 disposed immediately above the upper electrode 4 is directly above the force rectangular region 2a connected to the portion 12b disposed immediately above the rectangular region 2b of the lower electrode 2. It is not connected to the part 12a located in the area. The thin film electrode 12 is embedded in the openings 10a, 10c and 10d (see FIG. 6A) of the interlayer insulating film 9. Accordingly, the portion 12a of the thin film electrode 12 is connected to the rectangular region 2a and the hexagonal region 2c (see FIG. 6 (a)) of the lower electrode 2 through the opening 10a, and the portion 12b of the thin film electrode 12 is It is connected to the upper electrode 4 through the portion 12c and the opening 10c. The thin film electrode 12 is not embedded in the opening 10b of the interlayer insulating film 9.

Furthermore, as shown in FIG. 7 (c), thick film electrodes 11 and 13 are formed in a region immediately above the portion 12a and a region directly above the portion 12b of the thin film electrode 12, respectively. As a result, the thick film electrode 11 is connected to the rectangular region 2a and the hexagonal region 2c (see FIG. 6 (a)) of the lower electrode 2 via the portion 12a of the thin film electrode 12 and the opening 10a. 13 is connected to the upper electrode 4 through the portion 12b, the portion 12c, and the opening 10c of the thin film electrode 12.

Furthermore, as shown in FIGS. 8 (a) and (b), the insulating layer 5 is formed so as to cover the multilayer body 8, the interlayer insulating film 9, the thin film electrode 12, and the thick film electrodes 11 and 13. Has been. The insulating layer 5 is embedded in the opening 10 b of the interlayer insulating film 9, contacts the substrate 1, and adheres to the substrate 1. The insulating layer 5 is also bonded to the substrate 1 around the interlayer insulating film 9. Openings 7a and 7b are formed in portions of the insulating layer 5 corresponding to the regions immediately above the thick film electrodes 11 and 13, respectively. For this reason, the thick film electrode 11 is exposed in the opening 7a, and the thick film electrode 13 is exposed in the opening 7b. In this way, the capacitors shown in FIGS. 8 (a) and (b) are configured. [0059] As shown in Figs. 8 (a) and (b), the capacitor according to this embodiment includes three capacitors 8 each having a regular hexagonal shape in plan view, as compared with the third embodiment described above. The difference is that it is divided into units. Other configurations in the present embodiment are the same as those in the third embodiment described above.

Next, a method for manufacturing the capacitor according to the present embodiment will be described. FIGS. 9A to 9C are plan views showing the method of manufacturing a capacitor according to this embodiment in the order of the steps. In the manufacturing method of this embodiment, after the steps shown in FIGS. 9 (a) to 9 (c), FIGS. 6 (c), 7 (a), 7 (c), and 08 (a) are performed. The process shown continues.

First, as shown in FIG. 9 (a), a lower electrode layer 2d (see FIG. 9 (c)) and a dielectric layer are formed on the entire surface of the substrate 1 made of resin (see FIG. 8 (b)). 3a (see FIG. 9B) and the upper electrode layer 4a are formed in this order. Next, as shown in FIG. 9B, the upper electrode layer 4a is patterned to form the upper electrode 4. The upper electrode 4 is divided into three hexagonal regions that are regular hexagons in plan view. At this time, the dielectric layer 3a is exposed in a region other than the upper electrode 4. Next, as shown in FIG. 9 (c), the dielectric layer 3 a is patterned to form the dielectric film 3 directly below the upper electrode 4. The dielectric film 3 is divided into three hexagonal regions that are regular hexagons in plan view. At this time, the upper electrode layer 2d is exposed in a region other than the dielectric film 3.

Next, as shown in FIG. 6 (c), the lower electrode layer 2d (see FIG. 9 (c)) is patterned to form the lower electrode 2. The lower electrode 2 as described above includes two rectangular regions 2a and 2b, three hexagonal regions 2c arranged between the rectangular regions 2a and 2b, and a bridge portion. It has 14. A laminated body 8 is formed by the lower electrode 2, the dielectric film 3 and the upper electrode 4.

Next, as shown in FIG. 7A, an interlayer insulating film 9 is formed on the substrate 1 so as to cover the stacked body 8, and openings 10 a to 10 d are formed in the interlayer insulating film 9. At this time, the rectangular region 2a of the lower electrode 2 is exposed in the opening 10a, the substrate 1 is exposed in the opening 10b, the upper electrode 4 is exposed in the opening 10c, and the lower electrode 2 is exposed in the opening 10d. The rectangular area 2b is exposed.

Next, a plating seed layer (not shown) is formed on the entire surface such as on the substrate 1 and the interlayer insulating film 9. To do. This seed layer is patterned into a thin film electrode 12 in a later step. A resist is formed on the plating seed layer and patterned. Using the patterned resist as a mask, plating is performed using the plating seed layer to form the portion 12a of the thin film electrode 12. Thick film electrodes 11 and 13 are formed in the region immediately above the planned region and the region directly above the region where the portion 12b is to be formed, respectively.

Next, as shown in FIG. 7C, the plating seed layer is patterned to form the thin film electrode 12. In plan view, the shape of the thin-film electrode 12 is almost the same as the shape of the lower electrode 2, but the shape of the bridge portion 14 (see FIG. 6 (a)) that connects the hexagonal region 2c of the lower electrode 2 to the rectangular region 2a. The thin film electrode 12 is not formed in the upper region. The thin film electrode 12 is embedded in the openings 1 Oa, 10c and 10d (see FIG. 7A) of the interlayer insulating film 9. On the other hand, the thin-film electrode 12 is not buried in the opening 10b of the interlayer insulating film 9, and the substrate 1 remains exposed in the opening 10b. As a result, the thick film electrode 11 is connected to the rectangular region 2a and the hexagonal region 2c (see FIG. 6 (a)) of the lower electrode 2 through the portion 12a of the thin film electrode 12 and the opening 10a. Is connected to the upper electrode 4 through the portion 12b, the portion 12c, and the opening 10c of the thin film electrode 12.

Next, as shown in FIGS. 8 (a) and 8 (b), on the substrate 1, the laminated body 8, the interlayer insulating film 9, the thin film electrode 12, and the thick film electrodes 11 and 13 are covered. Insulating layer 5 is formed. At this time, the insulating layer 5 is embedded in the opening 10b of the interlayer insulating film 9 and adhered to the substrate 1. The insulating layer 5 is also bonded to the substrate 1 around the interlayer insulating film 9. Then, openings 7a and 7b are formed in portions of the insulating layer 5 corresponding to the regions immediately above the thick film electrodes 11 and 13, respectively. As a result, the thick film electrode 11 is exposed in the opening 7a, and the thick film electrode 13 is exposed in the opening 7b. As a result, the capacitor shown in FIGS. 8A and 8B is manufactured.

In this embodiment, since the insulating layer 5 is adhered to the substrate 1 in the opening 10b in addition to the periphery of the interlayer insulating film 9, the adhesion between the substrate 1 and the insulating layer 5 is maintained. High strength. Therefore, the lower electrode 2, the dielectric film 3 and the upper electrode 4 arranged between the substrate 1 and the insulating layer 5, the substrate 1 and the lower electrode 2, the upper electrode 4 and the insulating layer 5 Excellent adhesion between the two. In addition, since the shape of each unit of the laminated body 8 is a hexagonal shape compared to the third embodiment described above, it is applied to the laminated body 8 when the substrate 1 is bent in all directions. Stress can be relieved. For this reason, the resistance of the lower electrode 2, the dielectric film 3, and the upper electrode 4 with respect to the bending of the substrate 1 in all directions can be enhanced. Operations and effects other than those described above in the present embodiment are the same as those in the third embodiment described above.

[0068] Although the example in which the shape of each unit of the laminated body 8 is a regular hexagon is shown in this embodiment, the present invention is not limited to this, and the shape of each part is other than a regular hexagon. It may be a regular polygon or a polygon other than a regular polygon.

Next, a modification of the fourth embodiment will be described. FIG. 10 (a) is a plan view showing a capacitor according to this modification, and FIG. 10 (b) is a sectional view taken along line GG ′ shown in FIG. 10 (a). In FIGS. 10 (a) and (b), the same components as those shown in FIGS. 3 (a) and (b) are denoted by the same reference numerals, and detailed description thereof is omitted.

[0070] As shown in FIGS. 10 (a) and 10 (b), the capacitor according to the present modification has a larger number of units of the multilayer body 8 than the capacitor according to the above-described fourth embodiment. The difference is that each unit is arranged in the form of a hard cam. That is, in a plan view, a plurality of regular hexagonal units are arranged in a close-packed manner along three directions intersecting each other at an angle of 60 °. Other configurations of the present modification are the same as those of the fourth embodiment described above.

Next, a method for manufacturing a capacitor according to this variation will be described. 11 (a) to (c) and FIGS. 12 (a) to (c) are plan views showing a method of manufacturing a capacitor according to this modification in the order of the steps. First, as shown in FIG. 11 (a), a lower electrode layer 2d (see FIG. 11 (c)) and a dielectric layer 3a (see FIG. 11 (b)) are formed on the entire surface of the substrate 1 (see FIG. 10 (b)). ) And the upper electrode layer 4a are formed in this order. Next, as shown in FIG. 11B, the upper electrode layer 4a is patterned to form the upper electrode 4. The upper electrode 4 has a regular hexagonal shape in plan view and is divided into eight hexagonal regions arranged in a honeycomb shape and two regions that are bisected into two hexagonal regions. At this time, the dielectric layer 3a is exposed in a region other than the upper electrode 4. Next, as shown in FIG. 11 (c), the dielectric layer 3a is patterned to form the dielectric film 3. The dielectric film 3 is disposed immediately below the upper electrode 4. At this time, the upper electrode layer 2d is exposed in a region other than the dielectric film 3.

[0072] Next, as shown in FIG. 12 (a), the lower electrode layer 2d (see FIG. 11 (c)) is patterned, Lower electrode 2 is formed. The lower electrode 2 has two rectangular regions 2a and 2b disposed so as to sandwich the region where the dielectric film 3 and the upper electrode 4 are sandwiched, and eight regions disposed immediately below the dielectric film 3. A hexagonal region 2c is provided, and a bridge portion 14 is further provided. A laminated body 8 is formed by the lower electrode 2, the dielectric film 3 and the upper electrode 4.

Next, as shown in FIG. 12B, an interlayer insulating film 9 is formed on the substrate 1 so as to cover the stacked body 8, and openings 10 a to 10 d are formed in the interlayer insulating film 9. At this time, the rectangular region 2a of the lower electrode 2 is exposed in the opening 10a, the substrate 1 is exposed in the opening 10b, the upper electrode 4 is exposed in the opening 10c, and the lower electrode 2 is exposed in the opening 10d. The rectangular area 2b of is exposed.

Next, a plating seed layer (not shown) is formed on the entire surface such as on the substrate 1 and the interlayer insulating film 9. This seed layer is patterned into a thin film electrode 12 in a later step. A resist is formed on the plating seed layer and patterned. Using the patterned resist as a mask, plating is performed using the plating seed layer to form the portion 12a of the thin film electrode 12. Thick film electrodes 11 and 13 are formed in the region immediately above the planned region and the region directly above the region where the portion 12b is to be formed, respectively.

Next, as shown in FIG. 12 (c), the plating seed layer is patterned to form the thin film electrode 12. In plan view, the shape of the thin-film electrode 12 is almost the same as the shape of the lower electrode 2, but the thin-film electrode 12 is placed in the region immediately above the hexagonal region 2c and the rectangular region 2a of the lower electrode 2. Do not form. The thin film electrode 12 is embedded in the openings 10a, 10c and 10d (see FIG. 12B) of the interlayer insulating film 9. On the other hand, the thin-film electrode 12 is not embedded in the opening 10b of the interlayer insulating film 9, and the substrate 1 remains exposed in the opening 10b.

Next, as shown in FIGS. 10 (a) and (b), the insulating layer 5 is formed so as to cover the multilayer body 8, the interlayer insulating film 9, the thin film electrode 12 and the thick film electrodes 11 and 13. To do. At this time, the insulating layer 5 is embedded in the opening 10b of the interlayer insulating film 9 and adhered to the substrate 1. The insulating layer 5 is also bonded to the substrate 1 around the interlayer insulating film 9. Then, openings 7a and 7b are formed in portions of the insulating layer 5 corresponding to the regions immediately above the thick film electrodes 11 and 13, respectively. As a result, the thick film electrode 11 is exposed at the opening 7a, and the thick film electrode 13 is exposed at the opening 7b. As a result, the capacitor shown in FIGS. 10A and 10B is manufactured. [0077] In this modified example, compared to the above-described fourth embodiment, the number of units of the laminated body 8 is increased and arranged in the form of a hard cam, so that the resistance to stress is more excellent. Yes. Further, since the units of the laminated body 8 can be arranged in the closest packing, the area of the laminated body 8 per unit area can be increased, and the capacity density can be improved. Operations and effects other than those described above in the present modification are the same as those in the fourth embodiment described above.

[0078] Next, a fifth embodiment of the present invention will be described. FIG. 13 is a cross-sectional view showing a printed wiring board according to this embodiment. In FIG. 13, the same components as those shown in FIGS. 3 (a) and 3 (b) are denoted by the same reference numerals, and detailed description thereof is omitted. As shown in FIG. 13, in the printed wiring board according to the present embodiment, a core substrate 21 is provided, and inner layer wirings 22 are provided on the front surface and the back surface of the core substrate 21. An adhesive layer 23 made of an adhesive or a resin is provided on the entire surface of the core substrate 21 so as to cover the inner layer wiring 22. A capacitor 20 is provided on the adhesive layer 23. The configuration of the capacitor 20 is the same as that of the capacitor 20 (see FIGS. 3A and 3B) according to the second embodiment described above. In FIG. 13, the thin film electrode 12 of the capacitor 20 is not shown. The substrate 1 of the capacitor 20 is bonded to the core substrate 21 by the adhesive layer 23.

[0079] On the front surface and the back surface of the core substrate 21, a pre-preda 24 as an insulating film is laminated. The pre-preda 24 may be a copper-clad laminate that does not include cloth. A surface wiring 25 is provided on the surface of the pre-preda 24. Vias 26a and 26b are formed in regions immediately above the thick film electrodes 11 and 13 of the capacitor 20 in the pre-preader 24 provided on the surface of the core substrate 21, respectively. The vias 26a and 26b are, for example, laser vias. Further, a Cu plating layer 27 is provided on the inner surfaces of the vias 26a and 26b, and the insides of the vias 26a and 26b are hollow. The Cu plating layer 27 is connected to the thick film electrode 11 or 13 and is connected to the surface wiring 25. Thereby, the thick film electrode 11 is connected to a part of the surface wiring 25 via the Cu plating layer 27 in the via 26a, and the thick film electrode 13 is connected to the surface wiring 25 via the Cu plating layer 27 in the via 26b. Connected to other parts. One part of the surface wiring 25 and the other part are insulated from each other.

[0080] Further, the capacitor 20 in the multilayer body having the core substrate 21 and the pre-predator 24 force is disposed. A through-through hole 28 is formed in a part of the unexposed region so as to penetrate the laminate. A fitting electrode 29 is provided on the inner surface of the through hole 28, and the inside of the through hole 28 is a cavity. The plating electrode 29 is connected to the surface wiring 25 and the inner layer wiring 22. Thus, the surface layer wiring 25 is connected to the inner layer wiring 22 through the fitting electrode 29.

Note that the thickness of the capacitor 20 is 20 to 100 μm, preferably 30 to 70 μm, and the thickness of the pre-preda 24 is 50 to 200 μm, preferably 60 to 120 μm. If the thickness of the pre-preda 24 is equal to or greater than the thickness of the capacitor 20, the printed wiring board according to the present embodiment can be technically realized. However, one of the features of the capacitor in this embodiment is that it is thinner than an SMD (Surface Mount Device). Therefore, in order to obtain this feature, it is desirable that the thicknesses of the capacitor 20 and the pre-preder 24 are within the above-mentioned range.

According to the present embodiment, it is possible to obtain a printed wiring board having a built-in capacitor 20 having good adhesion between the substrate 1, the lower electrode 2, the dielectric film 3, and the upper electrode 4. As a result, even if the process of incorporating the capacitor 20 in the wiring board is performed, the interface peeling between the substrate 1, the lower electrode 2, the dielectric film 3 and the upper electrode 4 in the capacitor 20 does not occur. For this reason, it is possible to prevent the occurrence of defects due to the interface peeling of the capacitor.

In the present embodiment, an example in which the vias 26a and 26b and the through through hole 28 are hollow is shown, but a resin or a conductive material may be embedded.

[0084] Next, a sixth embodiment of the present invention will be described. FIG. 14 is a cross-sectional view showing a printed wiring board according to this embodiment. In FIG. 14, the same components as those shown in FIG. 13 are denoted by the same reference numerals, and detailed description thereof is omitted. As shown in FIG. 14, in the printed wiring board according to the present embodiment, unlike the printed wiring board according to the fifth embodiment described above (see FIG. 13), the adhesive layer 23 is not provided. Also, vias 26a and 26b and through-through holes 28 (see Fig. 13) are formed!

Then, in the printed wiring board according to the present embodiment, the through hole 31 reaching the core substrate 21 in a part of the pre-preda 24 except for the region directly above the capacitor 20. In this through hole 31, an electrode 32 for connecting the inner layer wiring 22 to the surface wiring 25 is provided. In addition, an inner layer pad 33 is provided in a region where the capacitor 20 is not disposed on the surface of the core substrate 21, and a through hole 34 is formed immediately above the inner layer pad 33 in the pre-preda 24. . The through hole 34 is formed by a laser, for example. The inner layer pad 33 is exposed on the bottom of the through hole 3 4!

[0086] A fitting electrode 35 is provided on the inner surface of the through hole 34, and is connected to the surface wiring 25 via the fitting electrode 35 of the inner layer pad 33. On the other hand, a paste layer 36 made of a conductive paste such as a silver paste is provided so as to connect the inner layer pad 33 to the thick film electrode 11 of the capacitor 20. Thus, the thick film electrode 11 of the capacitor 20 is connected to a part of the surface wiring 25 via the paste layer 36, the inner layer pad 33, and the plating electrode 35.

Furthermore, a paste layer 37 made of a conductive paste such as a silver paste is provided so as to connect the thick film electrode 13 of the capacitor 20 to the inner layer wiring 22. Thus, the thick film electrode 13 of the capacitor 20 is connected to the other part of the surface wiring 25 via the paste layer 37, the inner layer wiring 22, and the plating electrode 32. The paste layers 36 and 37 also serve to fix the capacitor 20 to the core substrate 21. Other configurations in the present embodiment are the same as those in the fifth embodiment described above.

In this embodiment, it is disadvantageous in that the area of the printed wiring board is large compared to the fifth embodiment described above. The through holes 31 and 34 are not formed in the region immediately above the capacitor 20. Therefore, the capacitor 20 is not damaged when the through holes 31 and 34 are formed. The effects of the present embodiment other than those described above are the same as those of the fifth embodiment described above.

Example

[0089] Hereinafter, the effects of the embodiments of the present invention will be specifically described in comparison with a comparative example in which the power of the claims is also excluded.

[0090] (Example 1)

Example 1 is an example corresponding to the first embodiment described above. Hereinafter, Example 1 Is described with reference to Figs. 1 (a) and (b). First, a commercially available polyimide film (thickness 50 m) was prepared as the substrate 1. Then, this polyimide film was loaded into a DC sputtering apparatus, and a Ti layer, a Mo layer, a Ti layer, and a Pt layer were formed in this order at room temperature by the DC sputtering method and laminated. The thickness of each layer was Ti layer: 20 nm, Mo layer: 600 nm, Ti layer: 20 nm, and Pt layer: 200 nm. Mo layer is a highly elastic conductive material layer, Pt layer is an acid-resistant conductive material layer, T-ring is an adhesive conductive material layer between the polyimide film and the Mo layer, and an adhesion between the Mo layer and the Pt layer It is a conductive material layer. As a result, a four-layer film in which a Ti layer, a Mo layer, a Ti layer, and a Pt layer were laminated in this order was formed on the substrate 1.

[0091] Next, the substrate 1 was loaded into an RF sputtering apparatus, and an SrTiO layer having a thickness of 500 nm was formed on the four-layer film by RF sputtering at a film formation temperature of 400 ° C. Next, board 1 again

Three

Inserted into a DC sputtering system, the thickness was 200η on the SrTiO layer at room temperature by DC sputtering.

Three

m Pt layer was deposited. Next, a photoresist film is formed on the Pt layer by a photolithography method, the photoresist film is patterned, and the patterned photoresist film is used as a mask to perform Pt by ion beam etching or chemical etching. The layer was selectively removed by etching to form the desired pattern. Thereafter, the photoresist film was removed by an organic solvent and oxygen plasma treatment. Thereby, the upper electrode 4 was formed.

[0092] Next, similarly to the processing method of the upper electrode 4, a photoresist film patterned into a desired shape is formed by a photolithography method, and the SrTiO layer is etched by a chemical etching method using this as a mask. Put it in the desired shape and then organic solvent

Three

Then, the photoresist film was removed by oxygen plasma treatment. Thereby, the dielectric film 3 was formed. Similarly, a pattern of a photoresist film was formed on the four-layer film, and the four-layer film was patterned by ion beam etching and chemical etching. Thereby, the lower electrode 2 was formed. At this time, a hole 6 was formed in a region outside the region immediately below the dielectric film 3 and the upper electrode 4 in the four-layer film. Then, the photoresist film was removed by organic solvent and oxygen plasma treatment.

[0093] Next, on the substrate 1, so as to cover the lower electrode 2, the dielectric film 3 and the upper electrode 4, a resin having good adhesion with the substrate 1, such as an epoxy resin, is applied, Patterned after exposure and development. At this time, openings 7a and 7b were formed. And heating in a nitrogen atmosphere, The resin layer was cured by holding, and the insulating layer 5 was formed as a capacitor cover layer. Thus, the capacitor shown in FIGS. 1 (a) and (b) was produced.

This capacitor has a structure in which a through hole 6 is formed in the lower electrode 2 and the substrate 1 and the insulating layer 5 are directly bonded via the through hole 6. Is provided in the hole 6 in addition to the outer periphery of the capacitor, so that it is possible to improve the adhesion at each interface existing in the capacitor. For this reason, even if the area of the capacitor was 1. Om m X l. Although FIG. 1 shows a capacitor in which the hole 6 has a slit shape and one location, the same effect is obtained without being limited to the shape and number of the holes 6.

[0095] (Comparative Example 1)

This Comparative Example 1 corresponds to the above-described comparative example. Hereinafter, the first comparative example will be described with reference to FIGS. 2 (a) and 2 (b). In this comparative example 1, when the lower electrode 2 was patterned, the hole 6 was not formed and it was strong. Of the capacitor manufacturing method according to Comparative Example 1, the other methods were the same as those in Example 1 described above. In Comparative Example 1, since the hole 6 shown in FIG. 1 is not formed, the coupling portion is only the outer peripheral portion of the capacitor, and when the area of the capacitor exceeds 1. Omm X l. It happened easily.

[Example 2]

Example 2 is an example corresponding to the second embodiment described above. Hereinafter, Example 2 will be described with reference to FIGS. 3 (a) and 3 (b). First, the lower electrode 2, the dielectric film 3 and the upper electrode 4 were formed on the substrate 1 by the same method as in Example 1 described above. At this time, a hole 6 was formed in the lower electrode 2.

Next, a photosensitive polyimide is applied on the substrate 1 so as to cover the lower electrode 2, the dielectric film 3, and the upper electrode 4, exposed and developed, and patterned to form an interlayer insulating film 9. Formed. At this time, openings 10a, 10b, and 10c were formed in the interlayer insulating film 9. Next, the substrate 1 was loaded into a DC sputtering apparatus, and a Ti layer and a Cu layer were successively formed at room temperature by a DC sputtering method to form a CuZTi laminated film on the entire surface. The film thickness of each layer constituting the CuZTi laminated film was Ti: 20 nm, Cu: 300 nm. The Ti layer is an adhesion layer for improving the adhesion between the Cu layer and the lower electrode 2, the upper electrode 4, and the interlayer insulating film 9. A Cr layer or a Zr layer may be used without limitation.

[0098] Next, a photoresist film was formed by a photolithography method, and openings were formed immediately above the openings 10a and 10c. Then, using this photoresist film as a mask, using a CuZTi laminated film as a power feeding layer, a Cu plating layer was formed to a thickness of 15 / zm by the electrolytic plating method, and the thickness was within each of the opening 10a and the opening 10c. Membrane electrodes 11 and 13 were formed. After Cu plating, the photoresist film was once removed by organic solvent and oxygen plasma treatment.

Next, a photoresist film is formed at a position where the upper electrode 4 and the thick film electrode 13 are electrically connected by a photolithography method, and etching is performed by a chemical etching method using the photoresist film as a mask. Then, unnecessary portions of the CuZTi multilayer film were selectively removed, and a thin film electrode 12 composed of a CuZTi multilayer film was formed.

[0100] Next, an epoxy resin having high adhesion to the substrate 1 was applied to the entire surface, and patterned by exposure and development to form the insulating layer 5. At this time, openings 7a and 7b were formed in the insulating layer 5 so that the thick film electrodes 11 and 13 were exposed from the insulating layer 5 and could be connected to the outside. As a result, the capacitor 20 shown in FIGS. 2 (a) and (b) was produced.

[0101] In this Example 2, compared to Example 1 described above, the thick film electrodes 11 and 13 by Cu plating are formed by the electrolytic plating method, so that the stress applied to the Cu plating is applied to the capacitor. By bringing the substrate 1 and the insulating layer 5 into close contact with each other through the force hole 6, it was possible to prevent peeling at the interface existing in the capacitor, and to prevent the occurrence of defects.

[0102] (Example 3)

Example 3 is an example corresponding to the above-described third embodiment. Hereinafter, Example 3 will be described with reference to FIGS. 4 (a) and 4 (b) to FIG. First, a four-layer film, an SrTiO layer, and a Pt layer were formed in this order on the substrate 1 by the same method as in Example 1 described above. Next, the actual

Three

The Pt layer was patterned by the same photolithography method as in Example 1. At this stage, the upper electrode 4 has four parts, and each part is not electrically connected to each other. Next, the SrTiO layer is etched by the same method as in Example 1 described above.

Three

Thus, the dielectric film 3 was formed. At this time, like the upper electrode 4, the dielectric film 3 also has four portions. In the same way, pattern the four-layer film and create a cross shape. The lower electrode 2 in which the hole 6 was formed was formed. At the same time, the bridge portion 14 was formed from the four-layer film. At this time, the lower electrode 2 is divided into four parts, but each part is connected to each other by the pledge part 14.

Next, an interlayer insulating film 9 having openings 10a to 10c formed thereon was formed by the same method as in Example 2 described above, and thick film electrodes 11 and 13 were formed. Next, a resist pattern that covers the region between the upper electrode 4 and the thin film electrode 12 is formed by a photolithography method, and chemical etching is performed using this resist pattern as a mask, and an unnecessary portion of the CuZTi laminated film is formed. Selectively removed. As a result, a thin film electrode 12 composed of a CuZTi laminated film was formed. In this step, the parts of the upper electrode 4 which are divided into four parts and are not electrically connected to each other are connected to each other via the bridge part 15. In the region of the capacitor where the bridge portion 15 is disposed, the substrate 1, the lower electrode 2, the interlayer insulating film 9, and the bridge portion 15 are laminated in this order from the bottom to the top. Further, the periphery of the pledge portion 14 is covered with the substrate 1 and the interlayer insulating film 9. Next, the insulating layer 5 in which the openings 7a and 7b were formed was formed by the same method as in Example 2 described above.

In this third embodiment, compared to the second embodiment, the cross-shaped hole 6 penetrates not only the lower electrode 2 but also the dielectric film 3, the upper electrode 4 and the interlayer insulating film 9. Therefore, although the capacitance decreased by the area of the hole 6, the adhesion between the substrate lower electrode 2, the dielectric film 3 and the upper electrode 4 could be further enhanced. Further, the strength of the laminate 8 with respect to the bending of the substrate 1 in the direction in which the openings 7a and 7b are arranged and in the direction perpendicular thereto can be further increased.

[0105] (Example 4)

Example 4 is an example corresponding to the above-described fourth embodiment. In Example 4, a capacitor was formed by the method shown in the fourth embodiment. That is, the shape of each unit of the laminated body 8 was a hexagon in plan view. The capacitor manufacturing method other than the above in Example 4 was the same as that in Example 3 described above.

[0106] In the fourth embodiment, the shape of each unit of the laminated body 8 is a regular hexagonal shape in plan view as compared with the above-described third embodiment, so that the substrate 1 can be bent in all directions. As a result, the strength of the capacitor could be increased and open defects due to peeling could be prevented. [Example 5]

Example 5 is an example corresponding to the fifth embodiment described above. Hereinafter, Example 5 will be described with reference to FIG. First, the inner layer wiring 22 was formed on the front and back surfaces of the core substrate 21. Then, an adhesive layer 23 was formed on the surface of the core substrate 21 by a printing method so as to cover the inner layer wiring 22. Next, a capacitor 20 having a thickness of 50 m was mounted on the adhesive layer 23. As a result, the substrate 1 of the capacitor 20 was fixed on the core substrate 21 via the adhesive layer 23. The configuration of the capacitor 20 was the same as that of the capacitor 20 of Example 2 described above.

Next, a pre-preder 24 as a build layer was laminated on the front surface and the back surface of the core substrate 21 so as to cover the capacitor 20. Then, a surface wiring 25 having a Cu plating layer force was formed on the surface of the pre-preda 24 by plating. Next, a via 26 a was formed in the region immediately above the thick film electrode 11 in the pre-preparer 24 and a via 26 b was formed in the region immediately above the thick film electrode 13 by laser processing. Next, through-holes 28 penetrating through the core substrate 21 and the pre-preparers 24 provided on both sides thereof were formed by a laser cage. Then, Cu plating was performed, a Cu plating layer 27 was formed on the inner surfaces of the vias 26a and 26b, and a plating electrode 29 was formed on the inner surface of the through-through hole 28. As a result, the surface wiring 25 was connected to the thick film electrodes 11 and 13 via the vias 26a and 26b, respectively. In addition, the plating electrode 29 connects the surface wiring 25 formed on the pre-preder 24 laminated on the front surface side of the core substrate 21 to the surface wiring 25 formed on the pre-preparation 24 laminated on the back surface side of the core substrate 21. did. As a result, a printed wiring board with a built-in capacitor 20 was manufactured.

In the fifth embodiment, in the step of incorporating the capacitor 20 in the printed wiring board, the capacitor 20 positioned immediately below the vias 26a and 26b even after the vias 26a and 26b are formed by the laser coating method. However, it was possible to prevent an open failure due to interfacial peeling. Further, before and after the process of incorporating the capacitor 20 in the printed circuit board, the change rate of the capacitance value of the capacitor 20 was 1% or less.

[0110] Further, the same effect can be obtained by incorporating the capacitors according to Example 3 and Example 4 instead of the capacitor 20 according to Example 2 described above. That is, when the capacitor of Example 3 was used, the resistance to bending of the printed wiring board in the two directions in which the holes 6 extend was high. The change rate of the capacitance value is 1%, and the capacity of Example 2 is as follows. The same as when using the On the other hand, when the capacitor of Example 4 was used, the resistance to bending in all directions was high, and the capacitance change rate without depending on the bending direction of the capacitor 20 and the printed wiring board was 1%. .

[0111] (Example 6)

Example 6 is an example corresponding to the above-described sixth embodiment. Hereinafter, Example 6 will be described with reference to FIG. First, the inner layer wiring 22 was formed on the front and back surfaces of the core substrate 21, and the inner layer pad 33 was formed on the front surface. Then, a capacitor 20 having a thickness of 50 m was temporarily fixed on the surface of the core substrate 21. Next, a paste layer 36 made of silver paste is formed so as to connect the thick film electrode 11 of the capacitor 20 and a part of the inner layer wiring 22, and the thick film electrode 13 and the other part of the inner layer wiring 22 are connected. Thus, a base layer 37 made of a silver paste was formed. Then, the paste layers 36 and 37 are heated and dried to fix the capacitor 20 to the core substrate 21 and to electrically connect the thick film electrodes 11 and 13 to the inner layer wiring 22 o

[0112] Next, a pre-pre- der 24 as a build layer was laminated on the surface of the core substrate 21 so as to cover the capacitor 20. A pre-preda 24 was also laminated on the back surface of the core substrate 21. Then, a surface wiring 25 made of Cu was formed on the surface of the pre-preda 24 by a plating method. Next, a through hole 34 was formed in the region immediately above the inner layer pad 33 in the pre-preda 24 by laser processing. In addition, a through hole 31 penetrating the pre-preda 24 was formed by laser processing. Then, Cu plating was performed to form plating electrodes 32 and 35 on the inner surfaces of the through holes 31 and 34, respectively. As a result, a printed wiring board with a built-in capacitor 20 was manufactured.

[0113] In the sixth embodiment, in the process of incorporating the capacitor 20 in the printed wiring board, even after the through hole 34 is formed by the laser coating method, the capacitor 20 has an open defect due to the separation of the interface. I was able to prevent it. Also, before and after the process of embedding capacitor 20 in the printed circuit board, the change rate of capacitance value of capacitor 20 is less than 1%.

[0114] Further, when the capacitor of Example 3 is used instead of the capacitor 20 according to Example 2 described above, resistance against bending of the printed wiring board in the two directions in which the holes 6 extend is shown. Was strong. Further, the change rate of the capacitance value was 1%, which was the same as the case of using the capacitor of Example 2. When the capacitor of Example 4 is used instead of the capacitor 20 according to Example 2, the resistance to bending in all directions is high, and it does not depend on the bending direction of the capacitor and the printed wiring board. The capacity change was 1%. Industrial applicability

The present invention can be suitably used for a capacitor built in a wiring board such as a printed wiring board of an electronic device and a wiring board containing the capacitor.

Claims

The scope of the claims

[1] a substrate, a lower electrode formed on the substrate, a dielectric film formed on the lower electrode, an upper electrode formed on the dielectric film, the lower electrode, and the dielectric An insulating layer formed of a material that is in close contact with the substrate so as to cover the laminated body including the film and the upper electrode, and the insulating layer is removed from the laminated body by removing a part of the laminated body. A capacitor characterized in that the other portion is in contact with the substrate.

[2] A substrate made of a resin, a lower electrode formed on the substrate, a dielectric film formed on a part of the lower electrode, an upper electrode formed on the dielectric film, An insulating layer made of resin that is provided on the substrate so as to cover the laminated body composed of the lower electrode, the dielectric film, and the upper electrode, and the laminated body is partially formed on the laminated body A capacitor is characterized in that a hole penetrating the substrate is formed, the insulating layer is embedded in the hole, and the insulating layer is in contact with the substrate at the bottom of the hole.

3. The capacitor according to claim 2, wherein the hole is formed in a part of a region of the lower electrode excluding a region immediately below the dielectric film.

4. The capacitor according to claim 2, wherein the hole is formed in a part of a region where the lower electrode, the dielectric film, and the upper electrode are stacked in the stacked body.

[5] The lower electrode, the dielectric film, and the upper electrode are each divided into a plurality of parts by the holes, and adjacent portions of the lower electrode are connected to each other, and the upper electrode 5. The capacitor according to claim 4, wherein adjacent portions of the electrodes are also connected to each other.

[6] The holes are formed in a lattice shape when viewed from a direction perpendicular to the surface of the substrate, and the shape of each part of the lower electrode, the dielectric film, and the upper electrode is rectangular. 6. The capacitor according to claim 5, wherein the capacitor is characterized in that:

[7] When viewed from a direction perpendicular to the surface of the substrate, at least one of the portions of the lower electrode, the dielectric film, and the upper electrode has a hexagonal shape, and the portions are 6. The capacitor according to claim 5, wherein the capacitor is arranged in a her cam shape.

[8] The hole with respect to the total area of the lower electrode as viewed from a direction perpendicular to the surface of the substrate. The capacitor according to any one of claims 2 to 7, wherein a ratio of the area of the light is 1 to 25%.

9. The capacitor according to claim 8, wherein the ratio is 5 to 10%.

[10] A first opening is formed in a portion of the insulating layer immediately above the lower electrode and out of the region directly above the dielectric film, and from the first opening A second opening is formed at a spaced position, and is provided in the second opening and the first external connection electrode provided in the first opening and connected to the lower electrode. 10. The capacitor according to claim 1, further comprising a second external connection electrode connected to the upper electrode.

[11] The lower electrode includes an adhesive conductive material layer provided on the substrate and an oxidation-resistant conductive material layer provided on the adhesive conductive material layer. 1 to 10 Any one of the capacitors described in item 1 above.

12. The capacitor according to claim 11, wherein the lower electrode has a highly elastic conductive material layer provided between the adhesive conductive material layer and the oxidation-resistant conductive material layer.

[13] The capacitor according to any one of [1] to [12], wherein the dielectric film is formed of an oxide having a bevelskite structure.

[14] A wiring board comprising: a core substrate; and the capacitor according to any one of claims 1 to 13 provided on at least one surface of the core substrate.

[15] An insulating film provided so as to cover the capacitor and a surface wiring provided on a surface of the insulating film, wherein a lower electrode of the capacitor is connected to a part of the surface wiring. 15. The wiring board according to claim 14, wherein an upper electrode of the capacitor is connected to the other portion of the surface wiring that is partly force-insulated.

[16] The capacitor is provided between the core substrate and the insulating film, the inner layer wiring provided in the region, and the first conductor layer connecting the lower electrode to a part of the inner layer wiring. And a second conductor layer that connects the upper electrode to another portion of the inner layer wiring that is insulated from the portion of the inner layer wiring, and the portion of the inner layer wiring and the other portion of the insulating film A first through hole and a second through hole are formed in a part of the region directly above, and the lower electrode is formed of the first conductor layer and the inner layer wiring. The upper electrode is connected to a part of the surface wiring through the first through hole, and the upper electrode is connected to the second conductor layer, the other part of the inner layer wiring, and the second through hole. 16. The wiring board according to claim 15, wherein the wiring board is connected to another part of the surface wiring via the wiring.