JP4784128B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4784128B2
JP4784128B2 JP2005100738A JP2005100738A JP4784128B2 JP 4784128 B2 JP4784128 B2 JP 4784128B2 JP 2005100738 A JP2005100738 A JP 2005100738A JP 2005100738 A JP2005100738 A JP 2005100738A JP 4784128 B2 JP4784128 B2 JP 4784128B2
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insulating film
semiconductor device
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wiring
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由隆 青木
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Casio Computer Co Ltd
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24265—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
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Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

従来の半導体装置には、基板上に集積回路が形成され、その上に絶縁膜が形成され、その上に強誘電体膜を有する薄膜容量素子が形成されたものがある（例えば、特許文献１参照）。この場合、強誘電体膜は、ＢａＴｉＯ3などの強誘電体材料を含むペーストを８００〜１０００℃と比較的高温で焼成して形成されるため、絶縁膜は耐熱性の関係から酸化シリコンによって形成している。 Some conventional semiconductor devices include an integrated circuit formed on a substrate, an insulating film formed thereon, and a thin film capacitor element having a ferroelectric film formed thereon (for example, Patent Document 1). reference). In this case, since the ferroelectric film is formed by baking a paste containing a ferroelectric material such as BaTiO 3 at a relatively high temperature of 800 to 1000 ° C., the insulating film is formed of silicon oxide because of heat resistance. is doing.

特許第３４９９２５５号公報Japanese Patent No. 3499255

ところで、上記のような構造の半導体装置において、絶縁膜の材料としてポリイミド系樹脂などの熱硬化性樹脂を用いる場合がある。しかしながら、ポリイミド系樹脂などの熱硬化性樹脂の耐熱温度は２５０℃程度と比較的低温であるため、その上に上記のような、比較的高温の処理を要する強誘電体膜を形成しようとすると、絶縁膜が熱的ダメージを受けてしまうという問題がある。   By the way, in the semiconductor device having the above structure, a thermosetting resin such as a polyimide resin may be used as a material of the insulating film. However, since the heat-resistant temperature of thermosetting resins such as polyimide resins is as low as about 250 ° C., an attempt is made to form a ferroelectric film that requires a relatively high temperature treatment as described above. There is a problem that the insulating film is thermally damaged.

そこで、この発明は、ポリイミド系樹脂などの熱硬化性樹脂からなる絶縁膜が熱的ダメージを受けないようにすることができる半導体装置およびその製造方法を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent an insulating film made of a thermosetting resin such as a polyimide resin from being thermally damaged.

この発明は、上記目的を達成するため、薄膜容量素子の強誘電体膜を水熱合成法により形成するようにしたことを特徴とするものである。   In order to achieve the above object, the present invention is characterized in that the ferroelectric film of the thin film capacitive element is formed by a hydrothermal synthesis method.

この発明によれば、水熱合成法により強誘電体膜を形成するときの処理温度が２００℃以下と比較的低温であるので、ポリイミド系樹脂などの熱硬化性樹脂からなる絶縁膜が熱的ダメージを受けないようにすることができる。   According to the present invention, since the processing temperature when forming the ferroelectric film by the hydrothermal synthesis method is a relatively low temperature of 200 ° C. or less, the insulating film made of a thermosetting resin such as polyimide resin is thermally You can prevent damage.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は平面方形状のシリコン基板（半導体基板）１を備えている。シリコン基板１の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウムやアルミニウム合金などのアルミニウム系金属からなる複数の接続パッド２ａ、２ｂが集積回路に接続されて設けられている。この場合、符号２ｂで示す接続パッドは、後述する薄膜容量素子７の下部電極８に接続されるものである。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. The semiconductor device includes a planar rectangular silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 1, and a plurality of connection pads 2a and 2b made of aluminum metal such as aluminum or aluminum alloy are connected to the integrated circuit on the periphery of the upper surface. Has been provided. In this case, the connection pad indicated by reference numeral 2b is connected to the lower electrode 8 of the thin film capacitive element 7 to be described later.

接続パッド２ａ、２ｂの中央部を除くシリコン基板１の上面には酸化シリコンなどからなる絶縁膜３が設けられ、接続パッド２ａ、２ｂの中央部は絶縁膜３に設けられた開口部４ａ、４ｂを介して露出されている。絶縁膜３の上面にはポリイミド系樹脂などの熱硬化性樹脂からなる保護膜（絶縁膜）５が設けられている。この場合、絶縁膜３の開口部４ａ、４ｂに対応する部分における保護膜５には、絶縁膜３の開口部４ａ、４ｂよりもやや大きめの開口部６ａ、６ｂが設けられている。   An insulating film 3 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 1 except for the central portions of the connection pads 2a and 2b. The central portions of the connection pads 2a and 2b are openings 4a and 4b provided in the insulating film 3. Is exposed through. A protective film (insulating film) 5 made of a thermosetting resin such as polyimide resin is provided on the upper surface of the insulating film 3. In this case, openings 6 a and 6 b that are slightly larger than the openings 4 a and 4 b of the insulating film 3 are provided in the protective film 5 at portions corresponding to the openings 4 a and 4 b of the insulating film 3.

絶縁膜３および保護膜５の開口部４ｂ、６ｂ内およびその周囲における保護膜５の上面には、薄膜容量素子７の最下層を構成する下部電極８が接続パッド２ｂに接続されて設けられている。この場合、下部電極８は、詳細には図示していないが、下から順に、チタン層、銅層およびチタン層の３層構造となっている。   On the upper surface of the protective film 5 in and around the openings 4b and 6b of the insulating film 3 and the protective film 5, a lower electrode 8 constituting the lowermost layer of the thin film capacitive element 7 is connected to the connection pad 2b. Yes. In this case, although not shown in detail, the lower electrode 8 has a three-layer structure of a titanium layer, a copper layer, and a titanium layer in order from the bottom.

下部電極８の上面全体には強誘電体膜９が設けられている。この場合、強誘電体膜９の材料としては、例えば、ＳＴＯ（ＳｒＴｉＯ3）、ＢＳＴ（（Ｂａ、Ｓｒ）ＴｉＯ3）、ＰＺＴ（Ｐｂ（Ｚｒ、Ｔｉ）Ｏ3）などが挙げられる。誘電率は、ＳＴＯで８０〜２００、ＢＳＴで４００〜８００、ＰＺＴで５００〜９００である。 A ferroelectric film 9 is provided on the entire upper surface of the lower electrode 8. In this case, examples of the material of the ferroelectric film 9 include STO (SrTiO 3 ), BST ((Ba, Sr) TiO 3 ), PZT (Pb (Zr, Ti) O 3 ), and the like. The dielectric constant is 80 to 200 for STO, 400 to 800 for BST, and 500 to 900 for PZT.

強誘電体膜９の上面全体には導電性保護膜１０が設けられている。この場合、導電性保護膜１０は、詳細には図示していないが、下から順に、チタン層および銅層の２層構造となっている。導電性保護膜１０の上面全体には銅からなる上部電極１１が設けられている。ここで、薄膜容量素子７は、下から順に、下部電極８、強誘電体膜９、導電性保護膜１０および上部電極１１の４層構造となっている。なお、導電性保護膜１０は、強誘電体膜９に耐性がある場合には、省略してもよい。   A conductive protective film 10 is provided on the entire top surface of the ferroelectric film 9. In this case, although not shown in detail, the conductive protective film 10 has a two-layer structure of a titanium layer and a copper layer in order from the bottom. An upper electrode 11 made of copper is provided on the entire upper surface of the conductive protective film 10. Here, the thin film capacitive element 7 has a four-layer structure of a lower electrode 8, a ferroelectric film 9, a conductive protective film 10, and an upper electrode 11 in order from the bottom. The conductive protective film 10 may be omitted if the ferroelectric film 9 is resistant.

薄膜容量素子７を含む保護膜５の上面にはポリイミド系樹脂などの熱硬化性樹脂からなる絶縁膜１２が設けられている。この場合、接続パッド２ａおよび上部電極１１の各中央部に対応する部分における絶縁膜１２には開口部１３ａ、１３ｂが設けられている。絶縁膜１２の上面には下地金属層１４ａ、１４ｂが設けられている。この場合、下地金属層１４ａ、１４ｂは、詳細には図示していないが、下から順に、チタン層および銅層の２層構造となっている。   An insulating film 12 made of a thermosetting resin such as polyimide resin is provided on the upper surface of the protective film 5 including the thin film capacitive element 7. In this case, openings 13 a and 13 b are provided in the insulating film 12 at portions corresponding to the central portions of the connection pad 2 a and the upper electrode 11. Base metal layers 14 a and 14 b are provided on the upper surface of the insulating film 12. In this case, although not shown in detail, the base metal layers 14a and 14b have a two-layer structure of a titanium layer and a copper layer in order from the bottom.

下地金属層１４ａ、１４ｂの上面全体には銅からなる配線１５ａ、１５ｂが設けられている。下地金属層１４ａを含む配線１５ａの一端部は、絶縁膜１２、保護膜５および絶縁膜３の開口部１３ａ、６ａ、４ａを介して接続パッド２ａに接続されている。下地金属層１４ｂを含む配線１５ｂの一端部は、絶縁膜１２の開口部１３ｂを介して上部電極１１に接続されている。   Wirings 15a and 15b made of copper are provided on the entire upper surface of the base metal layers 14a and 14b. One end of the wiring 15a including the base metal layer 14a is connected to the connection pad 2a through the insulating film 12, the protective film 5, and the openings 13a, 6a, and 4a of the insulating film 3. One end of the wiring 15 b including the base metal layer 14 b is connected to the upper electrode 11 through the opening 13 b of the insulating film 12.

配線１５ａ、１５ｂの接続パッド部上面には銅からなる柱状電極１６ａ、１６ｂが設けられている。配線１５ａ、１５ｂを含む絶縁膜１２の上面にはエポキシ系樹脂などの熱硬化性樹脂からなる封止膜１７がその上面が柱状電極１６ａ、１６ｂの上面と面一となるように設けられている。柱状電極１６ａ、１６ｂの上面には半田ボール１８ａ、１８ｂが設けられている。   Columnar electrodes 16a and 16b made of copper are provided on the upper surfaces of the connection pad portions of the wirings 15a and 15b. A sealing film 17 made of a thermosetting resin such as an epoxy resin is provided on the upper surface of the insulating film 12 including the wirings 15a and 15b so that the upper surface is flush with the upper surfaces of the columnar electrodes 16a and 16b. . Solder balls 18a and 18b are provided on the upper surfaces of the columnar electrodes 16a and 16b.

次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、ウエハ状態のシリコン基板１（半導体基板）上にアルミニウム系金属からなる複数の接続パッド２ａ、２ｂおよび酸化シリコンなどからなる絶縁膜３が設けられ、接続パッド２ａ、２ｂの中央部が絶縁膜３に形成された開口部４ａ、４ｂを介して露出されたものを用意する。この場合、ウエハ状態のシリコン基板１には、各半導体装置が形成される領域に所定の機能の集積回路（図示せず）が形成され、接続パッド２ａ、２ｂはそれぞれ対応する領域に形成された集積回路に電気的に接続されている。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a plurality of connection pads 2a, 2b made of an aluminum-based metal and an insulating film 3 made of silicon oxide or the like are provided on a silicon substrate 1 (semiconductor substrate) in a wafer state, and the connection pads 2a, A material in which the central portion of 2b is exposed through openings 4a and 4b formed in insulating film 3 is prepared. In this case, on the silicon substrate 1 in a wafer state, an integrated circuit (not shown) having a predetermined function is formed in a region where each semiconductor device is formed, and the connection pads 2a and 2b are formed in the corresponding regions. It is electrically connected to the integrated circuit.

次に、図３に示すように、絶縁膜３の開口部４ａ、４ｂを介して露出された接続パッド２ａ、２ｂの上面を含む絶縁膜３の上面全体に、スクリーン印刷法やスピンコート法などにより、ポリイミド系樹脂などの熱硬化性樹脂からなる保護膜５を形成する。次に、フォトリソグラフィ法により、絶縁膜３の開口部４ａ、４ｂに対応する部分における保護膜５に、絶縁膜３の開口部４ａ、４ｂよりもやや大きめの開口部６ａ、６ｂを形成する。   Next, as shown in FIG. 3, a screen printing method, a spin coating method, or the like is applied to the entire upper surface of the insulating film 3 including the upper surfaces of the connection pads 2a and 2b exposed through the openings 4a and 4b of the insulating film 3. Thus, the protective film 5 made of a thermosetting resin such as a polyimide resin is formed. Next, openings 6 a and 6 b that are slightly larger than the openings 4 a and 4 b of the insulating film 3 are formed in the protective film 5 at portions corresponding to the openings 4 a and 4 b of the insulating film 3 by photolithography.

次に、図４に示すように、絶縁膜３および保護膜５の開口部４ａ、６ａおよび開口部４ｂ、６ｂを介して露出された接続パッド２ａ、２ｂの上面を含む保護膜５の上面全体に、スパッタ法によりチタン、銅およびチタンを連続して成膜することにより、下部電極形成用膜８ａを形成する。次に、下部電極形成用膜８ａの上面にレジスト膜２１をパターン形成する。この場合、薄膜容量素子形成領域に対応する部分におけるレジスト膜２１には開口部２２が形成されている。   Next, as shown in FIG. 4, the entire upper surface of the protective film 5 including the upper surfaces of the connection pads 2 a and 2 b exposed through the openings 4 a and 6 a and the openings 4 b and 6 b of the insulating film 3 and the protective film 5. Further, titanium, copper and titanium are successively formed by sputtering, thereby forming the lower electrode forming film 8a. Next, a resist film 21 is patterned on the upper surface of the lower electrode forming film 8a. In this case, an opening 22 is formed in the resist film 21 in a portion corresponding to the thin film capacitor element formation region.

次に、レジスト膜２１の開口部２２内の下部電極形成用膜８ａの上面に、水熱合成法により、ＳＴＯ（ＳｒＴｉＯ3）、ＢＳＴ（（Ｂａ、Ｓｒ）ＴｉＯ3）、ＰＺＴ（Ｐｂ（Ｚｒ、Ｔｉ）Ｏ3）などからなる強誘電体膜９を形成する。この場合、強誘電体膜９は、下部電極形成用膜８ａの最上層のチタン層との反応により形成されるため、レジスト膜２１の開口部２２内の下部電極形成用膜８ａの上面のみに形成される。 Next, STO (SrTiO 3 ), BST ((Ba, Sr) TiO 3 ), PZT (Pb (Zr) are formed on the upper surface of the lower electrode forming film 8 a in the opening 22 of the resist film 21 by hydrothermal synthesis. , A ferroelectric film 9 made of Ti) O 3 ) or the like is formed. In this case, since the ferroelectric film 9 is formed by a reaction with the uppermost titanium layer of the lower electrode forming film 8a, only on the upper surface of the lower electrode forming film 8a in the opening 22 of the resist film 21. It is formed.

ここで、水熱合成法により、Ｐｂ（ＺｒＴｉ）Ｏ3からなる強誘電体膜９を形成する場合の、具体的な製造方法の一例について説明する。まず、Ｐｂ（ＮＯ3）2水溶液（１６ｍｍｏｌ）、ＺｒＯＣｌ2水溶液（８ｍｍｏｌ）、ＴｉＣｌ4水溶液（０．０８ｍｍｏｌ）およびＫＯＨ水溶液（０．３ｍｍｏｌ）の強アルカリの混合溶液中に、半導体基板１上に下部電極形成用膜８ａおよびレジスト膜２１が形成されたものを浸漬し、温度１８０℃、１０気圧中で１２時間の無電解式の水熱処理を行なうと、レジスト膜２１の開口部２２内の下部電極形成用膜８ａの上面にＰｂ（ＺｒＴｉ）Ｏ3の結晶核が生成される。 Here, an example of a specific manufacturing method in the case where the ferroelectric film 9 made of Pb (ZrTi) O 3 is formed by the hydrothermal synthesis method will be described. First, a Pb (NO 3 ) 2 aqueous solution (16 mmol), a ZrOCl 2 aqueous solution (8 mmol), a TiCl 4 aqueous solution (0.08 mmol), and a KOH aqueous solution (0.3 mmol) in a strong alkali mixed solution on the semiconductor substrate 1. When the bottom electrode forming film 8a and the resist film 21 formed are immersed and electroless hydrothermal treatment is performed at 180 ° C. and 10 atm for 12 hours, the lower part in the opening 22 of the resist film 21 is formed. Crystal nuclei of Pb (ZrTi) O 3 are generated on the upper surface of the electrode forming film 8a.

次に、Ｐｂ（ＮＯ3）2水溶液（１６ｍｍｏｌ）、ＺｒＯＣｌ2水溶液（８．３２ｍｍｏｌ）、ＴｉＣｌ4水溶液（７．６８ｍｍｏｌ）およびＫＯＨ水溶液（２．２４ｍｍｏｌ）の強アルカリの混合溶液（溶液合計６４０ｍｌ）中に、レジスト膜２１の開口部２２内の下部電極形成用膜８ａの上面にＰｂ（ＺｒＴｉ）Ｏ3の結晶核が生成されたものを浸漬し、温度１６０℃で１０時間の無電解式の水熱処理を行なうと、レジスト膜２１の開口部２２内の下部電極形成用膜８ａの上面にＫを含有するＰｂ（ＺｒＴｉ）Ｏ3の膜が形成される。 Next, a strongly alkaline mixed solution of Pb (NO 3 ) 2 aqueous solution (16 mmol), ZrOCl 2 aqueous solution (8.32 mmol), TiCl 4 aqueous solution (7.68 mmol) and KOH aqueous solution (2.24 mmol) (total solution 640 ml) Into the upper surface of the lower electrode forming film 8a in the opening 22 of the resist film 21 is immersed a Pb (ZrTi) O 3 crystal nucleus, and the electroless type is heated at 160 ° C. for 10 hours. When hydrothermal treatment is performed, a film of Pb (ZrTi) O 3 containing K is formed on the upper surface of the lower electrode forming film 8 a in the opening 22 of the resist film 21.

次に、純水中で３分間の超音波洗浄を２回行ない、次いで１ｍｏｌ／ｌの酢酸水溶液中で３分間の超音波洗浄を２回行ない、次いで純水中で３分間の超音波洗浄を２回行ない、次いで温度１００℃で１２時間の乾燥を行なうと、レジスト膜２１の開口部２２内の下部電極形成用膜８ａの上面にＰｂ（ＺｒＴｉ）Ｏ3の結晶膜からなる強誘電体膜９が膜厚１０μｍ程度に形成される。 Next, ultrasonic cleaning is performed twice for 3 minutes in pure water, then ultrasonic cleaning is performed twice for 3 minutes in 1 mol / l acetic acid aqueous solution, and then ultrasonic cleaning is performed for 3 minutes in pure water. After performing twice and then drying at a temperature of 100 ° C. for 12 hours, a ferroelectric film made of a crystalline film of Pb (ZrTi) O 3 is formed on the upper surface of the lower electrode forming film 8a in the opening 22 of the resist film 21. 9 is formed to a film thickness of about 10 μm.

ところで、ポリイミド系樹脂などの熱硬化性樹脂からなる保護膜５の耐熱温度は２５０℃程度と比較的低い。一方、上記水熱合成法による強誘電体膜９の形成方法では、処理温度は２００℃以下であり、保護膜５の耐熱温度２５０℃程度よりもかなり低いので、保護膜５に熱的ダメージを与えることはない。   By the way, the heat-resistant temperature of the protective film 5 made of thermosetting resin such as polyimide resin is relatively low at about 250 ° C. On the other hand, in the method of forming the ferroelectric film 9 by the hydrothermal synthesis method, the processing temperature is 200 ° C. or lower, which is much lower than the heat resistance temperature of the protective film 5 of about 250 ° C. Never give.

ここで、強誘電体膜９をスパッタ法により形成することも考えられるが、この場合の処理温度は５００〜６００℃であり、保護膜５の耐熱温度２５０℃程度よりもかなり高いので、保護膜５に熱的ダメージを与えることになり、好ましくない。   Here, it is conceivable to form the ferroelectric film 9 by sputtering, but the processing temperature in this case is 500 to 600 ° C., which is considerably higher than the heat resistance temperature of the protective film 5 of about 250 ° C. This will cause thermal damage to 5, which is not preferable.

また、比較的低温で形成することができる誘電体として、ＳｉＯ2（誘電率４程度（１桁））、Ｔａ2Ｏ5（誘電率２５程度（２桁前半））などがあるが、これらの誘電率は上記強誘電体の誘電率（８０〜９００（２桁後半〜３桁））よりもかなり小さいので、薄膜容量素子７の容量を大きくするには、薄膜容量素子７の平面的サイズをかなり大きくしなければならず、好ましくない。 Examples of dielectrics that can be formed at a relatively low temperature include SiO 2 (dielectric constant of about 4 (one digit)) and Ta 2 O 5 (dielectric constant of about 25 (first two digits)). Since the dielectric constant is considerably smaller than the dielectric constant of the ferroelectric substance (80 to 900 (second half to third digit)), in order to increase the capacitance of the thin film capacitive element 7, the planar size of the thin film capacitive element 7 must be increased. It must be quite large and is not preferred.

次に、レジスト膜２１の開口部２２内の強誘電体膜９の上面に、ハードマスク（図示せず）を用いたスパッタ法によりチタンおよび銅を連続して成膜することにより、導電性保護膜１０を形成する。次に、レジスト膜２１の開口部２２内の導電性保護膜１０の上面に、銅の無電解メッキにより、上部電極１１を形成する。   Next, conductive protection is achieved by continuously depositing titanium and copper on the upper surface of the ferroelectric film 9 in the opening 22 of the resist film 21 by sputtering using a hard mask (not shown). A film 10 is formed. Next, the upper electrode 11 is formed on the upper surface of the conductive protective film 10 in the opening 22 of the resist film 21 by electroless plating of copper.

次に、レジスト膜２１を剥離し、次いで、上部電極１１をマスクとして下部電極形成用膜８ａの不要な部分をエッチングして除去すると、図５に示すように、強誘電体膜９下に下部電極８が形成される。この場合、下部電極８は、下から順に、チタン層、銅層およびチタン層の３層の薄膜からなるいわゆる下地金属層のみからなっている。したがって、この下地金属層の上面全体に銅の電解メッキにより上部電極を形成する場合と比較して、工程数を低減することができる。また、この状態では、接続パッド２ａは、絶縁膜４および保護膜６の開口部４ａ、６ａを介して露出されている。   Next, the resist film 21 is peeled off, and then unnecessary portions of the lower electrode forming film 8a are removed by etching using the upper electrode 11 as a mask, so that the lower portion is formed under the ferroelectric film 9 as shown in FIG. Electrode 8 is formed. In this case, the lower electrode 8 is composed of only a so-called base metal layer composed of three thin films of a titanium layer, a copper layer, and a titanium layer in order from the bottom. Therefore, the number of steps can be reduced as compared with the case where the upper electrode is formed on the entire upper surface of the underlying metal layer by electrolytic plating of copper. In this state, the connection pad 2 a is exposed through the openings 4 a and 6 a of the insulating film 4 and the protective film 6.

次に、図６に示すように、絶縁膜４および保護膜６の開口部４ａ、６ａを介して露出された接続パッド２ａの上面および上部電極１１を含む保護膜５の上面全体に、スクリーン印刷法やスピンコート法などにより、ポリイミド系樹脂などの熱硬化性樹脂からなる絶縁膜１２を形成する。次に、フォトリソグラフィ法により、接続パッド２ａおよび上部電極１１の各上面中央部に対応する部分における絶縁膜１２に開口部１３ａ、１３ｂを形成する。   Next, as shown in FIG. 6, screen printing is performed on the entire upper surface of the protective film 5 including the upper surface of the connection pad 2 a and the upper electrode 11 exposed through the openings 4 a and 6 a of the insulating film 4 and the protective film 6. The insulating film 12 made of a thermosetting resin such as a polyimide resin is formed by a method such as a spin coating method. Next, openings 13a and 13b are formed in the insulating film 12 at portions corresponding to the center portions of the upper surfaces of the connection pad 2a and the upper electrode 11 by photolithography.

次に、図７に示すように、絶縁膜１２、保護膜５および絶縁膜３の開口部１３ａ、６ａ、４ａを介して露出された接続パッド２ａの上面および絶縁膜１２の開口部１３ｂを介して露出された上部電極１１の上面を含む絶縁膜１２の上面全体に、スパッタ法によりチタンおよび銅を連続して成膜することにより、下地金属層１４を形成する。   Next, as shown in FIG. 7, the upper surface of the connection pad 2a exposed through the openings 13a, 6a and 4a of the insulating film 12, the protective film 5 and the insulating film 3 and the opening 13b of the insulating film 12 are used. A base metal layer 14 is formed by continuously depositing titanium and copper on the entire upper surface of the insulating film 12 including the upper surface of the exposed upper electrode 11 by sputtering.

次に、下地金属層１４の上面にメッキレジスト膜２３をパターン形成する。この場合、配線１５ａ、１５ｂ形成領域に対応する部分におけるメッキレジスト膜２３には開口部２４ａ、２４ｂが形成されている。次に、下地金属層１４ａ、１４ｂをメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜２３の開口部２４ａ、２４ｂ内の下地金属層１４ａ、１４ｂの上面に配線１５ａ、１５ｂを形成する。次に、メッキレジスト膜２３を剥離する。   Next, a plating resist film 23 is pattern-formed on the upper surface of the base metal layer 14. In this case, openings 24a and 24b are formed in the plating resist film 23 in portions corresponding to the wiring 15a and 15b formation regions. Next, by performing copper electroplating using the base metal layers 14a and 14b as plating current paths, wirings 15a and 15b are formed on the upper surfaces of the base metal layers 14a and 14b in the openings 24a and 24b of the plating resist film 23. To do. Next, the plating resist film 23 is peeled off.

次に、図８に示すように、配線１５ａ、１５ｂを含む下地金属層１４の上面にメッキレジスト膜２５をパターン形成する。この場合、柱状電極１６ａ、１６ｂ形成領域に対応する部分におけるメッキレジスト膜２５には開口部２６ａ、２６ｂが形成されている。次に、下地金属層１４をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜２５の開口部２６ａ、２６ｂ内の配線１５ａ、１５ｂの接続パッド部上面に柱状電極１６ａ、１６ｂを形成する。次に、メッキレジスト膜２５を剥離し、次いで、配線１５ａ、１５ｂをマスクとして下地金属層１４の不要な部分をエッチングして除去すると、図９に示すように、配線１５ａ、１５ｂ下にのみ下地金属層１４ａ、１４ｂが残存される。   Next, as shown in FIG. 8, a plating resist film 25 is patterned on the upper surface of the base metal layer 14 including the wirings 15a and 15b. In this case, openings 26a and 26b are formed in the plating resist film 25 in portions corresponding to the columnar electrodes 16a and 16b formation regions. Next, by performing electrolytic plating of copper using the base metal layer 14 as a plating current path, the columnar electrodes 16a and 16b are formed on the upper surfaces of the connection pads of the wirings 15a and 15b in the openings 26a and 26b of the plating resist film 25. To do. Next, the plating resist film 25 is peeled off, and then unnecessary portions of the base metal layer 14 are removed by etching using the wirings 15a and 15b as a mask. As shown in FIG. 9, the base is only under the wirings 15a and 15b. The metal layers 14a and 14b remain.

次に、図１０に示すように、柱状電極１６ａ、１６ｂおよび配線１５ａ、１５ｂを含む絶縁膜１２の上面全体に、スクリーン印刷法やスピンコート法などにより、エポキシ系樹脂などの熱硬化性樹脂からなる封止膜１７をその厚さが柱状電極１６ａ、１６ｂの高さよりも厚くなるように形成する。したがって、この状態では、柱状電極１６ａ、１６ｂの上面は封止膜１７によって覆われている。   Next, as shown in FIG. 10, the entire upper surface of the insulating film 12 including the columnar electrodes 16a and 16b and the wirings 15a and 15b is made of a thermosetting resin such as an epoxy resin by a screen printing method or a spin coating method. The resulting sealing film 17 is formed so that its thickness is greater than the height of the columnar electrodes 16a, 16b. Therefore, in this state, the upper surfaces of the columnar electrodes 16 a and 16 b are covered with the sealing film 17.

次に、封止膜１７および柱状電極１６ａ、１６ｂの上面側を適宜に研磨し、図１１に示すように、柱状電極１６ａ、１６ｂの上面を露出させ、且つ、この露出された柱状電極１６ａ、１６ｂの上面を含む封止膜１７の上面を平坦化する。次に、図１２に示すように、柱状電極１６ａ、１６ｂの上面に半田ボール１８ａ、１８ｂを形成する。次に、ダイシング工程を経ると、図１に示す半導体装置が複数個得られる。本実施形態によれば、薄膜容量素子７を接続パッド２ｂの直上に形成し、その上に配線１５ｂを形成することができる。この場合、薄膜容量素子７の面積は比較的小さくなるが、誘電体として強誘電体膜１０を用いることができるため、比較的小さい面積であっても所望の容量値を得ることができる。   Next, the upper surface side of the sealing film 17 and the columnar electrodes 16a and 16b is appropriately polished to expose the upper surfaces of the columnar electrodes 16a and 16b as shown in FIG. 11, and the exposed columnar electrodes 16a and 16b The upper surface of the sealing film 17 including the upper surface of 16b is planarized. Next, as shown in FIG. 12, solder balls 18a and 18b are formed on the upper surfaces of the columnar electrodes 16a and 16b. Next, through a dicing process, a plurality of semiconductor devices shown in FIG. 1 are obtained. According to the present embodiment, the thin film capacitive element 7 can be formed immediately above the connection pad 2b, and the wiring 15b can be formed thereon. In this case, although the area of the thin film capacitive element 7 is relatively small, since the ferroelectric film 10 can be used as a dielectric, a desired capacitance value can be obtained even with a relatively small area.

なお、図６に示す絶縁膜１２形成工程（ただし、開口部１３ａは形成しない）を経た後に、絶縁膜１２の上面に、図４に示すような下地金属層１４およびレジスト膜２１を形成し、次いで同じく図４に示すような強誘電体膜９、導電性保護膜１０および上部電極１１を形成すると、薄膜容量素子７が２層（または３層以上）積層された半導体装置を得ることもできる。   After the insulating film 12 formation step shown in FIG. 6 (however, the opening 13a is not formed), a base metal layer 14 and a resist film 21 as shown in FIG. 4 are formed on the upper surface of the insulating film 12, Next, when the ferroelectric film 9, the conductive protective film 10, and the upper electrode 11 as shown in FIG. 4 are formed, a semiconductor device in which the thin film capacitor element 7 is laminated in two layers (or three layers or more) can be obtained. .

（第２実施形態）
図１３はこの発明の第２実施形態としての半導体装置の断面図を示し、図１４は図１３のXIV−XIV線に沿う一部（絶縁膜１２）を省略した平面図を示す。この半導体装置において、図１に示す半導体装置と大きく異なる点は、シリコン基板１上の接続パッド２（添付符号ａ、ｂは省略する、以下同じ）配置領域の内側に平面方形状の薄膜容量素子３１を設けた点である。この場合、薄膜容量素子３１は、下から順に、下地金属層３２、下部電極３３、下地金属層３４、強誘電体膜３５、下地金属層３６および上部電極３７の６層構造となっている。 (Second Embodiment)
FIG. 13 is a sectional view of a semiconductor device as a second embodiment of the present invention, and FIG. 14 is a plan view in which a part (insulating film 12) along the XIV-XIV line in FIG. 13 is omitted. This semiconductor device differs greatly from the semiconductor device shown in FIG. 1 in that a planar rectangular thin film capacitive element is disposed inside a connection pad 2 (attached symbols a and b are omitted, hereinafter the same) on the silicon substrate 1. 31 is provided. In this case, the thin film capacitive element 31 has a six-layer structure of a base metal layer 32, a lower electrode 33, a base metal layer 34, a ferroelectric film 35, a base metal layer 36, and an upper electrode 37 in order from the bottom.

すなわち、保護膜５の上面中央部には平面方形状の下地金属層３２を含む下部電極３３が設けられている。下地金属層３２を含む下部電極３３は、保護膜５の上面に設けられた下地金属層３８を含む下部配線３９に接続されている。下地金属層３８を含む下部配線３９の一端部は、絶縁膜３および保護膜５の開口部４、６を介して例えばＧＮＤ用の接続パッド２に接続されている。   That is, a lower electrode 33 including a planar rectangular base metal layer 32 is provided at the center of the upper surface of the protective film 5. The lower electrode 33 including the base metal layer 32 is connected to the lower wiring 39 including the base metal layer 38 provided on the upper surface of the protective film 5. One end of the lower wiring 39 including the base metal layer 38 is connected to, for example, the GND connection pad 2 through the openings 4 and 6 of the insulating film 3 and the protective film 5.

一方、例えばＶＤＤ用の接続パッド２およびその他の接続パッド２上における開口部４、６内およびその周囲の保護膜５の上面には下地金属層４０を含む上層接続パッド４１がそれぞれ対応する接続パッド２に接続されて設けられている。なお、以下では、その他の接続パッド２に対応するものについての説明は省略する。   On the other hand, for example, the upper connection pads 41 including the base metal layer 40 are provided on the upper surfaces of the protective films 5 in and around the openings 4 and 6 on the connection pads 2 for VDD and the other connection pads 2, respectively. 2 is provided. In the following description, explanations of other connection pads 2 are omitted.

下部電極３３、下部配線３９および上層接続パッド４１を含む保護膜５の上面には絶縁膜１２が設けられている。下部電極３３および上層接続パッド４１に対応する部分における絶縁膜１２には開口部４２、４３が設けられている。絶縁膜１２の開口部４２内の下部電極３３の上面には下地金属層３４および強誘電体膜３５が設けられている。絶縁膜１２の開口部４３内の上層接続パッド４１の上面には上下導通部４４が設けられている。   An insulating film 12 is provided on the upper surface of the protective film 5 including the lower electrode 33, the lower wiring 39, and the upper layer connection pad 41. Openings 42 and 43 are provided in the insulating film 12 in portions corresponding to the lower electrode 33 and the upper layer connection pads 41. A base metal layer 34 and a ferroelectric film 35 are provided on the upper surface of the lower electrode 33 in the opening 42 of the insulating film 12. A vertical conduction portion 44 is provided on the upper surface of the upper layer connection pad 41 in the opening 43 of the insulating film 12.

強誘電体膜３５を含む絶縁膜１２の上面には下地金属層３６を含む上部電極３７が設けられている。下地金属層３６を含む上部電極３７は、絶縁膜１２の上面に設けられた下地金属層４５を含む上部配線４６に接続されている。下地金属層４５を含む上部配線４６の一端部は上下導通部４４の上面に接続されている。   An upper electrode 37 including a base metal layer 36 is provided on the upper surface of the insulating film 12 including the ferroelectric film 35. The upper electrode 37 including the base metal layer 36 is connected to the upper wiring 46 including the base metal layer 45 provided on the upper surface of the insulating film 12. One end portion of the upper wiring 46 including the base metal layer 45 is connected to the upper surface of the vertical conduction portion 44.

上部電極３７および上部配線４６を含む絶縁膜１２の上面には上層絶縁膜４７が設けられている。下部配線３９の接続パッド部に対応する部分における上層絶縁膜４７および絶縁膜１２には開口部４８が設けられている。開口部４８内には上下導通部４９が下部配線３９の接続パッド部に接続されて設けられている。上部配線４６の接続パッド部に対応する部分における上層絶縁膜４７には開口部５０が設けられている。開口部５０内には上下導通部５１が上部配線４１の接続パッド部に接続されて設けられている。   An upper insulating film 47 is provided on the upper surface of the insulating film 12 including the upper electrode 37 and the upper wiring 46. An opening 48 is provided in the upper insulating film 47 and the insulating film 12 in a portion corresponding to the connection pad portion of the lower wiring 39. In the opening 48, a vertical conduction part 49 is provided connected to the connection pad part of the lower wiring 39. An opening 50 is provided in the upper insulating film 47 in a portion corresponding to the connection pad portion of the upper wiring 46. In the opening 50, a vertical conduction part 51 is provided connected to the connection pad part of the upper wiring 41.

上層絶縁膜４７の上面には下地金属層１４を含む配線１５が設けられている。このうち、ＧＮＤ用の下地金属層１４を含む配線１５の一端部は上下導通部４９の上面に接続されている。ＶＤＤ用の下地金属層１４を含む配線１５の一端部は上下導通部５１の上面に接続されている。なお、柱状電極１６、封止膜１７および半田ボール１８についてはその説明を省略する。また、各部の材料については次の製造方法において説明する。   A wiring 15 including a base metal layer 14 is provided on the upper surface of the upper insulating film 47. Among these, one end part of the wiring 15 including the ground metal layer 14 for GND is connected to the upper surface of the vertical conduction part 49. One end portion of the wiring 15 including the base metal layer 14 for VDD is connected to the upper surface of the vertical conduction portion 51. The description of the columnar electrode 16, the sealing film 17, and the solder ball 18 is omitted. Further, the material of each part will be described in the following manufacturing method.

次に、この半導体装置の製造方法の一例について説明する。図３に示す保護膜５形成工程を経た後に、図１５に示すように、絶縁膜３および保護膜５の開口部４、６を介して露出された接続パッド２の上面を含む保護膜５の上面全体に、スパッタ法によりチタン、銅およびチタンを連続して成膜することにより、下地金属層５１を形成する。   Next, an example of a method for manufacturing this semiconductor device will be described. After the protective film 5 forming step shown in FIG. 3, the protective film 5 including the insulating film 3 and the upper surface of the connection pad 2 exposed through the openings 4 and 6 of the protective film 5 is formed as shown in FIG. A base metal layer 51 is formed on the entire upper surface by successively depositing titanium, copper, and titanium by sputtering.

次に、下地金属層５１の上面にメッキレジスト膜５２をパターン形成する。この場合、下部電極３３形成領域および下部配線３９形成領域に対応する部分におけるメッキレジスト膜５２には開口部５３が形成されている。また、上層接続パッド４１形成領域に対応する部分におけるメッキレジスト膜５２には開口部５４が形成されている。   Next, a plating resist film 52 is patterned on the upper surface of the base metal layer 51. In this case, an opening 53 is formed in the plating resist film 52 in portions corresponding to the lower electrode 33 formation region and the lower wiring 39 formation region. An opening 54 is formed in the plating resist film 52 in a portion corresponding to the upper layer connection pad 41 formation region.

次に、下地金属層５１をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜５２の開口部５３内の下地金属層５１の上面に下部電極３３および下部配線３９を形成し、また、メッキレジスト膜５２の開口部５４内の下地金属層５１の上面に上層接続パッド４１を形成する。次に、メッキレジスト膜５２を剥離し、次いで、下部電極３３、下部配線３９および上層接続パッド４１をマスクとして下地金属層５１の不要な部分をエッチングして除去すると、図１６に示すように、下部電極３３、下部配線３９および上層接続パッド４１下にのみ下地金属層３２、３８、４０が残存される。   Next, by performing electrolytic plating of copper using the base metal layer 51 as a plating current path, the lower electrode 33 and the lower wiring 39 are formed on the upper surface of the base metal layer 51 in the opening 53 of the plating resist film 52. Then, the upper layer connection pad 41 is formed on the upper surface of the base metal layer 51 in the opening 54 of the plating resist film 52. Next, the plating resist film 52 is peeled off, and then unnecessary portions of the base metal layer 51 are removed by etching using the lower electrode 33, the lower wiring 39 and the upper layer connection pad 41 as a mask, as shown in FIG. Underlying metal layers 32, 38, 40 remain only under lower electrode 33, lower wiring 39 and upper layer connection pad 41.

次に、図１７に示すように、下部電極３３、下部配線３９および上層接続パッド４１を含む保護膜５の上面全体に、スクリーン印刷法やスピンコート法などにより、ポリイミド系樹脂などの熱硬化性樹脂からなる絶縁膜１２を形成する。次に、フォトリソグラフィ法により、下部電極３３の上面中央部に対応する部分および上層接続パッド４２の上面中央部に対応する部分における絶縁膜１２に開口部４２、４３を形成する。   Next, as shown in FIG. 17, the entire upper surface of the protective film 5 including the lower electrode 33, the lower wiring 39, and the upper layer connection pad 41 is thermosetting such as polyimide resin by screen printing or spin coating. An insulating film 12 made of resin is formed. Next, openings 42 and 43 are formed in the insulating film 12 at a portion corresponding to the central portion of the upper surface of the lower electrode 33 and a portion corresponding to the central portion of the upper surface of the upper connection pad 42 by photolithography.

次に、図１８に示すように、絶縁膜１２の開口部４２内の上部電極３３の上面に、ハードマスク（図示せず）を用いたスパッタ法により、チタンからなる下地金属層３４を形成する。次に、絶縁膜１２の開口部４２内の下地金属層３４の上面に、上記水熱合成法により、ＳＴＯ（ＳｒＴｉＯ3）、ＢＳＴ（（ＢａＳｒ）ＴｉＯ3）、ＰＺＴ（Ｐｂ（ＺｒＴｉ）Ｏ3）などからなる強誘電体膜３５を形成する。この場合も、強誘電体膜３５は、チタンからなる下地金属層３４との反応により形成されるため、絶縁膜１２の開口部４２内の下地金属層３４の上面のみに形成される。 Next, as shown in FIG. 18, a base metal layer 34 made of titanium is formed on the upper surface of the upper electrode 33 in the opening 42 of the insulating film 12 by sputtering using a hard mask (not shown). . Next, STO (SrTiO 3 ), BST ((BaSr) TiO 3 ), PZT (Pb (ZrTi) O 3 ) are formed on the upper surface of the base metal layer 34 in the opening 42 of the insulating film 12 by the hydrothermal synthesis method. ) Etc. is formed. Also in this case, since the ferroelectric film 35 is formed by reaction with the base metal layer 34 made of titanium, it is formed only on the upper surface of the base metal layer 34 in the opening 42 of the insulating film 12.

次に、図１９に示すように、絶縁膜１２の開口部４３内の上層接続パッド４１の上面に、銅の無電解メッキにより、上下導通部４４を形成する。次に、必要に応じて、強誘電体膜３５および上下導通部４４を含む絶縁膜１２の上面側を適宜に研磨する。次に、図２０に示すように、上部電極３５および上下導通部４４を含む絶縁膜１２の上面に、ハードマスク（図示せず）を用いたスパッタ法によりチタンおよび銅を連続して成膜することにより、下地金属層３６、４５を形成する。次に、下地金属層３６、４５の上面に、銅の無電解メッキにより、上部電極３７および上部配線４６を形成する。   Next, as shown in FIG. 19, the vertical conduction portion 44 is formed on the upper surface of the upper connection pad 41 in the opening 43 of the insulating film 12 by electroless plating of copper. Next, the upper surface side of the insulating film 12 including the ferroelectric film 35 and the upper and lower conductive portions 44 is appropriately polished as necessary. Next, as shown in FIG. 20, titanium and copper are successively formed on the upper surface of the insulating film 12 including the upper electrode 35 and the upper and lower conductive portions 44 by sputtering using a hard mask (not shown). Thereby, the base metal layers 36 and 45 are formed. Next, the upper electrode 37 and the upper wiring 46 are formed on the upper surfaces of the base metal layers 36 and 45 by electroless plating of copper.

次に、図２１に示すように、上部電極３７および上部配線４６を含む絶縁膜１２の上面全体に、スクリーン印刷法やスピンコート法などにより、ポリイミド系樹脂などの熱硬化性樹脂からなる上層絶縁膜４７を形成する。次に、レーザビームを照射するレーザ加工あるいはフォトリソグラフィ法により、下部配線３９および上部配線４６の各接続パッド部に対応する部分における上層絶縁膜４７に開口部４８、５０を形成する。   Next, as shown in FIG. 21, the entire upper surface of the insulating film 12 including the upper electrode 37 and the upper wiring 46 is covered with an upper insulating layer made of a thermosetting resin such as a polyimide resin by a screen printing method or a spin coating method. A film 47 is formed. Next, openings 48 and 50 are formed in the upper insulating film 47 at portions corresponding to the connection pad portions of the lower wiring 39 and the upper wiring 46 by laser processing or photolithography that irradiates a laser beam.

次に、上層絶縁膜４７の開口部４８、５０内の上部電極３７および上部配線４６の上面に、銅の無電解メッキにより、上下導通部４８、５１を形成する。次に、必要に応じて、上下導通部４８、５１を含む上層絶縁膜４７の上面側を適宜に研磨する。以下、図７〜図１２にそれぞれ示す工程、すなわち、下地金属層１４成膜工程、配線１５形成工程、柱状電極１６形成工程、下地金属層１４形成工程、封止膜１７形成工程、半田ボール１８形成工程およびダイシング工程を経ると、図１３に示す半導体装置が複数個得られる。本実施形態によれば、薄膜容量素子３１の面積を比較的大きくすることができ、しかも、誘電体として強誘電体膜３５を用いることができるため、薄膜容量素子３１の容量値を比較的大きくすることができる。これにより、この薄膜容量素子３１を２次電池として用いるようにしてもよい。   Next, upper and lower conductive portions 48 and 51 are formed on the upper surfaces of the upper electrode 37 and the upper wiring 46 in the openings 48 and 50 of the upper insulating film 47 by electroless plating of copper. Next, if necessary, the upper surface side of the upper insulating film 47 including the vertical conduction portions 48 and 51 is appropriately polished. Hereinafter, the processes shown in FIGS. 7 to 12, that is, the base metal layer 14 film forming process, the wiring 15 forming process, the columnar electrode 16 forming process, the base metal layer 14 forming process, the sealing film 17 forming process, the solder ball 18, respectively. Through the formation process and the dicing process, a plurality of semiconductor devices shown in FIG. 13 are obtained. According to the present embodiment, the area of the thin film capacitive element 31 can be made relatively large, and since the ferroelectric film 35 can be used as a dielectric, the capacitance value of the thin film capacitive element 31 is made relatively large. can do. Thereby, this thin film capacitive element 31 may be used as a secondary battery.

なお、上下導通部４８、５１を省略し、例えばＧＮＤ用の下地金属層１４を含む上層配線１５の一端部を上層絶縁膜４７および絶縁膜１２の開口部４８を介して下部配線３９の接続パッド部上面に接続させ、また、例えばＶＤＤ用の下地金属層１４を含む上層配線１５の一端部を上層絶縁膜４７の開口部５０を介して上部配線４６の接続パッド上面部に接続させるようにしてもよい。   The upper and lower conductive portions 48 and 51 are omitted, and for example, one end of the upper wiring 15 including the ground metal layer 14 for GND is connected to the connection pad of the lower wiring 39 through the upper insulating film 47 and the opening 48 of the insulating film 12. Further, for example, one end of the upper wiring 15 including the base metal layer 14 for VDD is connected to the upper surface of the connection pad of the upper wiring 46 through the opening 50 of the upper insulating film 47. Also good.

（第３実施形態）
図２２はこの発明の第３実施形態としての半導体装置の断面図を示し、図２３は図２２のXXIII−XXIII線に沿う一部（絶縁膜１２）を省略した平面図を示す。この半導体装置において、図１３および図１４に示す半導体装置と異なる点は、薄膜容量素子３１、つまり、下地金属層３２、下部電極３３、下地金属層３４、強誘電体膜３５、下地金属層４５および上部電極４６を保護膜５上の接続パッド２配置領域の内側および外側に設けた点である。 (Third embodiment)
22 is a cross-sectional view of a semiconductor device as a third embodiment of the present invention, and FIG. 23 is a plan view in which a part (insulating film 12) along the line XXIII-XXIII in FIG. 22 is omitted. This semiconductor device is different from the semiconductor device shown in FIGS. 13 and 14 in that the thin film capacitor 31, that is, the base metal layer 32, the lower electrode 33, the base metal layer 34, the ferroelectric film 35, and the base metal layer 45. The upper electrode 46 is provided inside and outside the connection pad 2 arrangement region on the protective film 5.

この場合、保護膜５上の接続パッド２配置領域の外側に設けられた下地金属層３２を含む下部電極３３は下地金属層３８を含む下部配線３９に接続されている。また、保護膜５上の接続パッド２配置領域の外側に設けられた下地金属層３６を含む上部電極３７は下地金属層４５を含む上部配線４６に接続されている。本実施形態によれば、薄膜容量素子３１の面積を上記第２実施形態の場合より更に大きくすることができ、薄膜容量素子３１の容量値を更に大きくすることができる。 In this case, the lower electrode 33 including the base metal layer 32 provided outside the region where the connection pad 2 is disposed on the protective film 5 is connected to the lower wiring 39 including the base metal layer 38. Further, the upper electrode 37 including the base metal layer 36 provided outside the region where the connection pad 2 is arranged on the protective film 5 is connected to the upper wiring 46 including the base metal layer 45. According to the present embodiment, the area of the thin film capacitive element 31 can be further increased as compared with the second embodiment, and the capacitance value of the thin film capacitive element 31 can be further increased.

（第４実施形態）
図２４はこの発明の第４実施形態としての半導体装置の断面図を示す。この半導体装置は平面方形状のベース板６１を備えている。ベース板６１は、ガラス繊維、アラミド繊維などにエポキシ系樹脂、ポリイミド系樹脂などの熱硬化性樹脂を含浸させたもの、シリコン、ガラス、セラミックス、樹脂単体などの絶縁材料、あるいは、銅やアルミニウムなどの金属材料からなっている。 (Fourth embodiment)
FIG. 24 is a sectional view of a semiconductor device as a fourth embodiment of the present invention. This semiconductor device includes a base plate 61 having a planar rectangular shape. The base plate 61 is made of glass fiber, aramid fiber or the like impregnated with a thermosetting resin such as epoxy resin or polyimide resin, insulating material such as silicon, glass, ceramics, resin alone, or copper or aluminum. Made of metal material.

ベース板６１の上面には、下から順に、ポリイミド系樹脂などの熱硬化性樹脂からなる下地絶縁膜６２、下地金属層６４および銅からなる下部電極６５が設けられている。この場合、下地金属層６４は、下から順に、チタン層および銅層の２層構造となっている。下部電極６５の上面中央部には、下から順に、チタンからなる下地金属層６６、強誘電体膜６７、下地金属層６８および銅からなる上部電極６９が設けられている。   On the upper surface of the base plate 61, a base insulating film 62 made of a thermosetting resin such as a polyimide resin, a base metal layer 64, and a lower electrode 65 made of copper are provided in order from the bottom. In this case, the base metal layer 64 has a two-layer structure of a titanium layer and a copper layer in order from the bottom. In the center of the upper surface of the lower electrode 65, a base metal layer 66 made of titanium, a ferroelectric film 67, a base metal layer 68, and an upper electrode 69 made of copper are provided in order from the bottom.

この場合も、強誘電体膜６７の材料としては、例えば、ＳＴＯ（ＳｒＴｉＯ3）、ＢＳＴ（（Ｂａ、Ｓｒ）ＴｉＯ3）、ＰＺＴ（Ｐｂ（Ｚｒ、Ｔｉ）Ｏ3）などが挙げられる。下地金属層６８は、下から順に、チタン層および銅層の２層構造となっている。そして、下地金属層６４、下部電極６５、下地金属層６６、強誘電体膜６７、下地金属層６８および上部電極６９により、薄膜容量素子６３が構成されている。 Also in this case, examples of the material of the ferroelectric film 67 include STO (SrTiO 3 ), BST ((Ba, Sr) TiO 3 ), PZT (Pb (Zr, Ti) O 3 ), and the like. The base metal layer 68 has a two-layer structure of a titanium layer and a copper layer in order from the bottom. The thin film capacitor 63 is configured by the base metal layer 64, the lower electrode 65, the base metal layer 66, the ferroelectric film 67, the base metal layer 68, and the upper electrode 69.

上部電極６９を含む下部電極６５の上面にはポリイミド系樹脂などの熱硬化性樹脂からなる下層絶縁膜７０が設けられている。下部電極６５の上面周辺部の所定の箇所に対応する部分における下層絶縁膜７０には開口部７１が設けられている。開口部７１内には銅からなる上下導通部７２が下部電極６５に接続されて設けられている。上部電極６９の上面周辺部の所定の箇所に対応する部分における下層絶縁膜７０には開口部７３が設けられている。開口部７３内には銅からなる上下導通部７４が上部電極６９に接続されて設けられている。   A lower insulating film 70 made of a thermosetting resin such as a polyimide resin is provided on the upper surface of the lower electrode 65 including the upper electrode 69. An opening 71 is provided in the lower insulating film 70 in a portion corresponding to a predetermined portion around the upper surface of the lower electrode 65. In the opening 71, a vertical conduction part 72 made of copper is provided connected to the lower electrode 65. An opening 73 is provided in the lower insulating film 70 in a portion corresponding to a predetermined location around the upper surface of the upper electrode 69. In the opening 73, a vertical conduction portion 74 made of copper is provided connected to the upper electrode 69.

上下導通部７２、７４を含む下層絶縁膜７０の上面にはポリイミド系樹脂などの熱硬化性樹脂からなる平坦化膜７５が設けられている。平坦化膜７５の上面中央部には、ベース板６１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体７６の下面がダイボンド材からなる接着層７７を介して接着されている。ここで、薄膜容量素子６３の平面的サイズは半導体構成体７６の平面的サイズよりもある程度大きくなっている。   A planarizing film 75 made of a thermosetting resin such as a polyimide resin is provided on the upper surface of the lower insulating film 70 including the vertical conduction portions 72 and 74. The lower surface of a planar rectangular semiconductor structure 76 having a size somewhat smaller than the size of the base plate 61 is bonded to the central portion of the upper surface of the planarizing film 75 via an adhesive layer 77 made of a die bond material. Here, the planar size of the thin film capacitive element 63 is somewhat larger than the planar size of the semiconductor structure 76.

半導体構成体７６は、一般的にはＣＳＰと呼ばれるものであり、平面方形状のシリコン基板（半導体基板）７８を備えている。シリコン基板７８の下面は接着層７７を介してベース板６１の上面に接着されている。シリコン基板７８の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属などからなる複数の接続パッド７９が集積回路に接続されて設けられている。   The semiconductor structure 76 is generally called a CSP, and includes a planar rectangular silicon substrate (semiconductor substrate) 78. The lower surface of the silicon substrate 78 is bonded to the upper surface of the base plate 61 through an adhesive layer 77. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 78, and a plurality of connection pads 79 made of aluminum-based metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit.

接続パッド７９の中央部を除くシリコン基板７８の上面には酸化シリコンなどからなる絶縁膜８０が設けられ、接続パッド７９の中央部は絶縁膜８０に設けられた開口部８１を介して露出されている。絶縁膜８０の上面にはポリイミド系樹脂などの熱硬化性樹脂からなる保護膜８２が設けられている。この場合、絶縁膜８０の開口部８１に対応する部分における保護膜８２には開口部８３が設けられている。   An insulating film 80 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 78 excluding the central portion of the connection pad 79, and the central portion of the connection pad 79 is exposed through an opening 81 provided in the insulating film 80. Yes. A protective film 82 made of a thermosetting resin such as a polyimide resin is provided on the upper surface of the insulating film 80. In this case, an opening 83 is provided in the protective film 82 in a portion corresponding to the opening 81 of the insulating film 80.

保護膜８２の上面には銅などからなる下地金属層８４が設けられている。下地金属層８４の上面全体には銅からなる配線８５が設けられている。下地金属層８４を含む配線８５の一端部は、絶縁膜８０および保護膜８２の開口部８１、８３を介して接続パッド７９に接続されている。配線８５の接続パッド部上面には銅からなる柱状電極８６が設けられている。配線８５を含む保護膜８２の上面にはエポキシ系樹脂などの熱硬化性樹脂からなる封止膜２２がその上面が柱状電極８６の上面と面一となるように設けられている。   A base metal layer 84 made of copper or the like is provided on the upper surface of the protective film 82. A wiring 85 made of copper is provided on the entire upper surface of the base metal layer 84. One end of the wiring 85 including the base metal layer 84 is connected to the connection pad 79 through the openings 81 and 83 of the insulating film 80 and the protective film 82. A columnar electrode 86 made of copper is provided on the upper surface of the connection pad portion of the wiring 85. The sealing film 22 made of a thermosetting resin such as an epoxy resin is provided on the upper surface of the protective film 82 including the wiring 85 so that the upper surface thereof is flush with the upper surface of the columnar electrode 86.

半導体構成体７６の周囲における平坦化膜７５の上面には方形枠状の絶縁層８８がその上面が半導体構成体７６の上面とほぼ面一となるように設けられている。絶縁層８８は、例えば、ガラス繊維やアラミド繊維などにエポキシ系樹脂やポリイミド系樹脂などの熱硬化性樹脂を含浸させたもの、あるいは、エポキシ系樹脂などの熱硬化性樹脂のみからなっている。   A rectangular frame-like insulating layer 88 is provided on the upper surface of the planarizing film 75 around the semiconductor structure 76 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 76. The insulating layer 88 is made of, for example, a glass fiber or an aramid fiber impregnated with a thermosetting resin such as an epoxy resin or a polyimide resin, or a thermosetting resin such as an epoxy resin.

半導体構成体７６および絶縁層８８の上面には、絶縁層８８と同一の材料からなる上層絶縁膜８９がその上面を平坦とされて設けられている。半導体構成体７６の柱状電極８６の上面中央部に対応する部分における上層絶縁膜８９には開口部９０が設けられている。上下導通部７２、７４の各上面中央部に対応する部分における上層絶縁膜８９、絶縁層８８および平坦化膜７５には開口部９１、９２が設けられている。   An upper insulating film 89 made of the same material as the insulating layer 88 is provided on the upper surface of the semiconductor structure 76 and the insulating layer 88 with the upper surface being flat. An opening 90 is provided in the upper insulating film 89 at a portion corresponding to the center of the upper surface of the columnar electrode 86 of the semiconductor structure 76. Openings 91, 92 are provided in the upper insulating film 89, the insulating layer 88, and the planarizing film 75 in the portions corresponding to the center portions of the upper surfaces of the upper and lower conductive portions 72, 74.

上層絶縁膜８９の上面には銅などからなる下地金属層９３が設けられている。下地金属層９３の上面全体には銅からなる上層配線９４が設けられている。下地金属層９３を含む上層配線９４は、開口部９１、９２、９３を介して上下導通部９１、９３、９５の上面に適宜に接続されている。   A base metal layer 93 made of copper or the like is provided on the upper surface of the upper insulating film 89. An upper layer wiring 94 made of copper is provided on the entire upper surface of the base metal layer 93. The upper wiring 94 including the base metal layer 93 is appropriately connected to the upper surfaces of the upper and lower conductive portions 91, 93, 95 through the openings 91, 92, 93.

上層配線９４を含む上層絶縁膜８９の上面にはソルダーレジストなどからなるオーバーコート膜９５が設けられている。上層配線９４の接続パッド部に対応する部分におけるオーバーコート膜９５には開口部９６が設けられている。開口部９６内およびその上方には半田ボール９７が上層配線９４の接続パッド部に接続されて設けられている。複数の半田ボール９７は、オーバーコート膜９５上にマトリクス状に配置されている。   An overcoat film 95 made of a solder resist or the like is provided on the upper surface of the upper insulating film 89 including the upper wiring 94. An opening 96 is provided in the overcoat film 95 in a portion corresponding to the connection pad portion of the upper wiring 94. Solder balls 97 are provided in and above the opening 96 so as to be connected to the connection pad portion of the upper layer wiring 94. The plurality of solder balls 97 are arranged in a matrix on the overcoat film 95.

次に、この半導体装置の製造方法の一例について説明する。まず、図２５に示すように、図２４に示す完成された半導体装置を複数個形成することが可能な面積を有するベース板６１を用意する。ベース板６１は、限定する意味ではないが、平面方形状である。ベース板６１は、例えば、ガラス繊維などにエポキシ系樹脂などの熱硬化性樹脂を含浸させ、熱硬化性樹脂を硬化させてシート状となしたものである。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 25, a base plate 61 having an area capable of forming a plurality of completed semiconductor devices shown in FIG. 24 is prepared. The base plate 61 is not limited, but has a planar square shape. The base plate 61 is formed into a sheet shape by impregnating a glass fiber or the like with a thermosetting resin such as an epoxy resin and curing the thermosetting resin.

次に、ベース板６１の上面に、スクリーン印刷法やスピンコート法などにより、ポリイミド系樹脂などの熱硬化性樹脂からなる下地絶縁膜６２を形成する。次に、下地絶縁膜６２の上面に、スパッタ法によりチタンおよび銅を連続して成膜することにより、下地金属層６４を形成する。次に、下地金属層６４の上面に、下地金属層６４をメッキ電流路とした銅の電解メッキにより、下部電極６５を形成する。   Next, a base insulating film 62 made of a thermosetting resin such as a polyimide resin is formed on the upper surface of the base plate 61 by screen printing or spin coating. Next, a base metal layer 64 is formed on the upper surface of the base insulating film 62 by continuously forming titanium and copper by sputtering. Next, the lower electrode 65 is formed on the upper surface of the base metal layer 64 by electrolytic plating of copper using the base metal layer 64 as a plating current path.

次に、図２６に示すように、下部電極６５の上面にレジスト膜１０１をパターン形成する。この場合、薄膜容量素子形成領域に対応する部分におけるレジスト膜１０１には開口部１０２が形成されている。次に、レジスト膜１０１の開口部１０２内の下部電極６５の上面に、ハードマスク（図示せず）を用いたスパッタ法によりチタンを成膜することにより、下地金属層６６を形成する。   Next, as shown in FIG. 26, a resist film 101 is patterned on the upper surface of the lower electrode 65. In this case, an opening 102 is formed in the resist film 101 in a portion corresponding to the thin film capacitor element formation region. Next, a base metal layer 66 is formed by depositing titanium on the upper surface of the lower electrode 65 in the opening 102 of the resist film 101 by sputtering using a hard mask (not shown).

次に、レジスト膜１０１の開口部１０２内の下地金属層６６の上面に、上記水熱合成法により、ＳＴＯ（ＳｒＴｉＯ3）、ＢＳＴ（（ＢａＳｒ）ＴｉＯ3）、ＰＺＴ（Ｐｂ（ＺｒＴｉ）Ｏ3）などからなる強誘電体膜６７を形成する。この場合も、強誘電体膜６７は、チタンからなる下地金属層６６との反応により形成されるため、レジスト膜１０１の開口部１０２内の下地金属層６６の上面のみに形成される。また、上記水熱合成法の処理温度は比較的低温であるため、ポリイミド系樹脂などの熱硬化性樹脂からなる下地絶縁膜６２が熱的ダメージを受けることはない。 Next, an STO (SrTiO 3 ), BST ((BaSr) TiO 3 ), PZT (Pb (ZrTi) O 3 ) film is formed on the upper surface of the base metal layer 66 in the opening 102 of the resist film 101 by the hydrothermal synthesis method. ) Or the like is formed. Also in this case, since the ferroelectric film 67 is formed by reaction with the base metal layer 66 made of titanium, it is formed only on the upper surface of the base metal layer 66 in the opening 102 of the resist film 101. Further, since the processing temperature of the hydrothermal synthesis method is relatively low, the base insulating film 62 made of a thermosetting resin such as a polyimide resin is not thermally damaged.

次に、レジスト膜１０１の開口部１０２内の強誘電体膜６７の上面に、ハードマスク（図示せず）を用いたスパッタ法によりチタンおよび銅を連続して成膜することにより、下地金属層６８を形成する。次に、レジスト膜１０１の開口部１０２内の下地金属層６８の上面に、銅の無電解メッキにより、上部電極６９を形成する。次に、レジスト膜１０１を剥離する。なお、レジスト膜１０１を剥離するとき、下地金属層６８が剥離しなければ、上部電極６９を省略し、下地金属層６８を上部電極としてもよい。   Next, titanium and copper are continuously formed on the upper surface of the ferroelectric film 67 in the opening 102 of the resist film 101 by a sputtering method using a hard mask (not shown), thereby forming a base metal layer. 68 is formed. Next, the upper electrode 69 is formed on the upper surface of the base metal layer 68 in the opening 102 of the resist film 101 by electroless plating of copper. Next, the resist film 101 is peeled off. When the resist film 101 is peeled off, if the base metal layer 68 is not peeled off, the upper electrode 69 may be omitted and the base metal layer 68 may be used as the upper electrode.

次に、図２７に示すように、上部電極６９を含む下部電極６５の上面に、スクリーン印刷法やスピンコート法などにより、ポリイミド系樹脂などの熱硬化性樹脂からなる下層絶縁膜７０を形成する。次に、レーザビームを照射するレーザ加工あるいはフォトリソグラフィ法により、下部電極６５および上部電極６９の各上面周辺部の所定の箇所に対応する部分における下層絶縁膜７０に開口部７１、７３を形成する。   Next, as shown in FIG. 27, a lower insulating film 70 made of a thermosetting resin such as a polyimide resin is formed on the upper surface of the lower electrode 65 including the upper electrode 69 by screen printing, spin coating, or the like. . Next, openings 71 and 73 are formed in the lower insulating film 70 at portions corresponding to predetermined portions in the peripheral portions of the upper surfaces of the lower electrode 65 and the upper electrode 69 by laser processing or photolithography with laser beam irradiation. .

次に、下層絶縁膜７０の開口部７１、７３内に上下導通部７２、７４を形成する。この場合、上下導通部７２は、下層絶縁膜７０の開口部７１内の下部電極６５の上面に、下地金属層６４をメッキ電流路とした銅の電解メッキにより形成する。上下導通部７４は、下層絶縁膜７０の開口部７３内の上部電極６９の上面に、銅の無電解メッキにより形成する。次に、必要に応じて、上下導通部７２、７４を含む下層絶縁膜７０の上面側を適宜に研磨する。   Next, upper and lower conductive portions 72 and 74 are formed in the openings 71 and 73 of the lower insulating film 70. In this case, the vertical conduction part 72 is formed on the upper surface of the lower electrode 65 in the opening 71 of the lower insulating film 70 by copper electrolytic plating using the base metal layer 64 as a plating current path. The vertical conduction part 74 is formed on the upper surface of the upper electrode 69 in the opening 73 of the lower insulating film 70 by electroless plating of copper. Next, if necessary, the upper surface side of the lower insulating film 70 including the vertical conduction portions 72 and 74 is appropriately polished.

次に、図２８に示すように、上下導通部７２、７４を含む下層絶縁膜７０の上面に、スクリーン印刷法やスピンコート法などにより、ポリイミド系樹脂などの熱硬化性樹脂からなる下層絶縁膜７０を形成する。   Next, as shown in FIG. 28, a lower insulating film made of a thermosetting resin such as a polyimide resin is formed on the upper surface of the lower insulating film 70 including the upper and lower conductive portions 72 and 74 by screen printing, spin coating, or the like. 70 is formed.

ここで、半導体構成体７６のシリコン基板７８の下面に接着層７７が設けられたものを用意する。接着層７７を有する半導体構成体７６は、例えば、ウエハ状態のシリコン基板７８上に配線８５、柱状電極８６、封止膜８７を形成した後、ウエハ状態のシリコン基板７８の下面に、ダイアタッチメントフィルムとして市販されているエポキシ系樹脂やポリイミド系樹脂などのダイボンド材からなる接着層７７を加熱加圧により半硬化させた状態で固着し、ダイシングにより個片化することにより得られる。   Here, a semiconductor structure 76 having an adhesive layer 77 provided on the lower surface of the silicon substrate 78 is prepared. The semiconductor structure 76 having the adhesive layer 77 is formed by, for example, forming a wiring 85, a columnar electrode 86, and a sealing film 87 on a silicon substrate 78 in a wafer state, and then attaching a die attachment film on the lower surface of the silicon substrate 78 in a wafer state. The adhesive layer 77 made of a die-bonding material such as an epoxy resin or a polyimide resin that is commercially available is fixed in a semi-cured state by heating and pressing, and is obtained by dividing into individual pieces by dicing.

次に、平坦化膜７５の上面の所定の複数箇所にそれぞれ半導体構成体７６のシリコン基板７８の下面に接着された接着層７７を接着する。ここでの接着は、加熱加圧により、接着層７７を本硬化させる。   Next, an adhesive layer 77 bonded to the lower surface of the silicon substrate 78 of the semiconductor structure 76 is bonded to a plurality of predetermined locations on the upper surface of the planarizing film 75. In this bonding, the adhesive layer 77 is fully cured by heating and pressing.

次に、図２９に示すように、半導体構成体７６の周囲における平坦化膜７５の上面に、スクリーン印刷法やスピンコート法などにより液状のエポキシ系樹脂などの熱硬化性樹脂を含む材料を塗布することにより、絶縁層形成用層８８ａを形成する。次に、絶縁層形成用層８８ａの上面に第２の絶縁膜形成用シート８９ａを配置する。この場合、第２の絶縁膜形成用シート８９ａは、ガラス繊維などにエポキシ系樹脂などの熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態としたものである。   Next, as shown in FIG. 29, a material containing a thermosetting resin such as a liquid epoxy resin is applied to the upper surface of the planarizing film 75 around the semiconductor structure 76 by a screen printing method, a spin coating method, or the like. Thus, the insulating layer forming layer 88a is formed. Next, the second insulating film forming sheet 89a is disposed on the upper surface of the insulating layer forming layer 88a. In this case, the second insulating film forming sheet 89a is obtained by impregnating a glass fiber or the like with a thermosetting resin such as an epoxy resin to make the thermosetting resin semi-cured.

次に、図３０に示すように、一対の加熱加圧板１０３、１０４を用いて上下から絶縁層形成用層８８ａおよび第２の絶縁膜形成用シート８９ａを加熱加圧すると、半導体構成体７６の周囲における第１の絶縁膜７５の上面に絶縁層８８が形成され、且つ、半導体構成体７６および絶縁層８８の上面に上層絶縁膜８９が形成される。この場合、上層絶縁膜８９の上面は、上側の加熱加圧板１０３の下面によって押さえ付けられるため、平坦面となる。   Next, as shown in FIG. 30, when the insulating layer forming layer 88 a and the second insulating film forming sheet 89 a are heated and pressed from above and below using the pair of heating and pressing plates 103 and 104, An insulating layer 88 is formed on the upper surface of the first insulating film 75 in the periphery, and an upper insulating film 89 is formed on the upper surfaces of the semiconductor structure 76 and the insulating layer 88. In this case, the upper surface of the upper insulating film 89 is pressed by the lower surface of the upper heating / pressing plate 103, and thus becomes a flat surface.

次に、図３１に示すように、レーザビームを照射するレーザ加工あるいはフォトリソグラフィ法により、半導体構成体７６の柱状電極８６の上面中央部に対応する部分における上層絶縁膜８９に開口部９０を形成し、且つ、上下導通部７２、７４の各上面中央部に対応する部分における上層絶縁膜８９、絶縁層８８および平坦化膜７５に開口部９１、９２を形成する。次に、必要に応じて、開口部９０、９１、９２内などに発生したエポキシスミアなどをデスミア処理により除去する。   Next, as shown in FIG. 31, an opening 90 is formed in the upper insulating film 89 at a portion corresponding to the center of the upper surface of the columnar electrode 86 of the semiconductor structure 76 by laser processing or photolithography with laser beam irradiation. In addition, openings 91 and 92 are formed in the upper insulating film 89, the insulating layer 88, and the planarizing film 75 in the portions corresponding to the central portions of the upper surfaces of the upper and lower conductive portions 72 and 74. Next, if necessary, epoxy smear generated in the openings 90, 91, and 92 is removed by desmear treatment.

次に、図３２に示すように、開口部９０、９１、９２を介して露出された柱状電極８６および上下導通部７２、７４の各上面を含む上層絶縁膜８９の上面全体に下地金属層９３を形成する。この場合、下地金属層９３は、無電解メッキにより形成された銅層のみであってもよく、またスパッタ法により形成された銅層のみであってもよく、さらにスパッタ法により形成されたチタンなどの薄膜層上にスパッタ法により銅層を形成したものであってもよい。   Next, as shown in FIG. 32, the base metal layer 93 is formed on the entire upper surface of the upper insulating film 89 including the upper surfaces of the columnar electrode 86 and the upper and lower conductive portions 72, 74 exposed through the openings 90, 91, 92. Form. In this case, the base metal layer 93 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and further may be titanium formed by sputtering. A copper layer may be formed on the thin film layer by sputtering.

次に、下地金属層９３の上面にメッキレジスト膜１０５をパターン形成する。この場合、上層配線９４形成領域に対応する部分におけるメッキレジスト膜１０５には開口部１０６が形成されている。次に、メッキレジスト膜１０５の開口部１０６内の下地金属層９３の上面に、下地金属層９３をメッキ電流路として銅の電解メッキを行なうことにより、上層配線９４を形成する。次に、メッキレジスト膜１０５を剥離し、次いで、上層配線９４をマスクとして下地金属層９３の不要な部分をエッチングして除去すると、図３３に示すように、上層配線９４下にのみ下地金属層９３が残存される。   Next, a plating resist film 105 is patterned on the upper surface of the base metal layer 93. In this case, an opening 106 is formed in the plating resist film 105 in a portion corresponding to the upper layer wiring 94 formation region. Next, the upper wiring 94 is formed on the upper surface of the base metal layer 93 in the opening 106 of the plating resist film 105 by performing electrolytic plating of copper using the base metal layer 93 as a plating current path. Next, the plating resist film 105 is peeled, and then unnecessary portions of the base metal layer 93 are removed by etching using the upper layer wiring 94 as a mask. As shown in FIG. 93 remains.

次に、図３４に示すように、上層配線９４を含む上層絶縁膜８９の上面に、スクリーン印刷法やスピンコート法などにより、ソルダーレジストなどからなるオーバーコート膜９５を形成する。この場合、上層配線９４の接続パッド部に対応する部分におけるオーバーコート膜９５には開口部９６が形成されている。   Next, as shown in FIG. 34, an overcoat film 95 made of a solder resist or the like is formed on the upper surface of the upper insulating film 89 including the upper wiring 94 by a screen printing method, a spin coating method, or the like. In this case, an opening 96 is formed in the overcoat film 95 at a portion corresponding to the connection pad portion of the upper layer wiring 94.

次に、開口部９６内およびその上方に半田ボール９７を上層配線９４の接続パッド部に接続させて形成する。次に、互いに隣接する半導体構成体７６間において、オーバーコート膜９５、上層絶縁膜８９、絶縁層８８、平坦化膜７５、下層絶縁膜７０、下部電極６５、下地金属層６４、下地絶縁膜６２およびベース板６１を切断すると、図２４に示す半導体装置が複数個得られる。本実施形態によれば、薄膜容量素子６３の面積を半導体構成体７６より大きくすることができ、且つ、誘電体として強誘電体膜６７を用いることができるため、薄膜容量素子６３の容量値を上記第１、第２実施形態の場合より更に大きくすることができる。   Next, solder balls 97 are formed in and above the openings 96 by connecting them to the connection pads of the upper wiring 94. Next, between the semiconductor structures 76 adjacent to each other, the overcoat film 95, the upper insulating film 89, the insulating layer 88, the planarizing film 75, the lower insulating film 70, the lower electrode 65, the base metal layer 64, and the base insulating film 62 are provided. When the base plate 61 is cut, a plurality of semiconductor devices shown in FIG. 24 are obtained. According to the present embodiment, the area of the thin film capacitive element 63 can be made larger than that of the semiconductor structure 76, and the ferroelectric film 67 can be used as a dielectric. It can be made larger than in the case of the first and second embodiments.

（第５実施形態）
例えば、上記第４実施形態では、図２４に示すように、ベース板１上に、下から順に、下地金属層６４、下部電極６５、下地金属層６６、強誘電体膜６７、下地金属層６８および上部電極６９からなる１層の薄膜容量素子６３を形成した場合について説明したが、これに限らず、２層以上としてもよく、例えば、図３５に示すこの発明の第５実施形態のように、２層としてもよい。 (Fifth embodiment)
For example, in the fourth embodiment, as shown in FIG. 24, the base metal layer 64, the lower electrode 65, the base metal layer 66, the ferroelectric film 67, and the base metal layer 68 are formed on the base plate 1 in this order from the bottom. However, the present invention is not limited to this, and the number of layers may be two or more. For example, as in the fifth embodiment of the present invention shown in FIG. It is good also as two layers.

すなわち、下地絶縁膜６２の上面には、下から順に、下地金属層６４Ａ、下部電極６５Ａ、下地金属層６６Ａ、強誘電体膜６７Ａ、下地金属層６８Ａおよび上部電極６９Ａからなる第１の薄膜容量素子６３Ａが設けられている。この場合、下地金属層６４Ａを含む下部電極６５Ａの一部は下地金属層６６Ａを含む強誘電体膜６７Ａの外側に配置されている。上部電極６９Ａを含む下部電極６５Ａの上面には第１の下層絶縁膜７０Ａが設けられている。   That is, on the upper surface of the base insulating film 62, in order from the bottom, the first thin film capacitor including the base metal layer 64A, the lower electrode 65A, the base metal layer 66A, the ferroelectric film 67A, the base metal layer 68A, and the upper electrode 69A. An element 63A is provided. In this case, a part of the lower electrode 65A including the base metal layer 64A is disposed outside the ferroelectric film 67A including the base metal layer 66A. A first lower insulating film 70A is provided on the upper surface of the lower electrode 65A including the upper electrode 69A.

第１の下層絶縁膜７０Ａの上面には、下から順に、下地金属層６４Ｂ、下部電極６５Ｂ、下地金属層６６Ｂ、強誘電体膜６７Ｂ、下地金属層６８Ｂおよび上部電極６９Ｂからなる第２の薄膜容量素子６３Ｂが設けられている。この場合、下地金属層６４Ｂを含む下部電極６５Ｂの一部は下地金属層６６Ｂを含む強誘電体膜６７Ｂの外側に配置されている。上部電極６９Ｂおよび下部電極６５Ｂを含む第１の下層絶縁膜７０Ａの上面には第２の下層絶縁膜７０Ｂが設けられている。   On the upper surface of the first lower insulating film 70A, a second thin film comprising a base metal layer 64B, a lower electrode 65B, a base metal layer 66B, a ferroelectric film 67B, a base metal layer 68B and an upper electrode 69B in this order from the bottom. A capacitive element 63B is provided. In this case, a part of the lower electrode 65B including the base metal layer 64B is disposed outside the ferroelectric film 67B including the base metal layer 66B. A second lower insulating film 70B is provided on the upper surface of the first lower insulating film 70A including the upper electrode 69B and the lower electrode 65B.

第２の下層絶縁膜７０Ｂの上面中央部には半導体構成体７６の下面が接着層７７を介して接着されている。下地金属層９３を含む上部電極９４は、上層絶縁膜８９、絶縁層８８、第２の下層絶縁膜７０Ｂおよび第１の下層絶縁膜７０Ａに設けられた開口部９１Ａおよび９２Ａを介して第１の薄膜容量素子６３Ａの下部電極６４Ａおよび上部電極６９Ａに接続され、また上層絶縁膜８９、絶縁層８８および第２の下層絶縁膜７０Ｂに設けられた開口部９１Ｂおよび９２Ｂを介して第２の薄膜容量素子６３Ｂの下部電極６４Ｂおよび上部電極６９Ｂに接続されている。本実施形態によれば、薄膜容量素子６３Ａ，６３Ｂを積層することにより、その容量値を上記第４実施形態の場合より更に大きくすることができる。   The lower surface of the semiconductor structure 76 is bonded to the central portion of the upper surface of the second lower insulating film 70 </ b> B through the adhesive layer 77. The upper electrode 94 including the base metal layer 93 includes the first insulating layer 89, the insulating layer 88, the second lower layer insulating film 70B, and the openings 91A and 92A provided in the first lower layer insulating film 70A. The second thin film capacitor is connected to the lower electrode 64A and the upper electrode 69A of the thin film capacitive element 63A, and through the openings 91B and 92B provided in the upper insulating film 89, the insulating layer 88, and the second lower insulating film 70B. The element 63B is connected to the lower electrode 64B and the upper electrode 69B. According to the present embodiment, by laminating the thin film capacitive elements 63A and 63B, the capacitance value can be made larger than in the case of the fourth embodiment.

（第６実施形態）
例えば、上記第４実施形態では、図２４に示すように、半導体構成体７６および絶縁層８８上に上層絶縁膜８９および上層配線９４をそれぞれ１層ずつ形成した場合について説明したが、これに限らず、それぞれ２層以上としてもよく、例えば、図３６に示すこの発明の第６実施形態のように、それぞれ２層としてもよい。 (Sixth embodiment)
For example, in the fourth embodiment, as shown in FIG. 24, the case where one upper insulating film 89 and one upper wiring 94 are formed on the semiconductor structure 76 and the insulating layer 88 has been described. Instead, each may have two or more layers. For example, each may have two layers as in the sixth embodiment of the present invention shown in FIG.

すなわち、半導体構成体７６および絶縁層８８の上面には第１の上層絶縁膜８９Ａが設けられている。第１の上層絶縁膜８９Ａの上面には第１の下地金属層９３Ａを含む第１の上層配線９４Ａが設けられている。第１の下地金属層９３Ａを含む第１の上層配線９４Ａは、第１の上層絶縁膜８９Ａの開口部９０Ａを介して半導体構成体７６の柱状電極８６の上面に接続されている。   That is, the first upper insulating film 89 </ b> A is provided on the upper surfaces of the semiconductor structure 76 and the insulating layer 88. A first upper layer wiring 94A including a first base metal layer 93A is provided on the upper surface of the first upper layer insulating film 89A. The first upper wiring 94A including the first base metal layer 93A is connected to the upper surface of the columnar electrode 86 of the semiconductor structure 76 through the opening 90A of the first upper insulating film 89A.

第１の上層配線９４Ａを含む第１の上層絶縁膜８９Ａの上面には第２の上層絶縁膜８９Ｂが設けられている。第２の上層絶縁膜８９Ｂの上面には第２の下地金属層９３Ｂを含む第２の上層配線９４Ｂが設けられている。第２の下地金属層９３Ｂを含む第２の上層配線９４Ｂは、第２の上層絶縁膜８９Ｂの開口部９０Ｂを介して第１の上層配線９４Ａの接続パッド部に接続されている。   A second upper insulating film 89B is provided on the upper surface of the first upper insulating film 89A including the first upper wiring 94A. A second upper layer wiring 94B including a second base metal layer 93B is provided on the upper surface of the second upper layer insulating film 89B. The second upper layer wiring 94B including the second base metal layer 93B is connected to the connection pad portion of the first upper layer wiring 94A through the opening 90B of the second upper layer insulating film 89B.

第２の上層配線９４Ｂを含む第２の上層絶縁膜８９Ｂの上面にはオーバーコート膜９５が設けられている。第２の上層配線９４Ｂの接続パッド部に対応する部分におけるオーバーコート膜９５には開口部９６が設けられている。開口部９６内およびその上方には半田ボール９７が第２の上層配線９４Ｂの接続パッド部に接続されて設けられている。   An overcoat film 95 is provided on the upper surface of the second upper layer insulating film 89B including the second upper layer wiring 94B. An opening 96 is provided in the overcoat film 95 in a portion corresponding to the connection pad portion of the second upper layer wiring 94B. Solder balls 97 are provided in and above the opening 96 so as to be connected to the connection pad portion of the second upper layer wiring 94B.

（その他の実施形態）
例えば、図２４に示す半導体装置において、薄膜容量素子６３を複数に分割するようにしてもよい。また、例えば、図２４に示す半導体装置では、半導体構成体７６として、外部接続用電極としての柱状電極８６および封止膜８７を有する場合について説明したが、これに限らず、例えば、柱状電極８６および封止膜８７を有せず、外部接続用電極としての接続パッド部を有する配線８５を有するものとしてもよい。 (Other embodiments)
For example, in the semiconductor device shown in FIG. 24, the thin film capacitive element 63 may be divided into a plurality of parts. For example, in the semiconductor device shown in FIG. 24, the case where the semiconductor structure 76 includes the columnar electrode 86 and the sealing film 87 as external connection electrodes has been described. The wiring 85 may be provided with a connection pad portion as an external connection electrode without the sealing film 87.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初の工程の断面図。Sectional drawing of the initial process in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. 図１３のXIII−XIII線に沿う一部を省略した平面図。The top view which abbreviate | omitted one part along the XIII-XIII line | wire of FIG. 図１３に示す半導体装置の製造方法の一例において、当初の工程の断面図 。FIG. 14 is a cross-sectional view of an initial step in the example of the method for manufacturing the semiconductor device shown in FIG. 13. 図１５に続く工程の断面図。FIG. 16 is a cross-sectional view of the process following FIG. 15. 図１６に続く工程の断面図。FIG. 17 is a cross-sectional view of the process following FIG. 16. 図１７に続く工程の断面図。FIG. 18 is a cross-sectional view of the process following FIG. 17. 図１８に続く工程の断面図。FIG. 19 is a cross-sectional view of the process following FIG. 18. 図１９に続く工程の断面図。FIG. 20 is a cross-sectional view of the process following FIG. 19. 図２０に続く工程の断面図。FIG. 21 is a cross-sectional view of the process following FIG. 20. この発明の第３実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 3rd Embodiment of this invention. 図２２のXXIII−XXIII線に沿う一部を省略した平図。The top view which abbreviate | omitted a part along the XXIII-XXIII line | wire of FIG. この発明の第４実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 4th Embodiment of this invention. 図２４に示す半導体装置の製造方法の一例において、当初の工程の断面図 。FIG. 25 is a cross-sectional view of an initial step in the example of the method for manufacturing the semiconductor device shown in FIG. 24. 図２５に続く工程の断面図。FIG. 26 is a sectional view of a step following FIG. 25. 図２６に続く工程の断面図。FIG. 27 is a sectional view of a step following FIG. 26; 図２７に続く工程の断面図。FIG. 28 is a sectional view of a step following FIG. 27. 図２８に続く工程の断面図。FIG. 29 is a sectional view of a step following FIG. 28. 図２９に続く工程の断面図。FIG. 30 is a sectional view of a step following FIG. 29; 図３０に続く工程の断面図。FIG. 31 is a sectional view of a step following FIG. 30. 図３１に続く工程の断面図。FIG. 32 is a cross-sectional view of the process following FIG. 31. 図３２に続く工程の断面図。FIG. 33 is a sectional view of a step following FIG. 32. 図３３に続く工程の断面図。FIG. 34 is a sectional view of a step following FIG. 33. この発明の第５実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 5th Embodiment of this invention. この発明の第６実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 6th Embodiment of this invention.

符号の説明Explanation of symbols

１ シリコン基板
２ 接続パッド
３ 絶縁膜
５ 保護膜
７ 薄膜容量素子
８ 下部電極
９ 強誘電体膜
１１ 上部電極
１２ 絶縁膜
１５ 配線
１６ 柱状電極
１７ 半田ボール
６１ ベース板
６２ 下地絶縁膜
６３ 薄膜容量素子
６５ 下部電極
６７ 強誘電体膜
６９ 上部電極
７０ 下層絶縁膜
７２、７４ 上下導通部
７５ 平坦化膜
７６ 半導体構成体
７７ 接着層
７８ シリコン基板
７９ 接続パッド
８０ 絶縁膜
８２ 保護膜
８５ 配線
８６ 柱状電極
８７ 封止膜
８９ 上層絶縁膜
９４ 上層配線
９５ オーバーコート膜
９７ 半田ボール DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 5 Protective film 7 Thin film capacitive element 8 Lower electrode 9 Ferroelectric film 11 Upper electrode 12 Insulating film 15 Wiring 16 Columnar electrode 17 Solder ball 61 Base plate 62 Underlying insulating film 63 Thin film capacitive element 65 Lower electrode 67 Ferroelectric film 69 Upper electrode 70 Lower insulating film 72, 74 Vertical conduction part 75 Flattening film 76 Semiconductor structure 77 Adhesive layer 78 Silicon substrate 79 Connection pad 80 Insulating film 82 Protective film 85 Wiring 86 Columnar electrode 87 Sealing Stop film 89 Upper layer insulating film 94 Upper layer wiring 95 Overcoat film 97 Solder ball

Claims (12)

ベース板と、
前記ベース板上に設けられた下部電極、該下部電極上に水熱合成法により形成されて設けられた強誘電体膜および該強誘電体膜上に設けられた上部電極を有する薄膜容量素子と、
前記薄膜容量素子を覆うように設けられた下層絶縁膜と、前記下層絶縁膜上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた外部接続用電極を有する平面方形状のシリコン基板と、
前記平面方形状のシリコン基板の周囲における前記下層絶縁膜上に設けられた絶縁層と、
前記平面方形状のシリコン基板および前記絶縁層上に設けられた上層絶縁膜と、
前記上層絶縁膜上に前記平面方形状のシリコン基板の外部接続用電極、前記薄膜容量素子の下部電極および上部電極に電気的に接続されて設けられた上層配線と、
を具備することを特徴とする半導体装置。 A base plate,
A thin film capacitor having a lower electrode provided on the base plate, a ferroelectric film formed by hydrothermal synthesis on the lower electrode, and an upper electrode provided on the ferroelectric film; ,
A lower insulating film provided to cover the thin film capacitor, a semiconductor substrate provided on the lower insulating film and having a plurality of connection pads, and electrically connected to the connection pads on the semiconductor substrate A planar rectangular silicon substrate having external connection electrodes provided;
An insulating layer provided on the lower insulating film around the planar rectangular silicon substrate ;
An upper insulating film provided on the planar rectangular silicon substrate and the insulating layer;
An upper layer wiring electrically connected to the external connection electrode of the planar rectangular silicon substrate , the lower electrode and the upper electrode of the thin film capacitive element on the upper insulating film;
A semiconductor device comprising: 請求項１に記載の発明において、前記薄膜容量素子の平面的サイズは前記平面方形状のシリコン基板の平面的サイズよりも大きくなっていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1 , wherein a planar size of the thin film capacitor element is larger than a planar size of the planar rectangular silicon substrate . 請求項１に記載の発明において、前記上層配線の接続パッド部を除く部分を覆うオーバーコート膜を有することを特徴とする半導体装置。 2. The semiconductor device according to claim 1 , further comprising an overcoat film that covers a portion of the upper wiring except for a connection pad portion. 請求項３に記載の発明において、前記上層配線の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。 4. The semiconductor device according to claim 3 , wherein a solder ball is provided on a connection pad portion of the upper layer wiring. 上面に複数の接続パッドを有する半導体基板と、前記半導体基板上に前記接続パッドを除く部分を覆うように設けられた樹脂からなる第１絶縁膜と、前記第１絶縁膜上に前記接続パッドに接続されて設けられた下部電極、該下部電極上に設けられた強誘電体膜および該強誘電体膜上に設けられた上部電極を有する薄膜容量素子とを具備する半導体装置の製造方法において、
前記薄膜容量素子の強誘電体膜を水熱合成法により形成することを特徴とする半導体装置の製造方法。 A semiconductor substrate having a plurality of connection pads on an upper surface; a first insulating film made of a resin provided on the semiconductor substrate so as to cover a portion excluding the connection pads; and the connection pads on the first insulating film. In a method of manufacturing a semiconductor device comprising a lower electrode connected and a ferroelectric film provided on the lower electrode and a thin film capacitor element having an upper electrode provided on the ferroelectric film,
A method of manufacturing a semiconductor device, comprising forming a ferroelectric film of the thin film capacitor by a hydrothermal synthesis method. 請求項５に記載の発明において、前記薄膜容量素子を覆う第２絶縁膜を形成し、前記第２絶縁膜上に配線を形成し、該配線の一端を前記薄膜容量素子の上部電極に接続することを特徴とする半導体装置の製造方法。 6. The semiconductor device according to claim 5 , wherein a second insulating film that covers the thin film capacitive element is formed, a wiring is formed on the second insulating film, and one end of the wiring is connected to the upper electrode of the thin film capacitive element. A method for manufacturing a semiconductor device. 請求項６に記載の発明において、前記配線の接続パッド部上に柱状電極を形成し、前記柱状電極の周囲を覆う封止膜を形成することを特徴とする半導体装置の製造方法。 7. The method of manufacturing a semiconductor device according to claim 6 , wherein a columnar electrode is formed on the connection pad portion of the wiring, and a sealing film covering the periphery of the columnar electrode is formed. 請求項７に記載の発明において、前記柱状電極上に半田ボールを形成することを特徴とする半導体装置の製造方法。 8. The method of manufacturing a semiconductor device according to claim 7 , wherein solder balls are formed on the columnar electrodes. ベース板と、前記ベース板上に設けられた下部電極、該下部電極上に設けられた強誘電体膜および該強誘電体膜上に設けられた上部電極を有する薄膜容量素子と、前記薄膜容量素子を覆うように設けられた下層絶縁膜と、前記下層絶縁膜上に設けられ、且つ、複数の接続パッドを有する半導体基板および該半導体基板上に前記接続パッドに電気的に接続されて設けられた外部接続用電極を有する平面方形状のシリコン基板と、前記平面方形状のシリコン基板の周囲における前記下層絶縁膜上に設けられた絶縁層と、前記平面方形状のシリコン基板および前記絶縁層上に設けられた上層絶縁膜と、前記上層絶縁膜上に前記平面方形状のシリコン基板の外部接続用電極、前記薄膜容量素子の下部電極および上部電極に電気的に接続されて設けられた上層配線とを具備する半導体装置の製造方法において、
前記薄膜容量素子の強誘電体膜を水熱合成法により形成することを特徴とする半導体装置の製造方法。 A thin film capacitor having a base plate, a lower electrode provided on the base plate, a ferroelectric film provided on the lower electrode, and an upper electrode provided on the ferroelectric film; and the thin film capacitor A lower insulating film provided to cover the element, a semiconductor substrate provided on the lower insulating film and having a plurality of connection pads, and provided on the semiconductor substrate and electrically connected to the connection pads external connection and the silicon substrate of square planar shape having an electrode, the planar sides and an insulating layer provided on the lower insulating film around the silicon substrate shape, the silicon substrate and the insulating layer of the planar square shape and an upper insulating film provided on the external connection electrodes of the silicon substrate of the square planar shape on the upper insulating film, provided to be electrically connected to the lower electrode and the upper electrode of the thin film capacitor element The method of manufacturing a semiconductor device including an upper layer interconnection,
A method of manufacturing a semiconductor device, comprising forming a ferroelectric film of the thin film capacitor by a hydrothermal synthesis method. 請求項９に記載の発明において、前記ベース板上に熱硬化性樹脂からなる下地絶縁膜を形成し、該下地絶縁膜上に前記下部電極を形成することを特徴とする半導体装置の製造方法。 10. The method for manufacturing a semiconductor device according to claim 9 , wherein a base insulating film made of a thermosetting resin is formed on the base plate, and the lower electrode is formed on the base insulating film. 請求項９に記載の発明において、前記絶縁層上に、前記上層配線の接続パッド部を除く部分を覆うオーバーコート膜を形成することを特徴とする半導体装置の製造方法。 10. The method of manufacturing a semiconductor device according to claim 9 , wherein an overcoat film is formed on the insulating layer so as to cover a portion excluding the connection pad portion of the upper layer wiring. 請求項１１に記載の発明において、前記上層配線の接続パッド部上に半田ボールを形成することを特徴とする半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 11 , wherein solder balls are formed on connection pad portions of the upper wiring.
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