JP2002083893A - Semiconductor package substrate, semiconductor device and their manufacturing methods - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new semiconductor package substrate with high reliability, which is easy to make multiple pins, densify and refine and which dispenses with mounting a stiffener, by improving existing semiconductor packages and flatness of multi-layered wiring structure film, a semiconductor device using the semiconductor package substrate and its manufacture. SOLUTION: A multi-layered wiring structure film 15 is laminated on a metal base 11 which is made of metal plates and has an opening for fitting a semiconductor element 16, semiconductor element 16 is fit into the opening of metal base 11 to flip-flop connect to a metal pad 12, and solder balls 19 for BGA are mounted on a metal pad 29. At that time, the surface of semiconductor element 16 is preferably placed on the same plane as that of metal base 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package substrate using a metal substrate, a semiconductor device using the same, and a method of manufacturing the same. The present invention relates to a semiconductor package substrate to be improved and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a multilayer wiring board, for example, a multilayer wiring board on which a semiconductor element is mounted has been disclosed in Japanese Patent Application Laid-Open No. 8-33047.
A ceramic multilayer wiring board capable of high-density wiring as disclosed in Japanese Patent Application Laid-Open No. 4 (1999) -143 is widely used. This ceramic multilayer wiring board is composed of an insulating substrate made of alumina or the like and a wiring conductor made of a high melting point metal such as W and Mo formed on the surface thereof, and a concave portion is formed in a part of the insulating substrate. The semiconductor element is housed in the recess and sealed with a lid.

Recently, as disclosed in Japanese Patent Application Laid-Open No. 11-17058 and Japanese Patent No. 2679681, a copper wiring is formed by using an organic resin as an insulating material by an etching method and a plating method. 2. Description of the Related Art A printed circuit board that forms a fine circuit and is multilayered, for example, a build-up board is used. An organic resin multilayer wiring board using an organic resin as an insulating material has also been proposed for application to a multichip module (MCM) or the like on which a large number of semiconductor elements are mounted. Such a printed board, in particular, a build-up board in which a thin film of an insulating layer is formed on a printed board can form a fine circuit on a surface layer, and is effective in increasing the density of the circuit.

Further, a chip size package (CSP)
As a form of a ball grid array (BGA), a tape-type substrate in which copper wiring is formed on a film of polyimide or the like disclosed in Japanese Patent Application Laid-Open No. 2000-58701 is used.

[0005]

However, the prior art has the following problems. The ceramic constituting the insulating substrate in the ceramic multilayer wiring board is:
Due to its hard and brittle nature, damage such as chipping and cracking is likely to occur in the manufacturing process and the transport process, and if damage occurs, the hermetic sealing of the semiconductor element will be impaired and it will be defective, resulting in a defective ceramic multilayer wiring board. There is a problem that the yield decreases.

A ceramic multilayer wiring board is manufactured by printing wiring on a green sheet before firing, laminating the respective sheets, and firing. In this manufacturing process, since shrinkage is caused by baking at a high temperature, there is a problem that a shape defect such as warpage, deformation and variation in dimensions is liable to occur in the fired substrate. Due to the occurrence of such a shape defect, it is not possible to sufficiently cope with the strict flatness required for a high-density circuit board and a substrate such as a flip chip. In other words, such a shape defect hinders the increase in the number of pins, the density, and the miniaturization of the circuit, and the flatness of the mounting portion of the semiconductor element is lost. There is a problem that cracks, peeling, and the like are likely to occur in the connected portions, which lowers the reliability of the semiconductor device.

Further, in a build-up board, the board is warped due to a difference in thermal expansion between a printed board used as a core material and an insulating resin film formed on a surface layer. This warpage also becomes an obstacle when flip-chip connecting a semiconductor element having a large number of pins, and as described above, hinders the increase in circuit density and decreases the yield of the build-up substrate.

Further, in a substrate using a tape of polyimide or the like, there is a large displacement due to expansion and contraction of the tape base material when mounting a semiconductor element, and it is not possible to sufficiently cope with a high density circuit. There is.

Furthermore, in the conventional substrate, a multilayer wiring structure film is formed on the substrate, and a semiconductor element is mounted on the multilayer wiring structure film. There is also a problem that undulation occurs and the connection between the multilayer wiring structure film and the semiconductor element becomes unstable.

Further, in the conventional semiconductor device, it is necessary to mount a stiffener in order to improve the rigidity of the substrate. For example, when a large heat sink that covers a plurality of semiconductor elements is mounted, a stiffener is inserted into a gap between the semiconductor element and the semiconductor element between the substrate and the heat sink. According to this method, although the rigidity of the substrate is improved, the manufacturing process of the semiconductor device is complicated, and the manufacturing cost of the semiconductor device is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is intended to improve the conventional semiconductor package substrate and improve the flatness of a multilayer wiring substrate to increase the number of pins, increase the density, and reduce the size. Is easy and reliable, and
It is an object of the present invention to provide a novel semiconductor package substrate and a semiconductor device which do not require a stiffener, and a method of manufacturing the same.

[0012]

A semiconductor package substrate according to the present invention comprises: a metal base made of a metal plate and having an opening for fitting a semiconductor element; a multilayer wiring structure film laminated on the metal base; Wherein the semiconductor element is mounted on the multilayer wiring structure film in the opening, and the multilayer wiring structure film is formed in a region in the opening on the first surface in contact with the metal base, and And a first metal pad to be connected.

In the present invention, since the multilayer wiring structure film is laminated on the flat metal base, the flatness of the multilayer wiring structure film is improved, and the metal base functions as a reinforcing material for the multilayer wiring structure film. Therefore, the deformation of the multilayer wiring structure film is suppressed, and it is possible to increase the number of pins, increase the density, and reduce the size of the circuit.

Preferably, a metal film is formed on an edge of the opening on a surface of the metal base on the side of the multilayer wiring structure film. Thereby, the stress applied from the metal base to the multilayer wiring structure film can be reduced, and the occurrence of cracks in the multilayer wiring structure film can be suppressed.

[0015] A semiconductor device according to the present invention includes: the semiconductor package substrate; and a semiconductor element fitted into the opening of the metal base in the semiconductor package substrate and connected to the first metal pad. Features.

In the present invention, the semiconductor element is fitted into the opening of the metal base, and this semiconductor element is connected to the outermost surface of the multilayer wiring structure film having no flatness and good flatness. The reliability at the connection part of the element is improved.

In a method of manufacturing a semiconductor package substrate according to the present invention, a step of forming a plurality of first metal pads on a first surface of a metal base made of a metal plate; and a step of forming the first surface on the metal base. A plurality of second metal pads on the surface comprising an insulating layer and a wiring layer, the second metal pads being multilayered so as to be connected to the first metal pads via the wiring layers, respectively; Forming a wiring structure film, and forming an opening for inserting a semiconductor element in the metal base so as to include a region where the first metal pad is formed, and exposing the first metal pad And a step.

In the present invention, a multilayer wiring structure film is laminated on a flat metal base as a substrate, and thereafter, an opening is provided in a region of the metal base where a semiconductor element is to be fitted, so that the multilayer wiring structure film is flattened. In particular, the flatness of the surface of the multilayer wiring structure film to which the semiconductor element is connected can be improved.

In another method of manufacturing a semiconductor package substrate according to the present invention, a step of forming a plurality of first metal pads on a first surface of a metal base made of a metal plate; Forming a metal film on a surface; and forming a plurality of second metal pads on the surface of the metal base, the second metal pads being formed of an insulating layer and a wiring layer. Forming a multi-layer wiring structure film so as to be connected to the first metal pad via the wiring layer, and including an area in the metal base where the first metal pad is formed; Forming an opening for fitting a semiconductor element in contact with the metal film and exposing the first metal pad and a part of the metal film.

Still another method of manufacturing a semiconductor package substrate according to the present invention includes a step of forming a plurality of first metal pads on first and second surfaces of a metal base made of a metal plate, respectively. On the first and second surfaces of the base, an insulating layer and a wiring layer are provided, and a plurality of second metal pads are provided on the surface. The second metal pads are each provided with the first metal pad via the wiring layer. Forming a multi-layer wiring structure film so as to be connected to the metal pad, dividing the metal base into two pieces along a plane parallel to the first surface, and forming each of the divided metal bases. Forming an opening for inserting a semiconductor element so as to include a region where the first metal pad is formed, and exposing the first metal pad.

According to still another method of manufacturing a semiconductor package substrate according to the present invention, there are provided a step of bonding two metal bases made of a metal plate to each other, and a step of bonding the first and second surfaces of the bonded metal base to each other. A step of forming a plurality of first metal pads, respectively; a step of forming a plurality of second metal pads on the surface comprising an insulating layer and a wiring layer on the first and second surfaces of the bonded metal base; Forming a multilayer wiring structure film such that the second metal pad is connected to the first metal pad via the wiring layer, respectively; and A step of dividing into metal bases, and forming an opening for inserting a semiconductor element so as to include a region where the first metal pad is formed in each of the divided metal bases; Exposing a first metal pad, and having a.

A method of manufacturing a semiconductor device according to the present invention is characterized in that a semiconductor element is connected to a first metal pad of a semiconductor package substrate manufactured by the above method.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. First, embodiments of a semiconductor package substrate and a semiconductor device according to the present invention will be described.

FIG. 1 is a diagram showing the configuration of a semiconductor package substrate and a semiconductor device according to a first embodiment of the device of the present invention. FIG. 1A is a perspective view of the semiconductor device viewed from the front side.
FIG. 1B is a perspective view of the semiconductor device viewed from the back side, and FIG.
(C) is a partial sectional view. In this embodiment, the present invention is applied to a full grid BGA.

The semiconductor device shown in FIGS. 1A to 1C includes a semiconductor package substrate 31a and a semiconductor element 16 mounted on the semiconductor package substrate 31a. As shown in FIG. 1A, in the semiconductor package substrate 31a, a metal base 1 made of a metal plate is used.
1, a multilayer wiring structure film 15 is formed. An opening penetrating the center of the metal base 11 is formed. A semiconductor element 16 is fitted into the opening and mounted on the multilayer wiring structure film 15. As shown in FIGS. 1B and 1C, the surface of the multilayer wiring structure film 15 where the metal base 11 and the semiconductor element 16 are not disposed (hereinafter referred to as the back surface of the multilayer wiring structure film 15) Two metal pads 29 are provided, and a BGA solder ball 19 is mounted on the second metal pad 29.

As shown in FIG. 1C, the metal base 11 on the surface of the multilayer wiring structure film 15 on the side where the metal base 11 and the semiconductor element 16 are arranged (hereinafter referred to as the surface of the multilayer wiring structure film 15). A first metal pad 12 for mounting a semiconductor element 16 is provided in the opening of the semiconductor element 16, and the first metal pad 12 is connected to a solder ball 18 of the semiconductor element 16. In addition, the multilayer wiring structure film 1
5, a wiring layer 14 composed of a wiring having a predetermined pattern and an insulating resin filled between the wirings;
Insulating layers 13 made of organic resin are alternately stacked.

The multi-layer wiring structure film 15 is laminated on the metal base 11 by a subtractive method, a semi-additive method, a full-additive method or the like used in the build-up method. The subtractive method is a method of forming a circuit pattern by etching a copper foil on a substrate or a resin as disclosed in, for example, JP-A-10-51105. The semi-additive method is disclosed in, for example, JP-A-9-64493,
This is a method in which electrolytic plating is deposited in a resist after forming a power supply layer, and after removing the resist, the power supply layer is etched to form a circuit pattern. In the full additive method, as disclosed in, for example, JP-A-6-334334, a pattern is formed with a resist after activating the surface of a substrate or a resin, and the resist is used as an insulating layer by an electroless plating method. This is a method of forming a circuit pattern.

The semiconductor element 16 is fitted into the opening of the metal base 11, that is, into the surface side of the multilayer wiring structure film 15,
The solder ball 18 is connected to the first metal pad 12 of the multilayer wiring structure film 15, and the space between the semiconductor element 16 and the multilayer wiring structure film 15 is filled with an underfill 17 between the solder balls 18. .

The BGA solder ball 19 is connected to the second metal pad 29, and the second metal pad 29
Is connected to the uppermost layer of the wiring layer 14, each layer of the wiring layer 14 is connected to each other via a via in the insulating layer 13, and the lowermost layer of the wiring layer 14 is connected to a via in the insulating layer 13. The first metal pad 12 is connected to the semiconductor element 16 via the solder ball 18.

The metal base 11 can be made of at least one kind of metal selected from the group consisting of stainless steel, iron, nickel, copper and aluminum or an alloy thereof. Optimal. Further, the thickness of the metal base 11 is suitably from 0.1 to 1.5 mm.

First metal pad 12 for mounting a semiconductor element
The material constituting the surface connected to the solder ball 18 in (1) is preferably any one of gold, tin, and solder, or an alloy thereof. In this embodiment, the metal pad 1
The surface of 2 is made of gold. FIG. 1 (c)
In the above, the contact surface between the metal pad 12 and the solder ball 18 is on the same plane as the surface of the multilayer wiring structure film 15, but the surface of the metal pad 12 is depressed from the surface of the multilayer wiring structure film 15, It is also possible to make the depression function as a dam for the solder ball 18.

The insulating layer 13 is made of epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB
(Benzocyclobutene) and PBO (p
(olibenzoxazole), and is formed of one or more organic resins selected from the group consisting of: One of these organic resins may be used for all the insulating layers 13 between the wiring layers 14 or the organic resin 2 may be used.
More than one kind of layer may be mixed and arranged between the wiring layers 14. In this embodiment, the insulating layer 13 is formed of, for example, a polyimide resin.
May be formed of a polyimide resin, and the second and subsequent layers may be formed of an epoxy resin.

The metal constituting the wiring in the wiring layer 14 is preferably copper from the viewpoint of cost, but at least one metal selected from the group consisting of gold, silver, aluminum and nickel or an alloy thereof can also be used. It is. In this embodiment, the wiring in the wiring layer 14 is made of copper.

In the semiconductor device according to the first embodiment, a semiconductor element 16 is mounted on a semiconductor package substrate 31a. Next, this mounting method will be described. First, the semiconductor element 16 is flip-chip connected to the metal pad 12 by the solder ball 18, and the underfill 17 is poured into the space between the semiconductor element 16 and the multilayer wiring structure film 15 and is cured. Next, the BGA solder balls 19 are mounted on the metal pads 29 of the multilayer wiring structure film 15. By this step, the semiconductor device shown in FIGS. 1A to 1C is manufactured. FIG. 1C shows an example in which the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18. And the semiconductor element 16 may be electrically connected to the multilayer wiring structure film 15 by means such as wire bonding.

In the semiconductor package substrate of the first embodiment configured as described above, since the multilayer wiring structure film 15 is provided on the flat metal base 11, the multilayer wiring structure film 15 has good flatness. . Further, in the semiconductor device of this embodiment, the semiconductor element 16 is fitted into the opening of the metal base 11 and connected to the outermost surface of the flat multilayer wiring structure film 15 without undulation. The connection with the semiconductor element 16 is stable and high in reliability. Furthermore,
A surface of the semiconductor element 16 that is not connected to the multilayer wiring structure film 15 (hereinafter referred to as a surface of the semiconductor element 16)
Is arranged on the same surface as the surface of the metal base 11 on the side not joined to the multilayer wiring structure film 15 (hereinafter referred to as the surface of the metal base 11). A function as a stiffener that restrains vertical displacement and improves buckling strength can be provided. When the surface of the semiconductor element 16 and the surface of the metal base 11 are not arranged on the same plane,
The metal base 11 can be used as a frame for suppressing deformation of the multilayer wiring structure film 15. Further, since the metal base 11 is made of metal, a function as a ground on the outermost layer can be added.

Next, a description will be given of a second embodiment of the semiconductor package substrate and the semiconductor device according to the present invention. FIG. 2 is a partial cross-sectional view illustrating a configuration of a semiconductor device using the semiconductor package substrate according to the present embodiment. The feature of the semiconductor package substrate according to the present embodiment is that the metal film 35 is provided in the opening of the metal base 11.

In the semiconductor device according to the second embodiment, the semiconductor element 16 is mounted on a semiconductor package substrate 31b. The multilayer wiring structure film 1 in the metal base 11
A metal film 35 is formed on the edge of the opening on the surface on the fifth side. A concave portion for fitting the metal film 35 is formed in the multilayer wiring structure film 15, and the metal film 35 is disposed in the concave portion. The other configuration of the semiconductor device according to the second embodiment is the same as the configuration of the semiconductor device according to the first embodiment described above.

Next, a method for mounting the semiconductor element 16 on the semiconductor package substrate 31b will be described. First, the semiconductor element 16 is flip-chip connected to the metal pad 12 arranged in the opening of the metal base 11 via the solder ball 18. Next, the underfill 17 is poured into the space between the semiconductor element 16 and the multilayer wiring structure film 15 and cured. Next, the BGA solder balls 19 are mounted on the metal pads 29 of the multilayer wiring structure film 15. Through the above-described steps, the semiconductor device shown in FIG. 2 is manufactured. Further, similarly to the first embodiment, the connection between the semiconductor element 16 and the multilayer wiring structure film 15 may be made by wire bonding.

In the semiconductor device according to the second embodiment, the metal film 35 is formed on the multi-layer wiring structure film 1 on the metal base 11.
Because it is formed at the edge of the opening on the surface on the 5th side,
The presence of the metal base 11 alleviates the stress applied from the metal base 11 to the multilayer wiring structure film 15, and prevents the stress from being directly applied to the multilayer wiring structure film 15.
Thereby, it is possible to suppress the occurrence of cracks in the multilayer wiring structure film 15 due to the stress.

Next, a description will be given of a third embodiment of the semiconductor package substrate and the semiconductor device according to the present invention. FIG. 3 is a partial cross-sectional view illustrating a configuration of a semiconductor device using the semiconductor package substrate according to the present embodiment. The feature of the semiconductor package substrate according to the present embodiment is that solder balls 20 are provided on the surfaces of the metal pads 12, and the solder balls 20 protrude from the surface of the multilayer wiring structure film 15. The configuration of a portion other than the solder balls 20 in the semiconductor device of the present embodiment is the same as that of the semiconductor device of the first or second embodiment.

In the semiconductor device according to the third embodiment, the semiconductor element 16 is mounted on a semiconductor package substrate 31c. Next, this mounting method will be described. First, the semiconductor element 16 is flip-chip connected to the metal pad 12 arranged in the opening of the metal base 11 via the solder ball 20. At this time, the semiconductor element 16 is
8 may not be provided, but if the solder ball 18 is provided, the solder ball 18 and the solder ball 2
0, the semiconductor element 16 is connected to the metal pad 12. Next, the underfill 17 is poured into the space between the semiconductor element 16 and the multilayer wiring structure film 15 and cured.
Next, the metal pad 29 in the multilayer wiring structure film 15 is formed.
Then, the BGA solder ball 19 is mounted. Through the above-described steps, the semiconductor device shown in FIG. 3 is manufactured. Further, similarly to the first and second embodiments, the connection between the semiconductor element 16 and the multilayer wiring structure film 15 may be connected by wire bonding.

In the semiconductor device of the third embodiment, when the semiconductor element 16 is flip-chip connected to the multilayer wiring structure film 15, the solder balls 20 function as solder or preliminary solder. Can be achieved. Further, the semiconductor element 16 does not need to include the solder ball 18.

Next, a description will be given of a fourth embodiment of the semiconductor package substrate and the semiconductor device according to the present invention. 4 and 5 are partial cross-sectional views illustrating the configuration of the semiconductor device according to the present embodiment. The features of the semiconductor package substrate of this embodiment are as follows.
The point is that the thin film capacitor 21 is attached to the metal pad 12. The configuration of the semiconductor device of this embodiment other than the thin film capacitor 21 is the same as that of the semiconductor device of the first, second, or third embodiment.

The thin film capacitor 21 is formed by sputtering or vapor deposition.
It is formed by a CVD method, an anodic oxidation method, or the like. This thin film
The material constituting the capacitor 21 is titanium oxide,
Nal, Al_TwoO_Three, SiO_Two, Nb_TwoO_Five, BST (Ba_x
Sr_1-xTiO_Three), PZT (PbZr_xTi_1-xO_Three),
PLZT (Pb_1-yLa_yZr_xTi_1-xO_Three) Or SrB
i _TwoTa_TwoO₉Perovskite materials such as
Good. However, for any of the above compounds, 0 ≦ x
≦ 1, 0 <y <1. In addition, the thin film capacitor 21
Is suitable for organic resins that can achieve the desired dielectric constant.
May be configured.

In the semiconductor device of the third embodiment, since the thin film capacitor 21 is attached to the metal pad 12,
A decoupling capacitor can be provided very close to the semiconductor element 16. Further, in the semiconductor device of this embodiment, as shown in FIG. 5, solder balls 20 may be provided on the surface of the metal pad 12 as in the third embodiment. Further, similarly to the first, second and third embodiments,
The connection between the semiconductor element 16 and the multilayer wiring structure film 15 may be made by wire bonding.

Next, a description will be given of a fifth embodiment of the semiconductor package substrate and the semiconductor device according to the present invention. FIG. 6 (a)
6A to 6C are diagrams showing the configuration of the semiconductor device according to the fifth embodiment. FIG. 6A is a perspective view of the semiconductor device viewed from the front side, and FIG. 6B is a semiconductor device viewed from the back side. FIG. 6C is a partial cross-sectional view. FIGS. 6A to 6C show the configuration of a semiconductor device using the printed circuit board 24 as a carrier base material.

As shown in FIGS. 6A to 6C, the feature of the semiconductor package substrate 31d according to the fifth embodiment is as follows.
A printed circuit board 24 is provided as a carrier base on the semiconductor package substrates 31a, 31b or 31c according to the first to fourth embodiments shown in FIGS. 1 to 5, and the printed circuit board is formed using an anisotropic conductive film or conductive paste 23. That is, conduction is made between the front and back of No. 24. Note that a printed board, a ceramic board, or an organic-inorganic composite board composed of at least one layer is suitable for the carrier base material. As an example of the organic-inorganic composite substrate, GVP (Grid) manufactured by NGK Insulators, Ltd.
Via Plate).

The carrier base material is bonded by any of an adhesive, thermocompression bonding, and bonding using a chemical reaction, and conduction in a desired pattern is performed by an anisotropic conductive film or conductive paste. In the example shown in FIGS. 6A to 6C, the printed circuit board 24 is used as the carrier base material, and the printed circuit board 24 is
Are connected to the metal pads 29 of the multilayer wiring structure film 15 via the conductive paste 23. As a method of connecting the printed board 24 to the metal pads 29, the connection may be performed by providing a connection pad on the surface of the printed board 24 without using the through hole 30, and the through hole 30 may be embedded with an insulating resin. The connection may be made by providing a metal pad on the surface of the insulating resin. Further, the through holes 30 may be embedded with a paste containing metal particles. Further, in order to seal the conductive paste 23 shown in FIG. 6C, the through-hole 30 may be further buried from above the conductive paste 23 with an insulating resin or the like.

The semiconductor device according to the fifth embodiment is formed by mounting a semiconductor element 16 on a semiconductor package substrate 31d. This mounting method will be described. FIG.
As shown in (c), the adhesive 2 is applied to the semiconductor package substrate 31a, 31b or 31c of the first to fourth embodiments so that the printed board 24 can be conducted at a desired position.
2 to form a semiconductor package substrate 31d. The semiconductor element 16 is flip-chip connected to the metal pad 12 on the semiconductor package substrate 31d. At this time, the solder balls 20 (FIG.
If the solder ball 20 is not provided, the connection is made by the solder ball 20. If the solder ball 20 is not provided, the connection is made by the solder ball 18. Further, both the solder ball 20 and the solder ball 18 may be used. Next, the underfill 17 is poured into the space between the semiconductor element 16 and the multilayer wiring structure film 15 and cured. Next, the printed circuit board 2
The BGA solder ball 19 is mounted on the pad on the surface of No. 4. Note that, similarly to the first to fourth embodiments, the semiconductor element 16 may be connected to the multilayer wiring structure film 15 by wire bonding.

In the semiconductor device of the fifth embodiment configured as described above, the ground function can be enhanced by providing the printed circuit board 24 as the carrier base material for the semiconductor package substrate 31d. Further, by incorporating passive components such as resistors and capacitors in the printed circuit board 24, it is possible to easily add functions to the semiconductor package substrate 31d. Further, by using the printed circuit board 24, the stress generated during the secondary mounting can be reduced, and the reliability of the semiconductor device can be improved.

Next, a description will be given of a sixth embodiment of the semiconductor package substrate and the semiconductor device according to the present invention. FIG. 7 is a partial sectional view showing the configuration of the semiconductor device according to the sixth embodiment.

As shown in FIG. 7, the feature of the semiconductor package substrate 31e according to the sixth embodiment is that the semiconductor package substrate 31e according to the first to fourth embodiments shown in FIGS.
a, 31b and 31c, a printed circuit board 24a is provided as a carrier base material, and an anisotropic conductive film or conductive paste 23 is provided.
And through holes 3 in the printed circuit board 24a.
That is, the connection pin 25 is attached to the “0”.

In this embodiment, similarly to the fifth embodiment, the carrier base material is joined by any one of an adhesive, thermocompression bonding, and bonding using a chemical reaction, and a conductive pattern is formed in a desired pattern. Is performed using an anisotropic conductive film or a conductive paste. In the example shown in FIG. 7, a printed circuit board 24a is used as a carrier base material, connection pins 25 are provided using through holes 30 of the printed circuit board 24a, and connection to the outside via the connection pins 25 is established. Is going. At this time, the connection position between the printed board 24a and the metal pad 29 may not be directly below the connection pin 25.

The semiconductor device according to the sixth embodiment is formed by mounting a semiconductor element 16 on a semiconductor package substrate 31e. This mounting method will be described. As shown in FIG. 7, the printed circuit board 24a is bonded to the semiconductor package substrates 31a, 31b or 31c of the first to fourth embodiments by an adhesive 22 so that conduction can be obtained at a desired position. Form. The semiconductor element 16 is flip-chip connected to the metal pad 12 on the semiconductor package substrate 31e. Next, the underfill 17 is poured into the space between the semiconductor element 16 and the multilayer wiring structure film 15 and cured. Next, the printed circuit board 2
The connection pin 25 is mounted in the through hole 30 of 4a. Note that the semiconductor element 1 is similar to the first to fourth embodiments.
6 may be connected to the multilayer wiring structure film 15 by wire bonding.

In the semiconductor device of the sixth embodiment configured as described above, similarly to the semiconductor device of the fifth embodiment, the semiconductor package substrate 31e has a printed circuit board 24a as a carrier base material, thereby enhancing the ground function. Can be achieved. In addition, by incorporating passive components such as resistors and capacitors in the printed circuit board 24a, functions can be easily added to the semiconductor package substrate 31e. Further, by using the printed circuit board 24a, the stress generated during the secondary mounting can be reduced, and the reliability of the semiconductor device can be improved. Furthermore, by using the through holes 30 of the printed circuit board 24a, the connection pins 25 that are firmly attached can be obtained.

Next, a description will be given of a seventh embodiment of the semiconductor package substrate and the semiconductor device according to the present invention. FIG. 8 is a partial sectional view showing the configuration of the semiconductor device according to the seventh embodiment.

As shown in FIG. 8, the semiconductor package substrate 31f according to the seventh embodiment is characterized in that the semiconductor package substrate 31f according to the first to fourth embodiments shown in FIGS.
a, 31b or 31c is provided with a ceramic substrate 26 as a carrier base material. A plurality of wiring layers are provided inside the ceramic substrate 26, and pads are formed on the surface of the ceramic substrate 26.

The semiconductor device according to the seventh embodiment is formed by mounting a semiconductor element 16 on a semiconductor package substrate 31f. This mounting method will be described. As shown in FIG. 8, the ceramic substrate 26 is bonded to the semiconductor package substrates 31a, 31b, or 31c of the first to fourth embodiments by an adhesive 22 so that conduction is obtained at a desired position. Form. The semiconductor element 16 is flip-chip connected to the metal pad 12 on the semiconductor package substrate 31f. Next, the underfill 17 is poured into the space between the semiconductor element 16 and the multilayer wiring structure film 15 and cured. Next, the BGA solder balls 19 are mounted on the pads on the surface of the ceramic substrate 26. At this time, the position of the BGA solder ball 19 may be directly above the via. The semiconductor element 16 may be connected to the multilayer wiring structure film 15 by wire bonding as in the first to fourth embodiments.

In the semiconductor device of the seventh embodiment configured as described above, the ground function can be enhanced by providing the semiconductor package substrate 31f with the ceramic substrate 26 as a carrier base material. Further, by incorporating passive components such as resistors and capacitors in the ceramic substrate 26, it is possible to easily add functions to the semiconductor package substrate 31f. Furthermore, the ceramic substrate 2
By using 6, the stress generated during the secondary mounting can be reduced, and the reliability of the semiconductor device can be improved.

An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below. FIGS. 9A to 9E and FIGS. 10A to 10D are partial cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. The method of this embodiment is for manufacturing a semiconductor device according to the first embodiment (see FIG. 1) of the semiconductor device of the present invention. Note that cleaning and heat treatment are appropriately performed between each step.

First, as shown in FIG.
A plating resist 27 is formed on the surface of the metal base 11 which is a metal plate of 1 to 1.5 mm. The method of forming
If the plating resist 27 is in a liquid state, it is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the plating resist 27 is photosensitive, it is patterned by a photolithography process or the like, and if it is non-photosensitive, it is patterned by a laser processing method or the like.

Next, as shown in FIG. 9B, at least one kind of metal selected from the group consisting of gold, tin and solder is formed in the opening of the plating resist 27 by electrolytic plating or electroless plating. Alternatively, the alloy is deposited to form a surface layer (not shown) of the first metal pad 12. Next, nickel is deposited as a barrier metal (not shown), and copper is further deposited to form a first metal pad 12. At this time, the metal constituting the metal base 11 and the metal pad 1
In the case where an intermetallic compound is formed between the metal layer and the metal forming the surface layer portion, a barrier metal such as nickel is deposited before the surface layer portion of the metal pad 12 is formed. This barrier metal is preferably a metal that can be removed by etching. In the case where the surface of the metal pad 12 is recessed from the surface of the multilayer wiring structure film 15 (see FIG. 10A) in a subsequent step shown in FIG. After being deposited to a thickness of
The metal constituting the surface layer of the metal pad 12 is deposited, nickel is deposited as a barrier metal, and copper is further deposited to form the metal pad 12.

Next, as shown in FIG. 9C, after the plating resist 27 is removed, the surface is cleaned.

Next, as shown in FIG.
Form 3 The method for forming the insulating layer 13 is as follows.
If the insulating resin constituting 3 is liquid, the spin coating method,
An insulating resin is laminated by a die coating method, a curtain coating method, a printing method, or the like, and, if the insulating resin is a dry film, the insulating resin is laminated by a laminating method or the like, and then a process such as drying is performed to solidify the insulating resin. . If the insulating resin is photosensitive, the insulating resin is patterned by a photolithography process or the like, or if the insulating resin is non-photosensitive, a laser processing method or the like is used to pattern the insulating resin to form a via hole 34 and cure. Then, the insulating resin is cured to form the insulating layer 13.

Next, as shown in FIG. 9E, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 14 is formed. At this time, the via hole 34 is filled with a conductive material, and the wiring layer 14 is connected to the metal pad 12.

Next, as shown in FIG. 10A, the step of forming the insulating layer 13 and the step of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method or the like are repeated. Then, a metal pad 29 is formed on the stacked body including the insulating layer 13 and the wiring layer 14. Thus, a multilayer wiring structure film 15 including the metal pads 12, the insulating layer 13, the wiring layer 14, and the metal pads 29 is formed.

Next, as shown in FIG. 10B, an etching resist 28 is formed on the back surface of the multilayer wiring structure film 15 and the surface of the metal base 11. The method of forming the etching resist 28 includes laminating the etching resist 28 by a spin coating method, a die coating method, a curtain coating method or a printing method if the etching resist 28 is in a liquid state, and a laminating method if the etching resist 28 is a dry film. After laminating the etching resist 28, a treatment such as drying is performed to harden the etching resist 28. If the etching resist 28 is photosensitive, a photolithography process is used. If the etching resist 28 is non-photosensitive, a laser processing method is used. Etching resist 2
8 is patterned. After that, using the etching resist 28 as a mask, the metal base 11 is etched until the multilayer wiring structure film 15 is exposed, thereby forming a concave portion 32.

Next, as shown in FIG. 10C, the etching resist 28 is removed, and the surface of the metal pad 12 and the surface of the metal pad 29 are cleaned to form a semiconductor package substrate 31a.

Next, as shown in FIG. 10D, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18, so that the space between the multilayer wiring structure film 15 and the semiconductor element 16 is formed. The underfill 17 is poured and cured. Next, the BGA solder balls 19 are mounted on the metal pads 29 to form a semiconductor device as shown in FIG.

This semiconductor device is the same as the semiconductor device according to the first embodiment of the device of the present invention. According to the above-described manufacturing method, this semiconductor device can be manufactured efficiently. Further, according to the manufacturing method according to the present embodiment, the multilayer wiring structure film 15 is stacked using the flat metal base 11 as a substrate, so that the flatness of the multilayer wiring structure film 15 can be improved. In particular, the flatness of the surface of the multilayer wiring structure film 15 connecting the semiconductor elements 16 can be improved.

Next, a second embodiment of the method of the present invention will be described. The method of the second embodiment is for manufacturing a semiconductor device (see FIG. 2) according to a second embodiment of the device of the present invention. The feature of the method of the present embodiment is that it has a step of providing a metal film 35 in addition to the method of the first embodiment. FIG.
(A) to (d), FIGS. 12 (a) to (c) and FIG.
7A to 7D are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between each step.

First, as shown in FIG. 11A, a metal base 11 which is a metal plate having a thickness of 0.1 to 1.5 mm is used.
A plating resist 27 is formed on the surface of the substrate. If the plating resist 27 is liquid, it can be formed by spin coating,
Laminated by a die coating method, a curtain coating method, a printing method, or the like, and if the plating resist 27 is a dry film, laminated by a laminating method or the like, and then subjected to processing such as drying and solidified,
If the plating resist 27 is photosensitive, it is patterned by a photolithography process or the like, and if it is non-photosensitive, it is patterned by a laser processing method or the like.

Next, as shown in FIG. 11B, at least one kind of metal selected from the group consisting of gold, tin and solder is formed in the opening of the plating resist 27 by electrolytic plating or electroless plating. Alternatively, the alloy is deposited to form a surface layer (not shown) of the first metal pad 12. next,
Nickel is deposited as a barrier metal (not shown),
Further, copper is deposited to form the first metal pad 12.
At this time, when an intermetallic compound is formed between the metal forming the metal base 11 and the metal forming the surface layer of the metal pad 12, a barrier such as nickel is formed before forming the surface layer of the metal pad 12. Deposit metal. This barrier metal is preferably a metal that can be removed by etching. When the surface of the metal pad 12 is recessed from the surface of the multilayer wiring structure film 15 in the subsequent step shown in FIG. 13A, first, an etchable metal such as nickel is deposited to a predetermined thickness. After letting metal pad 1
The metal constituting the surface layer portion 2 is deposited, nickel is deposited as a barrier metal, and copper is further deposited to form the metal pad 12.

Next, as shown in FIG. 11C, a plating resist 36 is formed. It is more suitable to form the plating resist 36 after removing the plating resist 27, but if possible, the plating resist 36 may be formed on the plating resist 27 and patterned together. If the plating resist 36 is in a liquid state, it is laminated by a spin coating method, a die coating method, a curtain coating method or a printing method, and if the plating resist 36 is a dry film, it is laminated by a laminating method or the like, and then dried. The plating resist 36 is solidified by patterning by a photolithography process or the like if the plating resist 36 is photosensitive, or by a laser processing method or the like if the plating resist 36 is non-photosensitive.

Next, as shown in FIG. 11D, a metal having etching resistance when etching the metal base 11 in the opening of the plating resist 36 by electrolytic plating, electroless plating or sputtering. That is, gold, platinum, silver, palladium, titanium, chromium, molybdenum, tantalum, nickel, and at least one metal selected from the group consisting of aluminum or an alloy thereof,
A surface layer (not shown) of the metal film 35 is formed. Next, in order to give the metal film 35 a thickness, a metal such as copper, nickel, gold, or palladium, which can be formed by an electrolytic plating method or an electroless plating method, is deposited to form the metal film 35. When electrical performance is added, a barrier metal (not shown) may be formed to suppress diffusion of the metal film 35. At this time, when an intermetallic compound is formed between the metal forming the metal base 11 and the metal forming the surface layer of the metal film 35, a barrier such as nickel is formed before forming the surface layer of the metal film 35. Deposit metal. This barrier metal is preferably a metal that can be removed by etching. In the case where the surface of the metal film 35 is depressed below the surface of the multilayer wiring structure film 15 in the subsequent step shown in FIG. 13A, first, an etchable metal such as nickel is deposited to a predetermined thickness. After that, the metal film 35 is formed. When the metal film 35 is projected from the multilayer wiring structure film 15 (not shown), a recess is formed in the metal base 11 by etching using the plating resist 36 as a mask, and then the metal film 35 is formed.

Next, as shown in FIG. 12A, after removing the plating resist 36, the surface is cleaned. next,
As shown in FIG. 12B, the insulating layer 13 is formed on the metal base 11. The method of forming the insulating layer 13 is as follows: if the insulating resin constituting the insulating layer 13 is in a liquid state, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. Then, after laminating the insulating resin by lamination method, etc.,
The insulating resin is hardened by performing processing such as drying. And
If the insulating resin is photosensitive, a photolithography process or the like, or if the insulating resin is non-photosensitive, a laser processing method or the like is used to pattern the insulating resin to form a via hole 34, cure the insulating resin, and perform insulation. The insulating layer 13 is formed by curing the resin.

Next, as shown in FIG. 12C, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method or the like, and a wiring layer 14 is formed. At this time, the via hole 34 is filled with a conductive material, and the wiring layer 14 is connected to the metal pad 12. In addition,
When the metal film 35 is used as a component of a circuit (not shown), the metal film 35 is used in a process shown in FIG.
Then, a via hole 34 is formed at a position where the wiring layer 14 is connected to the metal film 35 via the via hole 34 in a step shown in FIG.

Next, as shown in FIG. 13A, the step of forming the insulating layer 13 and the step of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method or the like are repeated. The multilayer wiring structure film 15 is formed.

Next, as shown in FIG. 13B, an etching resist 28 is formed on the back surface of the multilayer wiring structure film 15 and the surface of the metal base 11. The method of forming the etching resist 28 includes laminating the etching resist 28 by a spin coating method, a die coating method, a curtain coating method or a printing method if the etching resist 28 is in a liquid state, and a laminating method if the etching resist 28 is a dry film. After laminating the etching resist 28, a treatment such as drying is performed to harden the etching resist 28. If the etching resist 28 is photosensitive, a photolithography process is used. If the etching resist 28 is non-photosensitive, a laser processing method is used. Etching resist 2
8 is patterned. Thereafter, using the etching resist 28 as a mask, the metal base 11 is etched until the multilayer wiring structure film 15 and the metal film 35 are exposed, thereby forming the concave portions 32.

Next, as shown in FIG. 13C, the etching resist 28 is removed, the surfaces of the metal pads 12 and the metal pads 29 are cleaned, and a semiconductor package substrate 31b is formed.

Next, as shown in FIG. 13D, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18 so that the space between the multilayer wiring structure film 15 and the semiconductor element 16 is formed. The underfill 17 is poured and cured. Next, the BGA solder balls 19 are mounted on the metal pads 29 to form a semiconductor device as shown in FIG.

According to the method of the second embodiment, a semiconductor device having the metal film 35 shown in the second embodiment of the device of the present invention can be manufactured efficiently. In this semiconductor device, by arranging the metal film 35 in the opening of the metal base 11, the metal base 11
Of the multilayer wiring structure film 15
Can be prevented from being directly applied to. Thus, the occurrence of cracks in the multilayer wiring structure film 15 can be suppressed.

Next, a modification of this embodiment will be described. In this modification, the metal pad 12 and the metal film 35
Are simultaneously formed. 14A to 14E are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present modification in the order of steps. In this modification, after performing the steps shown in FIGS. 14A to 14E, FIGS. 13A to 13D
Are performed.

First, as shown in FIG. 14A, a metal base 11 which is a metal plate having a thickness of 0.1 to 1.5 mm is used.
A plating resist 27 is formed on the surface of the substrate. If the plating resist 27 is in a liquid state, it is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method or the like, and if the plating resist 27 is a dry film, it is laminated by a laminating method or the like, and then dried. The plating resist 27 is hardened by patterning, and is patterned by a photolithography process or the like if the plating resist 27 is photosensitive, or by a laser processing method or the like if the plating resist 27 is not photosensitive.

Next, as shown in FIG. 14B, at least one type of metal selected from the group consisting of gold, tin and solder is formed in the opening of the plating resist 27 by electrolytic plating or electroless plating. Alternatively, an alloy thereof is deposited to form a surface layer (not shown) of the first metal pad 12 and a surface layer (not shown) of the metal film 35. Next, nickel is deposited as a barrier metal (not shown), and copper is further deposited to form the first metal pad 12 and the metal film 35. At this time, when an intermetallic compound is formed between the metal constituting the metal base 11 and the metal forming the surface portion of the metal pad 12 and the metal film 35, the surface portion of the metal pad 12 and the metal film 35 is removed. Prior to formation, a barrier metal such as nickel is deposited. This barrier metal is preferably a metal that can be removed by etching. FIG.
When the surfaces of the metal pad 12 and the metal film 35 are depressed below the surface of the multilayer wiring structure film 15 in the subsequent step shown in FIG. 1A, an etchable metal such as nickel is first deposited to a predetermined thickness. After that, the metal constituting the surface layer of the metal pad 12 and the metal film 35 is deposited, nickel is deposited as a barrier metal, and copper is further deposited to form the metal pad 12 and the metal film 35.

Next, as shown in FIG. 14C, after the plating resist 27 is removed, the surface is cleaned. next,
As shown in FIG. 14D, the insulating layer 13 is formed. If the insulating resin forming the insulating layer 13 is in a liquid state, the insulating layer 13 is formed by laminating the insulating resin by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like,
If the insulating resin is a dry film, the insulating resin is laminated by a laminating method or the like, and then subjected to a treatment such as drying to harden the insulating resin. If the insulating resin is photosensitive, the insulating resin is patterned by a photolithography process or the like, or if the insulating resin is non-photosensitive, a laser processing method or the like is used to pattern the insulating resin to form a via hole 34 and cure. Then, the insulating resin is cured to form the insulating layer 13.

Next, as shown in FIG. 14E, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and the wiring layer 14 is formed. At this time, the via hole 34 is filled with a conductive material, and the wiring layer 14 is connected to the metal pad 12. In addition,
When the metal film 35 is used as an element constituting a circuit (not shown), a via hole 34 is formed at a position connected to the metal film 35 in the step shown in FIG. In the step shown in e), the wiring layer 14 is connected to the metal film 35 via the via hole 34.

Thereafter, the steps shown in FIGS. 13A to 13D are performed to manufacture the semiconductor device according to the second embodiment of the present invention. According to the present modification, since the metal pad 12 and the metal film 35 can be formed simultaneously, a semiconductor device can be manufactured more efficiently.

Next, a third embodiment of the method of the present invention will be described. The method of the third embodiment is for manufacturing a semiconductor device (see FIG. 3) according to a third embodiment of the present invention. The feature of the method of the present embodiment is that, in addition to the method of the first embodiment, a solder ball 20 is formed on the surface of the metal pad 12,
The point is that a step of projecting the solder balls 20 from the surface of the multilayer wiring structure film 15 is provided. FIGS. 15A to 15F and FIGS. 16A to 16D are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between each step.

First, as shown in FIG. 15A, a metal base 11 which is a metal plate having a thickness of 0.1 to 1.5 mm is used.
A plating resist 27 is formed on the surface of the substrate. The plating resist 27 is formed by, for example, laminating the plating resist 27 by a spin coating method, a die coating method, a curtain coating method or a printing method if the plating resist 27 is in a liquid state, or a laminating method if the plating resist 27 is a dry film. After the plating resist 27 is laminated, the plating resist 27 is solidified by performing a treatment such as drying. If the plating resist 27 is photosensitive, a photolithography process is used. If the plating resist 27 is non-photosensitive, a laser processing method is used. The plating resist 27 is patterned.

Next, as shown in FIG. 15B, half etching is performed on the metal base 11 using the plating resist 27 as a mask, and the solder balls 20 and the metal pads 1 are formed.
The recess 33 for forming the second 2 is formed.

Next, as shown in FIG. 15C, solder balls 20 are formed in the openings of the plating resist 27 by electrolytic plating or electroless plating, and nickel is deposited as a barrier metal (not shown). Then, copper is further deposited to form a metal pad 12. At this time, metal base 1
In the case where an intermetallic compound is formed between the metal constituting 1 and the solder ball 20, a barrier metal such as nickel is deposited before forming the solder ball 20. This barrier metal is preferably a metal that can be removed by etching.

Next, as shown in FIG. 15D, after removing the plating resist 27, the surfaces of the metal base 11 and the metal pads 12 are cleaned.

Next, as shown in FIG. 15E, an insulating layer 13 is formed. The method of forming the insulating layer 13 is as follows: if the insulating resin constituting the insulating layer 13 is in a liquid state, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. Then, after laminating the insulating resin by lamination method, etc.,
The insulating resin is hardened by performing processing such as drying. And
If the insulating resin is photosensitive, a photolithography process or the like, or if the insulating resin is non-photosensitive, a laser processing method or the like is used to pattern the insulating resin to form a via hole 34, cure the insulating resin, and perform insulation. The insulating layer 13 is formed by curing the resin. At this time, the curing temperature is lower than the melting point of the solder ball 20.

Next, as shown in FIG. 15F, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 14 is formed. At this time, the via hole 34 is filled with a conductive material, and the wiring layer 14 is connected to the metal pad 12.

Next, as shown in FIG. 16A, the step of forming the insulating layer 13 and the step of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method or the like are repeated. The multilayer wiring structure film 15 is formed.

Next, as shown in FIG. 16B, an etching resist 28 is formed on the back surface of the multilayer wiring structure film 15 and the surface of the metal base 11. The method of forming the etching resist 28 includes laminating the etching resist 28 by a spin coating method, a die coating method, a curtain coating method or a printing method if the etching resist 28 is in a liquid state, and a laminating method if the etching resist 28 is a dry film. After the etching resist 28 is laminated, a process such as drying is performed to harden the etching resist 28. If the etching resist 28 is photosensitive, a photolithography process is used. If the etching resist 28 is non-photosensitive, a laser processing method is used. Is patterned by etching. Thereafter, using the etching resist 28 as a mask, the metal base 11 is etched until the multilayer wiring structure film 15 is exposed, thereby forming a concave portion 32.

Next, as shown in FIG. 16C, the etching resist 28 is removed, the surfaces of the solder balls 20 and the surfaces of the metal pads 29 are cleaned, and a semiconductor package substrate 31c is formed.

Next, as shown in FIG. 16D, the semiconductor element 16 is applied to the metal pad 12 through the solder ball 20 or the solder ball 20 is used as a preliminary solder to form the solder ball 18 (see FIG. 13D). ), And the underfill 17 is poured into the space between the multilayer wiring structure film 15 and the semiconductor element 16 to be cured. Next, the BGA solder balls 19 are mounted on the metal pads 29 to form a semiconductor device as shown in FIG.

According to the method of the third embodiment, the semiconductor device having the solder balls 20 on the surfaces of the metal pads 12 shown in the third embodiment of the present invention can be manufactured efficiently. In this semiconductor device, when the semiconductor element 16 is flip-chip connected to the multilayer wiring structure film 15, the solder balls 20 function as solder or preliminary solder.
The pitch of the flip chip pads can be reduced. Further, the semiconductor element 16 does not need to include the solder ball 18. Further, the metal film 35 shown in the method of the second embodiment may be formed between the multilayer wiring structure film 15 and the metal base 11. In this case, the metal film 3 is formed by the steps shown in FIGS. 11 to 13 or FIGS.
5 can be formed.

Next, a fourth embodiment of the method of the present invention will be described. FIGS. 17A to 17F and FIGS. 18A to 18D are partial cross-sectional views showing a method of manufacturing a semiconductor device according to the fourth embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between each step. The method of the fourth embodiment is for manufacturing a semiconductor device according to the first embodiment of the present invention. The method of the fourth embodiment is characterized in that a concave portion for mounting a semiconductor is formed in the metal base 11 in advance as compared with the method of the first embodiment.

First, as shown in FIG. 17A, a metal base 11 which is a metal plate having a thickness of 0.1 to 1.5 mm is used.
A recess 32 for mounting a semiconductor element is formed on the surface of the substrate by etching or cutting with a drill or the like. Alternatively, the metal base 11 may be formed by laminating a smooth metal plate with a metal plate having a semiconductor element mounting portion opened.

Next, as shown in FIG. 17B, a plating resist 27 is formed on the back surface of the metal base 11. The method of forming the plating resist 27 is as follows.
If 7 is liquid, it is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the plating resist 27 is a dry film, the plating resist 27 is laminated by a lamination method or the like, and then subjected to a treatment such as drying. The plating resist 27 is hardened, and if the plating resist 27 is photosensitive, the plating resist 2 is formed by a photolithography process or the like.
If 7 is non-photosensitive, the plating resist 27 is patterned by a laser processing method or the like.

Next, as shown in FIG. 17C, at least one type of metal selected from the group consisting of gold, tin and solder is formed in the opening of the plating resist 27 by electrolytic plating or electroless plating. Alternatively, an alloy thereof is deposited to form a surface layer (not shown) of the metal pad 12. Next, a metal pad 12 is formed by depositing nickel as a barrier metal (not shown) and further depositing copper. At this time, when an intermetallic compound is formed between the metal forming the metal base 11 and the metal forming the surface layer of the metal pad 12, a barrier metal such as nickel is deposited before forming the metal pad 12. Let it. This barrier metal is preferably a metal that can be removed by etching. FIG.
When the surface of the metal pad 12 is depressed below the surface of the multilayer wiring structure film 15 (see FIG. 18C) in the subsequent step shown in FIG. Then, a metal forming the surface layer of the metal pad 12 is deposited, nickel is deposited as a barrier metal, and copper is further deposited to form the metal pad 12.

Next, as shown in FIG. 17D, after removing the plating resist 27, the surfaces of the metal base 11 and the metal pads 12 are cleaned.

Next, as shown in FIG. 17E, an insulating layer 13 is formed. The method of forming the insulating layer 13 is as follows: if the insulating resin constituting the insulating layer 13 is in a liquid state, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. Then, after laminating the insulating resin by lamination method, etc.,
The insulating resin is hardened by performing processing such as drying. And
If the insulating resin is photosensitive, a photolithography process or the like, or if the insulating resin is non-photosensitive, a laser processing method or the like is used to pattern the insulating resin to form a via hole 34, cure the insulating resin, and perform insulation. The insulating layer 13 is formed by curing the resin.

Next, as shown in FIG. 17F, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 14 is formed. At this time, the via hole 34 is filled with a conductive material, and the wiring layer 14 is connected to the metal pad 12.

Next, as shown in FIG. 18A, the step of forming the insulating layer 13 and the step of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method or the like are repeated. Then, after that, the metal pad 29 is formed on the stacked body including the insulating layer 13 and the wiring layer 14, and the multilayer wiring structure film 15 is formed.

Next, as shown in FIG. 18B, an etching resist 28 is formed on the back surface of the multilayer wiring structure film 15 and the surface of the metal base 11 and patterned. Thereafter, using the etching resist 28 as a mask, the metal base 11 is etched until the multilayer wiring structure film 15 is exposed. When the thickness of the metal base 11 in the semiconductor element mounting recess 32 is small to some extent, the etching can be performed without forming the etching resist 28 on the surface of the metal base 11.

Next, as shown in FIG. 18C, the etching resist 28 is removed, the surface of the metal pad 12 and the surface of the metal pad 29 are cleaned, and a semiconductor package substrate 31a is formed.

Next, as shown in FIG. 18D, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18 so that the space between the multilayer wiring structure film 15 and the semiconductor element 16 is formed. The underfill 17 is poured and cured. Next, the BGA solder balls 19 are mounted on the metal pads 29 to form a semiconductor device as shown in FIG.

This semiconductor device has the same configuration as the semiconductor device according to the first embodiment of the device of the present invention, that is, the semiconductor device manufactured by the method of the first embodiment. In the method of the fourth embodiment, a concave portion for mounting a semiconductor is formed in the metal base 11 in advance, so that the metal base 11 shown in FIG.
This has the advantage that the etching time can be shortened in the step of etching the semiconductor device, and the shape of the opening for mounting the semiconductor element becomes uniform. Note that FIG.
In the steps shown in (b) and (c), a metal film 35 (see FIG. 14B) may be formed. As a result, the semiconductor device (see FIG. 2) according to the second embodiment of the present invention can be manufactured efficiently.

Next, a fifth embodiment of the method of the present invention will be described. The manufacturing method of the fifth embodiment is a combination of the method of the third embodiment and the method of the fourth embodiment, and has both advantages. 19 (a) to 19 (f) and FIG.
(A) to (d) are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to the fifth embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between each step.

First, a recess 32 for mounting a semiconductor element is formed on the surface of a metal base 11 which is a metal plate having a thickness of 0.1 to 1.5 mm by the method shown in the method of the fourth embodiment. Next, as shown in FIG. 19A, a plating resist 27 is formed on the back surface of the metal base 11. The plating resist 27 is formed by laminating the plating resist 27 by a spin coating method, a die coating method, a curtain coating method or a printing method if the plating resist 27 is in a liquid state, and laminating the plating resist 27 if the plating resist 27 is a dry film. After laminating the plating resist 27 by a method or the like, the plating resist 27 is hardened by performing a treatment such as drying. If the plating resist 27 is photosensitive, a photolithography process or the like is used. If the plating resist 27 is non-photosensitive, The plating resist 27 is patterned by a laser processing method or the like.

Next, as shown in FIG. 19B, half etching is performed on the metal base 11 using the plating resist 27 as a mask to form the solder balls 20 and the metal pads 12.
Is formed. In the method of the fifth embodiment, the concave portion 33 for mounting the semiconductor element is formed on the metal base 11 and then the concave portion 33 is formed. However, the concave portion 33 is formed first and then the concave portion 32 is formed. May be formed simultaneously if possible.

Next, as shown in FIG. 19C, solder balls 20 are formed in the openings of the plating resist 27 by electrolytic plating or electroless plating, and nickel is deposited as a barrier metal (not shown). Then, copper is further deposited to form a metal pad 12. At this time, metal base 1
When an intermetallic compound is formed between the metal constituting the solder ball 1 and the solder ball 20, a barrier metal such as nickel is deposited first before the solder ball 20 is formed. This barrier metal is preferably a metal that can be removed by etching.

Next, as shown in FIG. 19D, after the plating resist 27 is removed, the surfaces of the metal base 11 and the metal pads 12 are cleaned.

Next, as shown in FIG. 19E, an insulating layer 13 is formed. The method of forming the insulating layer 13 is as follows: if the insulating resin constituting the insulating layer 13 is in a liquid state, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. Then, after laminating the insulating resin by lamination method, etc.,
The insulating resin is hardened by performing processing such as drying. And
If the insulating resin is photosensitive, a photolithography process or the like, or if the insulating resin is non-photosensitive, a laser processing method or the like is used to pattern the insulating resin to form a via hole 34, cure the insulating resin, and perform insulation. The insulating layer 13 is formed by curing the resin. At this time, the curing temperature is lower than the melting point of the solder ball 20.

Next, as shown in FIG. 19F, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and the wiring layer 14 is formed. At this time, the via hole 34 is filled with a conductive material, and the wiring layer 14 is connected to the metal pad 12.

Next, as shown in FIG. 20A, the step of forming the insulating layer 13 and the step of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method or the like are repeated. Form.
Thus, a multilayer wiring structure film 15 including the solder balls 20, the metal pads 12, the insulating layer 13, the wiring layer 14, and the metal pads 29 is formed.

Next, as shown in FIG. 20B, an etching resist 28 is formed and patterned on the back surface of the multilayer wiring structure film 15 and the surface of the metal base 11. Thereafter, using the etching resist 28 as a mask, the metal base 11 is etched until the multilayer wiring structure film 15 is exposed. When the thickness of the metal base 11 in the semiconductor element mounting recess 32 is small to some extent, the etching can be performed without forming the etching resist 28 on the surface of the metal base 11.

Next, as shown in FIG. 20C, the etching resist 28 is removed, and the surfaces of the solder balls 20 and the metal pads 29 are cleaned to form a semiconductor package substrate 31c.

Next, as shown in FIG. 20 (d), the semiconductor element 16 is applied to the metal pad 12 via the solder ball 20 or the solder ball 20 is used as a preliminary solder to form the solder ball 18 (see FIG. 18 (d)). ), And the underfill 17 is poured into the space between the multilayer wiring structure film 15 and the semiconductor element 16 to be cured. Next, the BGA solder balls 19 are mounted on the metal pads 29 to form a semiconductor device as shown in FIG.

This semiconductor device has the same structure as the semiconductor device according to the third embodiment of the present invention, that is, the semiconductor device manufactured by the method of the third embodiment (see FIG. 3). According to the manufacturing method according to the present embodiment, by forming the concave portion 32 for mounting the semiconductor in advance on the metal base 11, the time for etching the metal base 11 can be reduced, and the shape of the opening for mounting the semiconductor can be reduced. Can be made uniform. Also, since the solder balls 20 are provided on the surface of the metal pad 12, the semiconductor element 16 can be
5, when the flip-chip connection is made, the solder balls 20 function as solder or preliminary solder, so that the pitch of the flip-chip pads can be reduced. Further, the semiconductor element 16 does not need to include the solder ball 18.
In the steps shown in FIGS. 19A to 19C, the metal film 35 (FIG. 1) shown in the above-described second embodiment method is used.
4 (b)) can also be formed. This allows
The semiconductor device according to the third embodiment of the device of the present invention can be manufactured efficiently.

Next, a sixth embodiment of the method of the present invention will be described. The method according to the sixth embodiment corresponds to the semiconductor device according to the fourth embodiment of the present invention, that is, the metal pad 12 and the wiring layer 14.
For manufacturing a semiconductor device in which the thin film capacitor 21 is formed. FIGS. 21A and 21B are partial cross-sectional views showing a method of manufacturing a semiconductor device according to the sixth embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between each step.

First, according to the steps shown in FIGS. 9A to 9C, as shown in FIG.
2 is obtained. That is, FIG.
As shown in (a), a plating resist 27 is formed on the surface of a metal base 11 which is a metal plate having a thickness of 0.1 to 1.5 mm.
To form

Next, as shown in FIG. 9B, at least one kind of metal selected from the group consisting of gold, tin and solder is formed in the opening of the plating resist 27 by electrolytic plating or electroless plating. Alternatively, the metal pad 12 is formed by depositing an alloy thereof, depositing nickel as a barrier metal, and further depositing copper.

Next, as shown in FIG. 9C, after removing the plating resist 27, the surfaces of the metal base 11 and the metal pad 12 are cleaned to obtain a structure as shown in FIG. 21A.

At this time, instead of obtaining the metal base 11 having the metal pad 12 formed on the surface by the steps shown in FIGS. 9A to 9C, FIGS.
12 (a) or 14 (a) to 14 (c), the metal base 11 provided with the metal pad 12 and covered with the metal film 35 may be obtained. The metal base 11 including the metal pads 12 and the solder balls 20 may be obtained by the process shown in FIG.
The metal pad 1 is formed on the back surface by the steps shown in FIGS.
2, a metal base 11 having a surface on which a recess 32 for mounting a semiconductor is formed may be obtained. Further, the metal base 11 provided with the metal pad 12 and the solder ball 20 and having the recess 32 for mounting a semiconductor formed thereon may be obtained by the steps shown in FIGS. However, metal base 11
When the solder ball 20 includes the solder ball 20, the temperature at which the thin film capacitor 21 described later is formed must be lower than the melting point of the solder ball 20.

After obtaining the metal base 11 having the metal pads 12 formed on the surface as shown in FIG.
As shown in (b), only the surface of the desired metal pad 12 is exposed using a resist (not shown) as a mask, and a thin film capacitor 21 is formed by a sputtering method, a vapor deposition method, a CVD method, an anodic oxidation method, or the like. The material constituting the dielectric layer of the thin film capacitor 21 is titanium oxide, tantalum oxide,
Al ₂ O ₃ , SiO ₂ , Nb ₂ O ₅ , BST (Ba _x Sr _1-x
TiO ₃ ), PZT (PbZr _x Ti _1-x O ₃ ), PLZT
_{(Pb 1-y La y Zr} x Ti 1-x O 3) or SrBi ₂ Ta ₂
It is preferably a perovskite-based material such as O ₉ .
However, for any of the above compounds, 0 ≦ x ≦ 1, 0
<Y <1. Further, the thin film capacitor 21 may be made of an organic resin or the like that can realize a desired dielectric constant.

Next, unnecessary portions of the dielectric and the like are removed by a lift-off method for removing the resist. At this time, the thin film capacitor 21 may be formed at a desired position using a metal mask or the like.

The subsequent steps are the same as the steps shown in FIGS. 9D and 9E and FIGS. 10A to 10D. However,
9 (d) and 9 (e) and FIGS. 10 (a) to 10 (d), the thin film capacitor 21 is not shown. An insulating layer 13 is formed as shown in FIG. 9D, and a wiring pattern is formed and a wiring layer 14 is formed as shown in FIG. 9E.

Next, as shown in FIG. 10A, the insulating layer forming step and the wiring layer forming step are repeated to form a multilayer wiring structure film 15.

Next, as shown in FIG. 10B, an etching resist 28 is formed on the back surface of the multilayer wiring structure film 15 and the surface of the metal base 11. Thereafter, using the etching resist 28 as a mask, the metal base 11 is etched until the multilayer wiring structure film 15 is exposed.

Next, as shown in FIG. 10C, the etching resist 28 is removed, the surfaces of the metal pads 12 and the metal pads 29 are cleaned, and a semiconductor package substrate 31a is formed.

Next, as shown in FIG. 10D, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18 so that the space between the multilayer wiring structure film 15 and the semiconductor element 16 is formed. The underfill 17 is poured and cured. Next, the BGA solder balls 19 are mounted on the metal pads 29. Through the above steps, as shown in FIG. 4, a semiconductor device having the thin film capacitor 21 between the metal pad 12 and the insulating layer 13 can be manufactured.

Further, instead of using the metal base 11 having the metal pads 12 formed on the surfaces obtained by the steps shown in FIGS. 9A to 9C, FIGS. 11A to 11D and FIGS. 12 (a) or FIGS. 14 (a) to (c)
When the metal base 11 provided with the metal pad 12 obtained by the process shown in FIG. 1 and covered with the metal film 35 is used, after the thin film capacitor 21 is formed, FIG.
(C) and the steps shown in FIGS. 13 (a) to 13 (d), or the steps shown in FIGS. 14 (d), (e) and FIGS. 13 (a) to 13 (d). A semiconductor device (not shown) having both of them can be manufactured. Further, when using the metal base 11 having the metal pads 12 and the solder balls 20 obtained by the steps shown in FIGS.
1 (e), (f) and FIG.
A semiconductor device as shown in FIG. 5 can be manufactured by the steps shown in FIGS. Further, FIG.
In the case where the metal base 11 having the metal pads 12 on the surface obtained by the steps shown in (a) to (d) and having the recess 32 for mounting a semiconductor is used, after forming the thin film capacitor 21, 17 (e), (f) and FIG.
By the steps shown in FIGS. 4A to 4D, a semiconductor device as shown in FIG. 4 can be manufactured. Furthermore, FIG.
A concave portion 3 for mounting a semiconductor, comprising a metal pad 12 and a solder ball 20 obtained by the steps shown in FIGS.
In the case of using the metal base 11 on which the thin film capacitor 2 is formed, after forming the thin film capacitor 21, FIGS.
The semiconductor device shown in FIG. 5 can be manufactured by the steps shown in FIGS.

According to the manufacturing method of this embodiment, the thin film capacitor 21 is placed between one or more metal pads 12 and the wiring layer 14.
Is formed, and a semiconductor device having a decoupling capacitor very close to the semiconductor element 16 can be manufactured.

Next, a description will be given of a seventh embodiment of the method of the present invention. The method of the seventh embodiment is for manufacturing a semiconductor device according to the fifth embodiment of the present invention, that is, a semiconductor device in which a printed circuit board 24 is bonded as a carrier base material. FIGS. 22A to 22D and FIGS. 23A to 23C are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to the seventh embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between each step.

First, FIGS. 9A to 9E and FIG.
Through the process shown in FIG. 10A, a laminate (hereinafter, referred to as a laminate) in which the multilayer wiring structure film 15 is laminated on the metal base 11 as shown in FIG.

Further, at this time, instead of using a laminate in which the multilayer wiring structure film 15 is laminated on the metal base 11 as shown in FIG. 10A, FIG. 13A in the method of the second embodiment is used. A laminate in which the metal film 35 is provided may be used, or a laminate in which the solder balls 20 are provided in the laminate as shown in FIG. It is also possible to use a laminate in which a recess 32 for mounting a semiconductor element is provided in a laminate as shown in FIG. 18A in the method of the fourth embodiment. In the method of the fifth embodiment, the solder balls 20 and the recesses 3 for mounting the semiconductor elements are formed on the laminate as shown in FIG.
2 may be used, or a laminate in which the thin film capacitor 21 is provided in the laminate formed by the method of the sixth embodiment may be used.

Next, as shown in FIG. 22A, the surface of the multilayer wiring structure film 15 is cleaned, and as shown in FIG.
The adhesive 22 is applied to the area excluding the area 9. As a method of applying the adhesive 22 to a desired area, a printing method, a method of applying a mask to an area where the adhesive 22 is not applied such as a metal pad 29, applying the adhesive 22, and then removing the masking, etc. There is. When the adhesive 22 has photosensitivity, a method of patterning the adhesive 22 by a photolithography process may be used.

Next, as shown in FIG. 22C, a printed circuit board 24 as a carrier base material is placed in a through hole 30 of the printed circuit board 24 by a metal pad 2 of the multilayer wiring structure film 15.
9 are bonded to the back surface of the multilayer wiring structure film 15 so that the layers 9 are aligned. Although FIG. 22B shows an example in which the adhesive 22 is applied to the back surface of the multilayer wiring structure film 15, the adhesive 22 may be applied to the printed circuit board 24 for joining.

Next, as shown in FIG. 22D, the conductive paste 2 is placed in the through holes 30 of the printed circuit board 24.
3. Fill and heat to harden. Conductive paste 23
When there is a possibility that leakage and deformation may occur in the subsequent steps, it is preferable to further fill the through hole 30 with an insulating resin and to cure the resin.

Next, as shown in FIG. 23A, an etching resist 28 is formed on the surface of the printed circuit board 24, inside the through holes 30, and on the surface of the metal base 11. The method of forming the etching resist 28 includes laminating the etching resist 28 by a spin coating method, a die coating method, a curtain coating method or a printing method if the etching resist 28 is in a liquid state, and a laminating method if the etching resist 28 is a dry film. After laminating the etching resist 28, a treatment such as drying is performed to harden the etching resist 28. If the etching resist 28 is photosensitive, a photolithography process is used. If the etching resist 28 is non-photosensitive, a laser processing method is used. Is patterned by etching. Then, using the etching resist 28 as a mask, the metal base 1
1 is etched until the multilayer wiring structure film 15 is exposed. At this time, a recess 32 (see FIG. 18A) for mounting a semiconductor element is provided in the metal base 11 in advance.
When the thickness of the metal base 11 in the recess 32 is small to some extent, the etching can be performed without forming the etching resist 28 on the surface of the metal base 11.

Next, as shown in FIG. 23B, the etching resist 28 is removed, the surfaces of the metal pads 12 and the metal pads of the printed circuit board 24 are cleaned, and a semiconductor package substrate 31d is formed.

Next, as shown in FIG. 22C, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18. When a solder ball 20 (see FIG. 20A) is formed on the surface of the metal pad 12, the solder ball 20 is interposed or the solder ball 2 is formed.
0 is used as preliminary solder, and flip-chip connection is performed via the solder ball 18. After that, the underfill 17 is poured into the space between the multilayer wiring structure film 15 and the semiconductor element 16 and cured. Next, the BGA solder balls 19 are mounted on the metal pads of the printed circuit board 24.

As a modification of the seventh embodiment, as described in the sixth embodiment of the device of the present invention, the semiconductor device 16
After flip-chip connection to the metal pad 12, the connection pins 25 (see FIG. 7) may be attached to the through holes 30 of the printed board 24 a instead of attaching the BGA solder balls 19 to the metal pads of the printed board 24.

As described above, according to the manufacturing method of this embodiment, it is possible to efficiently manufacture a semiconductor device having a carrier base as shown in FIGS. 6C and 7.

Next, an eighth embodiment of the method of the present invention will be described. FIGS. 24A to 24C are partial cross-sectional views showing the method of the eighth embodiment in the order of steps. The method according to the eighth embodiment is for manufacturing a semiconductor device in which a carrier substrate is joined, and is different from the method according to the seventh embodiment in that the through-hole is filled with a conductive material or a connection material. It is characterized in that a carrier substrate having a separate pad is used. A printed circuit board, a ceramic substrate, or an organic-inorganic composite substrate is used as the carrier substrate. Note that cleaning and heat treatment are appropriately performed between each step.

First, similarly to the method of the seventh embodiment, FIG.
By the steps shown in FIGS. 10A to 10E and FIG.
A multilayer body in which the multilayer wiring structure film 15 is stacked on the metal base 11 is manufactured. At this time, similarly to the method of the seventh embodiment described above, instead of using the laminate shown in FIG. 9A, metal is added to the laminate shown in FIG. 13A in the method of the second embodiment. A film provided with the film 35 may be used, or a material provided with the solder balls 20 in the laminate shown in FIG. 16A in the method of the third embodiment may be used.
In the method of the fourth embodiment, a laminate having a recess 32 for mounting a semiconductor element may be used in the laminate shown in FIG. Further, the laminate shown in FIG. 20A in the method of the fifth embodiment in which the solder balls 20 and the concave portions 32 for mounting the semiconductor elements are provided may be used. The one provided with the thin film capacitor 21 can also be used.

Next, as shown in FIG. 24A, the surface of the multilayer wiring structure film 15 is cleaned, and as shown in FIG.
The adhesive 22 is applied to the area excluding the area 9. The method of applying the adhesive 22 to a desired area is the same as the method of the seventh embodiment.

Next, as shown in FIG. 24C, the ceramic substrate 26 is joined to the multilayer wiring structure film 15 so that the pads of the ceramic substrate 26 as the carrier base are connected to the conductive paste 23. In FIG. 24 (c),
Although an example in which the adhesive 22 and the conductive paste 23 are applied to the surface of the multilayer wiring structure film 15 is shown, the adhesive 22 and the conductive paste 23 are applied to the surface of the ceramic substrate 26 or the adhesive 22 and the conductive paste 23 are applied. The ceramic substrate 26 may be bonded to the multilayer wiring structure film 15 by separately applying the conductive paste 23 to either the surface of the multilayer wiring structure film 15 or the surface of the ceramic substrate 26.

The subsequent steps are the same as those shown in FIGS. That is, an etching resist 28 is formed on the surface of the ceramic substrate 26 and the surface of the metal base 11 and patterned. Thereafter, using the etching resist 28 as a mask, the metal base 11 is etched until the multilayer wiring structure film 15 is exposed. Next, the etching resist 28 is removed, and the surface of the metal pad 12 and the surface of the metal pad of the ceramic substrate 26 are cleaned to form a semiconductor package substrate.

Next, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18, and then the underfill 17 is poured into the space between the multilayer wiring structure film 15 and the semiconductor element 16 to be cured. . Next, the BGA solder balls 19 are mounted on the metal pads of the ceramic substrate 26.

As a modification of the eighth embodiment, after the semiconductor element 16 is flip-chip connected to the metal pad 12, the connection pins 25 are used instead of the BGA solder balls 19.
May be attached.

As described above, according to the manufacturing method of the eighth embodiment, as shown in FIG. 8, the carrier substrate in which the through holes are filled with the conductive material or the carrier substrate separately provided with the connection pads is provided. The semiconductor package substrate having the substrate mounted thereon can be manufactured efficiently.

Next, a ninth embodiment of the method of the present invention will be described. FIGS. 25A to 25C and FIGS. 26A and 26B are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to the ninth embodiment in the order of steps. The ninth embodiment is for manufacturing a semiconductor device according to a fifth embodiment of the present invention, that is, a semiconductor device having a carrier substrate bonded thereto (for example, see FIGS. 6A to 6C). It is. This embodiment is characterized in that an opening for fitting the semiconductor element 16 into the metal base 11 is provided before the metal base 11 is joined to the carrier base material. Note that cleaning and heat treatment are appropriately performed between each step.

FIGS. 25A to 25C and FIG. 26
(A) and (b) show an example in which a printed circuit board 24 is used as a carrier base, as in the method of the seventh embodiment. Further, FIGS. 25A to 25C and FIG. 26A
10B and 11B, a multilayer wiring structure film 15 is laminated on a metal base 11 as shown in FIG. 10C and an opening is provided in the metal base 11, and the subsequent steps are shown as examples. ing. In the ninth embodiment, FIG.
Instead of the one shown in (c), FIG. 13 (c), FIG.
(C), the one shown in FIG. 18 (c) or FIG. 20 (c) or the one provided with the thin film capacitor 21 formed by the method of the sixth embodiment can be used.

First, FIGS. 9A to 9E and FIG.
According to the steps shown in FIGS.
A multilayer wiring structure film 15 is laminated thereon, and a metal base 11 having openings provided therein is manufactured. That is, as shown in FIG. 9A, a plating resist 27 is formed on the surface of the metal base 11, which is a metal plate having a thickness of 0.1 to 1.5 mm, and is patterned.

Next, as shown in FIG. 9B, at least one type of metal selected from the group consisting of gold, tin and solder is formed in the opening of the plating resist 27 by electrolytic plating or electroless plating. Alternatively, the metal pad 12 is formed by depositing an alloy thereof, depositing nickel as a barrier metal, and further depositing copper.

Next, as shown in FIG. 9C, after the plating resist 27 is removed, the surface is cleaned.
9A, an insulating layer 13 is formed, and as shown in FIG. 9E, a wiring pattern is formed to form a wiring layer 14.

Next, as shown in FIG. 10A, the insulating layer forming step and the wiring layer forming step are repeated to form a multilayer wiring structure film 15, and a laminate as shown in FIG. obtain. Next, as shown in FIG. 10B, an etching resist 28 is formed on the back surface of the multilayer wiring structure film 15 and the surface of the metal base 11, and is patterned. Thereafter, using the etching resist 28 as a mask, the metal base 11 is etched until the multilayer wiring structure film 15 is exposed.

Next, as shown in FIG. 25A, the surface of the multilayer wiring structure film 15 is cleaned, and as shown in FIG.
The adhesive 22 is applied to the area excluding the area 9.

Next, as shown in FIG. 25 (c), a printed circuit board 24 as a carrier base material is placed in a through hole 30 of the printed circuit board 24 by a metal pad 2 of the multilayer wiring structure film 15.
9 are joined so that they match. FIG. 25B shows an example in which the adhesive 22 is applied to the surface of the multilayer wiring structure film 15. However, the bonding may be performed by applying the adhesive 22 to the printed circuit board 24.

Next, as shown in FIG. 26A, the conductive paste 2 is placed in the through holes 30 of the printed circuit board 24.
3. Fill and heat to harden. Conductive paste 23
When there is a possibility that leakage and deformation may occur in the subsequent steps, it is preferable to further fill the through hole 30 with an insulating resin and to cure the resin. By the above steps, FIG.
A semiconductor package substrate 31d as shown in FIG.

Next, as shown in FIG. 26B, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18. When the solder ball 20 is formed on the surface of the metal pad 12, the solder ball 2
0 or flip-chip connection through the solder ball 18 using the solder ball 20 as preliminary solder.
After that, the underfill 17 is poured into the space between the multilayer wiring structure film 15 and the semiconductor element 16 and cured. Next, the BGA solder balls 19 are mounted on the metal pads of the printed circuit board 24.

As a modification of the ninth embodiment,
As described in the sixth embodiment of the present invention, after the semiconductor element 16 is flip-chip connected to the metal pad 12, the BGA solder ball 19 is connected to the metal pad of the printed circuit board 24.
Instead of attaching the connection pins 25, the connection pins 25 may be attached to the through holes 30 of the printed circuit board 24a as shown in FIG.

As described above, according to the manufacturing method of the ninth embodiment, the opening for disposing the semiconductor element 16 in the metal base 11 can be provided before the carrier base is joined to the metal base 11. it can. Therefore, there is no need to perform an etching process on the metal base 11 after joining the carrier base material. Regarding the bonding between the multilayer wiring structure film 15 and the carrier base material, the bonding method is more seventh than the manufacturing method of the ninth embodiment.
Although the method of the eighth embodiment and the method of the eighth embodiment are more advantageous, when a carrier substrate which is easily damaged by the etching process is used, the manufacturing method of the ninth embodiment is more advantageous.

Next, a tenth embodiment of the method of the present invention will be described. 27A to 27C are partial cross-sectional views showing a method of manufacturing a semiconductor device according to the tenth embodiment in the order of steps. The manufacturing method according to the present embodiment is a method in which the manufacturing method according to the eighth embodiment method and the manufacturing method according to the ninth embodiment method are combined. That is, a manufacturing method for manufacturing a semiconductor package substrate bonded to a carrier base material,
As the carrier substrate, a carrier substrate in which through holes are filled with a conductive material or a carrier substrate separately provided with connection pads is used.
Before bonding to the semiconductor element 5, the semiconductor element 1 is connected to the metal base 11.
It is characterized in that an opening for disposing 6 is provided. A printed circuit board, a ceramic substrate, or an organic-inorganic composite substrate is used as the carrier substrate. Note that cleaning and heat treatment are appropriately performed between each step.

In FIGS. 27A to 27C, a ceramic substrate is used as an example. FIG.
FIGS. 10A to 10C show the method of the first embodiment shown in FIG.
The following process is shown as an example using a metal base 11 and a multilayer wiring structure film 15 shown in FIG. In the method of the tenth embodiment, the method shown in FIG. 13C, FIG.
8 (c) or FIG. 20 (c) or the one having the thin film capacitor 21 described in the method of the sixth embodiment can be used.

First, similarly to the method of the eighth embodiment, FIG.
By the steps shown in FIGS. 10A to 10E and FIGS. 10A and 10B, the multilayer wiring structure film 15 is formed on the metal base 11.
Are laminated.

Next, as shown in FIG. 27A, the etching resist 28 is removed, the surface of the multilayer wiring structure film 15 is cleaned, and as shown in FIG. The adhesive 22 is applied to a region other than the metal pad 29 on the back surface. After that, the conductive paste 23 is arranged on the opening of the region where the adhesive 22 is applied, that is, on the portion of the metal pad 29. Alternatively, the adhesive 22 may be applied after disposing the conductive paste 23 at a desired position first.

Next, as shown in FIG. 27C, the ceramic substrate 26 is joined to the multilayer wiring structure film 15 such that the metal pads of the ceramic substrate 26 as the carrier base material are connected to the conductive paste 23. . FIG. 27B shows an example in which the adhesive 22 and the conductive paste 23 are applied to the surface of the multilayer wiring structure film 15.
And the conductive paste 23 is applied to the surface of the ceramic substrate 26, or the adhesive 22 and the conductive paste 23 are separately applied to either the surface of the multilayer wiring structure film 15 or the surface of the ceramic substrate 26, respectively. The substrate 26 may be joined to the multilayer wiring structure film 15. Through the above steps, the semiconductor package substrate 3 as shown in FIG.
1e is formed.

The subsequent steps are the same as those shown in FIG. That is, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18, and then the underfill 17 is poured into the space between the multilayer wiring structure film 15 and the semiconductor element 16 to be cured. Next, the BGA solder balls 19 are mounted on the metal pads of the ceramic substrate 26.

As a modification of the method of the tenth embodiment, as described in the sixth embodiment of the device of the present invention (see FIGS. 6A to 6C), the semiconductor element 16 is
2, the connection pins 25 may be attached to the through holes 30 of the printed board 24a instead of attaching the BGA solder balls 19 to the metal pads of the printed board 24.

As described above, according to the manufacturing method of the tenth embodiment, the semiconductor package substrate to which the carrier substrate in which the through-hole is filled with the conductive material or the carrier substrate separately provided with the connection pad is attached. Can be manufactured efficiently. Further, before the carrier base is bonded to the multilayer wiring structure film 15, an opening for fitting the semiconductor element 16 in the metal base 11 is provided, so that the metal base 11 can be etched after bonding the carrier base. This eliminates the need to use a carrier substrate that can be easily damaged by the etching process.

Next, an eleventh embodiment of the method of the present invention will be described. 28 (a) to (e) and FIG. 29 (a)
And (b) are partial cross-sectional views showing a method of manufacturing a semiconductor device according to the eleventh example in the order of steps. Note that FIG.
Steps after 9 (b) are the same as the steps shown in FIGS. 10 (a) to 10 (d). In the manufacturing method of the present embodiment, the second surface of the metal base is formed by forming the multilayer wiring structure film 15 including the metal pads 12 on both surfaces of the metal base and dividing the metal base in half in the thickness direction. It is a method of forming. That is, by simultaneously forming the multilayer wiring structure film 15 on both surfaces of the metal base, the production rate of the semiconductor device can be doubled. Note that FIG.
8 (a) to 8 (e) and FIG. 28 (a) show the same steps as in the first embodiment method, but in this embodiment method, FIGS. 11 (a) to 11 (a) of the second embodiment method. d) and FIG.
2 (a) to (c) or the steps shown in FIGS. 14 (a) to 14 (e), and further the steps shown in FIGS. 13 (a) to 13 (d) to manufacture a semiconductor device. Alternatively, the semiconductor device may be manufactured by performing the steps shown in FIGS. 15A to 15F of the method of the third embodiment and further performing the steps shown in FIGS. 16A to 16D. Further, the one provided with the thin film capacitor 21 of the method of the sixth embodiment can be used. Note that cleaning and heat treatment are appropriately performed between each step.

First, as shown in FIG. 28A, a metal base 11 which is a metal plate having a thickness of 0.1 to 1.5 mm is used.
A plating resist 27 is formed on both surfaces of a. FIG.
The thickness of each metal base 11 after cutting shown in FIG.
When the thickness is 1 to 1.5 mm, the thickness of the metal base 11a shown in FIG. 28A is at least twice the thickness of the metal base 11, that is, 0.2 to 3.0 mm.
The plating resist 27 is formed by, if the plating resist 27 is in a liquid state, laminating it by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like.
If 7 is a dry film, it is laminated by a laminating method or the like, and then subjected to a treatment such as drying to be hardened.
Is photosensitive, such as by a photolithographic process,
If non-photosensitive, patterning is performed by a laser processing method or the like.

Next, as shown in FIG. 28B, at least one kind of metal selected from the group consisting of gold, tin and solder is formed in the opening of the plating resist 27 by electrolytic plating or electroless plating. Alternatively, the alloy is deposited to form a surface layer (not shown) of the first metal pad 12. next,
Nickel is deposited as a barrier metal (not shown), and copper is further deposited to form a first metal pad 12. At this time, when an intermetallic compound is formed between the metal forming the metal base 11 and the metal forming the surface layer of the metal pad 12, a barrier such as nickel is formed before forming the surface layer of the metal pad 12. Deposit metal. This barrier metal is preferably a metal that can be removed by etching. When the surface of the metal pad 12 is recessed from the surface of the multilayer wiring structure film 15 in the step shown in FIG. 29A described later, an etchable metal such as nickel is first deposited to a predetermined thickness. After that, the metal constituting the surface layer of the metal pad 12 is deposited, nickel is deposited as a barrier metal, and copper is further deposited to form the metal pad 12.

Next, as shown in FIG. 28C, after the plating resist 27 is removed, the surface is cleaned. next,
As shown in FIG. 28D, the insulating layers 13 are formed on both surfaces of the metal base 11a. The method of forming the insulating layer 13 is as follows: if the insulating resin constituting the insulating layer 13 is in a liquid state, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. Then, after laminating the insulating resin by a laminating method or the like, the insulating resin is hardened by performing a treatment such as drying. If the insulating resin is photosensitive, the insulating resin is patterned by a photolithography process or the like, or if the insulating resin is non-photosensitive, the insulating resin is patterned by a laser processing method or the like to form a via hole 34 and curing is performed. To cure the insulating resin to form the insulating resin 13.

Next, as shown in FIG. 28E, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and the wiring layer 14 is formed. At this time, the via hole 34 is filled with a conductive material, and the wiring layer 14 is connected to the metal pad 12.

Next, as shown in FIG. 29A, the step of forming the insulating layer 13 and the step of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method or the like are repeated. Form. Thereby, a multilayer wiring structure film 15 including the metal pads 12, the insulating layer 13, the wiring layer 14, and the metal pads 29 is formed.

Next, as shown in FIG. 29 (b), the metal base 11a is cut along a plane parallel to its surface by a slicer or a water cutter, and divided. That is,
The metal base 11a is divided into two in the thickness direction. As a result, the metal base 11a is divided into two metal bases 11 each having the multilayer wiring structure film 15 formed on one surface.

The subsequent steps are the same as the steps shown in FIGS. 10B to 10D. That is, an etching resist 28 is formed on the back surface of the multilayer wiring structure film 15 and the surface of the metal base 11, and etching is performed until the multilayer wiring structure film 15 is exposed to form the concave portion 32. Etching resist 2
8 is removed and the surface of the metal pad 12 and the metal pad 29 are removed.
Is cleaned to form a semiconductor package substrate 31a.

Next, as shown in FIG. 10D, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18, and the space between the multilayer wiring structure film 15 and the semiconductor element 16 is formed. The underfill 17 is poured and cured.

Next, the BGA solder balls 19 are mounted on the metal pads 29 to form a semiconductor device as shown in FIG.

A semiconductor device having a carrier substrate bonded thereto can be manufactured by performing the steps of the method of the seventh embodiment or the method of the eighth embodiment. At this time, the metal base 11a
May be divided and then the carrier base may be joined. However, after the carrier base is joined to the multilayer wiring structure film 15 formed on both sides of the metal base 11a, the metal base 11
May be divided.

As described above, according to the manufacturing method of this embodiment,
The manufacturing cost of the semiconductor device can be kept low.

Next, a twelfth embodiment of the method of the present invention will be described. 30 (a) to 30 (f) and FIG. 31 (a)
And (b) are partial cross-sectional views showing a method of manufacturing a semiconductor device according to the twelfth embodiment in the order of steps. FIG.
Steps after (b) are the same as the steps shown in FIGS. 10 (a) to 10 (d). In the manufacturing method of this embodiment, after two metal bases 11 are bonded, a multilayer wiring structure film 15 is formed on both surfaces of the bonded metal base (hereinafter, referred to as a metal base 11b), and then the metal base 11b is again mounted. By dividing into two metal bases 11, 2
This is a method for forming the second surface of the metal base 11. That is, by simultaneously forming the multilayer wiring structure film 15 on both surfaces of the metal base 11b, the production rate of the semiconductor device can be doubled. The steps shown in FIGS. 30A to 30F and FIG. 31A are the same as those in the method of the first embodiment, but the second method is used instead of the method of the first embodiment.
11 (a) to 11 (d) and 12 (a) of the method of the embodiment.
To (c) or (a) to (e) of FIG. 14 and then to the steps of (a) to (d) of FIG. 13 to manufacture a semiconductor device. The steps shown in FIGS. 15A to 15F of the example method are performed, and
A semiconductor device may be manufactured by performing the steps shown in (a) to (d). FIG. 17 of the method of the fourth embodiment.
After the metal base 11 shown in FIG.
7 (b) to 7 (f) are performed, and
A semiconductor device may be manufactured by performing the steps shown in (a) to (d). After bonding two metal bases 11 shown in FIG. FIGS. 19B to 19F with respect to the base.
20 (a) to 20 (d).
The semiconductor device may be manufactured by performing the steps shown in FIG. Further, the one provided with the thin film capacitor 21 of the method of the sixth embodiment can be used. Note that cleaning and heat treatment are appropriately performed between each step.

First, as shown in FIG. 30A, a metal base 11 which is a metal plate having a thickness of 0.1 to 1.5 mm is used.
Are bonded together to form a metal base 11b. At this time, the metal base 11 is placed between the metal bases 11.
A metal plate that can be eluted and removed by an etchant that does not elute may be interposed. Further, the metal base 11 on which the concave portion 32 is formed can be bonded. The bonding is performed by forming fine irregularities on the surface to be bonded of the metal base 11 so that the metal base 11 is engaged with each other, bonding the entire surface or only the end of the metal base 11 using an adhesive, or welding. This is performed by bonding the entire surface or only the end of the metal base 11. However, FIG.
In consideration of dividing the metal base 11b into two metal bases 11 again in the step shown in FIG. 1 (b), it is preferable that the bonding is performed by bonding or joining only the ends of the metal base 11.

Next, as shown in FIG. 30B, a plating resist 2 is formed on both surfaces of the metal base 11b which has been bonded.
7 is formed. If the plating resist 27 is in a liquid state, it is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method or the like, and if the plating resist 27 is a dry film, it is laminated by a laminating method or the like, and then dried. The plating resist 27 is hardened by patterning, and is patterned by a photolithography process or the like if the plating resist 27 is photosensitive, or by a laser processing method or the like if the plating resist 27 is non-photosensitive.

Next, as shown in FIG. 30C, at least one kind of metal selected from the group consisting of gold, tin and solder is formed in the opening of the plating resist 27 by electrolytic plating or electroless plating. Alternatively, the alloy is deposited to form a surface layer (not shown) of the first metal pad 12. next,
Nickel is deposited as a barrier metal (not shown), and copper is further deposited to form a first metal pad 12. At this time, when an intermetallic compound is formed between the metal forming the metal base 11 and the metal forming the surface layer of the metal pad 12, a barrier such as nickel is formed before forming the surface layer of the metal pad 12. Deposit metal. This barrier metal is preferably a metal that can be removed by etching. When the surface of the metal pad 12 is depressed below the surface of the multilayer wiring structure film 15 in the subsequent step shown in FIG. 31A, first, an etchable metal such as nickel is deposited to a predetermined thickness. Let the metal pad 12
The metal constituting the surface layer of the metal pad 1 is deposited, nickel is deposited as a barrier metal, and copper is further deposited.
Form 2

Next, as shown in FIG. 30D, after the plating resist 27 is removed, the surface is purified.

Next, as shown in FIG. 30E, an insulating layer 13 is formed. The method of forming the insulating layer 13 is as follows: if the insulating resin constituting the insulating layer 13 is in a liquid state, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. Then, after laminating the insulating resin by lamination method, etc.,
The insulating resin is hardened by a treatment such as drying. If the insulating resin is photosensitive, the insulating resin is patterned by a photolithography process or the like, or if the insulating resin is non-photosensitive, a laser processing method or the like is used to pattern the insulating resin to form a via hole 34 and cure. To cure the insulating resin to form the insulating resin 13.

Next, as shown in FIG. 30F, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method or the like, and the wiring layer 14 is formed. At this time, the via hole 34 is filled with a conductive material, and the wiring layer 14 is connected to the metal pad 12.

Next, as shown in FIG. 31A, the process of forming the insulating layer 13 and the process of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method or the like are repeated. Is formed to form the multilayer wiring structure film 15.

Next, as shown in FIG. 31B, the metal base 11b is divided into two metal bases 11. When the entire surface of the metal base 11 is bonded, the bonded surface of the metal base 11b is cut and divided by a slicer or a water cutter. In the case where only the end of the metal base 11 is adhered, the divided end is cut and removed. Note that FIG.
In the step shown in (a), when a metal plate that elutes in an etchant in which the metal base 11 does not elute is sandwiched between the metal bases 11, the metal plate is removed by etching with the etchant. The base 11b is divided into two metal bases 11. At this time, a resist may be formed on the surface of the multilayer wiring structure film 15 in order to protect the multilayer wiring structure film 15 from an etchant.

The subsequent steps are the same as the steps shown in FIGS. That is, an etching resist 28 is formed on the back surface of the multilayer wiring structure film 15 and the surface of the metal base 11, and etching is performed until the multilayer wiring structure film 15 is exposed to form the concave portion 32. Etching resist 2
8 is removed and the surface of the metal pad 12 and the metal pad 29 are removed.
Is cleaned to form a semiconductor package substrate 31a.

Next, as shown in FIG. 10D, the semiconductor element 16 is flip-chip connected to the metal pad 12 via the solder ball 18 so that a space between the multilayer wiring structure film 15 and the semiconductor element 16 is formed. The underfill 17 is poured and cured. Next, the BGA solder balls 19 are mounted on the metal pads 29 to form a semiconductor device as shown in FIG.

Further, the semiconductor device to which the carrier base material is bonded can be manufactured by performing the steps of the method of the seventh embodiment or the method of the eighth embodiment. At this time, the metal base 11b
May be divided and then the carrier base may be joined. However, after the carrier base is joined to the multilayer wiring structure film 15 formed on both sides of the metal base 11b, the metal base 11
b may be divided.

As described above, according to the manufacturing method of this embodiment,
The manufacturing cost of the semiconductor device can be kept low.

[0203]

As described in detail above, the semiconductor package substrate of the present invention has a multi-layer wiring structure film having a first metal pad for mounting a semiconductor element on a smooth metal base. The flatness of the element mounting portion is excellent, and the reliability of mounting the semiconductor element on the semiconductor package substrate can be improved. Also, by leaving the metal base in a portion other than the semiconductor element mounting portion, the warpage and dimensional change of the multilayer wiring structure film can be minimized,
It becomes easy to increase the number of pins, increase the density, and reduce the size of the multilayer wiring structure film. Further, since the amount of deformation of the metal base is smaller than the amount of deformation of the printed circuit board and the ceramic substrate, it is easy to increase the density of the multilayer wiring structure film.

Further, in the semiconductor device of the present invention, the metal base can be used as a stiffener by arranging the surface of the semiconductor element after mounting the semiconductor element and the surface of the metal base on the same plane. Thus, the step of mounting the stiffener on the substrate can be eliminated, so that the manufacturing cost of the semiconductor device can be reduced. Furthermore,
Since the metal film is formed on the edge of the opening in the surface of the metal base on the side of the multilayer wiring structure film, it is possible to prevent stress from being directly applied to the multilayer wiring structure film from the metal base, and Since the occurrence of cracks can be suppressed, the reliability of the semiconductor device is improved.

Further, by arranging solder balls on the surface of the metal pad for mounting the semiconductor element, it can be used as solder for connecting the semiconductor element or as spare solder, so that the pitch of the flip chip pads can be reduced.

Further, since a thin film capacitor can be formed after forming a metal pad for mounting a semiconductor element on a metal base, a decoupling capacitor can be provided near a chip pad.

Further, in the case of a semiconductor package substrate to which the carrier base material is not connected, the wiring length can be minimized, and the structure is effective for speeding up signals. On the other hand, by connecting the carrier base material, the ground function can be easily enhanced, and passive components such as a resistor and a capacitor can be added. Further, the stress generated at the time of mounting on the motherboard can be reduced by the carrier base material, and the reliability at the time of secondary mounting can be improved.

Furthermore, by simultaneously forming a multilayer wiring structure film on both surfaces of the metal base and dividing the metal base into two, it is possible to improve the production amount of the semiconductor package substrate, and to reduce the production of the semiconductor device. Cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a view showing a first embodiment of a semiconductor device according to the present invention, wherein FIG. 1 (a) is a perspective view seen from the front side, and FIG.
3 is a perspective view as viewed from the back side, and FIG. 3C is a partial cross-sectional view.

FIG. 2 is a partial sectional view showing a second embodiment of the semiconductor device according to the present invention.

FIG. 3 is a partial sectional view showing a third embodiment of the semiconductor device according to the present invention.

FIG. 4 is a partial sectional view showing a fourth embodiment of the semiconductor device according to the present invention.

FIG. 5 is a partial sectional view showing a fourth embodiment of the semiconductor device according to the present invention.

FIG. 6 is a view showing a fifth embodiment of the semiconductor device according to the present invention, wherein FIG. 5 (a) is a perspective view seen from the front side, and FIG.
3 is a perspective view as viewed from the back side, and FIG. 3C is a partial cross-sectional view.

FIG. 7 is a partial sectional view showing a sixth embodiment of the semiconductor device according to the present invention.

FIG. 8 is a partial sectional view showing a seventh embodiment of the semiconductor device according to the present invention.

FIGS. 9A to 9E are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIGS. 10A to 10D are partial cross-sectional views showing steps subsequent to FIG. 9 in the method of the first embodiment in the order of steps.

FIGS. 11A to 11D are partial sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIGS. 12A to 12C are partial cross-sectional views showing steps subsequent to FIG. 11 in the method of the second embodiment in the order of steps.

FIGS. 13A to 13D are partial cross-sectional views showing steps subsequent to FIG. 12 in the method of the second embodiment in the order of steps.

FIGS. 14A to 14E are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to a modification of the second embodiment in the order of steps; FIGS.

FIGS. 15A to 15F are partial sectional views showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIGS. 16A to 16D are partial cross-sectional views showing steps subsequent to FIG. 15 in the method of the third embodiment in the order of steps.

17A to 17F are partial cross-sectional views showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention in the order of steps.

FIGS. 18A to 18D are partial cross-sectional views showing steps subsequent to FIG. 17 in the method of the fourth embodiment in the order of steps.

FIGS. 19A to 19F are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention in the order of steps. FIGS.

FIGS. 20A to 20D are partial cross-sectional views showing steps subsequent to FIG. 19 in the method of the fifth embodiment in the order of steps.

FIGS. 21A and 21B are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention in the order of steps.

FIGS. 22A to 22D are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention in the order of steps.

FIGS. 23 (a) to 23 (c) are partial cross-sectional views showing steps subsequent to FIG. 22 in the method of the seventh embodiment in the order of steps.

FIGS. 24A to 24C are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention in the order of steps.

FIGS. 25A to 25C are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention in the order of steps.

26A and 26B are partial cross-sectional views showing the next step of FIG. 25 in the ninth embodiment in the order of steps.

FIGS. 27A to 27C are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to a tenth embodiment of the present invention in the order of steps.

FIGS. 28A to 28E are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention in the order of steps.

FIGS. 29A and 29B are partial cross-sectional views showing the next step of FIG. 28 in the method of the eleventh embodiment in the order of steps.

FIGS. 30A to 30F are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention in the order of steps.

FIGS. 31A and 31B are partial cross-sectional views showing the next step of FIG. 30 in the twelfth embodiment in the order of steps.

[Explanation of symbols]

 11, 11a, 11b; metal base 12, metal pad 13, insulating layer 14, wiring layer 15, multilayer wiring structure film 16, semiconductor element 17, underfill 18, solder ball 19, BGA solder ball 20, solder ball 21; Printed circuit board 25; Connection pin 26; Ceramic substrate 27; Resist 28; Resist 29; Metal pad 30; Through holes 31a-31e; Semiconductor package substrate 32; Recess 34; via hole 35; metal film 36; resist

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuhiro Baba 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Koji Matsui 5-7-1 Shiba, Minato-ku, Tokyo Japan F-term in the Electric Company (reference) 5E346 AA02 AA12 AA15 AA32 AA43 AA51 BB20 CC01 CC08 CC09 CC10 CC12 CC13 DD02 FF45 HH11 HH26 HH31

Claims (41)

[Claims] 1. A semiconductor device comprising: a metal base made of a metal plate and having an opening for fitting a semiconductor element; and a multilayer wiring structure film laminated on the metal base, wherein the semiconductor element is provided within the opening. The multilayer wiring structure film is mounted on a multilayer wiring structure film, wherein the multilayer wiring structure film has a first metal pad formed in a region within the opening on a first surface in contact with the metal base and connected to the semiconductor element. Semiconductor package substrate. 2. The multilayer wiring structure film according to claim 1, wherein the multilayer wiring structure film includes a plurality of wiring layers and insulating layers alternately stacked, a via provided in the insulating layer and connecting the wiring layers, and a via on a side opposite to the first surface. A second metal pad formed on a second surface, wherein the second metal pad is connected to the first metal pad via the wiring layer and the via. The semiconductor package substrate according to claim 1. 3. The semiconductor package substrate according to claim 1, wherein a metal film is formed at an edge of the opening on a surface of the metal base on the side of the multilayer wiring structure film. 4. The semiconductor package substrate according to claim 1, further comprising a thin film capacitor between at least one of the first metal pads and the wiring layer. 5. The metal base is made of stainless steel, iron,
The semiconductor package substrate according to any one of claims 1 to 4, wherein the substrate is made of at least one metal selected from the group consisting of nickel, copper, and aluminum or an alloy thereof. 6. A surface layer portion of the first metal pad,
At least one selected from the group consisting of gold, tin and solder
The semiconductor package substrate according to claim 1, wherein the semiconductor package substrate is covered with a kind of metal or an alloy thereof. 7. The insulating layer is made of epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB
(Benzocyclobutene) and PBO (p
The semiconductor package substrate according to any one of claims 2 to 6, wherein a layer made of one or more kinds of organic resins selected from the group consisting of polybenzoxazole is laminated. 8. The semiconductor device according to claim 2, further comprising a carrier substrate disposed on the second surface of the multilayer wiring structure film and connected to the second metal pad. 13. The semiconductor package substrate according to item 9. 9. The semiconductor package substrate according to claim 8, wherein the carrier base is connected to the second metal pad via a conductive paste or an anisotropic conductive film. 10. The semiconductor package substrate according to claim 8, wherein the carrier substrate is any one of a printed circuit board, a ceramic substrate, and an organic-inorganic composite substrate having at least one wiring layer. . 11. The semiconductor package substrate according to claim 8, wherein the carrier substrate has a resistance. 12. The semiconductor package substrate according to claim 8, wherein the carrier base has a capacitor. 13. The semiconductor package substrate according to claim 8, wherein the carrier base has a ground function. 14. A solder ball or a connection pin is disposed on a surface of the carrier substrate on which the multilayer wiring structure film is not disposed, and the solder ball or the connection pin is connected to the second via the carrier substrate. The semiconductor package substrate according to claim 8, wherein the semiconductor package substrate is connected to the metal pad. 15. The semiconductor package according to claim 1, wherein the semiconductor package is inserted into the opening of the metal base of the semiconductor package substrate and connected to the first metal pad. And a semiconductor device comprising: 16. The semiconductor device according to claim 15, wherein the semiconductor element is flip-chip connected to the first metal pad by using any one of a low melting point metal and a conductive resin. 17. The semiconductor device according to claim 1, wherein the semiconductor element is connected to the multilayer wiring structure film by at least one material selected from the group consisting of a low melting point metal, an organic resin, and a metal-containing resin. 17. The semiconductor device according to 15 or 16. 18. A step of forming a plurality of first metal pads on a first surface of a metal base made of a metal plate, and comprising an insulating layer and a wiring layer on the first surface of the metal base. Forming a multilayer wiring structure film having a plurality of second metal pads on the surface, the second metal pads being respectively connected to the first metal pad via the wiring layer; Forming an opening for fitting a semiconductor element in a metal base so as to include a region where the first metal pad is formed, and exposing the first metal pad. A method for manufacturing a semiconductor package substrate. 19. A step of forming a plurality of first metal pads on a first surface of a metal base made of a metal plate; a step of forming a metal film on a first surface of the metal base; On the first surface of the base, there are provided a plurality of second metal pads on the surface comprising an insulating layer and a wiring layer, and the second metal pads are respectively connected to the first metal pad via the wiring layer.
Forming a multilayer wiring structure film so as to be connected to the metal pad, and forming a semiconductor on the metal base so as to include a region where the first metal pad is formed, the edge of which is in contact with the metal film. Forming an opening for fitting an element and exposing a part of the first metal pad and the metal film. 20. The method according to claim 19, wherein the first metal pad and the metal film are formed at the same time. 21. A method of forming a recess in a region of the second surface of the metal base where the opening is to be formed before the step of forming the first metal pad. The method for manufacturing a semiconductor package substrate according to claim 18. 22. A step of forming a plurality of first metal pads on first and second surfaces of a metal base made of a metal plate, respectively; A multilayer wiring structure film comprising an insulating layer and a wiring layer, having a plurality of second metal pads on the surface, wherein the second metal pads are respectively connected to the first metal pad via the wiring layer; Forming the metal base, dividing the metal base into two pieces along a plane parallel to a first plane, and forming an area in each of the divided metal bases where the first metal pad is formed. Forming an opening for inserting a semiconductor element so as to include the semiconductor element and exposing the first metal pad. 23. A step of bonding two metal bases made of a metal plate to each other and a step of forming a plurality of first metal pads on the first and second surfaces of the bonded metal base, respectively. And a plurality of second metal pads on the first and second surfaces of the bonded metal base, the second metal pads each comprising an insulating layer and a wiring layer, wherein the second metal pads are respectively provided with the wirings. A step of forming a multilayer wiring structure film so as to be connected to the first metal pad via a layer; a step of dividing the bonded metal base into two metal bases again; Forming an opening for inserting a semiconductor element so as to include a region where the first metal pad is formed in the metal base, and exposing the first metal pad. A method for manufacturing a semiconductor package substrate. 24. The step of forming the first metal pad includes forming a first resist having an opening in a region where the first metal pad is to be formed on a first surface of the metal base. 19. The method according to claim 18, further comprising: forming a first metal pad by plating a metal using the first resist as a mask; and removing the first resist. To 23
The method for manufacturing a semiconductor package substrate according to any one of the above items. 25. The method according to claim 25, wherein the step of forming the first resist and the step of forming the first metal pad by plating a metal using the first resist as a mask are performed. 25. The semiconductor package according to claim 24, further comprising: forming a concave portion in a region where the first metal pad is to be formed on the surface of the metal base by etching the metal base using a mask as a mask. Substrate manufacturing method. 26. The method according to claim 26, wherein the step of forming the first resist and the step of forming the first metal pad by plating a metal using the first resist as a mask are performed. 26. The method of manufacturing a semiconductor package substrate according to claim 24, further comprising a step of forming a solder ball by plating solder with the mask as a mask. 27. The step of forming the metal film, comprising: forming a second resist having an opening in a region where the metal film is to be formed on the first surface of the metal base; Forming the metal film by plating a metal using the resist as a mask;
27. The method of manufacturing a semiconductor package substrate according to claim 19, further comprising: removing the resist. 28. A method according to claim 28, further comprising the step of forming at least one first metal pad between the step of forming the first metal pad and the step of forming a multilayer wiring structure film on the first metal pad. The method for manufacturing a semiconductor package substrate according to any one of claims 18 to 27, further comprising a step of forming a thin film capacitor. 29. The step of forming a multilayer wiring structure film on the first surface of the metal base includes forming an insulating layer made of an insulating resin, and forming a multilayer wiring structure film on the first metal pad in the insulating layer. A step of forming a via at a position matching the wiring, a step of forming a wiring layer composed of a wiring disposed at a position matching the via, and an insulating resin filled between the wiring, 29. The method of manufacturing a semiconductor package substrate according to claim 18, further comprising: forming the second metal pad so as to be exposed on a surface of the structural film. 30. A step of forming an opening for accommodating a semiconductor element so as to include a region where the first metal pad is formed in the metal base and exposing the first metal pad, Forming a third resist having an opening in a region where the opening is to be formed on the second surface of the metal base, and etching the metal base using the third resist as a mask; 30. The semiconductor package substrate according to claim 18, further comprising: forming a first metal pad to expose the first metal pad; and removing the third resist. Production method. 31. The second wiring structure film having a second surface on a surface thereof.
31. The method of manufacturing a semiconductor package substrate according to claim 18, further comprising a step of forming solder balls or connection pins so as to connect to the metal pads. 32. The metal constituting the metal base is at least one metal selected from the group consisting of stainless steel, iron, nickel, copper and aluminum, or an alloy thereof. 32. The method of manufacturing a semiconductor package substrate according to any one of items 31 to 31. 33. The method according to claim 18, further comprising a step of bonding a carrier base material to a surface of the multilayer wiring structure film on which the metal base is not disposed. A method for manufacturing a semiconductor package substrate. 34. The manufacturing of a semiconductor package substrate according to claim 33, wherein the carrier substrate is any one of a printed circuit board having at least one wiring layer, a ceramic substrate, and an organic-inorganic composite substrate. Method. 35. The method according to claim 33, wherein the step of bonding the carrier base material to the multilayer wiring structure film uses any one of an adhesive, thermocompression bonding, and bonding using a chemical reaction. 35. The method for manufacturing a semiconductor package substrate according to 34. 36. The method according to claim 33, further comprising the step of connecting the carrier base material to the second metal pad via a conductive paste or an anisotropic conductive film. Of manufacturing a semiconductor package substrate. 37. The method according to claim 33, further comprising a step of forming solder balls or connection pins on the surface of the carrier base so as to be connected to the second metal pad via the carrier base. 37. The method for manufacturing a semiconductor package substrate according to any one of items 36 to 36. 38. The step of bonding a carrier substrate to the multilayer wiring structure film is performed before a step of forming an opening in the metal base and exposing the first metal pad. 38. The method of manufacturing a semiconductor package substrate according to any one of items 33 to 37. 39. The method according to claim 33, wherein the step of bonding the carrier base material to the multilayer wiring structure film is performed after the step of forming an opening in the metal base and exposing the first metal pad. 38. The method of manufacturing a semiconductor package substrate according to any one of items 37 to 37. 40. A method of manufacturing a semiconductor device, comprising: connecting a semiconductor element to a first metal pad of a semiconductor package substrate manufactured by the method according to claim 18. Description: 41. The semiconductor device according to claim 40, wherein the semiconductor element is flip-chip connected to the first metal pad by using one of a low melting point metal and a conductive resin. Production method.