JP2000252163A - Capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an aggregate of capacitors connected in parallel to one another, which is of large capacity and low impedance over a wide range of frequencies. SOLUTION: This capacitor comprises a plurality of polygonal capacitor bodies 4, each of which is formed by alternately laminating first electrode layers 2a and second electrode layers 2b, while interposing dielectric layers 3 therebetween, respectively. These bodies 4 are arranged in the direction of surface of the layer 2. A plurality of first terminals 8 to be connected to the layers 2a and a plurality of second terminals 9 to be connected to the layers 2b are formed around the periphery of each body 4 so that the terminals 8 and 9 extend alternately. Terminal electrodes located between adjacent bodies 4 are shared in common by the electrode layers belonging to such adjacent bodies 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor in which a plurality of capacitor bodies are arranged on a plane, for example, disposed in an electric circuit which operates at high speed, for bypassing high-frequency noise or for preventing fluctuations in power supply voltage. The present invention relates to a large-capacity, low-impedance capacitor provided to

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been an increasing demand for electronic components installed in the electronic devices to be smaller, thinner, and compatible with high frequencies.

Particularly, in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is 400 MHz to 1 GHz, and the clock frequency of the bus between chips is also 75 MHz to 100 MHz even at the personal computer level. The speedup is remarkable.

As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, it has become essential for passive components, such as capacitors, to exhibit excellent characteristics with respect to high-frequency or high-speed pulses, along with increasing the size and capacity. I have.

[0005] In order to make a capacitor compact and high capacity,
It is most effective to make the dielectric layer sandwiched between the pair of electrodes thinner and thinner. The thinning is compatible with the above-mentioned tendency of voltage drop.

On the other hand, various problems associated with the high-speed operation of the IC circuit are more serious than miniaturization of each element. Of these, in the function of removing high-frequency noise, which is the role of a capacitor, what is particularly important is the instantaneous drop in the power supply voltage that occurs when logic circuits are switched at the same time.
This is a function to reduce the energy stored in the capacitor by supplying it instantaneously, and is a so-called decoupling capacitor.

The performance required of this decoupling capacitor lies in how quickly the current can be supplied in response to a current fluctuation in the load faster than the clock frequency.
Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.

However, an actual capacitor has a resistance component and an inductance component in addition to a capacitance component. The impedance of the capacitance component decreases with increasing frequency, and the inductance component increases with increasing frequency.

For this reason, as the operating frequency increases,
The inductance of the element limits the transient current to be supplied, causing an instantaneous drop in the power supply voltage on the logic circuit side or new voltage noise. As a result, an error occurs in the logic circuit. Especially recent L
In the SI, the power supply voltage is reduced in order to suppress an increase in power consumption due to an increase in the total number of elements, and the allowable fluctuation width of the power supply voltage is also reduced. Therefore, in order to minimize the voltage fluctuation width during high-speed operation, the impedance of the decoupling capacitor itself is reduced even in a high-frequency region, and it is very necessary to have the ability to supply the stored charge as a necessary current instantaneously. is important.

The standard of impedance reduction is AJ Rain
al, "Computing Inductive Noiseof CMOS Drivers", I
EEE Trans. Comp., Packag., Manufact. Technol.-Part
B, Vol. 19, pp. 789-802 (1996), the change in current per driver is 40 mA / ns. Power supply voltage is 1.8V, voltage fluctuation tolerance is 10%
0.18 V and the number of off-chip drivers is 64, the upper limit of the inductance is 0.14 nH and 1 G
The impedance at Hz must be less than about 0.4Ω.

In order to minimize the impedance of the capacitor in the required frequency range, the capacitance component of the capacitor itself is increased and the resistance component and the inductance component are reduced, or the equivalent series inductance ESL and the capacitance C Resonance frequency f ₀ = 1 / 2π (ES
L · C) The capacitance may be reduced so that ^1/2 is adjusted to the required frequency.

In the former method, first, regarding the capacitance,
As described above, it is most effective to reduce the thickness of the dielectric layer held between the electrode layers. The resistance component is determined by the dielectric loss of the dielectric and the resistance of the electrode layer. The resistance of the electrode layer can be considered to be substantially constant except for the skin effect that becomes significant at several GHz or more.

As a method of reducing the inductance, a method of minimizing the length of the current path, a method of minimizing the loop cross-sectional area by forming the current path into a loop structure, and a method of distributing the current path into n pieces to reduce the effective inductance Is set to 1 / n.

Attempts have been made to reduce the inductance of the capacitor by such a method and reduce the impedance of the element. However, the area where the impedance can be used at 0.4Ω or less is determined by the capacitance and the inductance of the capacitor. Only around the resonance frequency. If the capacitor is used with a reduced capacity in a frequency range higher than this, the capacitor will function only in the range of the resonance frequency ± several tens MHz.

As a method of overcoming the fact that the impedance drops only near the resonance frequency and realizing a capacitor that functions with low impedance in a wide frequency range, means for connecting capacitors having different capacities in parallel has been considered. For example, as disclosed in JP-A-6-77083, there is an attempt to obtain a capacitor having a large capacity and excellent high-frequency characteristics by arranging a plurality of dielectric materials having different relative dielectric constants in parallel.

In a multilayer ceramic capacitor, as described in JP-A-8-162368,
By changing the electrode area and the dielectric layer thickness in one capacitor, two capacitors having different capacitances are connected in parallel, a low impedance is promoted at the resonance point of the two capacitors having different capacitances, and a single component is formed. Attempts have been made to develop a noise absorbing function in a wide frequency range.

In Japanese Patent Application Laid-Open No. 9-246098, the electrodes of each layer are formed so that each capacitance is different, and each stage is connected in parallel via an inductor element, so that a wide frequency range can be obtained in the same manner as described above. Attempts have been made to develop a noise absorbing function.

[0018]

However, in the thin film capacitor disclosed in JP-A-6-77083, even if the dielectric layer is divided in a plane while the external terminal electrodes of the capacitor are kept as a pair, the equivalent circuit is not obtained. Since it is not different from a single capacitor, it is considered that only the parallel effect of the dielectric properties of the materials is used, and the effect on the equivalent circuit does not appear.

The capacitor disclosed in Japanese Patent Application Laid-Open No. 8-162368 is a parallel circuit on an equivalent circuit. However, if the self-inductance of two capacitive elements in a chip is large,
A great effect due to the parallel connection cannot be obtained.
Further, in this structure, current flows in the same direction in the two capacitance elements themselves, so that the mutual inductance between the two capacitance elements increases, and the effect of parallel connection cannot be expected.

Further, in a capacitor in which an inductor element is inserted between the capacitors disclosed in Japanese Patent Application Laid-Open No. 9-246098, the inductance of the entire element increases, which goes against lower impedance. As an even more important problem, there is a local maximum point of the impedance due to the parallel resonance between the resonance points.
There is a problem that the impedance cannot be reduced in a wide frequency range of z or more.

An object of the present invention is to provide a capacitor having a large capacity and a low impedance in a wide frequency range.

[0022]

According to the present invention, there is provided a capacitor comprising:
A plurality of polygonal capacitor bodies in which a first electrode layer and a second electrode layer are alternately stacked with a dielectric layer interposed therebetween are arranged, and the first electrode is provided around each capacitor body. Forming a plurality of first terminal electrodes connected to the layer and a plurality of second terminal electrodes connected to the second electrode layer alternately;
In addition, the first and second terminal electrodes of adjacent capacitor bodies are connected to each other.

In the present invention, the capacitor body means a portion where the dielectric layer is sandwiched between electrode layers having different polarities, that is, a portion which substantially generates capacitance. Therefore, a plurality of first electrode layers are formed on one main surface of one dielectric layer, and a second electrode layer facing the first electrode layer is formed on the opposite surface to form a plurality of capacitor bodies. The capacitors may be arranged side by side, or the dielectric layer itself may be independent for each capacitor body.

In the structure of the capacitor of the present invention, one of the first and second terminal electrodes is provided at a corner of the capacitor body, and the other terminal electrode is provided on a line connecting a pair of terminal electrodes provided at the corner. It is desirable that the other terminal electrode be provided at the center of a line connecting a pair of terminal electrodes provided at corners.

Furthermore, both the first terminal electrode and the second terminal electrode may be provided on the side of the capacitor body. In this case, when seen through in the stacking direction, the first terminal electrode (or the second terminal electrode) and the adjacent second terminal electrode (or the first
It is preferable to provide them so that the intervals between them are equal.

[0026]

In the conventional capacitor disclosed in Japanese Patent Application Laid-Open No. 8-162368, a current in the same direction flows through two adjacent capacitance elements, the mutual inductance between the two capacitance elements increases, and the effect of parallel connection is expected. I couldn't do that. If the distance between the two capacitors is increased, the mutual inductance is reduced, but the size is increased, and the overall inductance is increased by the terminal electrodes and conductors that supply current to the two capacitors. Did not achieve the effect of parallel connection.

On the other hand, in the capacitor of the present invention, current is divided and input to a plurality of (n) first terminal electrodes in each capacitor body. Then, in order to flow from one first terminal electrode to the second terminal electrode on both sides adjacent to the first terminal electrode, surely in each capacitor body in at least two directions or more from one first terminal electrode. Shunted.

For example, a first terminal electrode is provided at each corner of a capacitor body having a quadrangular planar shape, and second terminal electrodes are provided on a line connecting a pair of first terminal electrodes. A current is input from the first terminal electrode. To explain the case where
A current is input from the first terminal electrode at the corner of each capacitor body, and is diverted to the second terminal electrodes on both sides forming the apex angle. Further, both the first terminal electrode and the second terminal electrode are provided on the side of each capacitor body, and when a current is input from the first terminal electrode, the second terminal electrode on the same side as the first terminal electrode and the adjacent terminal Is shunted to the second terminal electrode on the side of Therefore, in any case, the effective inductance can be reduced. Moreover, each capacitor body is a circuit in which n capacitive elements consisting of one first terminal electrode and two adjacent second terminal electrodes are connected in parallel, and a plurality of such capacitor bodies are further connected in parallel to form a capacitor. Therefore, low impedance characteristics can be exhibited in a wide frequency range due to the shunt effect and the parallel connection.

Further, according to the present invention, even when the first terminal electrode and the second terminal electrode are provided close to each other in each capacitor main body, the first terminal electrode and the other first terminal electrode are separated from each other.
Since the direction of the current flowing through the second terminal electrodes provided therebetween can be reversed, mutual interference does not occur between the first terminal electrodes, and the current can be shunted reliably.

Further, for example, when the first terminal electrode is provided at the corner, the second terminal electrode is provided at the center on the line connecting the pair of first terminal electrodes, so that the second terminal electrode and the pair of first terminals are provided. The distance from the electrode is the same, the intensity of the current flowing from the first terminal electrode to the second terminal electrode is the same, and the above-described shunt effect can be further improved. In addition, the distance between the external terminal electrodes connected to the terminal electrodes becomes the same, and mounting on another substrate becomes easy.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The capacitor of the present invention can be realized in both a thin film type and a thick film type such as a chip capacitor, and is applicable not only to a capacitor having not only a single dielectric layer but also a plurality of dielectric layers. can do.
Hereinafter, a single-layer capacitor in which the dielectric layer is a thin film type will be described.

1 to 3 show a capacitor according to the present invention. FIG. 1 is an exploded perspective view, FIG. 2 is a plan view excluding a protective layer, and FIG. 3 is a sectional view taken along line XX of FIG. is there. In this example, it is an aggregate of four capacitor bodies 4. The capacitor 10 includes four capacitor bodies 4 each having a square planar shape and formed by alternately laminating two electrode layers 2 and one dielectric layer 3 on one insulator substrate 1. The first electrode layer 2a, the second electrode layer 2a,
This is the electrode layer 2b. However, the dielectric layer 3 is a single plate that straddles all of the four capacitor bodies 4, and the adjacent first electrode layers 2a and the adjacent second electrode layers 2b are first terminals located between them. It is connected by the electrode 5 and the second terminal electrode 6.

Here, the capacitor body 4 is a portion where the dielectric layer 3 is sandwiched between the first electrode layer 2a and the second electrode layer 2b, that is, a portion that substantially generates a capacitance. Therefore, the first terminal electrode 5 and the second terminal electrode 6 are provided around the capacitor main body 4, that is, provided to protrude outward from the capacitor main body 4. Adjacent capacitor bodies 4 share a terminal electrode located between them. Thereby, the four capacitor bodies 4 are connected in parallel.

The first electrode layer 2a includes nine first terminal electrodes 5, and the second electrode layer 2b includes twelve second terminal electrodes 6, including those located between the adjacent capacitor bodies 4.
Are alternately provided around each capacitor body 4 as clearly shown in FIG. Specifically, the first terminal electrode 5
Are provided at the corners of each capacitor body 4, and the second terminal electrode 6 is provided at the center on the side connecting two adjacent first terminal electrodes 5.

A protective layer 7 is formed on the insulator substrate 1 so as to cover the entire capacitor body 4 and the terminal electrodes 5 and 6.

The terminal electrodes 5 and 6 are connected to via hole conductors (not shown) penetrating in the thickness direction to the upper surface of the protective layer 7 and terminal portions 8 and 9 formed of solder bumps as necessary. Therefore, the terminal portions 8 and 9 are formed around each capacitor body 4 so as to correspond to the terminal electrodes 5 and 6. Specifically, the first terminal electrode 5 connected to the first electrode layer 2a is provided at a corner of the capacitor 4, and the second terminal electrode 6 connected to the second electrode layer 2b is provided at the center of each side of the capacitor body 4. ing. The dielectric layer 3 has slits or cutouts 31 so as to avoid these terminal electrodes 5 and 6.
32 are formed. Further, the second electrode layer 2b has a slit or a notch 21 formed so as to avoid the first terminal electrode 5. In particular, the slits or cutouts 31 and 21 have an essential structure because the first terminal electrode 5 needs to be led out to the protective layer 7 side.

Adjacent first terminal electrode 5 and second terminal electrode 6
Is preferably as short as possible, but is preferably 1.5 mm or less in consideration of the substantial outer shape of the capacitor 10 and the inductance of the entire device. This is because if it is larger than 1.5 mm, the inductance of the whole element becomes high and the size becomes large. On the other hand, in consideration of the easiness of fabrication, it is desirable that the thickness be 0.2 mm or more.

The material of the insulator substrate 1 is alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO ₃ single crystal,
The material is selected from silicon oxide, glass, quartz, and the like, and is not particularly limited.

The material of the electrode layer 2 and the terminal electrodes 5 and 6
Platinum (Pt), gold (Au), silver (Ag), palladium (Pd), low-resistance Cu, Ni, or the like can be suitably used as the material, and is a material having low reactivity with the dielectric layer 3. There is no particular limitation as long as it can be formed by a method such as vacuum evaporation or sputtering.

The material of the dielectric layer 3 may be a material having a high dielectric constant in a high frequency range, but may be composed of Pb, Mg,
b) a dielectric composed of a perovskite-type oxide crystal containing Pb, PZT, PLZT, BaTiO ₃ , Sr
TiO ₃ , Ta ₂ O _5, or a compound obtained by adding or substituting another metal oxide to these may be used, and is not particularly limited. In addition, in the case of a thin film type as in this embodiment, the film thickness is high in order to secure high capacity and insulation.
0.3 to 1.0 μm, particularly 0.4 to 0.8 μm is desirable.

The protective layer 7 is made of a photocurable resin, SiO ₂ or the like. The material of the via-hole conductor forming the terminal portions 8 and 9 is, for example, Ag-Pd, solder, gold or the like.
Any conductive material that can be formed inside may be used. Note that, on the upper surface of the via hole conductor, solder bumps formed by solder balls or solder paste, or screen printing of a paste such as Ag-Pd or Ni-solder are used to facilitate connection to other substrates or circuits. Plating, Ni-Sn
Pads formed by plating or the like are formed slightly wider than the cross-sectional area of the via-hole conductor. The via-hole conductor may be formed of the same material at the same time as the production of the bump or pad.

In the capacitor 10 configured as described above, as shown in FIG. 2, for example, a current is shunted to the nine first terminal electrodes 5 via the first terminal portions 8 and input. Therefore, in each of the four capacitor bodies 4, current is divided and input from the four first terminal electrodes 5. In each capacitor body 4, current flows from one first terminal electrode 5 to two adjacent second terminal electrodes 6, and hardly flows to the other second terminal electrodes 6. Also,
Even in the case where the first terminal electrode 5 and the second terminal electrode 6 are provided close to each other, the second terminal electrode provided between the first terminal electrode 5 and the other first terminal electrode 5 is provided between them. The direction of the current flowing through 6 can be reversed. Therefore, there is no mutual interference between the first terminal electrodes 5, the current can be shunted reliably, and the effective inductance can be reduced.

Further, in each capacitor body 4, one first terminal electrode 5 and two
Four capacitive elements composed of the second terminal electrodes 6 are formed by the pair of electrode layers 2 and the dielectric layer 3, and a circuit is obtained as if four capacitive elements were connected in parallel. Therefore, capacitor 1
From the viewpoint of 0, not only the above-described parallel connection of the four capacitor bodies 4 but also the same effect as connecting 16 capacitors in parallel due to the shunt effect can be obtained.
Low impedance characteristics can be exhibited in a wider frequency range.

Further, by providing the second terminal electrode 6 at the center on the side connecting the pair of first terminal electrodes 5, the distance L between the second terminal electrode 6 and the pair of first terminal electrodes 5 becomes equal. ,
The intensity of the current flowing from the first terminal electrode 5 to the second terminal electrode 6 becomes the same, and the above-described shunt effect can be further improved.
Moreover, in this case, since the distance between the terminal electrodes 5 and 6 is equal, the interval between the bumps or pads exposed from the protective layer 7 is equal, and mounting on another substrate becomes easy.

FIG. 5 is a plan view showing a single-plate type thin film capacitor according to the second embodiment. The capacitor of the second embodiment has the same configuration as the capacitor of the first embodiment except that the number of the four capacitor bodies 4 of the first embodiment is increased to nine. Therefore, the same effect as that obtained by connecting 36 capacitors in parallel can be obtained by the shunt effect.

[0046]

EXAMPLE This manufactures the capacitor of the first embodiment,
This is an example of evaluating performance. Each electrode layer was formed using a high-frequency magnetron sputtering method. First, Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation. At the time of sputtering, the substrate holder was moved to the target position of the kind of the material to be formed, and the distance between the substrate and the target was fixed at 60 mm.

Next, a high-frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high-frequency power source, and a high-density magnet is formed near the target by a magnetron magnetic field formed by a permanent magnet provided on the back of the target. The target surface was sputtered by generating plasma.

In this embodiment, the plasma is generated by applying only to the target closest to the substrate. The substrate holder had a heating mechanism using a heater, and was controlled so that the substrate temperature during sputter deposition was constant. Further, a metal mask having a thickness of 0.1 mm is provided on the target side of the substrate placed on the substrate holder, so that a required mask can be set on the substrate deposition surface according to the deposition pattern.

All the dielectric layers were produced by a sol-gel method.
Also, Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2, and refluxed in 1,3-propanediol (about 12%).
(At 4 ° C. for 6 hours), and a MgNb composite alkoxide solution (Mg = 5.0 mmol, Nb 10.0 mmol, 1,
3-propanediol (140 mmol) was synthesized.

Next, 15 mmol of lead acetate (trihydrate) was added to the MgNb composite alkoxide solution and dissolved at 60 ° C., and a Pb (Mg _1/3 Nb _2/3 ) O ₃ (PMN) precursor solution was added. Synthesized.

Then, the thickness of the insulating substrate 1 is 0.25 m.
A first electrode layer and a first terminal electrode made of Au having a thickness of 0.3 μm are formed on an alumina substrate having a thickness of 0.3 m by sputter deposition and photolithography, and the coating solution is applied thereon by a spin coater and dried. After that, heat treatment was performed at about 400 ° C. for 1 minute to produce a gel film.

After the operation of coating and heat treatment of the coating solution was repeated, baking was performed at about 800 ° C. for 2 minutes (in air) to obtain a 0.7 μm-thick PMN thin film. The perovskite generation rate was calculated to be about 9 based on the X-ray diffraction result of the obtained thin film.
5%. After that, the dielectric film was patterned by a photoresist process.

A second electrode layer made of Au and a second terminal electrode were formed on the surface of the dielectric film by sputter deposition and photolithography.

By changing the size of the first electrode layer pattern and the second electrode layer pattern, a sample was prepared in which the distance L between the first terminal electrode and the second terminal electrode was changed as shown in Table 1. After that, using a photocurable resin, a protective film having a via hole is formed, and in the via hole, after solder paste is printed by screen printing of a solder paste, and by a reflow process, together with a via hole conductor serving as a terminal electrode, Twenty-one solder bumps having a diameter of 0.1 mm were formed to obtain a single-plate type thin film capacitor as shown in FIGS. Table 1 shows the area of the capacitor body, that is, the area of the electrode layer.

The impedance characteristics of the manufactured thin film capacitor at 1 MHz to 1.8 GHz were measured using an impedance analyzer (HP429 manufactured by Hewlett-Packard Company).
1A) and the results of measurement using a microwave probe (manufactured by Pico Probe) are shown in Table 1. The capacitance in Table 1 is a value of 1 MHz, and the inductance is L = 1 / (2π
f ₀ ) A value calculated from ² × C.

[0056]

[Table 1]

It can be seen from Table 1 that the smaller the distance L between the first terminal electrode and the second terminal electrode, that is, the distance L between the first terminal section and the second terminal section, the smaller the inductance.

FIG. 4 shows the impedance characteristics of the sample No. 1 where the distance L between terminal electrodes is 0.2 mm. From this figure, it can be seen that low impedance characteristics are shown in a wide frequency range.

In the above embodiment, the first electrode layer and the second electrode layer are formed by a thin film technique such as vacuum evaporation or sputtering, and the dielectric layer is formed by a thin film technique such as spin coating. Although the description has been given of the type capacitor, for example, a thick film type capacitor of a printed multilayer in which each electrode layer and the dielectric layer are printed and coated with a conductive paste or a dielectric paste in a predetermined pattern and baked may be used. Furthermore, a ceramic green sheet is used for an insulating substrate, a green sheet of a dielectric material is used for a dielectric layer, and a first electrode layer is formed on the insulating ceramic green sheet by applying a conductive paste to a conductive film and a second electrode layer. A thick film type capacitor may be formed by forming a conductive film on a green sheet of a dielectric / electric material by applying a conductive paste, laminating each green sheet, and integrally firing a green sheet multilayer. .

[0060]

As described above in detail, according to the present invention, a current is shunted to a plurality of first terminal electrodes and input, and one of the first terminal electrodes is most often connected to the first terminal electrode. Since the current is reliably shunted in at least two directions from one first terminal electrode so as to flow to the adjacent second terminal electrodes on both sides, effective inductance can be reduced. Moreover, in each capacitor body, a circuit is formed in which four capacitive elements each composed of one first terminal electrode and two adjacent second terminal electrodes are connected in parallel, and these capacitor bodies are further connected in parallel to form a capacitor. ,
Due to the shunt effect and the parallel connection, low impedance characteristics can be exhibited in a wide frequency range.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of a thin film type capacitor according to a first embodiment of the present invention.

FIG. 2 is a plan view of FIG. 1 from which a protective layer is omitted.

FIG. 3 is a sectional view taken along line XX of FIG. 2;

FIG. 4 is an impedance characteristic of the capacitor of FIG.

FIG. 5 is a plan view of a capacitor according to a second embodiment of the present invention.

[Description of Signs] 10 ... Capacitor 1 ... Insulator substrate 2a ... First electrode layer 2b ... Second electrode layer 3 ... Dielectric layer 4 ... Capacitor body 5 ... 1st terminal electrode 6 ... 2nd terminal electrode 7 ... protective layer 8 ... 1st terminal part 9 ... 2nd terminal part

Claims (2)

[Claims] 1. A plurality of polygonal capacitor bodies in which a first electrode layer and a second electrode layer are alternately laminated with a dielectric layer interposed therebetween, and a plurality of polygonal capacitor bodies are arranged. A plurality of first terminal electrodes connected to the first electrode layer and a plurality of second terminal electrodes connected to the second electrode layer are alternately formed, and first and second terminal electrodes of adjacent capacitor bodies are formed. A capacitor characterized by connecting each other. 2. The capacitor according to claim 1, wherein one of the first and second terminal electrodes is provided at a corner of the capacitor body, and the other terminal electrode is provided on a line connecting a pair of terminal electrodes provided at the corner. The capacitor as described.