JP3600734B2 - Thin film capacitors and substrates - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a thin-film capacitor, for example, a thin-film capacitor and a large-capacity, low-inductance capacitor that are provided in an electric circuit that operates at high speed and that are used for bypassing high-frequency noise or preventing fluctuations in power supply voltage. is there.
[0002]
[Prior art]
In recent years, as electronic devices have become smaller and more sophisticated, there has been an increasing demand for electronic components installed in the electronic devices to be smaller, thinner, and compatible with high frequencies.
[0003]
Particularly in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is 100 MHz to several hundred MHz, and the clock frequency of the bus between chips is also 30 MHz to 100 MHz, even at the personal computer level. Is remarkable.
[0004]
In addition, as the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, it has become essential for passive components such as capacitors to exhibit excellent characteristics with respect to high-frequency or high-speed pulses, along with increasing the size and capacity. I have.
[0005]
In order to reduce the size and the capacity of the capacitor, it is most effective to make the dielectric sandwiched between the pair of electrodes thinner and thinner. The thinning also conforms to the above-mentioned tendency of voltage drop.
[0006]
On the other hand, the problems associated with the high-speed operation of the IC circuit are more serious problems than the miniaturization of each element. Of these functions, what is particularly important in the function of removing high-frequency noise, which is the role of the capacitor, is to instantaneously reduce the power supply voltage that occurs when logic circuits are switched at the same time. This function is reduced by supplying. A capacitor having such a function is a so-called decoupling capacitor.
[0007]
The performance required for the decoupling capacitor is how quickly the current can be supplied according to the current fluctuation of the load section faster than the clock frequency. Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.
[0008]
However, an actual capacitor element has a resistance component and an inductance component in addition to the capacitance component. The impedance of the capacitance component decreases as the frequency increases, but the inductance component increases as the frequency increases. Therefore, as the operating frequency increases, the inductance of the element limits the transient current to be supplied, causing an instantaneous drop in the power supply voltage on the logic circuit side or new voltage noise. As a result, an error occurs in the logic circuit.
[0009]
In particular, in recent LSIs, the power supply voltage has been reduced in order to suppress an increase in power consumption due to an increase in the total number of elements, and the allowable fluctuation width of the power supply voltage has been reduced. Therefore, it is very important to reduce the inductance of the decoupling capacitor element itself in order to minimize the voltage fluctuation width during high-speed operation.
[0010]
There are three ways to reduce inductance. The first is a method of minimizing the length of the current path, the second is a method of reducing the magnetic field formed by one current path by the magnetic field formed by another current path adjacent thereto, and the third is a method of reducing the number of current paths to n. This is a method of dividing the effective inductance to 1 / n.
[0011]
The first method is a method of increasing the capacity per unit area to reduce the size, and can be achieved by reducing the thickness of the capacitor element. Japanese Patent Application Laid-Open No. 60-94716 discloses a capacitor in which the thickness of a dielectric material is reduced to 1 μm or less for the purpose of obtaining a capacitor having a large capacity and good high-frequency characteristics.
[0012]
[Problems to be solved by the invention]
However, when considering a decoupling capacitor that can be mounted at a desired place, a dimension that can be handled is required to be about 0.5 mm × 0.5 mm or more, and the inductance is reduced only by the first thin film and the miniaturization method. Had limitations.
[0013]
A method using a combination of the first to third methods is also conceivable. However, a thin film capacitor having sufficient characteristics in terms of characteristics such as miniaturization, thinning, large capacity, and high frequency compatibility is still obtained. I couldn't do that.
[0014]
An object of the present invention is to provide a thin-film capacitor having a low inductance structure that is easy to mount and easy to stack.
[0015]
[Means for Solving the Problems]
In the thin film capacitor of the present invention, a plurality of capacitive elements each having a first electrode layer formed on a lower surface of a dielectric layer and a second electrode layer formed on an upper surface are arranged at predetermined intervals, and a plurality of capacitive elements are formed between the plurality of capacitive elements. And a terminal electrode layer for connecting the first electrode layers to each other and the second electrode layer to each other, and an external terminal is further provided on the terminal electrode layer.
[0016]
A multilayer thin film capacitor according to the present invention includes a capacitor in which a plurality of dielectric layers and a plurality of electrode layers are alternately stacked, and the electrode layers are alternately formed as a first electrode layer or a second electrode layer from below. A plurality of elements are juxtaposed at predetermined intervals, and terminal electrode layers for connecting the first electrode layers and the second electrode layers on the same plane are provided between the plurality of capacitance elements, respectively. An external terminal is provided on the upper terminal electrode layer.
[0017]
Further, the substrate of the present invention is obtained by providing the above-mentioned thin film capacitor on the surface and / or inside of the base.
[0018]
[Action]
In the thin film capacitor of the present invention, a plurality of capacitance elements are juxtaposed at a predetermined interval, and the first electrode layer and the second electrode layer of each capacitance element are connected to each other by a terminal electrode layer provided between the capacitance elements. Since each external terminal is formed on each terminal electrode layer, each capacitance element is divided into a plurality of parts, the current path can be divided, and the inductance can be reduced.
[0019]
In addition, a terminal electrode layer connecting the first electrode layers and a terminal electrode layer connecting the second electrode layers are formed between the capacitor elements, and external terminals are provided on these terminal electrode layers, respectively. Thereby, the distance between the terminal electrode layers is shortened, the effective current path is shortened, and the inductance can be further reduced.
[0020]
Further, each electrode layer can be connected at a terminal electrode formed between the capacitor elements, and can be manufactured by a similar manufacturing method only by changing the electrode shape of the conventional capacitor as shown in FIG. It becomes easy. In addition, since the external terminal used for the contact with the outside can be formed on the terminal electrode layer where the dielectric layer does not exist directly below, it is possible to prevent damage to the capacitive element due to thermal stress when forming the external terminal, In addition, there is no need to consider the adverse effects, and mounting is facilitated.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
In the single-plate type thin film capacitor of the present invention, as shown in FIGS. 1 and 2, a first electrode layer 2 as a positive electrode is formed on a lower surface of a dielectric layer 1 and a second electrode layer 3 as a negative electrode is formed on an upper surface. The capacitive elements A, B, C, and D are juxtaposed at a predetermined interval.
[0022]
Terminal electrode layers 4 and 5 are formed between the capacitance elements A, B, C and D, respectively, and the first electrode layers 2 and the second electrode layers 3 of the capacitance elements A, B, C and D are respectively connected to terminals. They are connected via the electrode layers 4 and 5. The capacitance elements A, B, C, D and the terminal electrode layers 4, 5 are formed on the upper surface of the substrate 6.
[0023]
Then, as shown in FIG. 2, the upper surfaces of the three terminal electrode layers 4 connecting the first electrode layers 2 and the upper surfaces of the three terminal electrode layers 5 connecting the second electrode layers 3 are provided with external parts. The external terminals 7 that are exposed to the outside are formed.
[0024]
FIG. 3 shows the planar shapes of the electrode layers 2 and 3 and the dielectric layer 1 connected by the terminal electrode layers 4 and 5 described above. The first electrode layer 2 and the terminal electrode layer 4, and the second electrode layer 3 and the terminal electrode layer 5 are formed on the same plane as shown in FIGS. 3A and 3C, and have a comb shape as a whole. I have.
[0025]
The terminal electrode layers 4 and 5 can be formed not only between the capacitors A, B, C and D, but also outside the capacitors A, B, C and D as shown in FIG. .
[0026]
Further, as shown in FIG. 3B, the dielectric layer 1 has a rectangular shape having a size covering the first electrode layer 2 or the second electrode layer 3. The dielectric layers 1 may be separated from each other at a predetermined interval as shown in FIG. 3B, or each of the terminal electrode layers may be formed as shown in FIG. The connecting portions 9 made of the same material as the dielectric layer 1 may be connected to each other so as not to cover the entire surfaces of the dielectric layers 4 and 5. By forming such a connection portion 9, the insulation between the terminal electrode layers 4 and 5 having different polarities can be improved.
[0027]
In the above example, the case where four capacitors A, B, C, and D are provided has been described. However, the number of capacitors may be three or more. As the number of capacitor elements increases, the number of terminal electrode layers increases, and the number of external terminals formed thereon can be increased. Therefore, the number of current path divisions increases, and inductance can be reduced.
[0028]
As shown in FIG. 2, the external terminals 7 of the thin film capacitor of the present invention can be formed on the terminal electrode layers 4 and 5, respectively, whereby the capacitance can be taken out. It is not necessary to form the external terminals 7 on all of the electrode layers 4, 5, and the external terminals 7 may be formed as many as necessary. However, in order to obtain the effect of dividing the current path, as shown in FIG. 4, it is desirable to form at least two terminal electrode layers 4 and 5, respectively. Further, as shown in FIG. 5, two or more external terminals 7 may be formed on one terminal electrode layer 4, 5. In this case, fixing when connecting to the substrate by the external terminals 7 can be reliably performed.
[0029]
The thickness of the dielectric layer 1 and the electrode layers 2 and 3 is 0.1 to 1 μm, and the size is 0.5 to 3 mm on one side. The thickness and size of each layer can be appropriately changed depending on the material and the application.
[0030]
As the substrate 6 used in the present invention, alumina, sapphire, MgO single crystal, SrTiO ₃ single crystal, SiO ₂ coated silicon and the like are desirable. In particular, alumina and sapphire are desirable in that they have low reactivity with a thin film, are inexpensive, have high strength, and have the crystallinity of a dielectric film or an electrode film.
[0031]
The electrode layers 2 and 3 and the terminal electrode layers 4 and 5 of the present invention are made of gold (Au), platinum (Pt), palladium (Pd), copper (Cu), silver (Ag), nickel (Ni) thin film, or the like. Among them, gold (Au), platinum (Pt), and copper (Cu) thin films having low resistance, which have low reactivity with the dielectric material and are not easily oxidized, are most suitable.
[0032]
Furthermore, the dielectric layer 1 only needs to have a high dielectric constant in a high frequency region, and its thickness is desirably 1 μm or less. For example, the dielectric layer 1 is a dielectric thin film made of a perovskite-type composite oxide crystal containing Pb, Mg, and Nb as metal elements, and has a dielectric constant of 1000 or more at a measurement frequency of 300 MHz (room temperature). Thin films are preferred. The dielectric layer 1 may be, for example, a perovskite-type composite oxide crystal containing Ba and Ti, PZT, PLZT, SrTiO ₃ , Ta ₂ O _{5 and the} like, and is not particularly limited. Such a dielectric layer 1 is manufactured by a known method such as a PVD method, a CVD method, and a sol-gel method.
[0033]
The external terminals 7 may be in the form of a bump, a foil, a plate, a wire, a paste, or the like, and are not particularly limited. A plurality of the external terminals 7 may be combined. In addition, the material includes solder, Pb, Sn, Ag, Au, Cu, Pt, Al, Ni, a conductive resin, and the like. The material is not particularly limited, and a plurality of materials may be combined.
[0034]
In the thin film capacitor configured as described above, since the electrode layers 2 and 3 of the capacitors A, B, C, and D are connected by the terminal electrode layers 4 and 5, the current path can be divided into four. And lower inductance can be achieved.
[0035]
Further, the terminal electrode layers 4 and 5 formed between the capacitance elements A, B, C and D can be made closer to each other, and the distance L between the external terminals 7 formed on the terminal electrode layers 4 and 5 can be shortened. Therefore, the current path can be shortened, and the inductance can be reduced.
[0036]
That is, in a conventional thin film capacitor as shown in FIG. 7, a first electrode layer 21, a dielectric layer 22, and a second electrode layer 23 are sequentially laminated on the upper surface of a substrate 20, and the first electrode layer 21, the second electrode layer 23, a capacitance take-out portion 24 is formed at the end thereof. A plurality of thin-film capacitors may be connected in parallel by connecting the capacity take-out portions 24. In this case, four current paths are provided. However, since the distance between the capacitance extracting portions 24 is long, the effect of reducing the inductance is small.
[0037]
In addition, since the external terminals 7 used for contact with the outside are formed on the terminal electrode layers 4 and 5, respectively, the positive and negative external terminals 7 are exposed upward, and, for example, the electrodes are formed. It can be mounted by bonding the external terminals 7 to the electrodes of the substrate, and mounting on a substrate or the like becomes easy.
[0038]
The laminated type thin film capacitor of the present invention will be described with reference to FIG. According to FIG. 6, the laminated thin film capacitor is obtained by further laminating a dielectric layer and an electrode layer on the single plate type thin film capacitor shown in FIG.
[0039]
That is, capacitance elements formed by alternately laminating the electrode layers 2 and 3 and the dielectric layer 1 are juxtaposed at predetermined intervals, and terminal electrode layers 4 and 5 are formed between the capacitance elements, respectively. The first electrode layers 2 of the layers and the second electrode layers 3 of the two layers are connected via terminal electrode layers 4 and 5, respectively. The capacitor and the terminal electrode layers 4 and 5 are formed on the upper surface of the substrate 6.
[0040]
The multilayer thin-film capacitor having the structure shown in FIG. 6 also has the effect of dividing the current path by the plurality of external terminals 7 and the terminal electrode, just like the single-plate thin-film capacitor shown in FIGS. Due to the effect of shortening the current path by forming the layers 4 and 5 close to each other, the inductance can be reduced, and the external terminals 7 can be formed on the uppermost terminal electrode layers 4 and 5, thereby facilitating the mounting. Furthermore, since the electrode layers 2 and 3 and the dielectric layer 1 are alternately laminated, a high capacity is obtained, and the terminal electrode layers 4 and 5 and the electrode layers 2 and 3 can be simultaneously formed, so that the lamination is easy. It becomes.
[0041]
Further, a terminal electrode layer 4 connecting the lower first electrode layers 2 to each other and a terminal electrode layer 4 connecting the upper first electrode layers 2 to each other are laminated, and the lower second electrode layers 3 are connected to each other. The terminal electrode layer 5 to be connected and the terminal electrode layer 5 to connect the upper second electrode layers 3 to each other are laminated, and the dielectric layer 1 does not exist directly under the terminal electrode layers 4 and 5. In addition, it is possible to prevent damage to the dielectric layer 1 due to thermal stress when forming external terminals.
[0042]
In addition, the thin film capacitor of the present invention is generally formed on the substrate surface as described above, and may be used by being built in the substrate. When the laminated type is built in the substrate, the terminal electrode layers are connected to each other by, for example, through-hole conductors formed in the substrate, and the external terminals can also be formed by through-hole conductors. Is taken out.
[0043]
In addition, although an example has been described in which the shape of the electrode layers 2 and 3 is rectangular, any shape such as a square shape or a circular shape may be used.
[0044]
【Example】
Example 1
The electrode layer, the terminal electrode layer, and the dielectric layer were all formed by using a high-frequency magnetron sputtering method. Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation.
[0045]
A substrate holder and three target holders are installed in the process chamber, and sputtering from three types of target materials is possible. At the time of sputtering, the substrate holder was moved to the target position of the kind of the material to be formed, and the distance between the substrate and the target was fixed at 60 mm.
[0046]
A high frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high frequency power supply, and a high density plasma is generated near the target by a magnetron magnetic field formed by a permanent magnet installed on the back of the target. The surface was sputtered.
[0047]
The application of the high-frequency voltage can be independently applied to the three targets. The substrate holder had a heating mechanism using a heater, and was controlled so that the substrate temperature during sputter deposition was constant.
[0048]
In addition, three types of metal masks having a thickness of 0.10 mm are provided on the target side of the substrate placed on the substrate holder, and a structure in which a necessary mask can be set on the substrate deposition surface according to a deposition pattern. .
[0049]
First, as shown in FIG. 3A, a first electrode layer was connected to each other by a terminal electrode layer on a 0.25 mm-thick alumina sintered body substrate by sputtering a Pt target with a first mask pattern. An electrode is integrally formed, subsequently, a target is made of Pb (Mg _1/3 Nb _2/3 ) O ₃ sintered body, a second mask pattern is set, and a substrate temperature is set to 535 ° C. and a high frequency power is set to 200 W. Thus, a dielectric layer as shown in FIG. 3B was formed.
[0050]
Next, a third mask pattern was set, and a comb-shaped electrode in which the second electrode layers were connected by a terminal electrode layer as shown in FIG. 3C was integrally formed by sputtering a Pt target. The total area of each of the first electrode layer and the second electrode layer was 0.8 mm ² .
[0051]
Solder bumps were formed on the terminal electrode layers of the manufactured single-plate type thin film capacitor, and mounted on an evaluation board. The used solder bumps had a diameter of 0.1 mm and were formed three on each terminal electrode layer to produce a thin film capacitor as shown in FIGS. The distance L between the solder bumps was 0.5 mm.
[0052]
The evaluation was performed using an impedance analyzer (HP4291A, manufactured by Hewlett-Packard Company) as an impedance characteristic at 1 MHz to 1.8 GHz. As a result, a value of 17.5 nF was obtained for the capacitance component and a value for the inductance component was 80 pH. After the above measurement, when the cross section of the thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.4 μm.
[0053]
As a comparative example, the capacitance component and the inductance component were measured in the same manner as described above except that the conditions such as the area of the electrode layer and the like were prepared except that the structure of the conventional general capacitor was used as shown in FIG. However, the capacitance component obtained a value of 17.6 nF, and the inductance component obtained a value of 380 pH.
[0054]
Example 2
A laminated thin-film capacitor having 10 dielectric layers was fabricated in exactly the same manner as in Example 1, and evaluated by the same method as in Example 1. As a result, a capacitance component of 176 nF and an inductance component of 80 pH were obtained. After the above measurement, when the cross section of the multilayer thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.4 μm.
[0055]
Example 3
The substrate material, the electrode material, the electrode forming method, the shape, and the dimensions were exactly the same as in Example 1, and only the dielectric layer was formed by the sol-gel method. The procedure for producing a film by the sol-gel method was as follows.
[0056]
Mg acetate and Nb ethoxide were weighed in a molar ratio of 1: 2, and reflux operation (124 ° C. for 24 hours) was performed in 2-methoxyethanol to obtain a MgNb composite alkoxide solution (Mg = 4.95 mmol, Nb = 10.05 mmol). , 2-methoxyethanol 150 mmol) was synthesized. Next, 15 mmol of lead acetate (anhydride) and 150 mmol of 2-methoxyethanol were mixed, and a Pb precursor solution was synthesized by a distillation operation at 120 ° C.
[0057]
The MgNb precursor solution and the Pb precursor solution are mixed at a molar ratio of Pb: (Mg + Nb) = 1: 1, sufficiently stirred at room temperature, and mixed with Pb (Mg _1/3 Nb _2/3 ) O ₃ (PMN) precursor. A body solution was synthesized.
[0058]
The concentration of this solution was diluted about 3-fold with 2-methoxyethanol to obtain a coating solution. Next, the coating solution was applied on the electrode layer by a spin coater, dried, and then heat-treated at 300 ° C. for 1 minute to produce a gel film. After repeating the operation of coating and heat treatment of the coating solution, baking was performed at 830 ° C. for 1 minute (in the air) to obtain a Pb (Mg _1/3 Nb _2/3 ) O ₃ thin film.
[0059]
A resist is applied on the obtained dielectric thin film, exposed and developed by a photolithography process, and the dielectric film is patterned into the same pattern shape as in Example 1 by wet etching using the resist as a mask. A thin-film capacitor similar to that of Example 1 was produced.
[0060]
The produced thin film capacitor was mounted on an evaluation board as in Example 1, and the impedance characteristics at 1 MHz to 1.8 GHz were measured using an impedance analyzer (HP4291A manufactured by Hewlett-Packard Co.). As a result, a capacitance component of 42.5 nF and an inductance component of 80 pH were obtained. After the above measurement, when the cross section of the thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.5 μm.
[0061]
【The invention's effect】
As described above in detail, in the thin-film capacitor of the present invention, each capacitance element is divided into a plurality, the current path can be divided, the inductance can be reduced, and the first electrode is provided between each capacitance element. A terminal electrode layer for connecting the layers and a terminal electrode for connecting the second electrode layers are formed. By providing external terminals to these terminal electrodes, the distance between the terminal electrodes is reduced, and the The current path becomes short and the inductance can be reduced. Furthermore, since the structure of the present invention can be easily laminated, and external terminals used for contact with the outside are formed on the terminal electrode layer, it is necessary to consider damage to the capacitive element due to thermal stress generated when forming the external terminals. And it is easy to mount.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view showing a single-plate type thin film capacitor of the present invention.
FIG. 2 is a plan view of FIG.
FIG. 3 is a plan view showing a comb-shaped electrode in which electrode layers of the thin film capacitor of the present invention are connected by a terminal electrode layer, and a dielectric layer.
FIG. 4 is a plan view of a thin film capacitor having a terminal electrode layer on which no external terminal is formed.
FIG. 5 is a plan view of a thin film capacitor in which two external terminals are formed on a terminal electrode layer.
FIG. 6 is an exploded perspective view showing a multilayer thin film capacitor of the present invention.
FIG. 7 is an exploded perspective view showing a conventional thin film capacitor.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Dielectric layer 2 ... 1st electrode layer 3 ... 2nd electrode layer 4, 5 ... Terminal electrode layer 6 ... Substrates A, B, C, D ... Capacitance element 7 ... External terminals

Claims (3)

A plurality of capacitive elements each having a first electrode layer formed on the lower surface of the dielectric layer and a second electrode layer formed on the upper surface thereof are arranged at predetermined intervals, and the first electrode layer is provided between the plurality of capacitive elements. And a terminal electrode layer for connecting the second electrode layers to each other, and an external terminal is further provided on the terminal electrode layer. A plurality of dielectric layers and a plurality of electrode layers are alternately stacked, and a plurality of capacitive elements in which the electrode layers are alternately formed as a first electrode layer or a second electrode layer from the lower side are juxtaposed at predetermined intervals. In addition, terminal electrode layers for connecting the first electrode layers and the second electrode layers on the same plane are respectively provided between the plurality of capacitive elements, and external terminals are further provided on the uppermost terminal electrode layer. A thin film capacitor characterized by being provided. A substrate comprising the thin film capacitor according to claim 1 provided on a surface and / or inside of a substrate.

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