JP2000150290A - Capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor which has large capacitance and low impedance over a wide frequency range. SOLUTION: Electrode layers 2 and dielectric layers 3 are alternately laminated, so that first and second electrode layers 2a and 2b of the electrode layer 2 are laminated alternately from the underside, a plurality of first terminal electrodes 5 to be connected with the first electrode layer 2a and a plurality of second terminal electrodes 6 to be connected with the second electrode layer 2b are formed alternately around a polygon shaped capacitor main body, the first or second terminal electrodes 5 or 6 are provided at the corners of the main body. When the first terminal electrodes 5 are provided at the corners of the main body, the second terminal electrodes 6 are provided in line connecting pairs of the first terminal electrodes 5. However, when the second terminal electrodes 6 are provided at the corners of the main body, the first terminal electrodes 5 are provided in line connecting the pairs of the second terminal electrodes 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a capacitor,
For example, the present invention relates to a large-capacity, low-impedance capacitor that is provided in an electric circuit that operates at high speed and that is used for bypassing high-frequency noise or preventing fluctuations in power supply voltage.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been a growing demand for electronic components installed in electronic devices to be smaller, thinner, and compatible with high frequencies.

Particularly, in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is 400 MHz to 1 GHz, and the clock frequency of the bus between chips is also 75 MHz to 100 MHz even at the personal computer level. The speedup is remarkable.

As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, it has become essential for passive components, such as capacitors, to exhibit excellent characteristics with respect to high-frequency or high-speed pulses, along with increasing the size and capacity. I have.

[0005] In order to make a capacitor compact and high capacity,
It is most effective to make the dielectric layer sandwiched between the pair of electrodes thinner and thinner. The thinning is compatible with the above-mentioned tendency of voltage drop.

On the other hand, various problems associated with the high-speed operation of the IC circuit are more serious than miniaturization of each element. Of these, in the function of removing high-frequency noise, which is the role of a capacitor, what is particularly important is the instantaneous drop in the power supply voltage that occurs when logic circuits are switched at the same time.
This is a function to reduce the energy stored in the capacitor by supplying it instantaneously, and is a so-called decoupling capacitor.

The performance required of this decoupling capacitor lies in how quickly the current can be supplied in response to a current fluctuation in the load faster than the clock frequency.
Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.

However, an actual capacitor has a resistance component and an inductance component in addition to a capacitance component. The impedance of the capacitance component decreases with increasing frequency, and the inductance component increases with increasing frequency.

For this reason, as the operating frequency increases,
The inductance of the element limits the transient current to be supplied, causing an instantaneous drop in the power supply voltage on the logic circuit side or new voltage noise. As a result, an error occurs in the logic circuit. Especially recent L
In the SI, the power supply voltage is reduced in order to suppress an increase in power consumption due to an increase in the total number of elements, and the allowable fluctuation width of the power supply voltage is also reduced. Therefore, in order to minimize the voltage fluctuation width during high-speed operation, the impedance of the decoupling capacitor itself is reduced even in a high-frequency region, and it is very necessary to have the ability to supply the stored charge as a necessary current instantaneously. is important.

The standard of impedance reduction is AJ Rain
al, "Computing Inductive Noiseof CMOS Drivers", I
EEE Trans. Comp., Packag., Manufact. Technol.-Part
B, Vol. 19, pp. 789-802 (1996), the change in current per driver is 40 mA / ns. Power supply voltage is 1.8V, voltage fluctuation tolerance is 10%
0.18 V and the number of off-chip drivers is 64, the upper limit of the inductance is 0.14 nH and 1 G
The impedance at Hz must be less than about 0.4Ω.

In order to minimize the impedance of the capacitor in the required frequency range, the capacitance component of the capacitor itself is increased and the resistance component and the inductance component are reduced, or the equivalent series inductance ESL and the capacitance C Resonance frequency f ₀ = 1 / 2π (ES
L · C) The capacitance may be reduced so that ^1/2 is adjusted to the required frequency.

In the former method, first, regarding the capacitance,
As described above, it is most effective to reduce the thickness of the dielectric layer held between the electrode layers. The resistance component is determined by the dielectric loss of the dielectric and the resistance of the electrode layer. The resistance of the electrode layer can be considered to be substantially constant except for the skin effect that becomes significant at several GHz or more.

As a method of reducing the inductance, a method of minimizing the length of the current path, a method of minimizing the loop cross-sectional area by forming the current path into a loop structure, and a method of distributing the current path into n pieces to reduce the effective inductance Is set to 1 / n.

Attempts have been made to reduce the inductance of the capacitor by such a method and reduce the impedance of the element. However, the area where the impedance can be used at 0.4Ω or less is determined by the capacitance and the inductance of the capacitor. Only around the resonance frequency. If the capacitor is used with a reduced capacity in a frequency range higher than this, the capacitor will function only in the range of the resonance frequency ± several tens MHz.

As a method of overcoming the fact that the impedance drops only near the resonance frequency and realizing a capacitor that functions with low impedance in a wide frequency range, means for connecting capacitors having different capacities in parallel has been considered. For example, as disclosed in JP-A-6-77083, there is an attempt to obtain a capacitor having a large capacity and excellent high-frequency characteristics by arranging a plurality of dielectric materials having different relative dielectric constants in parallel.

In a multilayer ceramic capacitor, as described in JP-A-8-162368,
By changing the electrode area and the dielectric layer thickness in one capacitor, two capacitors having different capacitances are connected in parallel, a low impedance is promoted at the resonance point of the two capacitors having different capacitances, and a single component is formed. Attempts have been made to develop a noise absorbing function in a wide frequency range.

In Japanese Patent Application Laid-Open No. 9-246098, the electrodes of each layer are formed so that each capacitance is different, and each stage is connected in parallel via an inductor element, so that a wide frequency range can be obtained in the same manner as described above. Attempts have been made to develop a noise absorbing function.

[0018]

However, in the thin film capacitor disclosed in JP-A-6-77083, even if the dielectric layer is divided in a plane while the terminal electrodes of the capacitor remain as a pair, the equivalent circuit is simple. Since this is not different from a single capacitor, it is considered that only the parallel effect of the dielectric properties of the materials does not produce an effect on the equivalent circuit.

In the parallel capacitor disclosed in Japanese Patent Application Laid-Open No. 8-162368, the equivalent circuit is a parallel circuit, but if the self-inductance of two capacitive elements in a chip is large, a great effect can be obtained by the parallel connection. Can not. Further, in this structure, current flows in the same direction in the two capacitance elements themselves, so that the mutual inductance between the two capacitance elements increases, and the effect of parallel connection cannot be expected.

Further, in a capacitor in which an inductor element is inserted between the parallel capacitors disclosed in Japanese Patent Application Laid-Open No. 9-246098, the inductance of the entire element increases, which goes against lower impedance. As an even more important problem, there is a local maximum point of the impedance due to the parallel resonance between the resonance points.
There is a problem that the impedance cannot be reduced in a wide frequency range of 0 MHz or more.

An object of the present invention is to provide a capacitor having a large capacity and a low impedance in a wide frequency range.

[0022]

According to the present invention, there is provided a capacitor comprising:
An electrode layer and a dielectric layer are alternately laminated, and the first electrode layer is formed around a polygonal capacitor body in which the electrode layers are alternately formed as a first electrode layer or a second electrode layer from below. And a plurality of second terminal electrodes connected to the second electrode layer are alternately formed.

Here, when the first terminal electrode or the second terminal electrode is provided at the apex corner of the capacitor body, and the first terminal electrode is provided at the apex corner of the capacitor body, the second terminal electrode is provided. Is provided on a line connecting a pair of the first terminal electrodes, and when the second terminal electrode is provided at a vertex of the capacitor body, the first terminal electrode is connected to the pair of the second terminal electrodes. It is desirable to be provided on the connecting line.

In the case where the first terminal electrode is provided at the vertex of the capacitor body, the second terminal electrode is connected to the pair of first terminal electrodes.
When the second terminal electrode is provided at the center of the capacitor main body on the line connecting the terminal electrodes,
It is preferable that the first terminal electrode is provided at a center on a line connecting the pair of second terminal electrodes.

Furthermore, both the first terminal electrode and the second terminal electrode may be provided on the side of the capacitor body. In this case, when seen through in the stacking direction, the first terminal electrode (or the second terminal electrode) and the adjacent second terminal electrode (or the first
It is preferable to provide them so that the intervals between them are equal.

[0026]

In the conventional parallel capacitor disclosed in Japanese Patent Application Laid-Open No. 8-162368, a current in the same direction flows through two adjacent capacitance elements, so that the mutual inductance between the two capacitance elements increases, and the effect of parallel connection is expected. I couldn't. Increasing the distance between the two capacitive elements reduces the mutual inductance, but increases the size and
The total inductance is increased by the terminal electrodes and the conductive wires that supply current to the two capacitive elements, and as a result, the effect of the parallel connection cannot be obtained with the conventional capacitor.

On the other hand, in the capacitor of the present invention, a current is divided and input to a plurality of (n) first terminal electrodes, and the current is diverted from one first terminal electrode to two adjacent terminals closest to the first terminal electrode. Of the first terminal electrode in at least two directions or more so as to flow to the second terminal electrode.

For example, the plane shape is a quadrangle (for example, a square)
A first terminal electrode is provided at each of the apical corners of the capacitor body, and a second terminal electrode is provided on a line connecting the pair of first terminal electrodes. A case where a current is input from the first terminal electrode will be described. A current is input from the first terminal electrode at the vertex of the main body, and is diverted to the second terminal electrodes on both sides forming the vertex. Further, both the first terminal electrode and the second terminal electrode are provided on the sides of the capacitor body, and when a current is input from the first terminal electrode, the second terminal electrode on the same side as the first terminal electrode and the second terminal electrode adjacent thereto Second on the side
The current is shunted to the terminal electrode. Therefore, in any case, the effective inductance can be reduced,
As if it were a circuit in which n capacitive elements each consisting of one first terminal electrode and the second terminal electrode on both sides were connected in parallel, low impedance characteristics could be exhibited in a wide frequency range by the shunt effect and the parallel connection.

In the present invention, the first terminal electrode and the second terminal electrode
Even when the terminal electrodes are provided close to each other, the direction of the current flowing from one first terminal electrode and the other first terminal electrode to the second terminal electrode provided therebetween can be reversed. Therefore, there is no mutual interference between the first terminal electrodes, and the flow can be reliably divided.

Further, for example, when the first terminal electrode is provided at the apex corner, the second terminal electrode is provided at the center on the line connecting the pair of first terminal electrodes, so that the second terminal electrode and the pair of first terminal electrodes are provided. The distance from the terminal electrode is the same, the intensity of the current flowing from the first terminal electrode to the second terminal electrode is the same, and the above-described shunt effect can be further improved. In addition, the distance between the terminal electrodes connected to the electrode layer becomes the same, and mounting on another substrate becomes easy.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The capacitor of the present invention can be realized in any of a thin film type and a thick film type such as a chip capacitor, and can be used not only in a single plate type but also in a laminated type. Hereinafter, each type will be described.

Embodiment 1 FIGS. 1 to 4 show a single-plate type thin film capacitor of the present invention, in which two electrode layers 2 and one dielectric layer 3 are alternately formed on an insulating substrate 1. A capacitor body 4 having a square planar shape formed by lamination is formed, and the electrode layer 2 is a first electrode layer 2a and a second electrode layer 2b from below.

As shown in FIG. 2, four first terminal electrodes 5 connected to the first electrode layer 2a and four second terminals connected to the second electrode layer 2b are provided around the capacitor body 4. Electrode 6
Are provided alternately.

The first terminal electrode 5 is provided at the vertex of the capacitor body 4, and the second terminal electrode 6 is provided on a line x connecting the first terminal electrodes 5 on both sides of the second terminal electrode 6. Have been. The second terminal electrode 6 includes a pair of first terminal electrodes 5.
Are provided at the center on the line x connecting the. Here, the capacitor body 4 refers to a portion where the dielectric layer 3 is sandwiched between the first electrode layer 2a and the second electrode layer 2b, that is, a portion that substantially generates a capacitance, and the first terminal electrode 5 and the second Terminal electrode 6
Are provided around the capacitor body 4, that is, protruding outward from the capacitor body 4.

Adjacent first terminal electrode 5 and second terminal electrode 6
Is preferably as short as possible, but is desirably 1.5 mm or less in consideration of the substantial outer shape of the element and the inductance of the entire element. If it is larger than 1.5 mm, the inductance of the whole element increases,
In addition, it is because the size is increased. On the other hand, in consideration of the easiness of fabrication, it is desirable that the thickness be 0.2 mm or more.

On the insulator substrate 1, as shown in FIG.
A protective layer 7 made of a photocurable resin, SiO ₂ or the like is formed so as to cover the capacitor body 4, the first terminal electrode 5, and the second terminal electrode 6, as shown in FIGS. 3 and 4.
Connected to the first terminal electrode 5 and the second terminal electrode 6, for example, A
Via-hole conductors 8 made of g-Pd, solder, gold or the like are respectively formed inside the protective layer 7, and external terminal electrodes 9 for connecting to another substrate or the like are formed on the upper surfaces of the via-hole conductors 8, respectively. I have. These external terminal electrodes 9 can be formed by a known technique such as solder bumps formed by solder balls or solder paste, screen printing of a paste such as Ag-Pd, Ni-solder plating, or Ni-Sn plating. I just need. Also, via-hole conductor 8
May be formed of the same material in the via hole at the same time when the external terminal electrode 9 is manufactured.

The insulator substrate 1 is selected from alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO ₃ single crystal, surface silicon oxide, glass, quartz, etc., and is not particularly limited.

The material of the electrode layer 2 and the terminal electrodes 5 and 6
Platinum (Pt), gold (Au), silver (Ag), palladium (Pd), low-resistance Cu, Ni, or the like can be suitably used as the material, and is a material having low reactivity with the dielectric layer 3. There is no particular limitation as long as it can be formed by a method such as vacuum evaporation or sputtering.

Further, the material of the dielectric layer 3 may be any material having a high dielectric constant in a high frequency range.
Dielectrics composed of perovskite-type oxide crystals containing Mg and Nb, PZT, PLZT, and BaTi
O ₃ , SrTiO ₃ , Ta ₂ O _5, or a compound obtained by adding or replacing other metal oxides thereto,
There is no particular limitation. In the case of a thin film type, the film thickness should be 0.3 to 30 to ensure high capacity and insulation.
A film thickness of 1.0 μm, particularly 0.4 to 0.8 μm is desirable.

In the capacitor configured as described above,
As shown in FIG. 2, for example, a current is shunted to four first terminal electrodes 5 via the external terminal electrodes 9 and input, and two second terminals on both sides from one first terminal electrode 5. Since it flows to the electrode 6 and hardly flows to the other second terminal electrodes 6,
Also, when the first terminal electrode 5 and the second terminal electrode 6 are provided close to each other, the first terminal electrode 5 and the other first terminal electrode 5 can be connected to the second terminal electrode 5 provided therebetween. Since the direction of the current flowing through the terminal electrodes 6 can be reversed, there is no mutual interference between the first terminal electrodes 5, the current can be shunted reliably, and the effective inductance can be reduced. .

Further, four capacitive elements each including one first terminal electrode 5 and two second terminal electrodes 6 on both sides of the first terminal electrode 5 form a pair of the electrode layer 2 and the dielectric layer 3. And a circuit in which four capacitive elements are connected in parallel, and low impedance characteristics can be exhibited in a wide frequency range by the above-described shunt effect and parallel connection.

Further, by providing the second terminal electrode 6 at the center on the line x connecting the pair of first terminal electrodes 5, the distance L between the second terminal electrode 6 and the pair of first terminal electrodes 5 is made equal. As a result, the intensity of the current flowing from the first terminal electrode 5 to the second terminal electrode 6 becomes the same, and the above-described shunt effect can be further improved. In this case, since the distance between the terminal electrodes 5 and 6 is equal, the mounting on another substrate becomes easy.

Embodiment 2 FIGS. 5 to 9 show a multilayer chip capacitor type capacitor according to a second embodiment of the present invention. In this capacitor, four electrode layers 10 and three dielectric layers 11 are provided. Capacitor body 12 formed by alternately stacking
Are formed, and a dielectric layer that does not substantially form a capacitance is laminated above and below the capacitor body 12. Here, the capacitor body 12 also refers to a portion where the dielectric layer 11 is sandwiched between the electrode layers 10, that is, a portion that substantially generates capacitance. The electrode layers 10 are alternately arranged on the first electrode layer 10 from below.
a or the second electrode layer 10b. In this case, the thickness of the dielectric layer 11 is not particularly limited as long as it is formed from several μm to several tens μm. As a material of the dielectric layer 11,
The same thing as Embodiment 1 can be applied.

That is, any material having a high dielectric constant in a high frequency region may be used, but a dielectric made of a perovskite-type oxide crystal containing Pb, Mg, and Nb, and other materials such as PZT, PLZT, BaTiO ₃ , and SrTiO ₃ ,
Ta ₂ O ₅ or other metal oxides may be added to these,
It may be a substituted compound and is not particularly limited.

As shown in FIG. 5, a first external terminal electrode 15 connected to the first electrode layer 10a and a second external terminal electrode 16 connected to the second electrode layer 10b are provided on the sides around the capacitor body 12. Are formed. The first and second external terminal electrodes 15 and 16 are respectively formed on one side. That is, four first external terminal electrodes 1 as a whole
It has five and four second external terminal electrodes 16. Also,
Each of the external terminal electrodes 15 and 16 is formed over three surfaces of the front surface, the end surface, and the rear surface of the capacitor body 12, and has a U-shaped cross section as shown in FIGS.

Then, the second external terminal electrode 16 on the same side as the first external terminal electrode 15 (second external terminal electrode 16)
The distance L ₁ (first external terminal electrodes 15), different from the second external terminal electrode 16 (the first external terminal be within side adjacent to the first external terminal electrode 15 (second external terminal electrodes 16) They are equal to each other a distance L ₂ between the electrodes 15).

As shown in FIG. 8, the first electrode layer 1
0a, extending to each of the four sides of the capacitor body 12,
Four first electrode lead-out portions (corresponding to the terminal electrodes in FIGS. 1 to 5) 13 each connected to the first external terminal electrode 15 are provided, while, as shown in FIG. The layer 10 b is provided with four second electrode lead-out portions (corresponding to the terminal electrodes in FIGS. 1 to 5) 14 extending to each of four sides of the capacitor body 12 and connected to the second external terminal electrodes 16. Have been.

Therefore, when the first electrode lead portion 13 of the first electrode layer 10a and the first electrode lead portion 14 of the second electrode layer 10b are viewed in plan, the first electrode lead portion 13 (the second electrode lead portion 13) the second electrode lead portions 14 in the same side as the lead portion 14) (the distance L ₁ between the first electrode lead-out portion 13), the first electrode lead-out portion 13 thereof be in a different side (second electrode lead portions the distance L ₂ are equal to each other and the second electrode lead-out portion 14 adjacent to the 14) (first electrode lead portions 13). Therefore, regardless of the first and second external terminal electrodes (electrode extraction portions) connected by a line, an octagon in plan view is formed.

The material of the electrode layers 10a and 10b and the material of the first and second electrode lead portions 13 and 14 are platinum (Pt), gold (A
u), silver (Ag), palladium (Pd), low-resistance C
u, Ni and the like can be suitably used, and are not particularly limited as long as they are materials having low reactivity with the dielectric layer 11, and may be formed by a method such as screen printing.

The first and second external terminal electrodes 15, 1
The six materials are prepared by baking silver (Ag) or silver palladium (Ag-Pd) alloy, and then Ni-solder plating, Ni-S
Any material that can be formed by a known technique such as n-plating may be used.

In the capacitor configured as described above,
As shown in FIG. 10, for example, the current supplied to the second electrode layer 10b is divided and input to the electrode lead-out portion 14 via the four second external terminal electrodes 16. The current shunted from one second electrode lead-out part 14 flows toward two adjacent first electrode lead-out parts 13 and hardly flows into the other first electrode lead-out parts 13. For this reason, even when the first electrode lead-out part 13 and the second electrode lead-out part 14 are provided close to each other, the one second electrode lead-out part 14 and the other second electrode lead-out part 14 are located between them. First electrode lead-out part 1 provided
Since the direction of the current flowing to the third electrode 3 can be reversed, there is no mutual interference between the second electrode lead-out portions 14, the current can be shunted reliably, and the effective inductance can be reduced.

Further, one second electrode lead-out portion 14 and two first electrode lead-out portions 1 on both sides of the second electrode lead-out portion 14 are provided.
And four capacitive elements consisting of a pair of electrode layers 10a, 1a
Ob and the dielectric layer 11 form a circuit in which four capacitive elements are connected in parallel, and low impedance characteristics can be exhibited in a wide frequency range by the above-described shunt effect and parallel connection.

The distance between the second external terminal electrode 16 (first external terminal electrode 15) and the adjacent first external terminal electrode 15 (second external terminal electrode 16), that is, the second electrode extraction portion 14
(1st electrode lead-out part 15) and 1st electrode lead-out part 13 next to it.
By setting all the distances L to the (second electrode lead-out part 14) the same, the first electrode lead-out part 1
3 have the same intensity, and the above-described shunt effect can be further improved. Moreover, in this case, since the distances between the external terminal electrodes 15 and 16 are equal, mounting on another substrate becomes easy.

Embodiment 3 FIGS. 11 to 15 also show a multilayer chip capacitor type capacitor according to a third embodiment of the present invention. The arrangement of the first and second external terminal electrodes is different from that of the second embodiment. different.
In the third embodiment, the first external terminal electrode 25 is provided at the vertex of the capacitor body 22 and the second external terminal electrode 2
6 is a pair of first external terminals adjacent to the second external terminal electrode 26.
It is provided at the center on the line connecting the external terminal electrodes 25.
Therefore, the distance L between the second external terminal electrode 26 and the first external terminal electrode 25 adjacent thereto is all equal. Then, as shown in FIG. 14, the first electrode layer 20a is
The first electrode lead-out portion (corresponding to the terminal electrode in FIGS. 1 to 5) 23 is extended to the four apexes. FIG.
As shown in (2), the second electrode layer 20b has a second electrode lead-out portion 24 (corresponding to the terminal electrodes in FIGS. 1 to 5) extending to the center of each side of the dielectric layer 21.

As the material of the electrode layer, the dielectric layer, and the external terminal electrode, the same materials as those used in the second embodiment can be applied.

In the capacitor configured as described above,
As shown in FIG. 16, for example, the second external terminal electrode 26
The current is divided and input to the four second electrode extraction portions 24 in plan view, and flows from one second electrode extraction portion 24 toward two adjacent first electrode extraction portions 23, and the other. Since it hardly flows to the first electrode lead-out part 23, and even when the first electrode lead-out part 23 and the second electrode lead-out part 24 are provided close to each other, one second electrode lead-out part 24 and the other second electrode lead-out part 24 are provided. Since the direction of the current flowing from the two-electrode extraction portion 24 to the first-electrode extraction portion 23 provided therebetween can be made opposite, the mutual interference between the second-electrode extraction portions 24 does not occur. ,
Shunting can be performed reliably, and the effective inductance can be reduced.

Further, four capacitive elements each including one second electrode lead-out portion 24 and two first electrode lead-out portions 23 on both sides of the second external terminal electrode 26 are formed by a pair of electrode layers 20a,
The circuit is formed of the capacitor 20b and the dielectric layer 21 and is as if four capacitance elements were connected in parallel. By the above-described shunt effect and parallel connection, low impedance characteristics can be exhibited in a wide frequency range.

The distance between the second external terminal electrode 26 (first external terminal electrode 25) and the adjacent first external terminal electrode 25 (second external terminal electrode 26), that is, the second electrode lead portion 24
(The first electrode lead-out part 23) and the adjacent first electrode lead-out part 23
By setting all the distances L to the (second electrode lead-out portion 24) the same, the first electrode lead-out portion 2
3 have the same intensity, and the above-described shunt effect can be further improved.

Moreover, in this case, each external terminal electrode 2
Since the distances between 5 and 26 are equal, mounting on another board becomes easy.

In the present invention, the capacitor bodies 4, 1
The planar shape of 2, 22 is desirably a polygonal shape having the same length on each side. With such a shape, the first external terminal electrodes 5, 15, 25 or the second external terminal electrodes 6, 16, 26, which are provided at the apex corners, and the second external terminal electrodes 6, 16, 26, which are provided on both sides thereof, are provided.
The distance L between the external terminal electrodes 6, 16, 26 or the first external terminal electrodes 5, 15, 25 becomes the shortest, the current easily flows between them, and the effect of the parallel connection can be sufficiently exhibited.

In the above embodiment, the electrode layers 2, 10, 2
Although 0 is a square shape, that is, the planar shape of the capacitor bodies 4, 12, and 22 is square, it may be a polygonal shape such as a triangular shape or a pentagonal shape.
In particular, a polygonal shape having four or more sides is desirable.

Embodiment 4 Next, an example of mounting the multilayer chip capacitor described in Embodiment 2 or Embodiment 3 will be described. FIG. 17 is a half-sectional view showing that the multilayer chip capacitor 30 of the present invention is mounted on the upper surface of the IC package 31 and the entire IC package 31 is mounted on the mounting substrate 32. FIG. 18 is also mounted on the lower surface of the IC package 31. FIG. 5 is a half sectional view showing a state where the IC package 31 is mounted on a mounting board 32. In any case, the connection state between the multilayer chip capacitor 30 of the second embodiment and the electrode pad 33 of the mounting board 32 or the electrode pad 34 of the IC package 31 is as shown in FIG. 19 in plan view.

Regardless of the multilayer chip capacitor of the second embodiment or the multilayer chip capacitor of the third embodiment, the first external terminal electrode connected to the first electrode lead portion and the second external terminal electrode connected to the second electrode lead portion Are arranged regularly, it is not necessary to change the wiring of the CPU chip itself, the wiring between the CPU chip and the mounting board, and the wiring of the mounting board itself. Therefore, it is not necessary to provide useless wirings and lands. As a result, compared to the conventional structure where the multilayer chip capacitor is mounted on the mounting board separately from the IC package,
The effect of inductance due to the wiring between the CPU chip and the capacitor can be reduced. Further, since the capacitor is arranged near the CPU chip, the efficiency as a decoupling capacitor can be improved.

[0064]

EXAMPLE 1 This is an example in which the capacitor of Embodiment 1 was manufactured and its performance was evaluated. Each electrode layer was formed using a high-frequency magnetron sputtering method. First, Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation. At the time of sputtering, the substrate holder is moved to the target position of the material type to form a film.
The distance between targets was fixed at 60 mm.

Next, a high frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high frequency power supply, and a high density magnetic field is generated near the target by a magnetron magnetic field formed by a permanent magnet installed on the back of the target. The target surface was sputtered by generating plasma.

In this embodiment, plasma is generated by applying only to the target closest to the substrate. The substrate holder had a heating mechanism using a heater, and was controlled so that the substrate temperature during sputter deposition was constant. Further, a metal mask having a thickness of 0.1 mm is provided on the target side of the substrate placed on the substrate holder, so that a required mask can be set on the substrate deposition surface according to the deposition pattern.

All the dielectric layers were formed by a sol-gel method.
Also, Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2, and refluxed in 1,3-propanediol (about 12%).
(At 4 ° C. for 6 hours), and a MgNb composite alkoxide solution (Mg = 5.0 mmol, Nb 10.0 mmol, 1,
3-propanediol (140 mmol) was synthesized.

Next, 15 mmol of lead acetate (trihydrate) was added to the MgNb composite alkoxide solution and dissolved at 60 ° C., and a Pb (Mg _1/3 Nb _2/3 ) O ₃ (PMN) precursor solution was added. Synthesized.

Then, a first electrode layer made of Au having a thickness of 0.3 μm was formed on an alumina substrate having a thickness of 0.25 mm, and the (PMN) precursor solution was applied by a spin coater and dried. Thereafter, a heat treatment was performed at about 400 ° C. for 1 minute to produce a gel film.

After repeating the operation of applying and heat-treating the (PMN) precursor solution, baking is performed at about 800 ° C. for 2 minutes (in the air) to form a 0.7 μm-thick PMN thin film to become the dielectric layer 3. Obtained. From the X-ray diffraction result of the obtained thin film, the perovskite generation rate was calculated to be about 95%. afterwards,
The patterning of the dielectric film was performed by a photoresist process.

A second electrode layer made of Au was sputter-deposited on the surface of the dielectric film. Then, by changing the size of the first electrode layer pattern and the second electrode layer pattern, a sample was manufactured in which the distance L between the first external terminal electrode and the second external terminal electrode was changed as shown in Table 1. Thereafter, a protective film having via holes is formed using a photocurable resin, and after solder paste is screen-printed in the via holes, eight solder bumps having a diameter of 0.1 mm are formed together with the via hole conductors by reflow processing. Thus, a single-plate type thin film capacitor as shown in FIGS. 1 to 4 was obtained.
Table 1 shows the area of the capacitor body, that is, the area of the electrode layer.

The impedance characteristics of the manufactured thin film capacitor at 1 MHz to 1.8 GHz were measured using an impedance analyzer (HP429 manufactured by Hewlett-Packard Company).
1A) and the results of measurement using a microwave probe (manufactured by Pico Probe) are shown in Table 1. The capacitance in Table 1 is a value of 1 MHz, and the inductance is L = 1 / (2π
f ₀ ) A value calculated from ² × C.

[0073]

[Table 1]

It is understood from Table 1 that the smaller the distance L between the first external terminal electrode and the second external terminal electrode, the smaller the inductance. FIG. 20 shows the distance between terminal electrodes L = 0.6.
5 shows the impedance characteristics of a sample No. 3 of 5 mm. From this figure, it can be seen that low impedance characteristics are shown in a wide frequency range.

Example 2 This is an example in which the capacitor of Embodiment 3 was manufactured and its performance was evaluated. First, barium titanate is the main component,
Using a slip obtained by mixing a sintering aid, a solvent, a dispersant, and a binder, a green sheet having a thickness of 10 μm was formed by a doctor blade method.

On the other hand, commercially available Ag-Pd
A paste was prepared, and a conductor film to be the first electrode layer 20a was formed on the green sheet by a screen printing method.
Next, a conductor film to be the second electrode layer 20b was formed on another green sheet by a screen printing method. Next, a green sheet on which the conductor film to be the first electrode layer 20a is printed and a green sheet on which the conductor film to be the second electrode layer 20b are printed are alternately laminated to a total of 24 layers, and finally the electrode layer is printed. The green sheets not subjected to the lamination were laminated and thermocompressed to obtain a molded body. At this time, by changing the size of the electrode pattern, the distance L (actually, the distance between the center points of the electrodes) L between the first external terminal electrode 25 and the second external terminal electrode 26 after firing is as shown in Table 2. I did it.

The obtained molded body was cut to expose the ends of the first electrode lead-out part 23 and the second electrode lead-out part 24, and then fired in air at a temperature of 1250 ° C. for 2 hours. A capacitor body as shown in FIGS. 11 to 15 was manufactured except that the number of dielectric layers and the number of dielectric layers were different.

Thereafter, the capacitor body 2 including the portions where the end portions of the first electrode lead-out portion 23 and the second electrode lead-out portion 24 are exposed.
Ag over the front, end and back of the side or top of Ag
After applying and drying a conductive paste made of Pd, 8
Baking was performed at 00 ° C., and a plating coating layer was formed on the baked thick film conductor by Ni-solder plating.
The first and second external terminal electrodes 25 and 26 as shown in FIG. 1 were formed to obtain a multilayer chip capacitor. Table 2 shows the area of the capacitor body, that is, the area of the electrode layer.

From 1 MHz to 1.8 of the manufactured capacitor
Impedance characteristics at GHz are measured with an impedance analyzer (HP4291A manufactured by Hewlett-Packard)
Table 2 shows the results obtained by using the above and a microwave probe (manufactured by Pico Probe). The capacitance in Table 2 is a value of 1 MHz, and the inductance is L = 1 / (2πf ₀ ).
^This is a value calculated from ² × C.

[0080]

[Table 2]

From Table 2, it can be seen that the smaller the distance L between the first external terminal electrode 25 and the second external terminal electrode 26, the smaller the inductance. FIG. 21 shows the distance L between terminal electrodes.
= Impedance characteristics of the multilayer chip capacitor of Sample No. 13 of 1.4 mm.

From FIG. 9, it can be seen that low impedance characteristics are exhibited in a wide frequency range.

[0083]

As described above in detail, according to the present invention, for example, a current is shunted to four first terminal electrodes (first electrode lead-out portions) and input to one first terminal electrode. (First
The second terminal electrode (second electrode lead portion) on both sides closest to the first terminal electrode (first electrode lead portion) from the electrode lead portion)
, The current is reliably diverted in at least two directions from one first terminal electrode (first electrode lead-out portion), thereby reducing the effective inductance and as if one first terminal electrode (first A circuit in which four capacitive elements each composed of one electrode lead-out part) and the second terminal electrodes (second electrode lead-out parts) on both sides are connected in parallel, and low impedance characteristics can be exhibited in a wide frequency range due to the shunt effect and the parallel connection. .

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of a thin film capacitor according to Embodiment 1 of the present invention.

FIG. 2 is a plan view of FIG. 1 from which a protective layer is omitted.

FIG. 3 is a sectional view taken along the line x in FIG. 2;

FIG. 4 is a perspective view of FIG. 1 from which a protective layer is omitted.

FIG. 5 is an external perspective view of a multilayer chip capacitor according to Embodiment 2 of the present invention.

FIG. 6 is a cross-sectional view of the capacitor body taken along the line AA in FIG. 5;

FIG. 7 is a BB diagram of the capacitor main body of FIG. 5;

FIG. 8 is a plan view showing a first electrode layer of the second embodiment.

FIG. 9 is a plan view showing a second electrode layer according to the second embodiment.

FIG. 10 is a diagram illustrating a flow of a current input to the capacitor according to the second embodiment as viewed from above a capacitor main body.

FIG. 11 is an external perspective view of a multilayer chip capacitor according to Embodiment 3 of the present invention.

FIG. 12 is an AA cross-sectional view of the capacitor main body of FIG.

FIG. 13 is a BB diagram of the capacitor main body of FIG. 11;

FIG. 14 is a plan view showing a first electrode layer of the third embodiment.

FIG. 15 is a plan view showing a second electrode layer according to the third embodiment.

FIG. 16 is a diagram illustrating a flow of a current input to the capacitor according to the third embodiment as viewed from above a capacitor body.

FIG. 17 is a half sectional view showing a state in which the multilayer chip capacitor according to the second or third embodiment is mounted in an IC package.

FIG. 18 is a half sectional view showing a state in which the multilayer chip capacitor of the second or third embodiment is incorporated in another IC package and mounted.

FIG. 19 is a plan view showing a state in which the multilayer chip capacitor of Embodiment 2 is connected to a mounting board.

FIG. 20 shows impedance characteristics of the thin film capacitor of FIG.

FIG. 21 shows impedance characteristics of the multilayer chip capacitor of FIG. 11;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Insulator substrate 2a, 10a, 20a ... 1st electrode layer 2b, 10b, 20b ... 2nd electrode layer 3, 11, 21 ... Dielectric layer 4, 12, 22 ... Capacitor body 5 1st terminal electrode 6 2nd terminal electrode 13 and 23 1st electrode lead-out part 14 and 24 2nd electrode lead-out 9 9 external terminal electrode 15 and 25 ... 1st external terminal electrode 16, 26 ... 2nd external terminal electrode 30 ... multilayer chip capacitor 31 ... IC package 32 ... mounting substrate 33, 34 ... electrode pad

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[Procedure amendment]

[Submission date] November 29, 1999 (1999.11.
29)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention]

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a capacitor,
For example, the present invention relates to a large-capacity, low-impedance capacitor that is provided in an electric circuit that operates at high speed and that is used for bypassing high-frequency noise or preventing fluctuations in power supply voltage.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been a growing demand for electronic components installed in electronic devices to be smaller, thinner, and compatible with high frequencies.

Particularly, in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is 400 MHz to 1 GHz, and the clock frequency of the bus between chips is also 75 MHz to 100 MHz even at the personal computer level. The speedup is remarkable.

As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, it has become essential for passive components, such as capacitors, to exhibit excellent characteristics with respect to high-frequency or high-speed pulses, along with increasing the size and capacity. I have.

In order to increase the size and the capacity of a capacitor, it is most effective to make the dielectric layer sandwiched between a pair of electrodes thinner and thinner. The thinning is compatible with the above-mentioned tendency of voltage drop.

On the other hand, various problems associated with the high-speed operation of the IC circuit are more serious than miniaturization of each element. Of these, in the function of removing high-frequency noise, which is the role of a capacitor, what is particularly important is the instantaneous drop in the power supply voltage that occurs when logic circuits are switched at the same time.
This is a function to reduce the energy stored in the capacitor by supplying it instantaneously, and is a so-called decoupling capacitor.

The performance required of this decoupling capacitor lies in how quickly the current can be supplied in response to a current fluctuation in the load faster than the clock frequency.
Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.

However, an actual capacitor has a resistance component and an inductance component in addition to a capacitance component. The impedance of the capacitance component decreases with increasing frequency, and the inductance component increases with increasing frequency.

For this reason, as the operating frequency increases,
The inductance of the element limits the transient current to be supplied, causing an instantaneous drop in the power supply voltage on the logic circuit side or new voltage noise. As a result, an error occurs in the logic circuit. Especially recent L
In the SI, the power supply voltage is reduced in order to suppress an increase in power consumption due to an increase in the total number of elements, and the allowable fluctuation width of the power supply voltage is also reduced. Therefore, in order to minimize the voltage fluctuation width during high-speed operation, the impedance of the decoupling capacitor itself is reduced even in a high-frequency region, and it is very necessary to have the ability to supply the stored charge as a necessary current instantaneously. is important.

The standard of impedance reduction is AJ Rain
al, ”Computing Inductive Noiseof CMOS Drivers”, I
EEE Trans. Comp., Packag., Manufact. Technol.-Part
B, Vol. 19, pp. 789-802 (1996), the change in current per driver is 40 mA / ns. Power supply voltage is 1.8V, voltage fluctuation tolerance is 10%
0.18 V and the number of off-chip drivers is 64, the upper limit of the inductance is 0.14 nH and 1 G
The impedance at Hz must be less than about 0.4Ω.

In order to minimize the impedance of the capacitor in the required frequency range, the capacitance component of the capacitor itself is increased and the resistance component and the inductance component are reduced, or the equivalent series inductance ESL and the capacitance C Resonance frequency f ₀ = 1 / 2π (ES
L · C) The capacitance may be reduced so that ^1/2 is adjusted to the required frequency.

In the former method, first, regarding the capacitance,
As described above, it is most effective to reduce the thickness of the dielectric layer held between the electrode layers. The resistance component is determined by the dielectric loss of the dielectric and the resistance of the electrode layer. The resistance of the electrode layer can be considered to be substantially constant except for the skin effect that becomes significant at several GHz or more.

As a method of reducing the inductance, a method of minimizing the length of the current path, a method of minimizing the loop cross-sectional area by forming the current path into a loop structure, and a method of distributing the current path into n pieces to reduce the effective inductance Is set to 1 / n.

Attempts have been made to reduce the inductance of the capacitor by such a method and reduce the impedance of the element. However, the area where the impedance can be used at 0.4Ω or less is determined by the capacitance and the inductance of the capacitor. Only around the resonance frequency. If the capacitor is used with a reduced capacity in a frequency range higher than this, the capacitor will function only in the range of the resonance frequency ± several tens MHz.

As a method of overcoming the fact that the impedance drops only near the resonance frequency and realizing a capacitor that functions with low impedance in a wide frequency range, means for connecting capacitors having different capacities in parallel has been considered. For example, as disclosed in JP-A-6-77083, there is an attempt to obtain a capacitor having a large capacity and excellent high-frequency characteristics by arranging a plurality of dielectric materials having different relative dielectric constants in parallel.

In a multilayer ceramic capacitor, as described in JP-A-8-162368,
By changing the electrode area and the dielectric layer thickness in one capacitor, two capacitors having different capacitances are connected in parallel, a low impedance is promoted at the resonance point of the two capacitors having different capacitances, and a single component is formed. Attempts have been made to develop a noise absorbing function in a wide frequency range.

In Japanese Patent Application Laid-Open No. 9-246098, the electrodes of each layer are formed so that each capacitance is different, and each stage is connected in parallel via an inductor element, so that a wide frequency range can be obtained in the same manner as described above. Attempts have been made to develop a noise absorbing function.

[0018]

However, in the thin film capacitor disclosed in JP-A-6-77083, even if the dielectric layer is divided in a plane while the terminal electrodes of the capacitor remain as a pair, the equivalent circuit is simple. Since this is not different from a single capacitor, it is considered that only the parallel effect of the dielectric properties of the materials does not produce an effect on the equivalent circuit.

In the parallel capacitor disclosed in Japanese Patent Application Laid-Open No. 8-162368, the equivalent circuit is a parallel circuit, but if the self-inductance of two capacitive elements in a chip is large, a great effect can be obtained by the parallel connection. Can not. Further, in this structure, current flows in the same direction in the two capacitance elements themselves, so that the mutual inductance between the two capacitance elements increases, and the effect of parallel connection cannot be expected.

Further, in a capacitor in which an inductor element is inserted between the parallel capacitors disclosed in Japanese Patent Application Laid-Open No. 9-246098, the inductance of the entire element increases, which goes against lower impedance. As an even more important problem, there is a local maximum point of the impedance due to the parallel resonance between the resonance points.
There is a problem that the impedance cannot be reduced in a wide frequency range of 0 MHz or more.

An object of the present invention is to provide a capacitor having a large capacity and a low impedance in a wide frequency range.

[0022]

According to the present invention, there is provided a capacitor comprising:
An electrode layer and a dielectric layer are alternately laminated, and the first electrode layer is formed around a polygonal capacitor body in which the electrode layers are alternately formed as a first electrode layer or a second electrode layer from below. And a plurality of second terminal electrodes connected to the second electrode layer are alternately formed.

Here, when the first terminal electrode or the second terminal electrode is provided at the apex corner of the capacitor body, and the first terminal electrode is provided at the apex corner of the capacitor body, the second terminal electrode is provided. Is provided on a line connecting a pair of the first terminal electrodes, and when the second terminal electrode is provided at a vertex of the capacitor body, the first terminal electrode is connected to the pair of the second terminal electrodes. It is desirable to be provided on the connecting line.

In the case where the first terminal electrode is provided at the vertex of the capacitor body, the second terminal electrode is connected to the pair of first terminal electrodes.
When the second terminal electrode is provided at the center of the capacitor main body on the line connecting the terminal electrodes,
It is preferable that the first terminal electrode is provided at a center on a line connecting the pair of second terminal electrodes.

Furthermore, both the first terminal electrode and the second terminal electrode may be provided on the side of the capacitor body. In this case, it is preferable that the distance between the first terminal electrode (or the second terminal electrode) and the adjacent second terminal electrode (or the first terminal electrode) be all equal when seen through in the stacking direction. .

[0026]

In the conventional parallel capacitor disclosed in Japanese Patent Application Laid-Open No. 8-162368, a current in the same direction flows through two adjacent capacitance elements, so that the mutual inductance between the two capacitance elements increases, and the effect of parallel connection is expected. I couldn't. Increasing the distance between the two capacitive elements reduces the mutual inductance, but increases the size and
The total inductance is increased by the terminal electrodes and the conductive wires that supply current to the two capacitive elements, and as a result, the effect of the parallel connection cannot be obtained with the conventional capacitor.

On the other hand, in the capacitor of the present invention, a current is divided and input to a plurality of (n) first terminal electrodes, and the current is diverted from one first terminal electrode to two adjacent terminals closest to the first terminal electrode. Of the first terminal electrode in at least two directions or more so as to flow to the second terminal electrode.

For example, the plane shape is a quadrangle (for example, a square)
A first terminal electrode is provided at each of the apical corners of the capacitor body, and a second terminal electrode is provided on a line connecting the pair of first terminal electrodes. A case where a current is input from the first terminal electrode will be described. A current is input from the first terminal electrode at the vertex of the main body, and is diverted to the second terminal electrodes on both sides forming the vertex. In addition, when both the first terminal electrode and the second terminal electrode are provided on the sides of the capacitor body, and when a current is input from the first terminal electrode, the second terminal electrode on the same side as the first terminal electrode and the second terminal electrode are adjacent to the first terminal electrode. Second on the side
The current is shunted to the terminal electrode. Therefore, in any case, the effective inductance can be reduced,
It is as if a circuit in which n capacitive elements each composed of one first terminal electrode and the second terminal electrode on both sides are connected in parallel is provided, and it is possible to exhibit low impedance characteristics in a wide frequency range by the shunt effect and the parallel connection.

In the present invention, the first terminal electrode and the second terminal electrode
Even when the terminal electrodes are provided close to each other, the direction of the current flowing from one first terminal electrode and the other first terminal electrode to the second terminal electrode provided therebetween can be reversed. In addition, there is no mutual interference between the first terminal electrodes, and the flow can be reliably divided.

Further, for example, when the first terminal electrode is provided at the apex corner, the second terminal electrode is provided at the center on the line connecting the pair of first terminal electrodes, so that the second terminal electrode and the pair of first terminal electrodes are provided. The distance from the terminal electrode is the same, the intensity of the current flowing from the first terminal electrode to the second terminal electrode is the same, and the above-described shunt effect can be further improved. In addition, the distance between the terminal electrodes connected to the electrode layer becomes the same, and mounting on another substrate becomes easy.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The capacitor of the present invention can be realized in any of a thin film type and a thick film type such as a chip capacitor, and can be used not only in a single plate type but also in a laminated type. Hereinafter, each type will be described.

Embodiment 1 FIGS. 1 to 4 show a single-plate type thin film capacitor of the present invention, in which two electrode layers 2 and one dielectric layer 3 are alternately formed on an insulating substrate 1. A capacitor body 4 having a square planar shape formed by lamination is formed, and the electrode layer 2 is a first electrode layer 2a and a second electrode layer 2b from below.

As shown in FIG. 2, four first terminal electrodes 5 connected to the first electrode layer 2a and four second terminals connected to the second electrode layer 2b are provided around the capacitor body 4. Electrode 6
Are provided alternately.

The first terminal electrode 5 is provided at the vertex of the capacitor body 4, and the second terminal electrode 6 is provided on a line x connecting the first terminal electrodes 5 on both sides of the second terminal electrode 6. Have been. In FIG. 2, the second terminal electrode 6 is a pair of first terminals.
It is provided at a central position on a line x connecting the terminal electrodes 5.
Here, the capacitor body 4 refers to a portion where the dielectric layer 3 is sandwiched between the first electrode layer 2a and the second electrode layer 2b, that is, a portion that substantially generates a capacitance, and the first terminal electrode 5 and the second The terminal electrode 6 is provided around the capacitor body 4, that is, protrudes outward from the capacitor body 4.

Adjacent first terminal electrode 5 and second terminal electrode 6
Write a distance L ₁ is as short as possible and is preferred, it is desirable that 1.5mm or less in consideration of the substantial outer shape and the element overall inductance of the device. 1.5mm
This is because the larger the size, the higher the inductance of the entire device and the larger the size. On the other hand, in consideration of the easiness of fabrication, it is desirable that the thickness be 0.2 mm or more.

On the insulator substrate 1, as shown in FIG.
A protective layer 7 made of a photocurable resin, SiO ₂ or the like is formed so as to cover the capacitor body 4, the first terminal electrode 5, and the second terminal electrode 6, as shown in FIGS. 3 and 4.
Connected to the first terminal electrode 5 and the second terminal electrode 6, for example, A
Via-hole conductors 8 made of g-Pd, solder, gold or the like are respectively formed inside the protective layer 7, and external terminal electrodes 9 for connecting to another substrate or the like are formed on the upper surfaces of the via-hole conductors 8, respectively. I have. These external terminal electrodes 9 can be formed by a known technique such as solder bumps formed by solder balls or solder paste, screen printing of a paste such as Ag-Pd, Ni-solder plating, or Ni-Sn plating. I just need. Also, via-hole conductor 8
May be formed of the same material in the via hole at the same time when the external terminal electrode 9 is manufactured.

The insulator substrate 1 is selected from alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO ₃ single crystal, surface silicon oxide, glass, quartz, etc., and is not particularly limited.

The material of the electrode layer 2 and the terminal electrodes 5 and 6
Platinum (Pt), gold (Au), silver (Ag), palladium (Pd), low-resistance Cu, Ni, or the like can be suitably used as the material, and is a material having low reactivity with the dielectric layer 3. There is no particular limitation as long as it can be formed by a method such as vacuum evaporation or sputtering.

Further, the material of the dielectric layer 3 may be any material having a high dielectric constant in a high frequency range.
Dielectrics composed of perovskite-type oxide crystals containing Mg and Nb, PZT, PLZT, and BaTi
O ₃ , SrTiO ₃ , Ta ₂ O _5, or a compound obtained by adding or replacing other metal oxides thereto,
There is no particular limitation. In the case of a thin film type, the film thickness should be 0.3 to 30 to ensure high capacity and insulation.
A film thickness of 1.0 μm, particularly 0.4 to 0.8 μm is desirable.

In the capacitor configured as described above,
As shown in FIG. 2, for example, a current is shunted to four first terminal electrodes 5 via the external terminal electrodes 9 and input, and two second terminals on both sides from one first terminal electrode 5. Since it flows to the electrode 6 and hardly flows to the other second terminal electrodes 6,
Also, when the first terminal electrode 5 and the second terminal electrode 6 are provided close to each other, the first terminal electrode 5 and the other first terminal electrode 5 can be connected to the second terminal electrode 5 provided therebetween. Since the direction of the current flowing through the terminal electrodes 6 can be reversed, there is no mutual interference between the first terminal electrodes 5, the current can be shunted reliably, and the effective inductance can be reduced. .

Further, four capacitive elements each including one first terminal electrode 5 and two second terminal electrodes 6 on both sides of the first terminal electrode 5 form a pair of the electrode layer 2 and the dielectric layer 3. And a circuit in which four capacitive elements are connected in parallel, and low impedance characteristics can be exhibited in a wide frequency range by the above-described shunt effect and parallel connection.

By providing the second terminal electrode 6 at the center on the line x connecting the pair of first terminal electrodes 5, the distance L ₁ between the second terminal electrode 6 and the pair of first terminal electrodes 5 is the same. And the intensity of the current flowing from the first terminal electrode 5 to the second terminal electrode 6 becomes the same, so that the above-described shunt effect can be further improved. In this case, since the distance between the terminal electrodes 5 and 6 is equal, the mounting on another substrate becomes easy.

Embodiment 2 FIGS. 5 to 10 show a multilayer chip capacitor type capacitor according to a second embodiment of the present invention. In this capacitor, four electrode layers 10 and three dielectric layers 11 are provided. Capacitor body 12 formed by alternately stacking
Are formed, and a dielectric layer which does not substantially form a capacitance is disposed in an upper region and a lower region of the capacitor body 12. Here, the capacitor body 12 also refers to a portion where the dielectric layer 11 is sandwiched between the electrode layers 10, that is, a portion that substantially generates capacitance. The electrode layers 10 are alternately formed as a first electrode layer 10a or a second electrode layer 10b from below. In this case, the thickness of the dielectric layer 11 is not particularly limited as long as it is formed from several μm to several tens μm. Dielectric layer 1
As the first material, the same material as that of the first embodiment can be applied.

That is, any material having a high dielectric constant in a high frequency region may be used, but a dielectric made of a perovskite-type oxide crystal containing Pb, Mg, and Nb, and other materials such as PZT, PLZT, BaTiO ₃ , and SrTiO ₃ ,
Ta ₂ O ₅ or other metal oxides may be added to these,
It may be a substituted compound and is not particularly limited.

As shown in FIG. 5, a first external terminal electrode 15 connected to the first electrode layer 10a and a second external terminal electrode 16 connected to the second electrode layer 10b are provided on the sides around the capacitor body 12. Are formed. The first and second external terminal electrodes 15 and 16 are respectively formed on one side. That is, four first external terminal electrodes 1 as a whole
It has five and four second external terminal electrodes 16. Also,
Each of the external terminal electrodes 15 and 16 is formed over three surfaces of the front surface, the end surface, and the rear surface of the capacitor body 12, and has a U-shaped cross section as shown in FIGS.

As shown in FIG. 8, the first electrode layer 1
0a, extending to each of the four sides of the capacitor body 12,
Four first electrode lead-out portions (corresponding to the terminal electrodes in FIGS. 1 to 4) 13 connected to the first external terminal electrodes 15 are provided, respectively. On the other hand, as shown in FIG. The layer 10 b is provided with four second electrode lead-out portions (corresponding to the terminal electrodes in FIGS. 1 to 4) 14 extending to each of four sides of the capacitor body 12 and connected to the second external terminal electrodes 16. Have been.

Therefore, when the first electrode lead portions 13 of the first electrode layer 10a and the first electrode lead portions 14 of the second electrode layer 10b are stacked and viewed in plan, the first electrode lead portions 13 ( Second
The second electrode lead-out part 14 located on the same side as the electrode lead-out part 14)
The distance from the first electrode lead-out part 13 is different from the distance from the first electrode lead-out part 13 to the second electrode lead-out part 14 (the first electrode lead-out part 13) adjacent to the first electrode lead-out part 13 (second electrode lead-out part 14). ) are equal to each other and the distance (indicated by L ₂ in the drawing). Therefore,
Regardless of the first electrode layer 10a and the second electrode layer 10b, connecting external terminal electrodes (electrode extraction portions) adjacent to each other with a line forms an octagon in plan view.

The material of the electrode layers 10a and 10b and the material of the first and second electrode lead portions 13 and 14 are platinum (Pt), gold (A
u), silver (Ag), palladium (Pd), low-resistance C
u, Ni and the like can be suitably used, and are not particularly limited as long as they are materials having low reactivity with the dielectric layer 11, and may be formed by a method such as screen printing.

The first and second external terminal electrodes 15, 1
The six materials were prepared by baking silver (Ag) or silver palladium (Ag-Pd) alloy, and then Ni-solder plating, Ni-S
Any material that can be formed by a known technique such as n-plating may be used.

In the capacitor configured as described above,
As shown in FIG. 10, for example, the current supplied to the second electrode layer 10b is divided and input to the electrode lead-out portion 14 via the four second external terminal electrodes 16. The current shunted from one second electrode lead-out part 14 flows toward two adjacent first electrode lead-out parts 13 and hardly flows into the other first electrode lead-out parts 13. For this reason, even when the first electrode lead-out part 13 and the second electrode lead-out part 14 are provided close to each other, the one second electrode lead-out part 14 and the other second electrode lead-out part 14 are located between them. First electrode lead-out part 1 provided
Since the direction of the current flowing to the third electrode 3 can be reversed, there is no mutual interference between the second electrode lead-out portions 14, the current can be shunted reliably, and the effective inductance can be reduced.

Further, one second electrode lead-out portion 14 and two first electrode lead-out portions 1 on both sides of the second electrode lead-out portion 14 are provided.
3 is formed by a pair of electrode layers 10a and 10b and the dielectric layer 11, and is a circuit as if four capacitance elements were connected in parallel. Characteristics can be shown.

The distance between the second external terminal electrode 16 (first external terminal electrode 15) and the adjacent first external terminal electrode 15 (second external terminal electrode 16), that is, the second electrode extraction portion 14
(1st electrode lead-out part 13) and 1st electrode lead-out part 13 next to it
By all the distance L ₂ between the (second electrode lead-out portion 14) are the same, the second electrode lead-out portion 14 becomes the intensity of the current flowing in the first electrode lead-out portion 13 is the same, the distribution effect described above It can be further improved.

Further, in this case, each external terminal electrode 1
Since the distances between 5 and 16 are substantially equal, mounting on another substrate becomes easy.

Embodiment 3 FIGS. 11 to 16 also show a multilayer chip capacitor type capacitor according to a third embodiment of the present invention. The arrangement of the first and second external terminal electrodes is different from that of the second embodiment. different.
In the third embodiment, the first external terminal electrode 25 is provided at the vertex of the capacitor body 22 and the second external terminal electrode 2
6 is a pair of first external terminals adjacent to the second external terminal electrode 26.
It is provided at the center on the line connecting the external terminal electrodes 25.
Therefore, the distance between the second external terminal electrode 26 and the first external terminal electrode 25 adjacent thereto is all equal. And FIG.
As shown in FIG. 4, the first electrode layer 20a has a first electrode lead portion (FIGS. 1 to 4) extending to four apexes of the dielectric layer 21.
23). Further, as shown in FIG. 15, the second electrode layer 20b has a second electrode lead portion 24 (corresponding to the terminal electrode in FIGS. 1 to 4) extending to the center of each side of the dielectric layer 21. ing.

As the material of the electrode layer, the dielectric layer, and the external terminal electrode, the same materials as those used in the second embodiment can be applied.

In the capacitor configured as described above,
As shown in FIG. 16, for example, the second external terminal electrode 26
The current is divided and input to the four second electrode extraction portions 24 in plan view, and flows from one second electrode extraction portion 24 toward two adjacent first electrode extraction portions 23, and the other. Since it hardly flows to the first electrode lead-out part 23, and even when the first electrode lead-out part 23 and the second electrode lead-out part 24 are provided close to each other, one second electrode lead-out part 24 and the other second electrode lead-out part 24 are provided. Since the direction of the current flowing from the two-electrode extraction portion 24 to the first-electrode extraction portion 23 provided therebetween can be made opposite, the mutual interference between the second-electrode extraction portions 24 does not occur. ,
Shunting can be performed reliably, and the effective inductance can be reduced.

Further, a capacitive element comprising one second electrode lead-out portion 24 and two first electrode lead-out portions 23 on both sides of the second external terminal electrode 26 comprises a pair of electrode layers 20a, 20b.
And a dielectric layer 21, as if four capacitance elements were connected in parallel, and low impedance characteristics can be exhibited in a wide frequency range by the above-described shunt effect and parallel connection.

The distance between the second external terminal electrode 26 (first external terminal electrode 25) and the adjacent first external terminal electrode 25 (second external terminal electrode 26), that is, the second electrode lead portion 24
(The first electrode lead-out part 23) and the adjacent first electrode lead-out part 23
(In the figure, the distance L indicated by ₃₎ all the same distance between the (second electrode lead portion 24) by the intensity of the current flowing from the second electrode lead portions 24 in the first electrode lead-out portion 23 is the same , And the above-described branching effect can be further improved.

Moreover, in this case, each external terminal electrode 2
Since the distances between 5 and 26 are equal, mounting on another board becomes easy.

In the present invention, the capacitor bodies 4, 1
The planar shape of 2, 22 is desirably a polygonal shape having the same length on each side. With such a shape, the first external terminal electrodes 5, 15, 25 or the second external terminal electrodes 6, 1
6, 26 and the second external terminal electrodes 6, 16, 26 or the first external terminal electrodes 5, 15, 25 provided on both sides thereof.
The distances L ₁ , L ₂ , and L ₃ are shortest, the current easily flows between them, and the effect of the parallel connection can be sufficiently exhibited.

In the above embodiment, the electrode layers 2, 10, 2
Although 0 is a square shape, that is, the planar shape of the capacitor bodies 4, 12, and 22 is a square, any polygonal shape such as a triangular shape or a pentagonal shape may be used.
In particular, a polygonal shape having four or more sides is desirable.

Fourth Embodiment Next, an example of mounting the multilayer chip capacitor described in the second or third embodiment will be described. FIG. 17 is a half-sectional view showing that the multilayer chip capacitor 30 of the present invention is mounted on the upper surface of the IC package 31 and the entire IC package 31 is mounted on the mounting substrate 32. FIG. 18 is also mounted on the lower surface of the IC package 31. FIG. 5 is a half sectional view showing a state where the IC package 31 is mounted on a mounting board 32. In any case, the connection relationship between the multilayer chip capacitor 30 of the second embodiment and the electrode pads 33 of the mounting substrate 32 or the electrode pads 34 of the IC package 31 is as shown in FIG.

Regardless of the multilayer chip capacitor of the second embodiment or the multilayer chip capacitor of the third embodiment, the first external terminal electrode 15 connected to the first electrode lead portion and the second external terminal connected to the second electrode lead portion are provided. Since the electrodes 16 are regularly arranged, it is not necessary to change the wiring of the CPU chip itself, the wiring between the CPU chip and the mounting board, and the wiring of the mounting board itself. Therefore, it is not necessary to provide useless wirings and lands. As a result, the influence of inductance due to the wiring between the CPU chip and the capacitor can be reduced as compared with the conventional structure in which the multilayer chip capacitor is mounted on the mounting board separately from the IC package. Also, CP
Since the capacitor is arranged near the U chip, the efficiency as a decoupling capacitor can be improved.

[0064]

EXAMPLE 1 This is an example in which the capacitor of Embodiment 1 was manufactured and its performance was evaluated. Each electrode layer was formed using a high-frequency magnetron sputtering method. First, Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation. At the time of sputtering, the substrate holder is moved to the target position of the material type to form a film.
The distance between targets was fixed at 60 mm.

Next, a high frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high frequency power supply, and a high density magnetic field is generated near the target by a magnetron magnetic field formed by a permanent magnet installed on the back of the target. The target surface was sputtered by generating plasma.

In this embodiment, plasma is generated by applying only to the target closest to the substrate. The substrate holder had a heating mechanism using a heater, and was controlled so that the substrate temperature during sputter deposition was constant. Further, a metal mask having a thickness of 0.1 mm is provided on the target side of the substrate placed on the substrate holder, so that a required mask can be set on the substrate deposition surface according to the deposition pattern.

All the dielectric layers were formed by a sol-gel method.
Also, Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2, and refluxed in 1,3-propanediol (about 12%).
(At 4 ° C. for 6 hours), and a MgNb composite alkoxide solution (Mg = 5.0 mmol, Nb 10.0 mmol, 1,
3-propanediol (140 mmol) was synthesized.

Next, 15 mmol of lead acetate (trihydrate) was added to the MgNb composite alkoxide solution and dissolved at 60 ° C., and a Pb (Mg _1/3 Nb _2/3 ) O ₃ (PMN) precursor solution was added. Synthesized.

Then, a 0.3 μm thick first electrode layer 2 a made of Au is formed on a 0.25 mm thick alumina substrate.
Was formed, and the (PMN) precursor solution was applied by a spin coater, dried, and then heat-treated at about 400 ° C. for 1 minute to prepare a gel film.

After repeating the operation of applying and heat-treating the (PMN) precursor solution, baking is performed at about 800 ° C. for 2 minutes (in the air) to form a 0.7 μm-thick PMN thin film to become the dielectric layer 3. Obtained. From the X-ray diffraction result of the obtained thin film, the perovskite generation rate was calculated to be about 95%. afterwards,
The patterning of the dielectric film was performed by a photoresist process.

A second electrode layer 2b made of Au was sputter-deposited on the surface of the dielectric film. Then, by changing the size of the first electrode layer pattern and the second electrode layer pattern, a sample in which the distance L ₁ between the first external terminal electrode 5 and the second external terminal electrode 6 was changed as shown in Table 1 was obtained. Produced. Thereafter, a protective film having via holes is formed using a photocurable resin, and after solder paste is screen-printed in the via holes, eight solder bumps having a diameter of 0.1 mm are formed together with the via hole conductors by reflow processing. Thus, a single-plate type thin film capacitor as shown in FIGS. 1 to 4 was obtained. Table 1 shows the area of the capacitor body, that is, the area of the electrode layer.
Shown in

The impedance characteristics of the manufactured thin film capacitor at 1 MHz to 1.8 GHz were measured using an impedance analyzer (HP429 manufactured by Hewlett-Packard Company).
1A) and the results of measurement using a microwave probe (manufactured by Pico Probe) are shown in Table 1. The capacitance in Table 1 is a value of 1 MHz, and the inductance L is L = 1 /
This is a value calculated from [(2πf ₀ ) ² × C].

[0073]

[Table 1]

From Table 1, the first external terminal electrode 5 and the second
As the distance L ₁ between the external terminal electrode 6 is small, it can be seen that the inductance is small. FIG. 20 shows the distance L ₁ between the terminal electrodes.
= 0.65 mm sample No. 3 shows the impedance characteristic of FIG. It can be seen that the graph shows low impedance characteristics in a wider frequency range than FIG.

Example 2 In this example, the capacitor of Embodiment 3 was manufactured and its performance was evaluated.

First, a green sheet having a thickness of 10 μm was formed by a doctor blade method using a slip containing barium titanate as a main component and a sintering aid, a solvent, a dispersant, and a binder.

On the other hand, a commercially available Ag-Pd
A paste was prepared, and a conductor film to be the first electrode layer 20a was formed on the green sheet by a screen printing method.
Next, a conductor film to be the second electrode layer 20b was formed on another green sheet by a screen printing method. Next, a green sheet on which a conductor film to be the first electrode layer 20a is formed and a green sheet on which a conductor film to be the second electrode layer 20b are formed are alternately laminated to a total of 24 layers, and finally the electrode layer is printed. The green sheets not subjected to the lamination were laminated and thermocompressed to obtain a molded body. At this time, by changing the size of the electrode pattern, the distance between the first external terminal electrode 25 and the second external terminal electrode 26 after firing (actually, the distance between the center points of the lead portions of the electrodes) is shown in Table 2. It was set to be the distance L _3.

After cutting the obtained molded body to expose the end portions of the first electrode lead-out portion 23 and the second electrode lead-out portion 24, the molded body was fired in air at a temperature of 1250 ° C. for 2 hours. A capacitor body as shown in FIGS. 11 to 16 was produced except that the number of dielectric layers and the number of dielectric layers were different.

Thereafter, the capacitor body 2 including the portions where the end portions of the first electrode lead portion 23 and the second electrode lead portion 24 are exposed.
Ag over the front, end and back of the side or top of Ag
After applying and drying a conductive paste made of Pd, 8
Baking was performed at 00 ° C., and a plating coating layer was formed on the baked thick film conductor by Ni-solder plating.
The first and second external terminal electrodes 25 and 26 as shown in FIG. 1 were formed to obtain a multilayer chip capacitor. Table 2 shows the area of the capacitor body, that is, the area of the electrode layer.

From 1 MHz to 1.8 of the manufactured capacitor
Impedance characteristics at GHz are measured with an impedance analyzer (HP4291A manufactured by Hewlett-Packard)
Table 2 shows the results obtained by using the above and a microwave probe (manufactured by Pico Probe). In Table 2, the capacitance is a value of 1 MHz, and the inductance L is L = 1 / [(2π
f ₀ ) ² × C].

[0081]

[Table 2]

From Table 2, it can be seen that the smaller the distance L ₃ between the first external terminal electrode 25 and the second external terminal electrode 26, the smaller the inductance. FIG. 21 shows a sample No. with a terminal electrode distance L ₃ = 1.4 mm. 13 illustrates impedance characteristics of the multilayer chip capacitor of No. 13.

From FIG. 21, it can be seen that low impedance characteristics are exhibited in a wide frequency range.

[0084]

As described in detail above, according to the present invention, for example, a current is divided and input to a plurality of, for example, four first terminal electrodes (first electrode extraction portions), and one first From the terminal electrode (first electrode lead-out part), the first terminal electrode (first electrode
In order to flow to the second terminal electrodes (second electrode extraction parts) on both sides closest to the electrode extraction parts, the current is surely divided in at least two directions or more from one first terminal electrode (first electrode extraction part). Circuit in which a plurality of capacitive elements composed of one first terminal electrode (first electrode lead portion) and adjacent two second terminal electrodes (second electrode lead portions) can be reduced in parallel with each other Thus, low impedance characteristics can be exhibited in a wide frequency range by the shunt effect and the parallel connection.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of a thin film capacitor according to Embodiment 1 of the present invention.

FIG. 2 is a plan view of FIG. 1 from which a protective layer is omitted.

FIG. 3 is a sectional view taken along the line x in FIG. 2;

FIG. 4 is a partial perspective view of FIG. 1 from which a protective layer is omitted.

FIG. 5 is an external perspective view of a multilayer chip capacitor according to Embodiment 2 of the present invention.

FIG. 6 is a sectional view of the capacitor body taken along line AA of FIG. 5;

FIG. 7 is a sectional view of the capacitor body taken along line BB of FIG. 5;

FIG. 8 is a plan view showing a first electrode layer of the second embodiment.

FIG. 9 is a plan view showing a second electrode layer according to the second embodiment.

FIG. 10 is a diagram illustrating a flow of a current input to the capacitor according to the second embodiment as viewed from above a capacitor main body.

FIG. 11 is an external perspective view of a multilayer chip capacitor according to Embodiment 3 of the present invention.

FIG. 12 is a cross-sectional view of the capacitor body taken along line AA of FIG. 11;

FIG. 13 is a sectional view of the capacitor body taken along line BB of FIG. 11;

FIG. 14 is a plan view showing a first electrode layer of the third embodiment.

FIG. 15 is a plan view showing a second electrode layer according to the third embodiment.

FIG. 16 is a diagram illustrating a flow of a current input to the capacitor according to the third embodiment as viewed from above a capacitor body.

FIG. 17 is a partial cross-sectional view showing a state in which the multilayer chip capacitor according to the second or third embodiment is mounted in an IC package.

FIG. 18 is a partial cross-sectional view showing a state in which the multilayer chip capacitor of the second or third embodiment is mounted in another IC package.

FIG. 19 is a plan view showing a state in which the multilayer chip capacitor of Embodiment 2 is connected to a mounting board.

FIG. 20 shows impedance characteristics of the thin film capacitor of FIG.

FIG. 21 shows impedance characteristics of the multilayer chip capacitor of FIG. 11;

[Description of Signs] 1 ... Insulator substrate 2a, 10a, 20a ... First electrode layer 2b, 10b, 20b ... Second electrode layer 3, 11, 21 ... Dielectric layer 4, 12 , 22 ... capacitor body 5 ... first terminal electrode 6 ... second terminal electrode 13, 23 ... first electrode lead-out part 14, 24 ... second electrode lead-out part 9 ... external terminal Electrodes 15, 25: First external terminal electrode 16, 26: Second external terminal electrode 30: Multilayer chip capacitor 31: IC package 32: Mounting substrate 33, 34: Electrode pad

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Claims (4)

[Claims] 1. A plurality of first electrode layers connected to the first electrode layer around a polygonal capacitor body in which first electrode layers and second electrode layers are alternately stacked with a dielectric layer interposed therebetween. A capacitor, wherein terminal electrodes and a plurality of second terminal electrodes connected to the second electrode layer are alternately formed. 2. The method according to claim 1, wherein one of the first and second terminal electrodes is provided at a vertex of the capacitor body, and the other terminal electrode is provided on a line connecting the pair of one terminal electrodes. Item 7. The capacitor according to Item 1. 3. A first terminal electrode or a second terminal electrode being misaligned at a vertex of a capacitor body, one terminal electrode being provided at the vertex, and the other terminal electrode being positioned at the center of a line connecting a pair of one terminal electrodes. The capacitor according to claim 1 or 2, wherein 4. The capacitor according to claim 1, wherein the first terminal electrode and the second terminal electrode are provided side by side on the capacitor body.