JP2000182878A - Capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor having a structure with large capacitance and low inductance that can function as a decoupling capacitor over a wide frequency region. SOLUTION: In a capacitor, wherein a dielectric layer 5 and an upper-side electrode layer 7 are successively laminated on a lower-side electrode layer 3 of an insulating substrate 1, the upper-side electrode layer 7 and the dielectric layer 5 are divided into a plurality of portions by a dividing groove 9, formed in the laminating direction so that a plurality of divided upper-side electrode layers 7a, 7b and a plurality of divided dielectric layers 5a, 5b are formed. The lower-side electrode layer 3 is exposed at the bottom of the dividing groove 9, and a first terminal electrode 11 is formed on the lower-side electrode layer 3 at the bottom of the dividing groove 9. Second terminal electrodes 17, 19 are formed on the divided upper-side electrode layers 7a, 7b, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a capacitor,
For example, the present invention relates to a large-capacity, low-inductance capacitor that is provided in an electric circuit that operates at high speed and that is used for bypassing high-frequency noise or preventing fluctuations in power supply voltage.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been an increasing demand for electronic components installed in electronic devices to be smaller, thinner, and compatible with high frequencies.

Particularly, in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is 400 MHz to 1 GHz, and the clock frequency of the bus between chips is also 75 MHz to 100 MHz even at the personal computer level. The speedup is remarkable.

[0004] On the other hand, problems associated with high-speed operation of IC circuits are more serious problems than miniaturization of each element. Of these, in the function of removing high-frequency noise, which is the role of the capacitor, it is particularly important that the instantaneous drop of the power supply voltage that occurs when simultaneous switching of the logic circuits occurs at the same time is the energy stored in the capacitor. This is a function of reducing by supplying instantaneously, and is a so-called decoupling capacitor.

[0005] The performance required of this decoupling capacitor lies in how quickly the current can be supplied in response to a current fluctuation in the load section faster than the clock frequency.
Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.

In order to function reliably in this frequency range, the impedance of the decoupling capacitor element itself must be reduced even in a high-frequency range, and the decoupling capacitor element must be capable of instantly supplying the stored charge as a necessary current. Very important.

In order to minimize the impedance of the capacitor element in a required frequency range, the capacitance element of the capacitor element itself is increased and the resistance component and the inductance component are reduced, or the equivalent series inductance ES is reduced.
Resonance frequency f ₀ = １ ／ determined by L and capacitance C
The capacitance may be reduced so that π (ESL · C) ^1/2 is adjusted to the required frequency.

In the former method, first, regarding the capacitance,
As described above, it is most effective to reduce the thickness of the dielectric layer held between the electrodes. The resistance component is determined by the dielectric loss of the dielectric and the resistance of the electrode portion, and the resistance of the electrode portion can be considered to be substantially constant except for the skin effect which becomes significant at several GHz or more.

There are the following three methods for reducing the inductance. The first method is to minimize the length of the current path, the second method is to make the current path a loop structure and the loop cross-sectional area is minimized, and the third method is to set the current path to n.
In this method, the effective inductance is reduced to 1 / n. These three methods are described in JP-A-60-947.
No. 16, JP-B-62-2449, JP-A-4-
It is disclosed in, for example, Japanese Patent Publication No. 211191.

However, in the multilayer chip capacitor, since the direction of the current is the same, the magnetic field formed by each electrode current is superimposed. That is, since the mutual inductance becomes large, the effective total inductance cannot be sufficiently reduced.

Although attempts have been made to reduce the impedance of the capacitor element by reducing the inductance of the capacitor element, the usable region is only around a resonance frequency determined by the capacitance and inductance of the capacitor. If the capacitor is used with a reduced capacity in a frequency range higher than this, the capacitor element functions only in the range of the resonance frequency ± several tens of MHz.

As a method of overcoming the fact that the impedance drops only near the resonance frequency and realizing a capacitor element that functions with low impedance in a wide frequency range, means for connecting capacitor elements having different capacities in parallel has been considered. .

For example, as disclosed in JP-A-6-77083, there is an attempt to obtain a capacitor having a large capacity and excellent high-frequency characteristics by arranging a plurality of dielectric materials having different relative dielectric constants in parallel. .

In a multilayer ceramic capacitor, as described in JP-A-8-162368,
By changing the electrode area and the dielectric layer thickness in one chip capacitor, two capacitors having different capacities are connected in parallel, and an attempt has been made to realize a noise absorbing function in a wide frequency range with a single component. . With this capacitor, a low impedance can be obtained at the resonance point of two capacitor elements having different capacities.

Japanese Patent Application Laid-Open No. 9-246098 also discloses that noise can be absorbed in a wide frequency range by forming electrodes of each layer so that each capacitance is different and connecting each stage in parallel via an inductor element. Attempts have been made to develop functions.

[0016]

However, in the thin-film capacitor disclosed in Japanese Patent Application Laid-Open No. 6-77083, even if a capacitor having an internal structure is divided in a plane while the external terminal electrodes of the capacitor element remain as a pair, the equivalent is obtained. Since the circuit is not different from a single capacitor element, it is considered that only the parallel effect of the dielectric properties of the materials is used and the effect on the equivalent circuit is not exhibited.

The parallel capacitor disclosed in Japanese Patent Application Laid-Open No. 8-162368 is a parallel circuit on an equivalent circuit. However, if the self-inductance of two capacitor elements in a chip is large, a great effect of the parallel connection can be obtained. Can not. Further, in this structure, current flows in the same direction in the two capacitor elements themselves, so that the mutual inductance between the two capacitors increases, and the effect of parallel connection cannot be expected.

Further, in a capacitor in which an inductor element is inserted between the parallel capacitors disclosed in Japanese Patent Application Laid-Open No. 9-246098, the inductance of the entire element increases, which goes against lower impedance. An even more important problem is that there is a local maximum point of impedance due to parallel resonance between each resonance point. Unless this parallel resonance is suppressed, the impedance cannot be reduced in a wide frequency range of 100 MHz or more.

The present invention solves the above-mentioned conventional problems,
An object is to provide a capacitor having a large capacity and a low inductance structure, which can function as a decoupling capacitor as a capacitor in a wide frequency range.

[0020]

According to the present invention, there is provided a capacitor comprising:
In a capacitor in which a dielectric layer and an upper electrode layer are sequentially laminated on a lower electrode layer formed on an insulating substrate, the upper electrode layer and the dielectric layer are divided into a plurality of parts by division grooves formed in the laminating direction. Forming a plurality of divided upper electrode layers and a plurality of divided dielectric layers, exposing the lower electrode layer on the bottom surface of the dividing groove, and forming a first terminal on the lower electrode layer on the bottom surface of the dividing groove. An electrode is formed, and a second terminal electrode is formed on each of the divided upper electrode layers. Here, the upper electrode layer is divided into two, and two rectangular divided upper electrode layers are formed. Assuming that the length of the divided upper electrode layer along the dividing groove is L and the width is W, L / L It is desirable to satisfy W ≧ 2.

Further, the capacitor according to the present invention has a structure in which dielectric layers and electrode layers are alternately laminated on a lower electrode layer formed on an insulating substrate, and the electrode layers are alternately arranged evenly from the lower side. In a capacitor that is a layer or an odd electrode layer, the even electrode layer, the odd electrode layer, and the dielectric layer,
A plurality of divided even-numbered electrode layers, a plurality of divided odd-numbered electrode layers, and a plurality of divided dielectric layers are formed by dividing into a plurality of divided grooves formed in the stacking direction, and the lower electrode is formed on the bottom surface of the divided groove. Exposing the layer, connecting the divided odd-numbered electrode layer to the lower electrode layer via an extending portion along the dividing groove, and connecting the divided even-numbered electrode layers to each other,
A first terminal electrode is formed on the extended portion on the bottom surface of the division groove, and a second terminal electrode is formed on each of the uppermost divided even-numbered electrode layers.

[0022]

In the capacitor according to the present invention, first, a current input from the first terminal electrode via the lower electrode layer flows to the divided upper electrode layer (divided even electrode layer, divided odd electrode layer). Therefore, the current is reliably divided in two or more directions without being affected by the mutual inductance, and the effect of the parallel connection appears on the equivalent circuit, so that the effective inductance can be reduced.

The upper electrode layer is divided into two, and two rectangular upper electrode layers are formed. If the length and width of the divided upper electrode layer along the dividing groove are L and W, respectively, /
By satisfying W ≧ 2, the input current shunted in two directions is further shunted by the divided upper electrode layer having an L / W ratio of 2 or more, and the effective inductance of the entire device can be greatly reduced. .

By making full use of the parallel connection and the shunt effect, low impedance characteristics can be exhibited in a wide frequency range.

[0025]

FIG. 1 is a schematic view of a capacitor according to the present invention. In this capacitor, a lower electrode layer 3 is formed on an insulating substrate 1, and a dielectric layer is formed on the lower electrode layer 3. The body layer 5 and the upper electrode layer 7 are sequentially laminated.

The upper electrode layer 7 and the dielectric layer 5
Are divided into two by a dividing groove 9 formed in the laminating direction, and two rectangular divided upper electrode layers 7a, 7b and two divided dielectric layers 5a, 5b are formed. The lower electrode layer 3 is exposed.

On the lower electrode layer 3 on the bottom surface of the dividing groove 9, five first terminal electrodes 11 are formed at a predetermined interval, and the upper electrode layers 7a and 7b are respectively provided with electrode lead portions. 13 and 15 are formed, and these electrode extraction portions 13 and 15 are formed.
The second terminal electrodes 17 and 19 are formed on the reference numeral 15 respectively. The five first terminal electrodes 11 and the five second terminal electrodes 17, 19 are formed to face each other with the divided dielectric layers 5a, 5b interposed therebetween.

The first terminal electrode 11, the second terminal electrodes 17, 19 are connected to the electrodes formed on the substrate, and the capacitor of the present invention is mounted on the substrate.

Assuming that the length of the side of the divided upper electrode layers 7a and 7b along the dividing groove 9 is L and the width orthogonal to the side is W, L / W ≧ 2 is satisfied.

The first terminal electrode 11 and the second terminal electrode 1
In order to ensure insulation between the capacitors 7 and 19, it is desirable to form an insulating protective film on the upper surface of the manufactured capacitor. In this case, first, before forming the first terminal electrode 11 and the second terminal electrodes 17, 19, these terminal electrodes 1
A mask is applied in advance so that a protective film is not formed at the formation positions of 1, 17, and 19, and after forming the protective film, the terminal electrodes 11, 17, and 19 are formed.

The width B of the dividing groove 9 is set to be equal to the first terminal electrode 1.
The first and second terminal electrodes 17, 19 need not be electrically connected, and are not particularly limited. If the width B of the dividing groove 9 is too large, the distance between the first terminal electrode 11 and the second terminal electrodes 17, 19, In addition, since the external dimensions of the capacitor increase and the total inductance increases, the width B of the dividing groove 9 is preferably 0.2 mm or less.

Further, the insulating substrate 1 is selected from alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO ₃ single crystal, surface oxide silicon, glass, quartz, etc., and is not particularly limited.

As a material for the electrode layer, platinum (P
t), gold (Au), silver (Ag), palladium (Pd),
The material is not particularly limited as long as it is a material that has low reactivity with the dielectric layer, such as low resistance Cu, Ni, or the like, and may be any material that can be formed by a method such as screen printing or sputtering.

The first terminal electrode 11 and the second terminal electrode 1
Reference numerals 7 and 19 may be any as long as they can be formed by a known technique such as screen printing of a solder bump formed of a solder ball or a solder paste or a paste of Ag-Pd, Ni-solder plating, or Ni-Sn plating.

The material of the dielectric layer may be any material having a high dielectric constant in a high frequency range.
g, Nb-containing perovskite-type oxide crystals, and PZT, PLZT, BaTiO ₃ ,
SrTiO ₃ , Ta ₂ O _5, or a compound obtained by adding or substituting another metal to these may be used, and is not particularly limited. In the case of a thin film type, the film thickness is desirably 0.3 to 1.0 μm, particularly 0.4 to 0.8 μm in order to ensure high capacity and insulation.

In the capacitor configured as described above,
First, the current input from the first terminal electrode 11 via the lower electrode layer 3 flows through the divided upper electrode layers 7a and 7b, as shown in FIG. In addition to the fact that the current is shunted in two directions without receiving the influence, the effect of the parallel connection appears on the equivalent circuit, and the effective inductance can be reduced.

The divided upper electrode layer 7 along the dividing groove 9
Assuming that the length of a and 7b is L and the width is W, L / W ≧ 2 is satisfied, so that the current input to the first terminal electrode 11 largely diverges in the divided upper electrode layers 7a and 7b. And the overall effective inductance can be greatly reduced.

[0038] A capacitor exhibiting low impedance characteristics in a wide frequency range can be obtained by sufficiently exhibiting the parallel connection and the shunt effect.

In the above example, an example in which the upper electrode layer 7 and the dielectric layer 5 are divided into two by the dividing groove 9 has been described, but it is needless to say that the upper electrode layer 7 and the dielectric layer 5 may be divided into three or more.

FIG. 2 is a schematic view of a multilayer capacitor according to the present invention. In this capacitor, a dielectric layer 39 and an electrode layer are formed on a lower electrode layer 38 formed on an insulating substrate 37. The electrode layers are alternately laminated, and the electrode layers are alternately formed as even-numbered electrode layers 41 or odd-numbered electrode layers 43 from below.

The even-numbered electrode layer 41, the odd-numbered electrode layer 43, and the dielectric layer 39 are divided into two by a dividing groove 45 formed in the laminating direction, and the two divided even-numbered electrode layers 41a, 41
b, two divided odd-numbered electrode layers 43a and 43b and two divided dielectric layers 39a and 39b are formed, and the divided groove 45 is formed.
The lower electrode layer 38 is exposed at the bottom surface of the substrate.

An extended portion 49 along the dividing groove 45 is connected to the divided odd-numbered electrode layers 43a and 43b.
The divided odd-numbered electrode layers 43 a and 43 b are connected to the lower electrode layer 38 by the extending portions 49. The extension 49 can be formed simultaneously with the production of the divided odd-numbered electrode layers 43a and 43b. The first terminal electrode 51 is formed on the extension 49.

The divided even-numbered electrode layers 41a and 41b are connected to each other by electrode lead portions 52 and 53, and the second terminal electrode 5 is provided on the uppermost divided even-numbered electrode layers 41a and 41b.
4, 55 are formed.

In this capacitor, the first terminal electrode 51,
Except for the positions where the second terminal electrodes 54 and 55 are formed, an insulating protective film 57 is formed on the upper surface, and the first terminal electrode 51 and the second terminal electrode 54 are formed in the holes formed in the protective film 57. , 55 are formed. The first terminal electrode 51
Is filled with a conductor in the hole formed in the protective film 57 and is connected to the lower electrode layer 38 by the conductor.

Also, in this capacitor, the divided electrode layers 41a, 41b,
Assuming that the length of 3a and 43b is L and the width is W, L / W ≧ 2
Are satisfied.

The same effect as in the above example can be obtained with the multilayer capacitor having the above-described structure, but the capacitance can be further increased with this capacitor.

[0047]

EXAMPLE Each electrode layer was formed by using a high-frequency magnetron sputtering method. First, Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation. At the time of sputtering, the substrate holder was moved to the target position of the kind of the material to be formed, and the distance between the substrate and the target was fixed at 60 mm.

Next, a high-frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high-frequency power source, and a high-density magnet is formed near the target by a magnetron magnetic field formed by a permanent magnet provided on the back of the target. The target surface was sputtered by generating plasma.

In this embodiment, plasma is generated by applying only to the target closest to the substrate. The substrate holder had a heating mechanism using a heater, and was controlled so that the substrate temperature during sputter deposition was constant. Further, a metal mask having a thickness of 0.1 mm is provided on the target side of the substrate placed on the substrate holder, so that a required mask can be set on the substrate deposition surface according to the deposition pattern.

All the dielectric layers were formed by a sol-gel method.
That is, Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2 and refluxed in 1,3-propanediol (about 12 times).
(At 4 ° C. for 6 hours) to obtain a MgNb composite alkoxide solution (Mg = 5.0 mmol, Nb = 10.0 mmol,
1,3-propanediol 100 mmol) was synthesized. Next, 15 mmol of lead acetate (trihydrate) was added to the MgNb composite alkoxide solution and dissolved at 60 ° C. to synthesize a Pb (Mg _1/3 Nb _2/3 ) O ₃ (PMN) precursor solution.

Then, the lower electrode layer shown in FIG.
0.3 μm by a mask pattern of m × 1.0 mm)
On a 0.25 mm thick alumina substrate on which a thick Au electrode is formed, the coating solution is applied by a spin coater, dried, and then heat-treated at about 400 ° C. for 1 minute,
A gel film was prepared.

After the operation of coating and heat treatment of the coating solution was repeated, baking was performed at about 800 ° C. for 2 minutes (in air) to obtain a 0.7 μm-thick PMN thin film. The perovskite generation rate was calculated to be about 95% from the X-ray diffraction results of the obtained thin films. After that, the dielectric film was patterned by a photoresist process.

An Au electrode was sputter-deposited on the surface of the dielectric layer using the mask pattern of the upper electrode layer shown in FIG.
The distance between the divided upper electrode layers is 0.2 mm, and the area of each divided upper electrode layer is 1.0 mm × 0.35 mm.
The W ratio was 2.85.

Also, samples having different L / W ratios were prepared in the same manner. After the formation of each element, a protective film having a via hole is formed using a photosensitive resin, a solder paste is printed in the via hole by screen printing of a solder paste, and a diameter of 0.1 m is formed by a reflow process.
m solder bumps were formed, and a first terminal electrode and a second terminal electrode (inter-terminal distance: 0.6 mm) were formed to obtain a thin film capacitor as shown in FIG.

The impedance characteristics of the manufactured thin film capacitor at 1 MHz to 1.8 GHz were measured using an impedance analyzer (HP429 manufactured by Hewlett-Packard Company).
1A) and a microwave probe (manufactured by Pico Probe) to measure capacitance and inductance. Table 1 shows the results.

[0056]

[Table 1]

As can be seen from Table 1, when the L / W ratio is 2 or more, the capacitance is large and the inductance is small. FIG. 3 shows the impedance characteristics of Sample No. 1 in Table 1. It can be seen that this sample has low impedance characteristics over a wide frequency range.

In Table 1, the capacitance is a value of 1 MHz, and the inductance is a value calculated from L = 1 / (2πfo) ² × C.

[0059]

According to the capacitor of the present invention, the current input from the lower electrode layer flows into the upper electrode layer divided into two or more parts, so that it is ensured in two or more directions without being affected by mutual inductance. And the effect of parallel connection appears on the equivalent circuit, and the effective inductance can be reduced. Further, the input current shunted in two directions is further shunted on the divided upper electrode layer having an L / W ratio of 2 or more, so that the effective inductance of the entire device can be significantly reduced. By sufficiently exhibiting the parallel connection and the shunt effect, low impedance characteristics can be exhibited in a wide frequency range.

[Brief description of the drawings]

1A and 1B show a capacitor according to the present invention, wherein FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line AA of FIG.

FIG. 2 is a cross-sectional view of the multilayer capacitor of the present invention.

FIG. 3 is a diagram showing impedance characteristics of a thin film capacitor of Sample No. 1;

[Explanation of symbols]

 1, 37: insulating substrate 3, 38: lower electrode layer 5, 39: dielectric layer 5a, 5b, 39a, 39b: divided dielectric layer 7: upper electrode layer 7a, 7b ... divided upper electrode layer 9, 45 ... divided groove 11, 51 ... first terminal electrode 17, 19, 54, 55 ... second terminal electrode 41a, 41b ... divided even electrode layer 43a, 43b: divided odd-numbered electrode layer 49: extended portion

Claims (3)

[Claims] 1. A capacitor in which a dielectric layer and an upper electrode layer are sequentially stacked on a lower electrode layer formed on an insulating substrate, wherein the upper electrode layer and the dielectric layer are divided in a stacking direction. A plurality of divided upper electrode layers, a plurality of divided dielectric layers are formed by dividing into a plurality of grooves, and the lower electrode layer is exposed on the bottom of the divided groove, and the lower electrode layer on the bottom of the divided groove is formed. A capacitor comprising: a first terminal electrode formed thereon; and a second terminal electrode formed on each of the divided upper electrode layers. 2. An upper electrode layer is divided into two, and two rectangular upper electrode layers are formed. When the length of the upper electrode layer along the dividing groove is L and the width is W, L / W
2. The capacitor according to claim 1, wherein satisfies ≧ 2. 3. A dielectric layer and an electrode layer are alternately laminated on a lower electrode layer formed on an insulating substrate, and said electrode layer is alternately formed with an even electrode layer or an odd electrode layer from the lower side. In the capacitor, the even electrode layer, the odd electrode layer,
And dividing the dielectric layer into a plurality of divisions by division grooves formed in the stacking direction to form a plurality of divided even-numbered electrode layers, a plurality of divided odd-numbered electrode layers, and a plurality of divided dielectric layers. Exposing the lower electrode layer on the groove bottom surface, connecting the divided odd-numbered electrode layer to the lower electrode layer via an extending portion along the division groove, and connecting the divided even-numbered electrode layers to each other, Further, a first terminal electrode is formed on the extending portion on the bottom surface of the division groove, and a second terminal electrode is formed on each of the uppermost divided even electrode layers.