JP3692258B2 - Capacitor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor, for example, a large-capacity, low-inductance capacitor that is disposed in an electric circuit that operates at high speed and is used for bypassing high-frequency noise or for preventing fluctuations in power supply voltage.
[0002]
[Prior art]
In recent years, with the downsizing and high functionality of electronic devices, there are increasing demands for downsizing, thinning, and high frequency compatibility for electronic components installed in electronic devices.
[0003]
Particularly in a high-speed digital circuit of a computer that needs to process a large amount of information at high speed, the clock frequency in the CPU chip is 400 MHz to 1 GHz and the clock frequency of the inter-chip bus is 75 MHz to 100 MHz even at the personal computer level. It is remarkable. As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to reduce power consumption. As these IC circuits increase in speed, density, and voltage, passive components such as capacitors are required to exhibit excellent characteristics with respect to high-frequency or high-speed pulses in conjunction with downsizing and large capacity. .
[0004]
In order to make a capacitor small and high capacity, it is most effective to make the dielectric sandwiched between the pair of electrodes thin and thin. Thinning is also compatible with the above-mentioned tendency of voltage reduction.
[0005]
On the other hand, various problems associated with high-speed operation of the IC circuit are more serious than miniaturization of each element. Of these, the high-frequency noise removal function, which is the role of the capacitor, is particularly important in that the energy stored in the capacitor is instantaneously reduced due to the instantaneous drop in power supply voltage that occurs when simultaneous switching of logic circuits occurs simultaneously. This is a function that is reduced by supplying to the so-called decoupling capacitor.
[0006]
The performance required for this decoupling capacitor is how quickly a current can be supplied with respect to the current fluctuation of the load part faster than the clock frequency. Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.
[0007]
However, an actual capacitor element has a resistance component and an inductance component in addition to a capacitance component. The impedance of the capacitive component decreases with increasing frequency, and the inductance component increases with increasing frequency.
[0008]
For this reason, as the operating frequency increases, the inductance of the element limits the transient current to be supplied, causing an instantaneous drop in the power supply voltage on the logic circuit side or new voltage noise. As a result, an error on the logic circuit is caused. Particularly in recent LSIs, the power supply voltage is lowered to suppress the increase in power consumption due to the increase in the total number of elements, and the allowable fluctuation range of the power supply voltage is also reduced. Therefore, in order to minimize the voltage fluctuation range during high-speed operation, the impedance of the decoupling capacitor element itself can be reduced even in the high frequency region, and the stored charge can be instantaneously supplied as necessary current. Very important.
[0009]
Impedance reduction guidelines are described in AJ Rainal, "Computing Inductive Noise of CMOS Drivers", IEEE Trans. Comp., Packag., Manufact. Technol.-Part B, Vol. 19, pp. 789-802 (1996). As shown, the current change per driver is 40 mA / ns. If the power supply voltage is 1.8V, the allowable range of voltage fluctuation is 10%, 0.18V, and the number of off-chip drivers is 64, the upper limit of inductance is 0.14nH, and the impedance at 1GHz is about 0.4Ω or less. And shall be.
[0010]
In order to minimize the impedance of the capacitor in the necessary frequency range, the capacitance component of the capacitor itself is increased, the resistance component and the inductance component are decreased, or determined by the equivalent series inductance ESL and the capacitance C. The resonance frequency f ₀ = 1 / 2π (ESL · C) _1/2 may be lowered so as to match the required frequency.
[0011]
The former method is most effective for reducing the thickness of the dielectric layer sandwiched between the electrodes as described above with respect to the capacitance. The resistance component is determined by the dielectric loss of the dielectric and the resistance of the electrode portion. The resistance of the electrode portion may be considered to be a substantially constant value except for the skin effect that becomes prominent at several GHz or more.
[0012]
There are the following three methods for reducing the inductance. The first method is a method of minimizing the length of the current path, the second is a method of making the current path a loop structure and minimizing the loop cross-sectional area, and the third is an effective inductance by distributing the current path into n pieces. Is 1 / n.
[0013]
In this way, attempts have been made to reduce the impedance of the capacitor element by reducing the inductance of the capacitor element, but the area where the impedance is 0.4Ω or less can be used only near the resonance frequency determined by the capacitance and inductance of the capacitor. is there. When the capacitor is used in a frequency range lower than this, the capacitor functions only in the region near the resonance frequency.
[0014]
As a method of overcoming the point that the impedance is reduced only near the resonance frequency and realizing a capacitor that functions with a low impedance in a wide frequency range, means for connecting capacitors having different capacities in parallel has been considered. For example, as disclosed in JP-A-6-77083, there is an attempt to obtain a capacitor having a large capacity and excellent high frequency characteristics by arranging a plurality of dielectric materials having different relative dielectric constants in parallel.
[0015]
In the multilayer ceramic capacitor, as described in JP-A-8-162368, two capacitors having different capacities are connected in parallel by changing the electrode area and the dielectric layer thickness in one chip capacitor. Attempts have been made to develop a noise absorbing function in a wide frequency range with a single component. A low impedance can be achieved at the resonance point of two capacitor elements having different capacities.
[0016]
Japanese Patent Laid-Open No. 9-246098 discloses a noise absorbing function in a wide frequency range by forming electrodes of each layer so that each capacitance is different and connecting each stage in parallel via an inductor element. Attempts have been made.
[0017]
[Problems to be solved by the invention]
However, in the thin film capacitor disclosed in Japanese Patent Laid-Open No. 6-77083, the external terminal electrodes of the capacitor element are a pair, and even if the internal structure capacitor is divided in a plane, the equivalent circuit is no different from a single capacitor element. Therefore, it is considered that the effect on the equivalent circuit does not appear only by the parallel effect of the dielectric characteristics of the material.
[0018]
Further, even in the parallel capacitor disclosed in Japanese Patent Laid-Open No. 8-162368, since the pair of external terminal electrodes is paired in the same manner as described above, the equivalent circuit is no different from a single capacitor element. Furthermore, in this structure, since the pair of external terminal electrodes is paired, currents in the same direction simultaneously flow through the two capacitor elements themselves, so the mutual inductance between the two capacitors increases, and the effect of parallel connection is expected. I can't do it.
[0019]
Furthermore, in Japanese Patent Application Laid-Open No. 9-246098, the inductance of the entire element increases and goes against low impedance. A further important problem is that there is a maximum point of impedance due to parallel resonance between the resonance points. Unless this parallel resonance is suppressed, the impedance cannot be lowered in a wide frequency range of 100 MHz or more.
[0020]
An object of the present invention is to provide a capacitor having a large capacity and a low inductance that can function as a decoupling capacitor in a higher frequency range and in a wider frequency range.
[0021]
[Means for Solving the Problems]
In the capacitor according to the present invention, upper and lower electrodes are formed on the upper and lower surfaces of the dielectric layer by forming electrode layers forming two outermost capacitance generating portions and a central capacitance generating portion in a row at predetermined intervals. And forming the outermost capacitance generating portion and the central capacitance generating portion in a row by using the layer and the dielectric layer therebetween, and making the capacitances of the two outermost capacitance generating portions equal, and It is smaller than the capacitance of the capacitance generating portion in the central portion, the electrode layers adjacent to the same surface of the dielectric layer are connected by a conductor, and the outermost electrode layer on the same surface of the dielectric layer Each of the extraction electrode layers is provided, and each of the extraction electrode layers is provided with an external connection terminal.
[0022]
Here, it is desirable that the extraction electrode layers are respectively extended in the same direction from the upper and lower electrode layers constituting the capacitance generating portion. In addition, it is desirable that the capacity generation unit includes a large capacity generation unit and a small capacity generation unit, and the capacity of the large capacity generation unit is 10 times or less than the capacity of the small capacity generation unit.
[0023]
[Action]
In the capacitor of the present invention, a plurality of electrode layers having different areas are connected by a conductor, and current flows from the extraction electrode layer provided in the outermost electrode layer. For example, when current fluctuation occurs in the LSI First, current flows into the LSI through the extraction electrode layer and the external connection terminal from the small-capacity generation unit, and after the current flow from the small-capacity generation unit is finished, the large-capacity generation unit through the extraction electrode layer and the external connection terminal Current will flow. For this reason, as if the two capacitors act independently, the effect of parallel connection appears on the equivalent circuit.
[0024]
In addition, since the external connection terminals are provided on the lead electrodes extending from the outermost electrode layer, there are two or more pairs of external connection terminals. For example, when current flows into an LSI in which current fluctuation has occurred. In addition, the current can be reliably divided in two directions.
[0025]
And by exhibiting the effect of parallel connection and shunting, it becomes possible to exhibit low impedance characteristics in a wide frequency range.
[0026]
In addition, by extending the extraction electrode layer in the same direction from the upper and lower electrode layers constituting the capacitance generation portion, the end portions of the extraction electrode layer connected to the upper and lower electrode layers constituting the capacitance generation portion are provided adjacent to each other. The distance between the external connection terminals of different polarities can be minimized as much as possible, and a low impedance can be realized.
[0027]
Furthermore, since the capacitor is symmetrical in structure by making the capacitance of the outermost capacitance generation unit smaller than the capacitance of the central capacitance generation unit, the direction of connection to the LSI or the like is not considered. Further, since the capacitance of the capacitance generating unit on the side connected to the LSI or the like is small, higher frequency can be promoted.
[0028]
Furthermore, the capacity generating section is composed of a large capacity generating section and a small capacity generating section, and the capacity of the large capacity generating section is less than 10 times the capacity of the small capacity generating section, thereby exhibiting a low impedance characteristic. The area can be maximized, the impedance in this area can be flattened, and the frequency range used can be further expanded.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
1 is an external perspective view of the multilayer capacitor of the present invention, FIG. 2 is a cross-sectional view taken along line xx of FIG. 1, and FIG. 3 is a plan view showing an electrode pattern. As shown in FIG. 1, the capacitor of the present invention has external terminal electrodes 2a, 2b, 3a, 3b formed on opposite side surfaces of the capacitor body 1.
[0030]
As shown in FIG. 2, the capacitor body 1 has two electrode layers 5a and 7a formed on the upper surface of the dielectric layer 4 at a predetermined interval, and two electrode layers 5b and 7b on the lower surface. Is formed. The electrode layers 5a and 5b, the electrode layers 7a and 7b have the same area, and the electrode layers 5a and 5b and the electrode layers 7a and 7b have different areas. As a result, two capacitance generating portions A and B having different capacities are formed by the upper and lower electrode layers 5a and 5b and the dielectric layer 4 therebetween, and the electrode layers 7a and 7b and the dielectric layer 4 therebetween. Is formed.
[0031]
A protective layer 8 made of the same material as that of the dielectric layer 4 is formed on the upper and lower surfaces of the dielectric layer 4, thereby forming the capacitor body 1.
[0032]
The electrode layer 5a and the electrode layer 7a are connected by a conductor 9 as shown in FIG. 3 (a), and the electrode layer 5b and the electrode layer 7b are connected by a conductor 10 as shown in FIG. 3 (b). Has been. The electrode layers 5a and 5b and the electrode layers 7a and 7b are provided with extraction electrode layers 11 and 12, respectively. The extraction electrode layer 11 has external connection terminals 2b and 3b, and the extraction electrode layer 12 has external connection terminals 2a. 3a are provided.
[0033]
The extraction electrode layers 11 and 12 extend in the same direction from the upper and lower electrode layers 5a and 5b constituting the capacitance generating portions A and B, or from the electrode layers 7a and 7b, respectively. That is, the extraction electrode layer 11 extended from the electrode layer 5a and the extraction electrode layer 12 extended from the electrode layer 5b are exposed on the same side surface of the capacitor body 1 and extended from the electrode layer 7a. The extraction electrode layer 11 and the extraction electrode layer 12 extending from the electrode layer 7 b are exposed on the same side surface of the capacitor body 1.
[0034]
Further, the capacity of the capacity generator B is formed smaller than the capacity of the capacity generator A, and the capacity generator A is 10 times or less the capacity of the capacity generator B. The capacity generator A is preferably 1.5 to 4 times, more preferably 1.5 to 2.5 times the capacity of the capacity generator B.
[0035]
The external connection terminals 2a and 3a are connected to the ground, and the external connection terminals 2b and 3b are connected to a power source. The LSI is connected to the external connection terminal 3b.
[0036]
In the capacitor configured as described above, for example, when an instantaneous voltage drop occurs in the LSI, a current flows from the capacitance generation unit B via the external connection terminal 3b, and the flow of the capacitance from the capacitance element B is completed. After that, a current flows from the capacitance generation unit A via the external connection terminal 3b, and a capacitance flows from the capacitance generation unit A. Therefore, as if the two capacitors act independently, the effect of parallel connection appears on the equivalent circuit. Moreover, since the electrode layers 5a and 7a and the electrode layers 5b and 7b have the external connection terminals 2b and 3b and the external connection terminals 2a and 3a, the current can be surely divided in two directions. By exhibiting the effect of the above parallel connection and shunting, low impedance characteristics can be shown in a wide frequency range.
[0037]
The lead electrode layer 11 extended from the electrode layer 5a and the lead electrode layer 12 extended from the electrode layer 5b are exposed on the same side surface of the capacitor body 1 and connected to the external connection terminals 2a and 2b. The lead electrode layer 11 extending from the electrode layer 7a and the lead electrode layer 12 extending from the electrode layer 7b are exposed on the same side surface of the capacitor body 1 and connected to the external connection terminals 3a and 3b. Therefore, the extraction electrode layer 11 and the extraction electrode layer 12 can be brought close to each other on the same side surface of the capacitor body 1, and the external connection terminals 2a and 2b and the external connection terminals 3a and 3b can be formed close to each other, thereby reducing the lower impedance. Can be realized.
[0038]
Furthermore, since the LSI is connected to the external connection terminal 3b connected to the electrode layer 7a of the capacity generation part B, the capacity of the capacity generation part B on the side connected to the IC is small, so that higher frequency can be promoted.
[0039]
In the above example, two electrode layers 5a, 7a, 5b, and 7b are formed on the upper and lower surfaces of the dielectric layer 4, respectively, but three or more electrodes are formed on the upper and lower surfaces of the dielectric layer. A layer may be formed. In this case, since the capacitor has symmetry by reducing the capacitance of the capacitance generating portions on both sides (outermost) than the capacitance of the central capacitance generating portion, the direction for connecting to the LSI or the like is set. There is no consideration. Further, since the capacitance of the capacitance generating unit on the side connected to the LSI or the like is small, higher frequency can be promoted. FIG. 4 shows an electrode pattern of a capacitor in which three or more electrode layers 15a, 17a, 19a and electrode layers 15b, 17b, 19b are formed on the upper and lower surfaces of the dielectric layer 14.
[0040]
Further, as shown in FIG. 5, an extraction electrode layer 21 may be formed on the electrode layers 5a and 7a, and an extraction electrode layer 22 may be formed on the electrode layers 5b and 7b.
[0041]
Further, in the above example, the example in which the electrode layers are formed on the upper and lower surfaces of one dielectric layer has been described. However, the capacitor of the present invention may have electrode layers formed on the upper and lower surfaces of a plurality of dielectric layers.
[0042]
6 and 7 show a thin film capacitor of the present invention. Two electrode layers 35a and 37a are formed on the upper surface of an insulating substrate 31 at a predetermined interval, and the upper surfaces of these electrode layers 35a and 37a are shown. A dielectric layer 38 is formed, and two electrode layers 35b and 37b are formed on the upper surface of the dielectric layer 38 at a predetermined interval.
[0043]
The electrode layer 35a and the electrode layer 37a are connected by a conductor 39, the electrode layer 35b and the electrode layer 37b are connected by a conductor 40, and the lead electrode layer 41 is connected to the electrode layers 35a and 35b and the electrode layers 37a and 37b. , 42 are provided.
The upper surface of the electrode layers 37a and 37b is covered with a protective layer 39, and the protective layer 39 where the extraction electrode layers 41 and 42 are located is opened, and the extraction electrode layer 41 and the electrode layer connected to the electrode layers 35a and 37a, respectively. The lead electrode layer 42 connected to 35b and 37b is exposed, the exposed portion of the lead electrode layer 41 of the electrode layer 35a has an external connection terminal 52a, and the exposed portion of the lead electrode layer 42 of the electrode layer 35b has an external connection. A terminal 52b is provided. Although not shown, external connection terminals are also formed on the exposed portion of the extraction electrode layer 41 of the electrode layer 37a and the exposed portion of the extraction electrode layer 42 of the electrode layer 37b.
[0044]
Even with the thin film capacitor configured as described above, the same effect as described above can be obtained.
[0045]
The electrode layer material used in the capacitor of the present invention is preferably platinum (Pt), gold (Au), silver (Ag), palladium (Pd), low resistance copper (Cu), nickel (Ni), or the like. The material is not particularly limited as long as it is a material that can be used and has low reactivity with the dielectric layer, and may be formed by a method such as screen printing or sputtering.
[0046]
In addition, the external connection terminals are solder bumps formed of solder balls or solder paste, screen printing of pastes mainly composed of Ag, Pd, Cu, and Ni, and a dipping method in which they are aligned with a plate called a carrier plate. It may be formed by a known technique such as Ni-solder plating or Ni-Sn plating.
[0047]
Furthermore, the dielectric material may be any material having a high dielectric constant in the high frequency region. However, the dielectric material is composed of a perovskite oxide crystal containing Pb, Mg, Nb, and other PZT, PLZT, BaTiO ₃ , SrTiO. ₃ , Ta ₂ O ₅ or a compound obtained by adding or substituting other metals to these may be used, and is not particularly limited.
[0048]
In the case of the thin film type, the film thickness is preferably 0.3 μm to 1.0 μm, particularly 0.4 μm to 0.8 μm in order to ensure high capacity and insulation. In the case of the multilayer chip capacitor type, the film thickness is not particularly limited as long as it is formed from several μm to several tens of μm. In the case of the thin film type, the insulator substrate to be used is not particularly limited and is selected from alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO ₃ single crystal, surface silicon oxide, glass, quartz and the like.
[0049]
【Example】
(Example 1)
First, a green sheet having a thickness of 10 μm was formed by a doctor blade method using a slip composed mainly of barium titanate and mixed with a sintering aid, a solvent, a dispersant, a binder and the like. On the other hand, a commercially available Pd paste was prepared as an internal electrode.
[0050]
And the green sheet in which the electrode pattern as shown to Fig.3 (a) was formed, the green sheet in which the electrode pattern as shown in FIG.3 (b) was formed, and the green sheet in which the electrode pattern was not formed Were sequentially laminated, and a laminated molded body was obtained by thermocompression bonding.
[0051]
The obtained laminated molded body was cut so as to have a predetermined size, and then fired in the atmosphere at a temperature of 1250 ° C. for 2 hours. Thereafter, a conductive paste containing silver as a main component was applied and dried, followed by baking at 800 ° C. to form external connection terminals.
[0052]
Thereafter, a plating coating layer is formed on the outermost layer of the external connection terminal by Ni-solder plating to form a terminal electrode, and the capacity of the capacity generation part A is twice, three times, four times, 10 times the capacity of the capacity generation part B. A multilayer capacitor as shown in FIGS. 1 to 3 was obtained.
[0053]
The impedance characteristics of the produced capacitor at 1 to 1.8 GHz were measured using an impedance analyzer (HP 4291A manufactured by Hewlett Packard) and a microwave probe (manufactured by Pico Probe), and the results are shown in FIG. 8A shows the impedance characteristics when the capacitance of the capacitance generator A is twice that of the capacitance generator B, (b) is 3 times, (c) is 4 times, and (d) is 10 times. It is.
[0054]
A capacitor disclosed in JP-A-8-162368 with a pair of external terminal electrodes was produced and evaluated in the same manner as described above. In addition, the effective electrode areas in the capacity generation portions A and B are the same. The results are shown in FIG.
[0055]
8 and 9, it can be seen that the impedance is lower in a higher frequency range and in a wider frequency range.
[0056]
(Example 2)
A thin film capacitor was produced as follows. Each electrode layer was formed using a high-frequency magnetron sputtering method. First, Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation. At the time of sputtering, the substrate holder was moved to the target position of the material type to be deposited, and the distance between the substrate and the target was fixed at 60 mm.
[0057]
Next, a high frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high frequency power source, and high density plasma is generated in the vicinity of the target by a magnetron magnetic field formed by a permanent magnet installed on the back surface of the target. The target surface was sputtered.
[0058]
In this example, plasma was generated by applying only to the target closest to the substrate. The substrate holder had a heating mechanism with a heater, and the substrate temperature during sputtering film formation was controlled to be constant. In addition, a metal mask having a thickness of 0.1 mm is installed on the target side of the substrate placed on the substrate holder, and a necessary mask can be set on the substrate deposition surface according to the deposition pattern.
[0059]
All dielectric layers were prepared by the sol-gel method. Further, Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2, and refluxed in 1,3-propanediol (at about 124 ° C. for 6 hours) to obtain an MgNb composite alkoxide solution (Mg = 5.0 mmol, Nb 10.0 mmol, 1,3-propanediol 100 mmol) was synthesized. Next, 15 mmol of lead acetate (trihydrate) was added to the MgNb composite alkoxide solution and dissolved at 60 ° C. to synthesize a Pb (Mg _1/3 Nb _2/3 ) O ₃ (PMN) precursor solution.
[0060]
Then, an Au electrode having a thickness of 0.3 μm is formed on an alumina substrate having a thickness of 0.25 mm by using the mask pattern of the electrode layer (0.9 mm × 1.0 mm) shown in FIG. The coating solution was applied with a spin coater and dried, followed by heat treatment at about 400 ° C. for 1 minute to produce a gel film.
[0061]
After repeating the operation of applying the coating solution and heat treatment, baking was performed at about 800 ° C. for 2 minutes (in the air) to obtain a PMN thin film having a thickness of 0.7 μm. From the result of X-ray diffraction of the obtained thin film, the perovskite production rate was calculated to be about 95%. Thereafter, the dielectric film was patterned by a photoresist process.
[0062]
An Au electrode was sputter-deposited on the surface of this PMN film with the mask pattern of the electrode layer shown in FIG. After each element is formed, a protective film having a via hole is formed using a photosensitive resin, solder paste is printed in the via hole by screen printing of solder paste, and then soldered to 0.1 mmφ by reflow processing. Four bumps were formed to obtain a thin film capacitor as shown in FIGS.
[0063]
FIG. 9 shows the results of measuring the impedance characteristics of the produced thin film capacitor from 1 MHz to 1.8 GHz using an impedance analyzer (HP 4291A manufactured by Hewlett Packard) and a microwave probe (manufactured by Pico Probe). From FIG. 9, it can be seen that the thin film capacitor of the present invention has a low impedance in a higher frequency range and a wider frequency range.
[0064]
【The invention's effect】
In the capacitor of the present invention, a plurality of electrode layers having different areas are connected by a conductor, and current flows from the extraction electrode layer provided in the outermost electrode layer. For example, when current fluctuation occurs in the LSI First, current flows into the LSI from the small-capacity generation unit via the extraction electrode layer and the external connection terminal, and after the current flow from the small-capacity generation unit is finished, the extraction electrode layer and the external connection terminal are connected from the large capacity generation unit. Current flows in through. For this reason, as if the two capacitors act independently, the effect of parallel connection appears on the equivalent circuit.
[0065]
Further, since the external connection terminals are respectively provided on the lead electrodes extending from the outermost electrode layer, there are two or more pairs of external connection terminals, and when current flows into the LSI in which current fluctuation occurs, The current can be reliably shunted in two directions.
[0066]
And by exhibiting the effect of parallel connection and shunting, it becomes possible to exhibit low impedance characteristics in a wide frequency range.
[Brief description of the drawings]
FIG. 1 is an external perspective view of a capacitor.
2 is a cross-sectional view taken along line xx of FIG.
3 is a plan view showing an electrode pattern of FIG. 2. FIG.
FIG. 4 is a plan view showing an electrode pattern of another example of the capacitor of the present invention.
FIG. 5 is a plan view showing the electrode pattern of the capacitor of the present invention in which the lead-out direction of the lead-out electrode is changed.
FIG. 6 is a cross-sectional view of a thin film capacitor.
7 is a plan view showing an electrode layer pattern of FIG. 6. FIG.
FIG. 8 shows impedance characteristics of the multilayer capacitor.
FIG. 9 shows impedance characteristics of the multilayer capacitor disclosed in Japanese Patent Laid-Open No. 8-162368.
FIG. 10 shows impedance characteristics of a thin film capacitor.
[Explanation of symbols]
4 ... Dielectric layers 5a, 5b, 7a, 7b ... Electrode layers A, B ... Capacitance generators 9, 10 ... Conductors 11, 12 ... Lead electrode layers 2a, 2b, 3a, 3b: External connection terminal

Claims (3)

On the upper and lower surfaces of the dielectric layer, electrode layers for forming the two outermost capacitance generating portions and the central capacitance generating portion are formed in a row at predetermined intervals, and the upper and lower electrode layers and the dielectric between them are formed. The two outermost capacitance generation units and the central capacitance generation unit are formed in a row by the layer , the capacitances of the two outermost capacitance generation units are equalized, and the capacitance generation of the central unit is performed. The electrode layers adjacent to each other on the same surface of the dielectric layer are connected by a conductor, and an extraction electrode layer is provided on each outermost electrode layer on the same surface of the dielectric layer. An external connection terminal is provided on each of the extraction electrode layers. 2. The respective extraction electrode layers provided on the outermost electrode layer are extended in the same direction from electrode layers on the same surface of the dielectric layer constituting the capacitance generating portion. Capacitor. The capacity generating unit includes a large capacity generating unit that is a capacity generating unit in the center and a small capacity generating unit that is an outermost capacity generating unit, and the capacity of the large capacity generating unit is the capacity of the small capacity generating unit. The capacitor according to claim 1, wherein the capacitor is 10 times or less.

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