JP3860675B2 - Capacitor - Google Patents

Description

【００５７】
この表１から、第１端子電極と第２端子電極との間の距離Ｌ、すなわち第１端子部と第２端子部の距離Ｌが小さいほど、インダクタンスが小さいことが判る。
【００５８】
図４に端子電極間距離Ｌ＝０．２ｍｍの試料Ｎo.１のインピーダンス特性を示す。この図より、広い周波数領域で低いインピーダンス特性を示していることがわかる。
【００５９】
尚、上述の実施例では、第１の電極層及び第２の電極層を、真空蒸着やスパッタリングなどの薄膜技法により形成し、また、誘電体層をスピンコート法などで形成した薄膜タイプのコンデンサで説明したが、例えば、各電極層及び誘電体層を、導電性ペーストや誘電体ペーストを所定パターンに印刷塗布し焼きつける印刷多層による厚膜タイプのコンデンサであってもよい。さらに、絶縁基板にセラミックグリーンシートを用い、誘電体層に誘電体材料のグリーンシートを用い、第１の電極層を絶縁セラミックグリーンシート上に導電性ペーストの塗布により導体膜、第２の電極層を誘電体電体材料のグリーンシート上に導電性ペーストの塗布により導体膜を夫々形成し、各グリーンシートを積層し、一体的に焼成したグリーンシート多層による厚膜タイプのコンデンサであってもよい。
【００６０】
【発明の効果】
以上の詳述したように、本発明によれば、電流が複数個の第１端子電極に分流されて入力され、一つの第１端子電極から、この第１端子電極に最も近い両隣の第２端子電極に流れるように、１つの第１端子電極から少なくとも２方向以上に確実に分流されるので、実効的なインダクタンスを減少させることができる。しかも、各コンデンサ本体において、あたかも一つの第１端子電極と両隣の第２端子電極からなる容量素子を４個並列接続した回路となり、それらコンデンサ本体が更に並列接続されてコンデンサを形成しているので、分流効果と並列接続により幅広い周波数領域で低インピーダンス特性を示すことができる。
【図面の簡単な説明】
【図１】本発明の第１実施形態に関わる薄膜タイプのコンデンサの分解斜視図である。
【図２】保護層を省略した図１の平面図である。
【図３】図２のＸ−Ｘ線に沿う断面図である。
【図４】図１のコンデンサのインピーダンス特性である。
【図５】本発明の第２実施形態に関わるコンデンサの平面図である。
【符号の説明】
１０・・・コンデンサ
１・・・絶縁体基板
２ａ・・・第１電極層
２ｂ・・・第２電極層
３・・・誘電体層
４・・・コンデンサ本体
５・・・第１端子電極
６・・・第２端子電極
７・・・保護層
８・・・第１端子部
９・・・第２端子部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor in which a plurality of capacitor bodies are arranged side by side on a plane. For example, the capacitor is disposed in an electric circuit that operates at high speed, and is used for bypassing high-frequency noise or for preventing fluctuations in power supply voltage. This relates to a low impedance capacitor.
[0002]
[Prior art]
In recent years, with the downsizing and high functionality of electronic devices, there has been an increasing demand for downsizing, thinning, and high frequency compatibility for electronic components installed in electronic devices.
[0003]
In particular, in a high-speed digital circuit of a computer that needs to process a large amount of information at high speed, the clock frequency in the CPU chip is 400 MHz to 1 GHz, the clock frequency of the inter-chip bus is 75 MHz to 100 MHz, etc. even at the personal computer level. The speedup is remarkable.
[0004]
As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to reduce power consumption. As these IC circuits increase in speed, density, and voltage, passive components such as capacitors have become essential to exhibit excellent characteristics for high-frequency or high-speed pulses in conjunction with downsizing and large capacity. Yes.
[0005]
In order to reduce the size and capacity of the capacitor, it is most effective to make the dielectric layer sandwiched between the pair of electrodes thinner and thinner. Thinning is also compatible with the above-mentioned tendency of voltage reduction.
[0006]
On the other hand, various problems associated with high-speed operation of the IC circuit are more serious than miniaturization of each element. Of these, the high-frequency noise removal function, which is the role of the capacitor, is particularly important because the instantaneous drop in the power supply voltage that occurs when the logic circuit is switched at the same time This is a function that is reduced by supplying to the so-called decoupling capacitor.
[0007]
The performance required for this decoupling capacitor is how quickly a current can be supplied with respect to the current fluctuation of the load part faster than the clock frequency. Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.
[0008]
However, an actual capacitor has a resistance component and an inductance component in addition to a capacitance component. The impedance of the capacitive component decreases with increasing frequency, and the inductance component increases with increasing frequency.
[0009]
For this reason, as the operating frequency increases, the inductance of the element limits the transient current to be supplied, causing an instantaneous drop in the power supply voltage on the logic circuit side or new voltage noise. As a result, an error on the logic circuit is caused. Particularly in recent LSIs, the power supply voltage is lowered to suppress the increase in power consumption due to the increase in the total number of elements, and the allowable fluctuation range of the power supply voltage is also reduced. Therefore, in order to minimize the voltage fluctuation range during high-speed operation, the impedance of the decoupling capacitor itself is reduced even in the high-frequency region, and it has the ability to supply the stored charge as the necessary current instantly. is important.
[0010]
Impedance reduction guidelines are described in AJ Rainal, "Computing Inductive Noise of CMOS Drivers", IEEE Trans. Comp., Packag., Manufact. Technol.-Part B, Vol. 19, pp. 789-802 (1996). As shown, the current change per driver is 40 mA / ns. If the power supply voltage is 1.8V, the allowable range of voltage fluctuation is 10%, 0.18V, and the number of off-chip drivers is 64, the upper limit of inductance is 0.14nH, and the impedance at 1GHz is about 0.4Ω or less. And shall be.
[0011]
In order to minimize the impedance of the capacitor in the necessary frequency range, the capacitance component of the capacitor itself is increased, the resistance component and the inductance component are decreased, or determined by the equivalent series inductance ESL and the capacitance C. The resonance frequency f ₀ = 1 / 2π (ESL · C) ^1/2 may be lowered so as to match the required frequency.
[0012]
The former method is most effective for reducing the thickness of the dielectric layer sandwiched between the electrode layers as described above with respect to the capacitance. The resistance component is determined by the dielectric loss of the dielectric and the resistance of the electrode layer. The resistance of the electrode layer may be considered to be a substantially constant value except for the skin effect that becomes noticeable at several GHz or more.
[0013]
As a method of reducing the inductance, there are a method of minimizing the length of the current path, a method of making the current path a loop structure and minimizing the loop cross-sectional area, and dividing the current path into n pieces to reduce the effective inductance to 1 /. There is a method of setting n.
[0014]
Attempts have been made to reduce the inductance of the capacitor and reduce the impedance of the element by such a method, but the area that can be used when the impedance is 0.4Ω or less is around the resonance frequency determined by the capacitance and inductance of the capacitor Only. When the capacitor is used in a lower frequency range than this, it becomes a capacitor that functions only in the region of the resonance frequency ± several tens of MHz.
[0015]
As a method of overcoming the point that the impedance is lowered only near the resonance frequency and realizing a capacitor that functions with a low impedance in a wide frequency range, means for connecting capacitors having different capacities in parallel has been considered. For example, as disclosed in JP-A-6-77083, there is an attempt to obtain a capacitor having a large capacity and excellent high frequency characteristics by arranging a plurality of dielectric materials having different relative dielectric constants in parallel.
[0016]
In the multilayer ceramic capacitor, as described in JP-A-8-162368, by changing the electrode area and the dielectric layer thickness in one capacitor, two capacitive elements having different capacitances are connected in parallel, Attempts have been made to promote low impedance at the resonance point of two capacitive elements having different capacities and to develop a noise absorbing function in a wide frequency range with a single component.
[0017]
Japanese Patent Laid-Open No. 9-246098 discloses a noise absorbing function in a wide frequency range as described above by forming electrodes of each layer so that each capacitance is different and connecting each stage in parallel via an inductor element. Attempts have been made to express.
[0018]
[Problems to be solved by the invention]
However, in the thin film capacitor disclosed in Japanese Patent Application Laid-Open No. 6-77083, the equivalent circuit is not different from that of a single capacitor even if the dielectric layer is divided in a plane while the external terminal electrodes of the capacitor remain one pair. It is considered that the effect on the equivalent circuit does not appear only by the parallel effect of the dielectric property of the material.
[0019]
The capacitor disclosed in Japanese Patent Laid-Open No. 8-162368 is a parallel circuit on the equivalent circuit, but if the self-inductance of the two capacitive elements in the chip is large, a large effect due to the parallel connection cannot be obtained. Furthermore, in this structure, currents in the same direction flow through the two capacitive elements themselves, so that the mutual inductance between the two capacitive elements increases, and the effect of parallel connection cannot be expected.
[0020]
In addition, in a capacitor in which an inductor element is inserted between capacitors disclosed in Japanese Patent Laid-Open No. 9-246098, the inductance of the entire element increases, which goes against low impedance. More importantly, there is a maximum point of impedance due to parallel resonance between each resonance point, and there is a problem that impedance cannot be lowered in a wide frequency range of 100 MHz or more unless this parallel resonance is suppressed. .
[0021]
An object of the present invention is to provide a capacitor having a large capacity and a low impedance in a wide frequency range.
[0022]
[Means for Solving the Problems]
The capacitor according to the present invention includes a plurality of square capacitor bodies in which a first electrode layer and a second electrode layer are alternately stacked with a dielectric layer interposed therebetween in a planar direction. Around the body, a plurality of first terminal electrodes connected to the first electrode layer and a plurality of second terminal electrodes connected to the second electrode layer are alternately arranged, and either the first or the second The terminal electrode is provided at a corner portion of the capacitor body, and the other terminal electrode is provided on a line connecting the pair of one terminal electrodes provided at the corner portion, between the first terminal electrode and the second terminal electrode. formed so that the distance is the same distance, further adjacent connecting the first and second terminal electrodes to each other of said capacitor body, said adjacent said between capacitor body to the first and second terminal electrodes are present to a volume non-formation portions, the first , Characterized by providing first connecting respectively to the second terminal electrode, the second terminal portion on one side main surface of the capacitor body.
[0023]
In the present invention, the capacitor body refers to a portion where a dielectric layer is sandwiched between electrode layers having different polarities, that is, a portion that substantially generates a capacitance. Accordingly, a plurality of first electrode layers are formed on one main surface of one dielectric layer, and a second electrode layer opposite to the first electrode layer is formed on the opposite surface to form a plurality of capacitor bodies. The capacitors may be arranged, or the dielectric layer itself may be made independent for each capacitor body.
[0024]
In the configuration of the capacitor of the present invention, either one of the first and second terminal electrodes is provided at the corner of the capacitor body, and the other terminal electrode is provided on a line connecting a pair of terminal electrodes provided at the corner . As the distance between the first terminal electrode and the second terminal electrode is the same distance, it is provided in the center of the line connecting the pair of terminal electrodes provided with the other terminal electrodes at the corners.
[0026]
[Action]
In the conventional capacitor disclosed in JP-A-8-162368, current in the same direction flows through two adjacent capacitative elements, so that the mutual inductance between the two capacitative elements increases, and the effect of parallel connection cannot be expected. There wasn't. If the distance between the two capacitive elements is increased, the mutual inductance is reduced, but the size is increased and the overall inductance is increased by the terminal electrode and the conductive wire for supplying current to the two capacitive elements. As a result, the conventional capacitor is increased. Then, the effect of parallel connection was not obtained.
[0027]
On the other hand, in the capacitor of the present invention, in each capacitor body, a current is divided and input to a plurality (n) of first terminal electrodes. And, in order to flow from one first terminal electrode to both adjacent second terminal electrodes closest to the first terminal electrode, it is ensured in each capacitor body in at least two directions from one first terminal electrode. Divided.
[0028]
For example, a case where a first terminal electrode is provided at each corner of a capacitor body having a square planar shape, a second terminal electrode is provided on a line connecting a pair of first terminal electrodes, and current is input from the first terminal electrode. to illustrate, is current from the first terminal electrodes is input corners of the capacitor body, is diverted to the second terminal electrodes on both sides to form the apex angle, it is possible to reduce the effective inductance . Moreover, each capacitor body is a circuit in which n capacitive elements each composed of one first terminal electrode and two adjacent second terminal electrodes are connected in parallel, and a plurality of such capacitor bodies are connected in parallel to form a capacitor. Therefore, it is possible to exhibit low impedance characteristics in a wide frequency range by the shunt effect and parallel connection.
[0029]
Further, in the present invention, even when the first terminal electrode and the second terminal electrode are provided close to each other in each capacitor body, from one first terminal electrode and the other first terminal electrode, between them, Since the direction of the current flowing through the provided second terminal electrode can be reversed, mutual interference between the first terminal electrodes does not occur, and the current can be reliably divided.
[0030]
Further, for example, when the first terminal electrode is provided at the corner, the second terminal electrode is provided at the center on the line connecting the pair of first terminal electrodes, so that the second terminal electrode and the pair of first terminal electrodes The distance becomes the same, the strength of the current flowing from the first terminal electrode to the second terminal electrode becomes the same, and the above-described shunt effect can be further improved. In addition, the distance between the external terminal electrodes connected to the terminal electrode is the same, and mounting on another substrate becomes easy.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
The capacitor of the present invention can be realized in either a thin film type or a thick film type shape such as a chip capacitor, and can be applied to a capacitor using not only a single layer but also a plurality of layers. Hereinafter, a single layer capacitor having a thin dielectric layer will be described.
[0032]
1 to 3 show a capacitor of the present invention. FIG. 1 is an exploded perspective view, FIG. 2 is a plan view excluding a protective layer, and FIG. 3 is a cross-sectional view taken along line XX in FIG. In this example, it is an assembly of four capacitor bodies 4. The capacitor 10 includes four capacitor bodies 4 each having a square shape in plan view, which is formed by alternately laminating two electrode layers 2 and one dielectric layer 3 on a single insulating substrate 1. The electrode layer 2 is formed as a first electrode layer 2a and a second electrode layer 2b from the lower side. However, the dielectric layer 3 is a single plate straddling all four capacitor bodies 4, and the first electrode layers 2a and the second electrode layers 2b adjacent to each other are first terminals located between them. The electrode 5 and the second terminal electrode 6 are connected.
[0033]
Here, the capacitor body 4 refers to a portion where the dielectric layer 3 is sandwiched between the first electrode layer 2a and the second electrode layer 2b, that is, a portion that substantially generates a capacitance. Accordingly, the first terminal electrode 5 and the second terminal electrode 6 are provided around the capacitor body 4, that is, projecting outward from the capacitor body 4. Adjacent capacitor bodies 4 share a terminal electrode located between them. Thereby, the four capacitor bodies 4 are connected in parallel.
[0034]
The first electrode layer 2 a includes nine first terminal electrodes 5, and the second electrode layer 2 b includes twelve second terminal electrodes 6, including those located between the adjacent capacitor bodies 4. As shown in FIG. 4, they are alternately provided around each capacitor body 4. Specifically, the first terminal electrode 5 is provided at the corner of each capacitor body 4, and the second terminal electrode 6 is provided at the center on the side connecting the two adjacent first terminal electrodes 5.
[0035]
A protective layer 7 is formed on the insulating substrate 1 so as to cover the entire capacitor body 4 and terminal electrodes 5 and 6.
[0036]
The terminal electrodes 5 and 6 are respectively connected to unillustrated via hole conductors penetrating to the upper surface of the protective layer 7 in the thickness direction and terminal portions 8 and 9 made of solder bumps if necessary. Accordingly, the terminal portions 8 and 9 are formed around each capacitor body 4 so as to correspond to the terminal electrodes 5 and 6. Specifically, the first terminal electrode 5 connected to the first electrode layer 2 a is provided at the corner of the capacitor 4, and the second terminal electrode 6 connected to the second electrode layer 2 b is provided at the center of each side of the capacitor body 4. ing. The dielectric layer 3 is formed with slits or notches 31 and 32 so as to avoid the terminal electrodes 5 and 6. Further, the second electrode layer 2 b is formed with slits or notches 21 so as to avoid the first terminal electrode 5. In particular, the slits or notches 31 and 21 are indispensable structures because it is necessary to lead the first terminal electrode 5 to the protective layer 7 side.
[0037]
The distance L between the adjacent first terminal electrode 5 and the second terminal electrode 6 is preferably as short as possible, but it is 1.5 mm or less in consideration of the substantial outer shape of the capacitor 10 element and the inductance of the entire element. Is desirable. This is because if it exceeds 1.5 mm, the inductance of the entire element increases and the size increases. On the other hand, considering the ease of production, 0.2 mm or more is desirable.
[0038]
The material of the insulator substrate 1 is not particularly limited and is selected from alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO ₃ single crystal, surface silicon oxide, glass, quartz and the like.
[0039]
In addition, as the electrode layer 2 material and the terminal electrode 5 and 6 materials, platinum (Pt), gold (Au), silver (Ag), palladium (Pd), low resistance Cu, Ni, and the like can be suitably used. The material is not particularly limited as long as it is a material having low reactivity with the dielectric layer 3, and may be formed by a method such as vacuum deposition or sputtering.
[0040]
The material of the dielectric layer 3 may be any material as long as it has a high dielectric constant in the high-frequency region, but a dielectric made of a perovskite oxide crystal containing Pb, Mg, Nb, other PZT, PLZT, BaTiO ₃ , SrTiO ₃ , Ta ₂ O _5, and compounds obtained by adding or substituting other metal oxides to these may be used, and are not particularly limited. In the case of a thin film type as in this embodiment, the film thickness is preferably 0.3 to 1.0 [mu] m, particularly 0.4 to 0.8 [mu] m, in order to ensure high capacity and insulation.
[0041]
The protective layer 7 is made of a photo-curing resin, SiO _2, etc., and the material of the via-hole conductor constituting the terminal portions 8 and 9 can be formed inside the protective layer 7 such as Ag—Pd, solder, gold, etc. Any conductive material may be used. In addition, on the upper surface of the via hole conductor, solder bumps formed by solder balls or solder paste, or screen printing of paste such as Ag-Pd or Ni-solder in order to facilitate connection to other substrates or circuits. A pad formed by plating, Ni—Sn plating or the like is formed slightly wider than the cross-sectional area of the via-hole conductor. Further, the via-hole conductor may be formed of the same material simultaneously with the production of the bump or pad.
[0042]
In the capacitor 10 configured as described above, as shown in FIG. 2, for example, a current is divided and input to nine first terminal electrodes 5 via the first terminal portion 8. Accordingly, in each of the four capacitor bodies 4, current is divided and input from the four first terminal electrodes 5. In each capacitor body 4, current flows from one first terminal electrode 5 to two adjacent second terminal electrodes 6, and hardly flows to the other second terminal electrodes 6. Even when the first terminal electrode 5 and the second terminal electrode 6 are provided close to each other, the second terminal provided between the first terminal electrode 5 and the other first terminal electrode 5 is provided. The direction of the current flowing through the terminal electrode 6 can be reversed. For this reason, mutual interference between the first terminal electrodes 5 does not occur, and the current can be reliably shunted, and the effective inductance can be reduced.
[0043]
Further, in each capacitor body 4, four capacitive elements each made up of one first terminal electrode 5 and two second terminal electrodes 6 on both sides of the first terminal electrode 5 are connected to the pair of electrode layers 2 and dielectric. The body layer 3 is a circuit in which four capacitive elements are connected in parallel. Therefore, from the viewpoint of the capacitor 10, not only by the parallel connection of the four capacitor bodies 4 described above, but also by the shunt effect, the same effect as when 16 capacitors are connected in parallel can be obtained. Impedance characteristics can be shown.
[0044]
Further, by providing the second terminal electrode 6 at the center on the side connecting the pair of first terminal electrodes 5, the distance L between the second terminal electrode 6 and the pair of first terminal electrodes 5 becomes the same, and the first The intensity of the current flowing from the terminal electrode 5 to the second terminal electrode 6 becomes the same, and the above-described shunt effect can be further improved. In addition, in this case, since the distances between the terminal electrodes 5 and 6 are equal, the intervals between the bumps or pads exposed from the protective layer 7 are equal, and mounting on another substrate becomes easy.
[0045]
FIG. 5 is a plan view showing a single plate type thin film capacitor of the second embodiment. The capacitor according to the second embodiment has the same configuration as the capacitor according to the first embodiment except that the number of the four capacitor bodies 4 according to the first embodiment is increased to nine. Therefore, the same effect as that obtained by connecting 36 capacitors in parallel can be obtained by the shunt effect.
[0046]
【Example】
This is an example of manufacturing the capacitor of the first embodiment and evaluating the performance. Each electrode layer was formed using a high-frequency magnetron sputtering method. First, Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation. At the time of sputtering, the substrate holder was moved to the target position of the material type to be deposited, and the distance between the substrate and the target was fixed at 60 mm.
[0047]
Next, a high frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high frequency power source, and high density plasma is generated in the vicinity of the target by a magnetron magnetic field formed by a permanent magnet installed on the back surface of the target. The target surface was sputtered.
[0048]
In this example, plasma was generated by applying only to the target closest to the substrate. The substrate holder had a heating mechanism with a heater, and the substrate temperature during sputtering film formation was controlled to be constant. In addition, a metal mask having a thickness of 0.1 mm is installed on the target side of the substrate placed on the substrate holder, and a necessary mask can be set on the substrate deposition surface according to the deposition pattern.
[0049]
All dielectric layers were prepared by the sol-gel method. Further, Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2, and refluxed in 1,3-propanediol (at about 124 ° C. for 6 hours) to obtain an MgNb composite alkoxide solution (Mg = 5.0 mmol, Nb 10.0 mmol, 1,3-propanediol 140 mmol) was synthesized.
[0050]
Next, 15 mmol of lead acetate (trihydrate) was added to the MgNb composite alkoxide solution and dissolved at 60 ° C. to synthesize a Pb (Mg _1/3 Nb _2/3 ) O ₃ (PMN) precursor solution.
[0051]
Then, a first electrode layer and a first terminal electrode made of 0.3 μm thick Au are formed by sputtering deposition and photolithography on an alumina substrate having a thickness of 0.25 mm to be the insulating substrate 1, and on the first electrode layer and the first terminal electrode, The coating solution was applied with a spin coater and dried, followed by heat treatment at about 400 ° C. for 1 minute to produce a gel film.
[0052]
After repeating the operation of applying the coating solution and heat treatment, baking was performed at about 800 ° C. for 2 minutes (in the air) to obtain a PMN thin film having a thickness of 0.7 μm. From the X-ray diffraction result of the obtained thin film, the perovskite production rate was calculated to be about 95%. Thereafter, the dielectric film was patterned by a photoresist process.
[0053]
A second electrode layer and a second terminal electrode made of Au were formed on the surface of the dielectric film by sputtering deposition and photolithography.
[0054]
By changing the sizes of the first electrode layer pattern and the second electrode layer pattern, a sample in which the distance L between the first terminal electrode and the second terminal electrode was changed as shown in Table 1 was produced. After that, using a photocurable resin, a protective film having a via hole is formed, and after solder paste is printed by screen printing of the solder paste in the via hole, by reflow processing, along with the via hole conductor to be a terminal electrode, Twenty-one solder bumps having a diameter of 0.1 mm were formed to obtain a single plate type thin film capacitor as shown in FIGS. Table 1 shows the area of the capacitor body, that is, the area of the electrode layer.
[0055]
Table 1 shows the results of measuring the impedance characteristics of the manufactured thin film capacitor from 1 MHz to 1.8 GHz using an impedance analyzer (HP 4291A manufactured by Hewlett Packard) and a microwave probe (manufactured by Pico Probe). In Table 1, the capacitance is a value of 1 MHz, and the inductance is a value calculated from L = 1 / (2πf ₀ ) ² × C.
[0056]
[Table 1]

[0057]
From Table 1, it can be seen that the smaller the distance L between the first terminal electrode and the second terminal electrode, that is, the distance L between the first terminal portion and the second terminal portion, the smaller the inductance.
[0058]
4 shows the impedance characteristics of the sample No. 1 having a distance L between terminal electrodes of L = 0.2 mm. From this figure, it can be seen that low impedance characteristics are shown in a wide frequency range.
[0059]
In the above-described embodiments, the first electrode layer and the second electrode layer are formed by a thin film technique such as vacuum deposition or sputtering, and the dielectric layer is formed by a spin coating method or the like. As described above, for example, a thick film type capacitor having a printed multilayer structure in which each electrode layer and the dielectric layer are printed and coated with a conductive paste or a dielectric paste in a predetermined pattern may be used. Further, a ceramic green sheet is used for the insulating substrate, a green sheet made of a dielectric material is used for the dielectric layer, and the first electrode layer is formed by applying a conductive paste on the insulating ceramic green sheet, and the second electrode layer. Alternatively, a thick film type capacitor having a multilayered green sheet in which conductive films are formed by applying a conductive paste on a green sheet of dielectric material, each green sheet is laminated, and integrally fired may be used. .
[0060]
【The invention's effect】
As described above in detail, according to the present invention, a current is shunted and inputted to the plurality of first terminal electrodes, and the second second adjacent to the first terminal electrode is adjacent to the first terminal electrode. Since the current is reliably shunted from at least two directions from one first terminal electrode so as to flow to the terminal electrode, the effective inductance can be reduced. In addition, in each capacitor body, it is a circuit in which four capacitive elements composed of one first terminal electrode and two adjacent second terminal electrodes are connected in parallel, and these capacitor bodies are further connected in parallel to form a capacitor. The low impedance characteristic can be shown in a wide frequency range by the shunt effect and the parallel connection.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view of a thin film type capacitor according to a first embodiment of the present invention.
FIG. 2 is a plan view of FIG. 1 with a protective layer omitted.
3 is a cross-sectional view taken along line XX of FIG.
4 is an impedance characteristic of the capacitor of FIG.
FIG. 5 is a plan view of a capacitor according to a second embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Capacitor 1 ... Insulator board | substrate 2a ... 1st electrode layer 2b ... 2nd electrode layer 3 ... Dielectric layer 4 ... Capacitor main body 5 ... 1st terminal electrode 6 ... Second terminal electrode 7 ... Protective layer 8 ... First terminal part 9 ... Second terminal part

Claims (1)

A plurality of square capacitor bodies in which a first electrode layer and a second electrode layer are alternately laminated with a dielectric layer interposed therebetween are arranged in a plane direction, and the periphery of each capacitor body is A plurality of first terminal electrodes connected to the first electrode layer and a plurality of second terminal electrodes connected to the second electrode layer are alternately arranged, and one of the first and second terminal electrodes is Provided at the corner of the capacitor body, and the other terminal electrode is provided on a line connecting the pair of one terminal electrodes provided at the corner, and the distance between the first terminal electrode and the second terminal electrode is the same distance so as to form, further adjacent connecting the first and second terminal electrodes to each other of said capacitor body, and the present is adjacent said inter capacitor body to the first and second terminal electrode capacitance nonconductive portion, It is applied to the first and second terminal electrodes. First capacitor, wherein a second terminal portion provided on one side main surface of the capacitor body to be connected.

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