JP3882779B2

JP3882779B2 - Thin film capacitor, composite passive component including thin film capacitor, method for manufacturing the same, and wiring board incorporating them

Info

Publication number: JP3882779B2
Application number: JP2003136846A
Authority: JP
Inventors: 透森; 明信渋谷; 新太郎山道
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 2002-05-27
Filing date: 2003-05-15
Publication date: 2007-02-21
Anticipated expiration: 2023-05-15
Also published as: JP2004056097A

Description

【０００１】
【発明の属する技術分野】
本発明は、絶縁性基材上に形成した薄膜キャパシタおよび薄膜キャパシタを含む複合受動部品、特に有機材料からなる電子回路基板の内部に実装されるのに適した構造の薄膜キャパシタおよび薄膜キャパシタを含む複合受動部品とそれらの製造方法ならびに当該薄膜キャパシタおよび薄膜キャパシタを含む複合受動部品を内蔵した配線基板に関するものである。
【０００２】
【従来の技術】
近年、電子機器の高性能化のために受動部品の高密度実装に対する市場の要求が高まっている。このような要求に応えるために受動部品は１００５サイズ（Ｌ：１．０ｍｍ×Ｗ：０．５ｍｍ）、０６０３サイズ（Ｌ：０．６ｍｍ×Ｗ：０．３ｍｍ）と小型化の一途をたどっている。さらに０４０２サイズ（Ｌ：０．４ｍｍ×Ｗ：０．２ｍｍ）の受動部品も開発される傾向にある。しかし一方では、これ以上のチップサイズの小型化は技術上および実装機側の事情から困難であるとの認識がある。そういった背景から以前より受動部品を電気回路基板に内蔵することによって基板面積を削減しようとする技術が注目されている。特にキャパシタは電子回路を構成する要素の中で最も多く用いられている部品の一つであるので、キャパシタを電子回路基板に内蔵できると基板の面積削減に特に大きな効果が期待できる。
【０００３】
電子回路基板にキャパシタを内蔵する技術として、特開２０００−２４３８７３号公報、特開平１１−４５９５５号公報に開示されたような多層基板のある一層に設けた空洞に電子部品を埋め込んだもの、特開平２０００−２７７９２２号公報、特開２００１−７７５３９号公報に開示されたような多層基板を構成する絶縁層をキャパシタの誘電体層として利用するものが挙げられる。特に絶縁層をキャパシタとして用いる場合、絶縁層に無機フィラーを混合した樹脂を適用することによって比誘電率を高くする技術も提案されている。
【０００４】
【発明が解決しようとする課題】
しかし多層基板のある一層に空洞を設けて電子部品を埋め込む場合、電子部品の厚さが通常のチップ部品で０．３ｍｍが下限であるとすると、上下にプリント基板のプリプレグを一層ずつ積層したとしても、プリプレグの最小限の厚さを０．１ｍｍと仮定すると基板の厚さを０．５ｍｍ以下にすることは不可能になる。また、絶縁層をキャパシタとして用いる場合、比誘電率が２〜４、無機フィラーを混合しても比誘電率を３０以上にすることは極めて困難であり、かつ1層の厚さが最低でも数十μｍもあるために、１ｍｍ²あたりの容量はせいぜい９ｐＦ（絶縁層厚さ２０μｍ、比誘電率２０と仮定）しか得ることができない。
【０００５】
以上のような課題を解決するためにチップ部品よりも薄くかつ単位あたりの容量が高い薄膜コンデンサを基板に内蔵することが有効である。薄膜コンデンサに関する技術は多数報告されているが、そのうち多くはリジッドなＳｉ基板、セラミック基板上に形成された薄膜キャパシタに関する技術である。リジッドな基板上に形成した薄膜キャパシタは誘電体薄膜の形成温度を５００〜６００℃以上にすることが可能であるためにより比誘電率の高い誘電体材料を使うことができるというメリットがある反面、基板の厚さが通常０．１ｍｍ以上あるためそれを内蔵した多層基板の厚さを０．５ｍｍより薄くすることが困難である。また、多層配線基板のような樹脂基板の内部にリジッドな基材上に形成された薄膜キャパシタを内蔵する場合、樹脂基板、例えば多層配線基板の製造工程にある熱圧着によりリジッドな基材が破損する恐れがある。
【０００６】
それに対して樹脂や金属箔のようなフレキシブルな基材上に形成された薄膜キャパシタは、基材の厚さを薄くできる、および多層配線基板製造工程の熱圧着でもフレキシブル基材が破損されない点でメリットがある。フレキシブル基材上に形成された薄膜キャパシタに関しては特開昭５９−１３５７１４号公報に有機高分子からなる可撓性フィルム上に金属薄膜を設けさらに高誘電体薄膜を形成する技術が開示されている。また、特開２０００−３５７６３１号公報にフレキシブル薄膜コンデンサ（＝キャパシタ）において有機高分子または金属箔からなるフレキシブル基板と無機高誘電体膜および金属電極膜を強固に接着させるために接着膜、好ましくは金属酸化物接着膜を設ける技術が開示されている。
【０００７】
しかし有機高分子膜または金属箔といったフレキシブル基材上に高誘電率薄膜を形成した薄膜キャパシタの信頼性を向上させるためには、特開２０００−３５７６３１号公報に記載されているように基材と金属膜、高誘電体薄膜の密着性を上げることは効果的な対策であるが、さらに高誘電率薄膜を形成するにあたって樹脂のキュア温度よりも高い温度でアニールしたときに生じる応力によって誘電体薄膜そのものが変形しないような、換言すれば誘電体薄膜そのものが破損しないような手段が必要であった。
さらに薄膜キャパシタだけでなく、抵抗、インダクタも配線基板に内蔵する場合には、キャパシタ、抵抗、インダクタの各受動部品を１個ずつ内蔵すると、内蔵受動部品の間隔を一定以上確保する必要があることから、受動部品内蔵基板の省面積化には改善の余地が残る。
【０００８】
薄膜キャパシタを配線基板のような絶縁基板に内蔵する方法の一つとして、特開２００１−１６８５３４号公報に、薄膜キャパシタの両端に端子電極を形成し、端子電極を貫通するスルーホールによって絶縁基板の内層電極ないし外層電極に接続させる技術が開示されている。この場合、スルーホールの内面に形成されたCu層と薄膜キャパシタの端子電極が電気的に接続される必要がある。しかし薄膜装置で形成した下部電極や上部電極は厚さがせいぜい１μｍ程度しか得られないためにスルーホール内壁のCu層と薄膜キャパシタ電極の接続信頼性を十分に確保することができないという問題があった。
本発明の課題は、上述した従来技術の問題点を解決することであって、その目的は、第１に、フレキシブル配線基板にも実装可能な薄い（例えば、０．１ｍｍ以下）薄膜キャパシタを特性のばらつきがなく信頼性高く提供できるようにすることであり、第２に、そのような薄い薄膜キャパシタを配線基板内に接続信頼性高く実装できるようにすることである。
【０００９】
【課題を解決するための手段】
上記の目的を達成するため、本発明によれば、厚さ２μｍ以上１００μｍ以下の基材上に、下部電極、誘電体薄膜および上部電極が積層されている薄膜キャパシタにおいて、前記下部電極が、前記基材と接する第１の密着電極と、前記誘電体薄膜と接する耐酸化電極と、前記第１の密着電極と前記耐酸化電極の間に設けられた、前記耐酸化電極よりも高いヤング率を有する材料からなる高弾性電極と、を有し、前記第１の密着電極がＴｉ、Ｃｒ、Ｚｒのいずれかにより形成され、かつ高弾性電極がＩｒ、Ｒｕ、Ｒｈ、Ｗ、Ｍｏ、Ｆｅ、Ｎｉ、Ｃｏのいずれかにより形成されていることを特徴する薄膜キャパシタ、が提供される。
また、上記の目的を達成するため、本発明によれば、厚さ２μｍ以上１００μｍ以下の基材上に、下部電極、誘電体薄膜および上部電極が積層されている薄膜キャパシタにおいて、前記下部電極が、前記基材と接する第１の密着電極と、前記誘電体薄膜と接する耐酸化電極と、前記第１の密着電極と前記耐酸化電極の間に設けられた、前記耐酸化電極よりも高いヤング率を有する材料からなる高弾性電極と、を有し、前記第１の密着電極がＴｉ、Ｃｒ、Ｚｒのいずれかにより形成され、かつ高弾性電極がＩｒ、Ｒｕ、Ｒｈ、Ｗ、Ｍｏ、Ｆｅ、Ｎｉ、Ｃｏのいずれかにより形成されていることを特徴する薄膜キャパシタとともに、薄膜抵抗またはインダクタないし薄膜抵抗とインダクタの双方が同一の基材の上に形成されていることを特徴とする複合受動部品、が提供される。
【００１０】
また、上記の目的を達成するため、本発明によれば、
厚さ２μｍ以上１００μｍ以下の基材上に、下部電極、誘電体薄膜および上部電極が積層されている薄膜キャパシタにおいて、前記下部電極が、前記基材と接する第１の密着電極と、前記誘電体薄膜と接する耐酸化電極と、前記第１の密着電極と前記耐酸化電極の間に設けられた、前記耐酸化電極よりも高いヤング率を有する材料からなる高弾性電極と前記耐酸化電極と、前記耐酸化電極と前記高弾性電極との間に第２の密着電極が形成されており、前記第１および第２の密着電極がＴｉ、Ｃｒ、Ｚｒのいずれかにより形成され、かつ高弾性電極がＩｒ、Ｒｕ、Ｒｈ、Ｗ、Ｍｏ、Ｆｅ、Ｎｉ、Ｃｏのいずれかにより形成されていることを特徴する薄膜キャパシタ、および薄膜キャパシタを含む複合受動部品、が提供される。
そして、好ましくは、高弾性電極の膜厚は好ましくは３００ｎｍ以上、より好ましくは４００ｎｍ以上に、もしくは、誘電体薄膜の膜厚の二倍以上になされる。また、好ましくは、高弾性電極は、Ｉｒ、Ｒｕ、Ｒｈ、Ｗ、Ｍｏ、Ｆｅ、Ｎｉ、Ｃｏ、Ｔａのいずれかにより形成される。また、一層好ましくは、絶縁基材には、樹脂フレキシブル基材が用いられる。
【００１２】
また、上記の目的を達成するため、本発明によれば、厚さが２μｍ以上１００μｍ以下の基材上に、前記基材と接するＴｉ、Ｃｒ、Ｚｒのいずれかにより形成された第１の密着電極と、前記第１の密着電極上に形成されたＩｒ、Ｒｕ、Ｒｈ、Ｗ、Ｍｏ、Ｆｅ、Ｎｉ、Ｃｏのいずれかにより形成されている、膜厚が３００ｎｍ以上の高弾性電極と、前記高弾性電極上に形成された、前記高弾性電極よりも低いヤング率を有する材料からなる耐酸化電極と、を有する下部電極を形成する工程と、前記下部電極上に誘電体薄膜を形成する工程と、前記誘電体薄膜上に上部電極を形成する工程と、前記上部電極をパターニングする工程と、前記誘電体薄膜をパターニングする工程と、前記下部電極を、前記誘電体薄膜より広い面積を占めるようにパターニングする工程と、を有することを特徴とする薄膜キャパシタの製造方法、が提供される。
また、上記の目的を達成するため、本発明によれば、厚さが２μｍ以上１００μｍ以下の基材上に、前記基材と接するＴｉ、Ｃｒ、Ｚｒのいずれかにより形成された第１の密着電極と、前記第１の密着電極上に形成されたＩｒ、Ｒｕ、Ｒｈ、Ｗ、Ｍｏ、Ｆｅ、Ｎｉ、Ｃｏのいずれかにより形成されている、膜厚が３００ｎｍ以上の高弾性電極と、前記高弾性電極上に形成された、前記高弾性電極よりも低いヤング率を有する材料からなる耐酸化電極と、を有する下部電極を形成する工程と、前記下部電極上に誘電体薄膜を形成する工程と、前記誘電体薄膜上に上部電極を形成する工程と、前記上部電極をパターニングする工程と、前記誘電体薄膜をパターニングする工程と、前記下部電極を、前記誘電体薄膜より広い面積を占めるようにパターニングする工程と、感光性樹脂ないし感光性ガラスを用いて絶縁層を形成する工程と、前記絶縁層が下部電極の全面を覆うようにパターニングする工程と、引き出し電極の密着層と薄膜抵抗を同一の材料にて成膜する工程と、引き出し電極とインダクタを同一の材料にて同時に形成する工程と、を有することを特徴とする薄膜キャパシタを含む複合受動部品の製造方法、が提供される。
【００１３】
また、上記の目的を達成するため、本発明によれば、上記の薄膜キャパシタまたは薄膜キャパシタを含む複合受動部品が樹脂基板内に埋め込まれ、前記薄膜キャパシタの下部電極は前記薄膜キャパシタに到達するビアホールまたは前記薄膜キャパシタを貫通するスルーホールまたは前記薄膜キャパシタが固着された導電性パターンのいずれかを介して引き出され、前記薄膜キャパシタの上部電極は前記薄膜キャパシタに到達するビアホールまたは前記薄膜キャパシタを貫通するスルーホールのいずれかを介して引き出され、薄膜抵抗およびスパイラルインダクタのそれぞれの電極は前記薄膜抵抗およびスパイラルインダクタに到達するビアホールまたは前記薄膜抵抗およびスパイラルインダクタを貫通するスルーホールのいずれかを介して引き出されていることを特徴とする薄膜キャパシタおよび薄膜キャパシタを含む複合受動部品を内蔵する配線基板、が提供される。
【００１４】
［作用］
本発明の薄膜キャパシタでは、誘電体薄膜の下層に下部電極の一部として、高ヤング率材料からなる厚い高弾性電極が設けられる。これにより、樹脂のキュア温度よりも高い温度で誘電体薄膜を形成した際に生じる応力を緩和することができる。このような効果が期待できるのはその膜厚が３００ｎｍ以上からであり、その効果がより確実になるのは４００ｎｍ以上である。しかし、その膜厚を１．５μｍ以上に厚く形成するのは得策ではない。一定以上に厚くしても応力緩和効果の向上を期待できない上に成膜時間が長期化するからである。かくして、高い応力を生じさせることなく誘電体薄膜の高温度でのアニールが可能になったことにより、高い容量密度（概ね３０ｐＦ／ｍｍ²以上）を実現することができる。また、ベースとなる基材に、２μｍ以上１００μｍ以下、例えば１０〜７０μｍのフレキシブル基材を用いることにより、厚さ０．１ｍｍ以下で、キャパシタを樹脂基板内に内蔵する樹脂基板製造プロセスにおいて破損することのないの薄膜キャパシタを提供することが可能になる。なお、本発明においては、２〜１００μｍ厚の基材が用いられるが、厚み１００μｍ以下の基材を用いるのは０．１ｍｍ以下の厚さのキャパシタを製造するために必要なことであり、また基材が十分の厚みを有し強固である場合には本発明において要請される高弾性電極を用いる必要性が低くなるからである。また、薄膜キャパシタを配線基板に内蔵する場合、プリプレグを用いて薄膜キャパシタを埋め込むことが多いが、その場合硬化されたプリプレグの厚さが０．１ｍｍ程度となることを想定すると、７０μｍ以下の基材を用いることがより好ましい。また、２μｍ以下の基材では機械的強度が不足し、また製造工程中の取り扱いが困難になることから、これ以上厚さが必要となる。製造工程中の安定性をより確実にするには１０μｍ以上の厚みの基材を用いることがより好ましい。
【００１５】
また、本発明の薄膜キャパシタには、下部電極および上部電極上に電解めっきにより１μｍ以上、より好ましくは２．５μｍ以上の膜厚の引き出し電極が形成される。そのため、薄膜キャパシタを樹脂基板に内蔵した場合に、薄膜キャパシタの電極とスルーホールの内面に形成されたＣｕ層との電気的接続を確実にすることができる。また、引き出し電極の厚さが１μｍを下回ると、熱サイクル試験において引き出し電極と貫通スルーホールの内面Cuめっきとの電気的接続が失われる恐れが高くなるが、その意味においても引き出し電極の厚さを１μｍ以上とすることは有効である。この場合に、薄膜キャパシタに電解めっき等で厚膜電極を形成すると誘電体薄膜にさらに応力がかかるようになるが、この応力も本発明により下部電極に高弾性電極を用いたことにより緩和され、誘電体薄膜が破損されることを抑制することができる。
【００１６】
【発明の実施の形態】
次に、本発明の実施の形態について図面を参照して詳細に説明する。
図１（ａ）、（ｂ）は、本発明の薄膜キャパシタの第１の実施の形態を示す平面図と断面図である。樹脂または金属からなる好ましくは厚さ２〜１００μｍ、より好ましくは１０〜７０μｍのフレキシブル基材１上に、下部電極５と、無機材料によって構成された高誘電率薄膜８と、上部電極９とが積層されてキャパシタが構成されている。そして、下部電極５は、フレキシブル基材１の密着性を高めるために設けられる密着電極２と、高誘電率薄膜８と接触する、難酸化性材料からなる耐酸化電極４と、耐酸化電極４と密着電極２の間に挟まれた、耐酸化電極４よりも高い弾性率（ヤング率）を有する高弾性電極３とにより構成される。高弾性電極３はフレキシブル基材１が変形するような外部応力がかけられても高誘電率薄膜８が損傷を受けないようにするために設けられた電極であり、３００ｎｍ以上であることが望ましく、より好ましくは４００ｎｍ以上の厚さである。また、高弾性電極３と、耐酸化電極４との密着性を向上させるために両者の間に密着層を介在させることができる。この密着層と上記の密着電極は、Cｒ、Ｔｉ、Ｚｒのいずれかを用いて形成することができる。
【００１７】
本発明の薄膜キャパシタには、外部配線との接続のために１μｍ以上、より好ましくは２．５μｍ以上の厚さを有する引き出し電極７および引き出し電極１０が備えられている。図１（ａ）の７ａは、引き出し電極７の上部電極９に対するコンタクト部である。この引き出し電極７を、引き出し電極１０およびそれと電気的に接続している下部電極５と十分に絶縁させるために、引き出し電極７、１０の接触領域以外は絶縁層６により被覆されている。本発明の構成の必須要件ではないが、薄膜キャパシタの最上層には感光性樹脂を用いた厚さ１〜５μｍの保護層１１が形成されている。この保護層１１には、引き出し電極７および１０の一部が露出するように開口１１ａ、１１ｂが設けられている。この開口は、薄膜キャパシタの静電容量を測定する際に、測定器のプローブを直接薄膜キャパシタの引き出し電極に当てるために、また薄膜キャパシタを配線基板に内蔵した際に配線基板の導電膜を薄膜キャパシタの引き出し電極に接触させることができるようにするため用いられる。
【００１８】
図１の高弾性電極３には、耐酸化電極４に通常用いられるＰｔ（ヤング率Ｅ＝１６５ＧＰａ）よりも高い弾性率（ヤング率）を有する金属が用いられる。具体的にはＭｏ、Ｗ、Ｒｕ、Ｉｒ等が挙げられるが、耐酸化電極よりも高い弾性率（ヤング率）を有しかつ高い導電性があれば上記金属に限定されない。すなわち、Ｆｅ、Ｎｉ、Ｃｏ、Ｔａ等も使用可能である。耐酸化電極４は、Ｐｔ以外にＲｕ、ＲｕＯ₂、ＩｒＯ₂、Ｐｄ、Ａｕ等を用いて形成してもよい。高誘電率薄膜８には、チタン酸バリウムストロンチウム（（Ｂａ，Ｓｒ）ＴｉＯ₃）、チタン酸ストロンチウム（ＳｒＴｉＯ₃）、ジルコン酸チタン酸鉛（Ｐｂ（Ｚｒ，Ｔｉ）Ｏ₃）のようなペロブスカイト構造を有する無機複合酸化物、酸化チタン（ＴｉＯ₂）、酸化タンタル（Ｔａ₂Ｏ₅）等が用いられる。また、高誘電率薄膜８と上部電極９との間に両者の密着性を向上させるためにＣｒやＴｉやＺｒ等からなる密着層を形成してもよい。また、引き出し電極７、１０には、めっき法などの厚膜形成が可能なプロセスで形成されるのに適したＣｕ、Ｎｉ等を用いることが、絶縁層６には、パターン形成が容易な感光性樹脂を用いることがそれぞれ適している。高弾性電極３自体が耐酸化性材料により形成されている場合には、、耐酸化電極４を省略して、高弾性電極３上に直接または密着層を介して誘電体薄膜を形成するようにしてもよい。
【００１９】
図２（ａ）、（ｂ）は、本発明の薄膜キャパシタの第２の実施の形態を示す平面図と断面図である。図２において、図１に示した第１の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明は省略する。本実施の形態の図１に示した第１の実施の形態の薄膜キャパシタと相違する点は、フレキシブル基材１上に、高誘電率薄膜８に接する下部電極５以外に、下部電極５と電気的に絶縁されかつ下部電極５と同じ層構造を有する引き出し電極受け５ａが形成されており、上部電極から延びる引き出し電極７が、この引き出し電極受け５ａにまで引き延ばされている点である。このように、引き出し電極７が横方向に引き延ばされたことにより、図１に示した薄膜キャパシタと比較して、薄膜キャパシタの形状が大きくなる、上部電極９に接続される引き出し電極７の引き回しが長くなるために高周波特性が劣るというデメリットはあるが、上部電極９に接続される引き出し電極７が高誘電率薄膜８の真上外に引き出されているために、配線基板に内蔵したときに表面配線層との電気的接続にプロセス上安価な貫通スルーホールを使うことができるメリットがある。また、引き出し電極７を単にフレキシブル基材１上や絶縁層６上に延在させるのに比較して、引き出し電極７を引き出し電極受け５ａに接続するようにすることにより、スルーホール形成時の引き出し電極の剥がれをより有効に防止することができる。なお、図２（ａ）の７、７ｂは、引き出し電極７の上部電極９と引き出し電極受け５ａに対するコンタクト部である。
【００２０】
図３は、本発明の薄膜キャパシタの第３の実施の形態を示す断面図である。図３において、図１に示した第１の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明は省略する。本実施の形態の図１に示した第１の実施の形態の薄膜キャパシタと相違する点は、フレキシブル基材１に開口が設けられ、該開口内が下部電極５の引き出し電極１２となる導電性材料により埋め込まれている点である。
引き出し電極１２が埋設されたフレキシブル基材１は、以下のように形成することができる。ガラス、シリコン、サファイア、セラミック、金属などからなるリジットな仮基板上に電解めっき法もしくは厚膜印刷法により、引き出し電極１２となる導電性ポストを形成し、あるいは仮基板上に金属フィルムを貼り付けエッチングによって導電性ポストを形成し、ポリイミドのワニスのような基材形成材料を塗布し、硬化させてフレキシブル基材１を形成する。ＣＭＰなどにより表面平坦化した後、その上にキャパシタを形成する。キャパシタ形成後に薄膜キャパシタを仮基板から剥離する。あるいは、仮基板をエッチング除去する。
引き出し電極１２の埋設されたフレキシブル基材１の他の形成方法は、フレキシブル基材１上にキャパシタを形成した後、基材裏面より基材を選択的にエッチングし、もしくはレーザ光照射により基材を選択的に除去して開口を形成し、該開口内に導電性塗料やはんだを埋め込む。あるいは、電解めっき法により開口内に導電層プラグを形成する。
【００２１】
図４は、本発明の薄膜キャパシタの第２の実施の形態を示す断面図である。図4において、図１、図２に示した第１、第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明は省略する。本実施の形態の図１に示した第１の実施の形態の薄膜キャパシタと相違する点は、上部電極９上にさらに高誘電率薄膜８′、下部電極５′、高誘電率薄膜８″、上部電極9′が積層され、下部電極５、５′同士が並列に接続され、上部電極９、9′同士が引き出し電極７により並列に接続されていることである。本実施の形態によれば、面積当たりの容量を大きくすることができる。本発明のキャパシタの厚みは、フレキシブル基材１と引き出し電極との膜厚によってほぼ決定されるため、キャパシタを多層構造としたことによって、キャパシタの厚さが大きく厚くなることはない。多層に重ねる高誘電率薄膜の層数は、２でもよくまた４以上であってもよい。
図３、図４に示した第３、第４の実施の形態のキャパシタにおいても、表面に絶縁性の保護層を形成するようにしてもよい。
【００２２】
図５（ａ）、（ｂ）は、本発明の薄膜キャパシタを含む複合受動部品の第１の実施の形態を示す平面図と断面図である。図５において、図１、図２に示した第１、第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明は省略する。同一のフレキシブル基材1の上に薄膜キャパシタと薄膜抵抗が形成されている。図の左側部には、図１に示した第1の実施の形態の薄膜キャパシタに密着電極を付加したものが形成されている。すなわち、上部電極９ないし下部電極の耐酸化電極６と厚膜で形成された引き出し電極７および１０との間に密着電極１４ａが形成されている。図の右側部は薄膜抵抗形成部であって、薄膜抵抗体１４ｂは密着電極１４ａと同一材料からなり、密着電極１４ａと同時に形成されたものである。薄膜抵抗体１４ｂの上に引き出し電極１５が形成される。なお第１から第４の実施の形態で示したように、表面に絶縁性の保護層１１を形成するようにしてもよい。その場合、保護層１１には引き出し電極１５上に開口１１ｃ、１１ｄが開けられる。また、図５においては薄膜抵抗体１４ｂの両端が引き出し電極１５の両端と一致するように記載されているが、薄膜抵抗体１４ｂと引き出し電極１５が電気的に接触していれば、一致していなくてもよい。ここで、薄膜キャパシタの下部電極５の右端と薄膜抵抗体１４ｂの左端の距離は２０μｍまで近づけることができる。
また、図５には薄膜キャパシタと薄膜抵抗の２つが同一基材上に形成されている形態を示したが、薄膜キャパシタと薄膜インダクタとが、または薄膜キャパシタと薄膜抵抗と薄膜インダクタとが同一基材上に形成されていてもよい。
【００２３】
図６は、本発明の薄膜キャパシタを含む複合受動部品の第２の実施の形態を示す断面図である。図６において、図５示した複合受動部品の第１の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明は省略する。本実施の形態においては、同一のフレキシブル基材1の上に薄膜キャパシタとスパイラルインダクタとが形成されている。すなわち、図６の左側部には図５に示した第1の実施の形態の薄膜キャパシタが形成されており、右側部にはスパイラルインダクタ１６が形成されている。スパイラルインダクタ１６は、薄膜キャパシタの下部電極５と同一材料からなり、下部電極５のパターニング時に同時に形成されたものである。スパイラルインダクタ１６の上に引き出し電極１７が形成される。なお、表面に絶縁性の保護層１１を形成するようにしてもよい。その場合、保護層１１には引き出し電極１７上に開口が開けられる。
【００２４】
図７は、本発明の薄膜キャパシタを内蔵した配線基板の第１の実施の形態を示す断面図である。本実施の形態は、本発明に係る薄膜キャパシタを多層配線基板に内蔵した例に関する。図７に示す薄膜キャパシタ内蔵多層配線基板は以下のように作製される。両面に内層パターン２２となる配線が形成されたコア層２１上に、本発明に係る薄膜キャパシタ２０ａを接着層２３を介して固着した後、コア層２１の上下面にプリプレグを配置し、加圧・加熱してプリプレグ硬化層２４を形成する。そして、薄膜キャパシタの引き出し電極７および１０を貫通するように、基板を貫通するスルーホール２５を開設し、プリプレグ硬化層２４の表面に配線パターン２６を形成すると共に、スルーホール内壁面に、配線パターン２６と、薄膜キャパシタ２０ａの引き出し電極７、１０や内層パターン２２とを接続するCuめっき層２６を形成する。
プリプレグ硬化層２４を形成しめっきのみによって配線パターンを形成する方式に代え、プリプレグ硬化層２４をコア層に接着する際にその上に銅箔を設けるかあるいは樹脂コート銅（RCC、resin coated copper）を貼り付けその銅箔層を用いて配線パターンを形成するようにしてもよい。図７から明らかなように、本実施の形態に用いられる薄膜キャパシタ２０ａはプリプレグ硬化層２４よりも薄いことが必須である。望ましくは薄膜キャパシタの厚さはプリプレグの概ね７０％以下である。したがってプリプレグ層一層の厚さを０．１ｍｍとしたとき、許容される薄膜キャパシタの厚さは７０μｍ以下ということになる。
【００２５】
図８は、本発明の薄膜キャパシタを内蔵した配線基板の第２の実施の形態を示す断面図である。本実施の形態は、本発明に係る薄膜キャパシタをビルドアップ基板のコア基板に内蔵した例に関する。コア基板３０は、次のように作成される。内層パターン２２となる配線パターンを有するコア層２１上に本発明に係る薄膜キャパシタ２０ｂを接着層２３を介して接着し、そのコア層２１の上下面にプリプレグを配置し、押圧し硬化させてプリプレグ硬化層２４を形成する。コア基板を貫通するスルーホール２５を形成すると共に薄膜キャパシタ２０ｂの引き出し電極７、１０の表面を露出させるビアホール２８を開設する。ビアホール２８内壁面に形成されたＣｕめっき層２９を介して薄膜キャパシタ２０ｂの引き出し電極７、１０に接続された配線パターン２６を形成すると共に、スルーホール２５の内壁面にＣｕめっき層２７を形成しこれにより基板表裏面の配線パターン２６を電気的に接続する。プリプレグ硬化層２４を形成する際にその上に銅箔を設けるようにしてもよい。このようにして作製されたコア基板３０の表裏面にビルドアップ層３１を形成する。ビルドアップ層３１は、プリプレグ硬化層３２を形成しビアホール３３を形成した後、配線パターン３５とビアホール３３の内壁面を覆うＣｕめっき層３４を形成する工程を、１ないし複数回行うことによって形成される。
ビルドアップ層３１は、プリプレグ硬化層３２を用いて形成する方式に代え、薄い絶縁樹脂フィルムを貼り付ける方法、ワニスを塗布し硬化させる方法、感光性樹脂を塗布し露光・現像を行って膜形成と同時にビアホール形成行う方法等を用いてもよい。また、プリプレグ硬化層３２を形成する際に、その上に銅箔を設けるようにしてもよい。
【００２６】
図９は、本発明の薄膜キャパシタを内蔵した配線基板の第３の実施の形態を示す断面図である。本実施の形態は、本発明に係る薄膜キャパシタをフレキシブル配線基板内に実装した例に関する。内層パターン４２となる配線パターンを有する、ポリイミドフィルムのような樹脂フィルムで形成された樹脂層４１上に接着層２３を介して薄膜キャパシタ２０ａを固着し、その上に樹脂シートを積層し熱圧着して樹脂層４３を形成する。その後、基板を貫通するスルーホール４４を開設し基板表裏面に配線パターン４６を形成すると共に、スルーホール４４の内壁面に配線パターン４６と薄膜キャパシタ２０ａの引き出し電極７、１０や内層パターン４２とを接続するＣｕめっき層４５を形成する。樹脂層４３は、ワニスを塗布しこれを硬化させることによって形成してもよい。また、樹脂層４１として、その内層パターン４２が形成されていない側に予め銅箔を有するフィルムを使うことができる。さらに、樹脂層４３を形成する際にも銅箔付きの樹脂層を形成するようにしてもよい。
【００２７】
本実施の形態は、樹脂層４１、４３からなる厚さ１００μｍ以下のフレキシブル基板中に薄膜キャパシタを内蔵させたものであり、樹脂層各層の厚さはそれぞれ約５０μｍよりも薄いものである。そのため薄膜キャパシタの厚さは総厚で３５μｍ程度以下であることが望ましい。また薄膜キャパシタを埋め込むための樹脂層４３を構成する樹脂は熱可塑性を有することが望ましい。しかし樹脂層と薄膜キャパシタを一体化するプロセスにおいて薄膜キャパシタが破壊されなければ樹脂層３５は熱硬化性樹脂でも差し支えない。また樹脂層４３の表面の配線パターンと薄膜キャパシタの引き出し電極７ないし１０を基板貫通しないビアホールによって電気的に接続するようにしてもよい。
【００２８】
図１０は、本発明の薄膜キャパシタを内蔵した配線基板の第４の実施の形態を示す断面図である。本実施の形態は、本発明に係る、裏面電極引き出し型薄膜キャパシタをフレキシブル配線基板内に実装した例に関する。ポリイミドフィルムのような樹脂フィルムで形成された樹脂層４１上に形成された内層パターン４２上に、はんだまたは導電性塗料などからなる導電性接着層２３を介して薄膜キャパシタ２０ｃを固着し、その上に樹脂シートを積層し熱圧着して樹脂層４３を形成し薄膜キャパシタ２０ｃを埋め込む。そして、薄膜キャパシタ２０ｃの引き出し電極７の表面を露出されるビアホール４８を開け、さらに基板を貫通するスルーホール４４を開設する。その後、電解めっきにより、ビアホール４８内壁面にＣｕめっき層４９を、基板表裏面に配線パターン４６を形成すると共に、スルーホール４４の内壁面に配線パターン４６間や配線パターン４６と内層パターン４２を接続するＣｕめっき層４５を形成する。樹脂層４３は、ワニスを塗布しこれを硬化させることによって形成してもよい。また、樹脂層４１として、その内層パターン４２が形成されていない側に予め銅箔を有するフィルムを使うことができる。さらに、樹脂層４３を形成する際にも銅箔付きの樹脂層を形成するようにしてもよい。
【００２９】
図１１は、本発明の薄膜キャパシタを含む複合部品を内蔵した配線基板の第1の実施の形態を示す断面図である。本実施の形態は、本発明に係る薄膜キャパシタを含む複合部品を多層配線基板に内蔵した例に関する。図１１に示す複合部品内蔵多層配線基板は以下のように作製される。両面に内層パターン５４となる配線が形成されたコア層５１上に、本発明に係る薄膜キャパシタと薄膜抵抗が同一の基材上に形成された複合部品５０ａを、接着層５５を介して固着した後、コア層５１の上下面にプリプレグを配置し、加圧・加熱してプリプレグ硬化層５２を形成する。基板を貫通するスルーホール５６を形成すると共に薄膜キャパシタの引き出し電極７、１０および薄膜抵抗の引き出し電極１５の表面を露出させるビアホール５８を開設する。ビアホール５８内壁面に形成されたＣｕめっき層５９を介して薄膜キャパシタの引き出し電極７、１０に接続された配線パターン５３を形成すると共に、スルーホール５６の内壁面にＣｕめっき層５７を形成しこれにより配線基板の表面配線と内層ないし裏面配線とを電気的に接続するとともに、これらと薄膜抵抗の引き出し電極１５とを電気的に接続する。プリプレグ硬化層５２を形成する際にその上に銅箔を設けるようにしてもよい。本発明の薄膜キャパシタを内蔵した配線基板の第１の実施の形態と同様に、本実施の形態に用いられる薄膜キャパシタを含む複合受動部品はプリプレグ硬化層５２よりも薄いことが必須である。
【００３０】
【実施例】
次に、本発明の実施例について詳細に説明する。
[実施例１]
図１２に示すステンレス鋼製の固定枠６１、６２に、ベースフィルム６３として市販のポリイミドフィルム(厚さ５０μｍ)を固定した後、ＤＣスパッタ装置に導入し、フィルム上にＣｒ、W、Ｔｉ、ＰｔをそれぞれＣｒ：２０ｎｍ、W：５００ｎｍ、Ｔｉ：２０ｎｍ、Ｐｔ：２５０ｎｍの膜厚に成膜した。ここで、Ｃｒは密着電極（図１の２）、Ｗは高弾性電極（図１の３）、Ｔｉは密着電極（図１の３、４の間）、Ｐｔは耐酸化電極（図１の４）に対応する。Ｐｔ電極の上にＲＦスパッタ法でペロブスカイト構造を有するチタン酸ストロンチウム（ＳｒＴｉＯ₃）薄膜（図１の８）を２００ｎｍ厚に成膜し、さらにその上にＤＣスパッタ法で上部電極(図１の９)としてＰｔを２００ｎｍの膜厚に成膜した。成膜後、４００℃にてアニールを行った。次に、フォトリソグラフィ法により形成すべき上部電極のパターンのレジスト膜を形成し、イオンビームエッチング（ＩＢＥ）法でＰｔ膜をパターニングした。同様に、フォリソグラフィ法で形成すべき高誘電率誘電体膜のパターンのレジスト膜を形成し、化学エッチング法によってＳｒＴｉＯ₃膜をパターニングした。さらにフォトリソグラフィ法により下部電極（図１の５）のパターン状にレジスト膜を形成し、ＩＢＥ法により下部電極膜（Ｐｔ、Ｔｉ、W、Ｃｒ膜）をパターニングした。
【００３１】
次に、上部電極（図１の９）と電気的に接続される引き出し電極（図１の７）と下部電極（図１の５）を電気的に確実に絶縁させるため、エポキシ樹脂からなる感光性樹脂を塗布し露光・現像によりパターニングして厚さ約２μｍの絶縁層（図１の６）を形成した。次に、ＤＣスパッタ法でＴｉを約２０ｎｍ、Ｃｕを約１００ｎｍの順で全面に成膜しめっき下地層を形成した。Ｔｉ層はＣｕ膜の密着性を高めるために設けたものであり、この用途のために外にＣｒやＺｒを用いることもできる。次に、フォトリソグラフィ法により形成すべき引き出し電極形状の開口を有するレジスト膜を形成し、その開口に電解めっき法によってCuを１８μｍ成膜し、これを引き出し電極（図１の７、１０）とした。レジスト膜を除去し、露出しためっき下地層をエッチング除去した後に、最上層全面に感光性エポキシ樹脂を塗布し、露光・現像を行って厚さ約２μｍの保護層（図１の１１）を形成した。
【００３２】
その後、固定枠６１、６２から取り外し、外形に沿って切断して、個々の薄膜キャパシタとした。このようにして作製した薄膜キャパシタを上から見た図を図１３に示す。上からは保護層１１とその開口１１ａ、１１ｂに露出した引き出し電極７、１０を見ることができだけである。開口１１ａ、１１ｂのサイズは０．５ｍｍ□とした。図１３中の点線は上部電極９の外形を示し、この面積および高誘電率誘電体薄膜８の厚さによって薄膜キャパシタの静電容量が決まる。薄膜キャパシタの上部電極９のサイズを０．１ｍｍ×０．１ｍｍ〜１ｍｍ×１ｍｍの範囲で変えたときの薄膜キャパシタの静電容量と誘電損失をＬＣＲメータで測定した。
測定された静電容量から式（１）によって高誘電率薄膜８の比誘電率εｒを求めたところεｒ＝８０〜８５という数値が得られた。有効面積Ｓが小さい方がやや高めのεｒが得られた。誘電損失はｆ＝１ｋＨｚで０．００８、ｆ＝１ＭＨｚで０．０１０であった。
この結果からＳｉウエハ等のリジッドな基板上に形成した場合とほとんど同等の比誘電率εｒが得られ、かつ誘電損失も実用的な数値であるといえる。
εｒ＝Cｄ／ε₀S・・・・・・・・・・・・・・・・・・・・・・（１）
ここで、Cは静電容量（F）、ｄは高誘電率薄膜の厚さ（ｍ）、ε₀は真空中での誘電
率、Sは上部電極９の面積（ｍ²）である。
【００３３】
［実施例２］
実施例1と同様に、図１２に示すように、市販のポリイミドフィルム（厚さ５０μｍ）を固定枠６１、６２に固定した後、ＤＣスパッタ装置に導入し、フィルム上にCr、Ｗ、Ｔｉ、ＰｔをそれぞれCr：２０ｎｍ、Ｗ：１０００ｎｍ、Ｔｉ：２０ｎｍ、Ｐｔ：２５０ｎｍの膜厚に成膜した。ここでＣｒは密着電極（図２の２）、Ｗは高弾性電極（図２の３）、Ｔｉは密着電極（図２の３、４の間）、Ｐｔは耐酸化電極（図２の４）に対応する。Ｐｔ電極の上にゾルゲル法でペロブスカイト構造を有するジルコン酸チタン酸ランタン鉛（（Ｐｂ_0.94Ｌａ_0.06）（Ｚｒ_0.5Ｔｉ_0.5）Ｏ₃）薄膜（図２の８）を膜厚２００ｎｍに成膜し、さらにその上にＤＣスパッタ法で上部電極(図２の９)となるＰｔを２００ｎｍ厚に成膜した。成膜後、ジルコン酸チタン酸ランタン鉛を４５０℃でアニールした。次に、フォトリソグラフィ法により形成すべき上部電極形状のパターンのレジスト膜を形成し、イオンビームエッチング（ＩＢＥ）法でＰｔ膜をパターニングした。同様にフォトリソグラフィ法によりレジスト膜を形成し、化学エッチング法によってジルコン酸チタン酸ランタン鉛膜をパターニングした。さらにフォトリソグラフィ法によりレジスト膜を形成し、ＩＢＥ法により下部電極膜（Ｐｔ、Ｔｉ、Ｗ、Cr膜）をパターニングして、下部電極（図２の５）、引き出し電極受け（図２の５ａ）を作成した。
【００３４】
絶縁層（図２の６）、引き出し電極（図２の７、図２の１０）および保護層(図２の１１)は実施例１で述べた方法と同様にして形成した。薄膜キャパシタの上部電極のサイズを実施例１と同様に０．１ｍｍ×０．１ｍｍ〜１ｍｍ×１ｍｍとしたときの静電容量と誘電損失をＬＣＲメータで測定し、（１）式にしたがって比誘電率εｒを計算したところ、εｒ＝２７０〜３２０であった。実施例１のチタン酸ストロンチウム薄膜の比誘電率よりは高いものの、Ｓｉウエハなどのリジッドな基板上で作製したジルコン酸チタン酸ランタン鉛薄膜の比誘電率（εｒ＝８００〜１０００）よりははるかに低い。これはアニール温度が低いことによるものと推定される。なお、誘電損失はｆ＝１ｋＨｚで０．０２、ｆ＝１ＭＨｚで０．０３５であった。
【００３５】
［実施例３］
本実施例は、図３に示した裏面電極引き出し型キャパシタに係る。シリコン基板上に電子ビーム蒸着法によりＴｉ／Ｃｕを蒸着してめっき下地層を形成し、フォトリソグラフィ法により引き出し電極１２の形成領域に開口を有するレジスト膜を形成し電解めっき法によって引き出し電極１２となる、厚さ２５μｍの導電性ポストを形成した。レジスト膜を除去し、露出しためっき下地層を除去した後、基板上にポリイミドのワニスをスピンコート法によって塗布し、所定の乾燥・キュアを行うことによってフレキシブル基材1を形成した。引き出し電極１２の厚さはこのフレキシブル基材1よりも若干厚く形成しておくことが好ましい。その後、引き出し電極１２を研磨することによって、引き出し電極１２とフレキシブル基材1の表面との段差をなくした。引き出し電極１２が埋設されたフレキシブル基材1上に、スパッタ法により密着電極２（Ｔｉ）、高弾性電極３（Ｒｕ）および耐酸化電極４（Ｐｄ）をそれぞれ５０ｎｍ、４００ｎｍ、２００ｎｍの膜厚に堆積して下部電極５を形成した。耐酸化電極４上にＣＶＤ法により酸化タンタル（Ｔａ₂Ｏ₅）を５０ｎｍの膜厚に堆積して高誘電率薄膜８を形成した。その上にスパッタ法で上部電極９となるＰｔを１５０ｎｍ厚に成膜した。成膜後、フォトリソグラフィ法により上部電極９となるＰｔ膜と高誘電率薄膜８のパターニングを行ない、絶縁層６を形成した後、実施例１と同様の方法を用いて上部電極９上に引き出し電極７を形成した。最後に、仮基板であるシリコン基板を剥離除去しフレキシブル基材を切断分離して個々のキャパシタを得た。
【００３６】
［実施例４］
本実施例は、図４に示した積層型キャパシタに係る。フレキシブル基材1となる厚さ３０μｍのポリイミドフィルムをシリコンウェハ上に耐熱性の高い接着剤を用いて固定した。シリコン以外にもガラス、サファイア、セラミック、金属などのリジットな基板であれば用いることができる。ポリイミドフィルム上に、スパッタ法により、密着電極２（Ｔｉ）、高弾性電極３（Ｗ）、耐酸化電極４（Ｐｔ）をそれぞれ20ｎｍ、500ｎｍ、250ｎｍの膜厚に堆積して下部電極5を形成した。Ｐｔ電極の上に、高誘電率薄膜８としてゾルゲル法でペロブスカイト構造を有するジルコン酸チタン酸鉛（Ｐｂ（Ｚｒ_0.5Ｔｉ_0.5）Ｏ₃）薄膜を膜厚２００ｎｍに形成し、フォトリソグラフィ法によりパターニングし、さらにスパッタ法で上部電極９となるＰｔを２００ｎｍ厚に成膜しパターニングした。上部電極９のパターニングには、フォトエッチング法やリフトオフ法を用いることができる。その後、さらに高誘電率薄膜８′となるジルコン酸チタン酸鉛薄膜をゾルゲル法で膜厚２００ｎｍに形成し、フォトリソグラフィ法によりパターニングした後、スパッタ法により、密着電極２（Ｔｉ：20ｎｍ）、耐酸化電極４（Ｐｔ：250ｎｍ）を堆積しパターニングして下部電極５′を形成した。下部電極５′のパターニングには、フォトエッチング法やリフトオフ法を用いることができる。その後、さらに高誘電率薄膜８″となるジルコン酸チタン酸鉛薄膜をゾルゲル法で膜厚２００ｎｍに形成し、フォトリソグラフィ法によりパターニングした後、スパッタ法により、Ｐｔを２００ｎｍ厚に成膜し同様にパターニングして上部電極９′を形成した。そして、最下層の電極層をパターニングして下部電極５と引き出し電極受け５ａを形成した。最下層の電極層のパターニングは、高誘電率薄膜８の形成前に行うことができる。その場合、リフトオフ法によりパターニングするようにしてもよい。ジルコン酸チタン酸鉛薄膜を４５０℃で一括アニールした後、エポキシ系の感光性樹脂を用いて、絶縁層６を形成し、その後に、実施例1と同様の方法を用いてＣｕを主体とする引き出し電極７、１０を形成した。最後に、フレキシブル基材をシリコンウェハより剥離し、個々の薄膜キャパシタに切断分離した。
【００３７】
［比較例］
実施例１と同一プロセスによってチタン酸ストロンチウム薄膜を高誘電率薄膜８に用いた薄膜キャパシタを作製した。実施例１と異なる点は下部電極５の層構成である。比較例では、Ｔｉ：２０ｎｍ、Ｐｔ：５００ｎｍを下部電極とした。ここで、Ｔｉは密着電極（図１の２）、Ｐｔは耐酸化電極（図１の４）に対応し、高弾性電極３に対応する電極を設けていない。高誘電率薄膜８としてチタン酸ストロンチウムを下部電極５上に成膜しアニールを行った時点で図１４に示したような誘電体薄膜の「しわ」が観察された。その後、実施例１と同一プロセスによって薄膜キャパシタの静電容量と誘電損失を測定できるようにしたところ、２０個測定して全数がショートモードの不良であった。これは高誘電率薄膜形成の際に発生した応力によってフレキシブル基板１にしわが発生し、結果として高誘電率薄膜８にクラック等が発生しショートしたものと推察される。
【００３８】
［実施例５］
本実施例は図５に示した本発明の薄膜キャパシタを含む複合受動部品の製造方法に関わる。図１５〜１７は、その製造方法を示す工程順の断面図である。最初に、図１５（ａ）に示されるシリコンウエハ１ａ上にポリイミドワニスをスピンコート法で塗布し、４００℃窒素雰囲気中でキュアすることでフレキシブル基材１を形成した〔図１５（ｂ）〕。続いて、密着層、高弾性金属、耐酸化性金属を順次堆積して下部電極膜５ｂを形成し〔図１５（ｃ）〕、高誘電率薄膜８を堆積し〔図１５（ｄ）〕、上部電極膜９ａを成膜した〔図１５（ｅ）〕。上部電極膜９ａをパターニングして上部電極９を形成し〔図１６（ｆ）〕、高誘電率薄膜８をパターニングした〔図１６（ｇ）〕後、引き続き下部電極膜５ｂをパターニングして下部電極５を形成した〔図１６（ｈ）〕。その後、エポキシ系感光性樹脂により絶縁層６を形成した〔図１６（ｉ）〕。なお、下部電極膜５ｂを堆積する工程から絶縁層６を形成するまでの工程〔図１５（ｃ）〜図１６（ｉ）〕は、実施例１と同じである。次に、密着電極１４ａと薄膜抵抗体１４ｂとなるＴｉＮ膜（厚さ５０ｎｍ）を反応性スパッタ法により堆積し、引き続き通常のＤＣスパッタ法によりＣｕ（厚さ２００ｎｍ）を連続して成膜した。次に、フォトリソグラフィ法により形成すべき引き出し電極形状の開口を有するレジスト膜を形成し、その開口に電解めっき法によってCuを１２−１８μｍ厚に成膜し、引き出し電極７、１０、１５を形成した。レジスト膜を除去し、露出しためっき下地であるＣｕ層を、ＴｉＮを溶かさないエッチング液（例えば硫酸＋過酸化水素水）を用いて除去した後に、フォトリソグラフィ法により抵抗パターンを形成するためのレジスト膜を形成し、開口部のＴｉＮ膜をエッチング除去した後にレジストを剥離した〔図１６（ｊ）〕。次に、最上層全面に感光性エポキシ樹脂を塗布し、露光・現像を行って厚さ約２μｍの保護層を形成した〔図１７（ｋ）〕。最後に、薄膜キャパシタと薄膜抵抗が形成されたフレキシブル基材をシリコンウエハ１ａから剥離した〔図１７（ｌ）、図１７（ｍ）〕。そして個々の複合受動部品に切断した〔図１７（ｎ）〕。一例として１０００ｐＦの薄膜キャパシタ１０個と５０ｋΩの薄膜抵抗１個を同時に形成した複合受動部品を上から見た図を図１８に示す。図１８において、７１は薄膜キャパシタ部、７２は薄膜抵抗部である。この複合受動部品のサイズは縦５．７６ｍｍ、横３．８６ｍｍ、厚さ４０μｍ（フレキシブル基材〜保護層）であった。
薄膜抵抗に代えてあるいは薄膜抵抗とともにインダクタを形成することができる。インダクタは、スパッタリングされたＴｉＮ層とCu層との積層膜を用いて形成することができる。あるいは、引き出し電極を形成するＣｕめっき層を含めた導電膜によって形成するようにしてもよい。
【００３９】
［実施例６］
図１９、２０は、図６に示した本発明の薄膜キャパシタを含む複合受動部品の製造方法を示す工程順の断面図である。実施例５と同様の方法を用いて、シリコンウエハ１ａ上にフレキシブル基材１を形成し、密着層、高弾性金属、耐酸化性金属からなる下部電極膜５ｂを形成した後、高誘電率薄膜８を堆積し、上部電極膜９ａを成膜した〔図１９（ａ）〕。上部電極膜９ａをパターニングして上部電極９を形成し、高誘電率薄膜８をパターニングした後、引き続き下部電極膜５ｂをパターニングして下部電極５とスパイラルインダクタ１６を形成した〔図１９（ｂ）〕。その後、エポキシ系感光性樹脂により、薄膜キャパシタとスパイラルインダクタ１６の引き出し電極形成領域に開口を有する絶縁層６を形成した〔図１９（ｃ）〕。次に、膜厚５０ｎｍのＴｉＮ膜と膜厚２００ｎｍのCu層をスパッタ法により堆積して、下地膜１３を形成した〔図１９（ｄ）〕。
次に、フォトリソグラフィ法により形成すべき引き出し電極形状の開口を有するレジスト膜１８を形成し、その開口に電解めっき法によってCuを１２−１８μｍ厚に成膜し、薄膜キャパシタの引き出し電極７、１０と、スパイラルインダクタ１６の引き出し電極１７を形成した〔図２０（ｅ）〕。レジスト膜１８を除去し、露出した下地膜１３をエッチング除去した〔図２０（ｆ）〕。次に、最上層全面に感光性エポキシ樹脂を塗布し、露光・現像を行って厚さ約２μｍの保護層１１を形成した〔図２０（ｇ）〕。最後に、薄膜キャパシタとスパイラルインダクタ１６が形成されたフレキシブル基材１をシリコンウエハ１ａから剥離した〔図２０（ｈ）〕。
スパイラルインダクタに代えてあるいはスパイラルインダクタとともに薄膜抵抗を形成することができる。薄膜抵抗は、３層の導電膜からなる下部電極膜５ｂを用いて、あるいは密着層のみを用いて若しくは密着層と高弾性金属膜とを用いて形成することができる。
【００４０】
［実施例７］
実施例２で作製した薄膜キャパシタを内蔵した配線基板を次のようにして作製した。図７に示すように、多層配線基板のコア基板として両面に配線パターンを形成した厚さ０．４〜０．６ｍｍのコア基板２１の一方の面に薄膜キャパシタ２０ａを絶縁性の接着剤２３を用いて接着した。次に、コア基板の上下面に厚さ０．１〜０．３ｍｍの銅張りのプリプレグまたはガラスクロスを含まない樹脂コート銅（ＲＣＣ：resin coated copper）を配し、熱圧着により一体化した。次に、０．３〜０．３５ｍｍφのドリルによって基板を貫通するスルーホール２５を開け、その後通常のプレイテッドスルーホール形成方法に従い、活性化処理、無電解めっき、電解めっき、選択的エッチングを行って、配線パターン２６を形成すると共に、スルーホール２５内壁面に厚さ１８〜３０μｍのＣｕめっき層２７を形成した。表面の配線パターン２６、２６にプローブを当ててＬＣＲメータで基板に内蔵した薄膜キャパシタの静電容量および誘電損失を測定したところ、内蔵前の薄膜キャパシタの静電容量が２２５０ｐＦ、誘電損失が０．０１（ｆ＝１ｋＨｚ、２０個平均）であったものが、静電容量２０８０ｐＦ、誘電損失０．０１２（いずれもｆ＝１ｋＨｚ、２０箇所平均）であった。基板内蔵前後で静電容量および誘電損失の差はほとんどないといえる。
【００４１】
［実施例８］
実施例１で作製した薄膜キャパシタを内蔵した多層ビルドアップ基板を次のようにし作製した。図８に示すコア基板３０を、実施例５にて説明した多層配線基板の製造方法と同様の方法により作製した。但し、実施例５とは異なり、薄膜キャパシタ２０ａの引き出し電極７および１０の表面を露出させるビアホール２８をレーザ光により開設し、その内壁面に形成したＣｕめっき層２９によって、引き出し電極７、１０と配線パターン２６との電気的接続を実現している。而して、薄膜キャパシタ２０ａの引き出し電極１０については、高誘電率薄膜８および下部電極５の直上にないためにビアホールに代え貫通スルーホールを用いて配線パターン２６ないし内層パターン２２と電気的に接続させても差し支えない。薄膜キャパシタ２０ａを内蔵したコア基板３０の上下面に感光性絶縁樹脂を塗布し露光・現像を行ってビアホール３３が開けられた絶縁層（プリプレグ硬化層３２に相当）を形成し、Ｃｕめっき層３４、配線パターン３５を形成して１層分のビルドアップ層を作成した。以下、このプロセスを必要回数繰り返すことによってビルドアップ層３１を形成して、薄膜キャパシタ内蔵ビルドアップ基板を作製した。
【００４２】
ビルドアップ基板表面の配線パターン３５、３５にプローブを当ててＬＣＲメータで基板に内蔵した薄膜キャパシタの静電容量および誘電損失を測定したところ、内蔵前の薄膜キャパシタの静電容量が８８０ｐＦ、誘電損失が０．００８（ｆ＝１ｋＨｚ、２０個平均）であったものが、静電容量８５０ｐＦ、誘電損失０．０１（いずれもｆ＝１ｋＨｚ、２０箇所平均）であった。ビルドアップ基板に薄膜キャパシタを内蔵しても、内蔵前後で静電容量および誘電損失の差はほとんどないといえる。
【００４３】
［実施例９］
実施例２で作製した薄膜キャパシタを次のような方法でフレキシブル配線基板に内蔵した。図９に示すように、片側に銅箔を有し他の片側に予め内層パターン４２となる配線パターンが形成されている厚さ約５０μｍのポリイミドフィルム（樹脂層４１）上に薄膜キャパシタ２０ａを接着剤２３で固定し、その上に片面がＣｕでコーティングされた厚さ５０〜７０μｍの熱可塑性樹脂フィルムを、Ｃｕコーティングされていない面を薄膜キャパシタに覆い被せるようにして積層し熱圧着することによって一体化して樹脂層４３を形成した。ドリルでスルーホール４４を開設し、その後通常のプレイテッドスルーホール形成方法により、基板表裏面に配線パターン４６を形成すると共に、スルーホール４４の内壁面に銅めっき層４５を形成した。ここで内蔵した薄膜キャパシタのベースとなるフレキシブル基材１の厚さは、実施例２では５０μｍとしたがここでは２０μｍとして、薄膜キャパシタ全体の厚さが３５μｍ以下となるようにした。
【００４４】
内蔵した薄膜キャパシタの静電容量および誘電損失を、基板表面の配線パターン４６、４６にプローブをに当てることによって測定した。測定した２０箇所のうち、２箇所に絶縁不良が発生していた。これは薄膜キャパシタのフレキシブル基材１が実施例１および２で用いたものよりも薄くかつ樹脂層４３の厚さが実施例５ないし４におけるプリプレグ硬化層２４よりも薄いために、熱圧着工程において薄膜キャパシタの高誘電率薄膜８に高い応力が負荷されて絶縁破壊に至ったためと推定される。しかし９０％の歩留まりで絶縁不良のないキャパシタ内蔵基板が得られた。内蔵前の薄膜キャパシタの静電容量が２２５０ｐＦ、誘電損失が０．０１（ｆ＝１ｋＨｚ、２０個平均）であったものが、内蔵後は静電容量が１９６０ｐＦ、誘電損失が０．０１２（いずれもｆ＝１ｋＨｚ、１８箇所平均）となった。実施例５よりも基板内蔵による静電容量の減少がわずかに大きい結果となった。
【００４５】
以上好ましい実施例について説明したが、本発明はこれら実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲内において適宜の変更が可能なものである。例えば、実施例では、絶縁層や保護層を感光性樹脂を用いて形成していたが、これに代え感光性ガラスを用いて絶縁層や保護層を形成するようにしてもよい。あるいは、非感光性材料により形成するようにしてもよい。
【００４６】
【発明の効果】
本発明の薄膜キャパシタは、誘電体薄膜の下層に高弾性材料からなる電極層を配したものであるので、薄いフレキシブルな基材上に薄い高誘電率誘電体薄膜を信頼性高く形成することが可能になり、薄くかつ大容量の薄膜キャパシタを信頼性高く提供することが可能になる。したがって、本発明によれば、大容量キャパシタを内蔵した配線基板の薄型化が実現できると共に、大容量キャパシタを内蔵したフレキシブル基板を提供することが可能になる。また、フレキシブル基材上に薄膜キャパシタを構成することができることにより薄膜キャパシタを配線基板内に実装する際に薄膜キャパシタを損傷しないようにすることができる。また、本発明の薄膜キャパシタには、１μｍ以上の膜厚の引き出し電極が形成されるので、熱サイクルによって破壊されない、低抵抗で接続信頼性の高いスルーホール接続を実現することができる。また、本発明の薄膜キャパシタを含む複合受動部品およびその製造方法によって、大容量キャパシタと薄膜抵抗ないし薄膜インダクタを高密度に同一のフレキシブル基材上に形成することが可能になり、かつ当該複合受動部品を内蔵した配線基板を小さくすることが可能になる。
【図面の簡単な説明】
【図１】本発明の薄膜キャパシタの第１の実施の形態を示す平面図と断面図。
【図２】本発明の薄膜キャパシタの第２の実施の形態を示す平面図と断面図。
【図３】本発明の薄膜キャパシタの第３の実施の形態を示す断面図。
【図４】本発明の薄膜キャパシタの第４の実施の形態を示す断面図。
【図５】本発明の薄膜キャパシタを含む複合受動部品の第１の実施の形態を示す断面図。
【図６】本発明の薄膜キャパシタを含む複合受動部品の第２の実施の形態を示す断面図。
【図７】本発明の薄膜キャパシタ内蔵配線基板の第１の実施の形態を示す断面図。
【図８】本発明の薄膜キャパシタ内蔵配線基板の第２の実施の形態を示す断面図。
【図９】本発明の薄膜キャパシタ内蔵配線基板の第３の実施の形態を示す断面図。
【図１０】本発明の薄膜キャパシタ内蔵配線基板の第４の実施の形態を示す断面図。
【図１１】本発明の薄膜キャパシタを含む受動部品内蔵配線基板の第１の実施の形態を示す断面図。
【図１２】本発明の薄膜キャパシタの作製工程を説明するための上面図と断面図。
【図１３】本発明の実施例１、２により形成された薄膜キャパシタの上面図。
【図１４】比較例の薄膜キャパシタの製造工程における高誘電率薄膜形成後の表面状態を示す金属顕微鏡写真。
【図１５】本発明の実施例５の複合受動部品の製造方法を示す工程順の断面図（その１）。
【図１６】本発明の実施例５の複合受動部品の製造方法を示す工程順の断面図（その２）。
【図１７】本発明の実施例５の複合受動部品の製造方法を示す工程順の断面図（その３）。
【図１８】本発明の実施例５で作製した複合受動部品の上面図。
【図１９】本発明の実施例６の複合受動部品の製造方法を示す工程順の断面図（その１）。
【図２０】本発明の実施例６の複合受動部品の製造方法を示す工程順の断面図（その２）。
【符号の説明】
１フレキシブル基材
１ａシリコンウエハ
２密着電極
３高弾性電極
４耐酸化電極
５下部電極
５ａ引き出し電極受け
５ｂ下部電極膜
６絶縁層
７、１０、１２、１５、１７引き出し電極
７ａ、７ｂコンタクト部
８高誘電率薄膜
９上部電極
９ａ上部電極膜
１１保護層
１１ａ、１１ｂ、１１ｃ、１１ｄ開口
１３下地膜
１４ａ密着電極
１４ｂ薄膜抵抗体
１６スパイラルインダクタ
１８レジスト膜
２０ａ、２０ｂ、２０ｃ薄膜キャパシタ
２１、５１コア層
２２、４２、５４内層パターン
２３、５５接着層
２４、３２、５２プリプレグ硬化層
２５、４４、５６スルーホール
２６、３５、４６、５３配線パターン
２７、２９、３４、４５、４９、５７、５９Ｃｕめっき層
２８、３３、４８、５８ビアホール
３０コア基板
３１ビルドアップ層
４１、４３樹脂層
４７導電性接着層
５０ａ複合部品
６１、６２固定枠
６３ベースフィルム
７１薄膜キャパシタ部
７２薄膜抵抗部[0001]
BACKGROUND OF THE INVENTION
The present invention includes a thin film capacitor formed on an insulating substrate and a composite passive component including the thin film capacitor, in particular, a thin film capacitor and a thin film capacitor having a structure suitable for being mounted inside an electronic circuit board made of an organic material. The present invention relates to a composite passive component, a method of manufacturing the same, a thin film capacitor, and a wiring board incorporating the composite passive component including the thin film capacitor.
[0002]
[Prior art]
In recent years, the market demand for high-density mounting of passive components has been increasing in order to improve the performance of electronic devices. In order to meet such demands, passive components are 1005 size (L: 1.0 mm x W: 0.5 mm), 0603 size (L: 0.6 mm x W: 0.3 mm) Yes. Furthermore, a passive component of 0402 size (L: 0.4 mm × W: 0.2 mm) tends to be developed. However, on the other hand, there is a recognition that further chip size reduction is difficult from the technical and mounting machine side. From such a background, a technique for reducing the board area by incorporating passive components in an electric circuit board has attracted attention. In particular, since the capacitor is one of the most frequently used components constituting the electronic circuit, if the capacitor can be built in the electronic circuit board, a particularly great effect can be expected in reducing the area of the board.
[0003]
As a technique for embedding a capacitor in an electronic circuit board, a technique in which an electronic component is embedded in a single layer of a multilayer board as disclosed in Japanese Patent Application Laid-Open Nos. 2000-243873 and 11-45955, Examples include those using an insulating layer constituting a multilayer substrate as disclosed in Kaihei 2000-277922 and JP-A-2001-77539 as a dielectric layer of a capacitor. In particular, when an insulating layer is used as a capacitor, a technique for increasing the relative dielectric constant by applying a resin in which an inorganic filler is mixed in the insulating layer has been proposed.
[0004]
[Problems to be solved by the invention]
However, when embedding an electronic component by providing a cavity in one layer of a multilayer substrate, assuming that the thickness of the electronic component is a normal chip component and 0.3 mm is the lower limit, it is assumed that the printed circuit board prepregs are stacked one layer at a time However, assuming that the minimum thickness of the prepreg is 0.1 mm, it becomes impossible to make the thickness of the substrate 0.5 mm or less. Further, when an insulating layer is used as a capacitor, it is extremely difficult to make the relative dielectric constant 2 to 4, even if an inorganic filler is mixed, and to make the relative dielectric constant 30 or more, and the thickness of one layer is at least several. Because there is 10μm, 1mm ² The per-capacitance can be obtained only 9 pF (assuming that the insulating layer thickness is 20 μm and the relative dielectric constant is 20).
[0005]
In order to solve the above-described problems, it is effective to incorporate a thin film capacitor that is thinner than a chip component and has a higher capacity per unit in the substrate. Many techniques relating to thin film capacitors have been reported, but most of them are techniques relating to thin film capacitors formed on rigid Si substrates and ceramic substrates. A thin film capacitor formed on a rigid substrate has a merit that a dielectric material having a higher relative dielectric constant can be used because a dielectric thin film can be formed at a temperature of 500 to 600 ° C. or higher. Since the thickness of the substrate is usually 0.1 mm or more, it is difficult to make the thickness of the multilayer substrate incorporating the substrate thinner than 0.5 mm. In addition, when a thin film capacitor formed on a rigid substrate is built inside a resin substrate such as a multilayer wiring substrate, the rigid substrate is damaged by thermocompression bonding in the manufacturing process of the resin substrate, for example, the multilayer wiring substrate. There is a fear.
[0006]
On the other hand, thin-film capacitors formed on flexible substrates such as resin and metal foil can reduce the thickness of the substrate, and the flexible substrate is not damaged even by thermocompression bonding in the multilayer wiring board manufacturing process. There are benefits. Regarding a thin film capacitor formed on a flexible substrate, Japanese Patent Application Laid-Open No. 59-135714 discloses a technique for forming a high dielectric thin film by providing a metal thin film on a flexible film made of an organic polymer. . JP-A-2000-357631 discloses a flexible thin film capacitor (= capacitor) in which an adhesive film, preferably a flexible substrate made of an organic polymer or metal foil, an inorganic high dielectric film, and a metal electrode film are firmly bonded. A technique for providing a metal oxide adhesive film is disclosed.
[0007]
However, in order to improve the reliability of a thin film capacitor in which a high dielectric constant thin film is formed on a flexible base material such as an organic polymer film or a metal foil, as described in JP-A-2000-357631, Increasing the adhesion of metal films and high-dielectric thin films is an effective measure, but in forming high-dielectric thin films, dielectric thin films are formed by the stress generated when annealing is performed at a temperature higher than the cure temperature of the resin. There was a need for a means that would not deform itself, in other words, that the dielectric thin film itself would not be damaged.
Furthermore, when not only thin-film capacitors but also resistors and inductors are built in the wiring board, it is necessary to secure a certain interval between the built-in passive components if each capacitor, resistor and inductor passive component is built in one by one. Therefore, there is still room for improvement in area saving of the passive component built-in substrate.
[0008]
As one method for incorporating a thin film capacitor in an insulating substrate such as a wiring substrate, Japanese Patent Application Laid-Open No. 2001-168534 discloses that a terminal electrode is formed at both ends of a thin film capacitor and a through hole penetrating the terminal electrode is used to form the insulating substrate. A technique for connecting to an inner layer electrode or an outer layer electrode is disclosed. In this case, the Cu layer formed on the inner surface of the through hole and the terminal electrode of the thin film capacitor need to be electrically connected. However, since the thickness of the lower electrode and the upper electrode formed by the thin film device can only be about 1 μm at most, the connection reliability between the Cu layer on the inner wall of the through hole and the thin film capacitor electrode cannot be sufficiently secured. It was.
An object of the present invention is to solve the above-mentioned problems of the prior art. The purpose of the present invention is to firstly characterize a thin (for example, 0.1 mm or less) thin film capacitor that can be mounted on a flexible wiring board. Secondly, it is possible to provide such a thin thin film capacitor in a wiring board with high connection reliability.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, in a thin film capacitor in which a lower electrode, a dielectric thin film, and an upper electrode are laminated on a substrate having a thickness of 2 μm or more and 100 μm or less, the lower electrode includes the A first contact electrode in contact with the substrate, an oxidation resistant electrode in contact with the dielectric thin film, and a Young's modulus higher than the oxidation resistance electrode provided between the first contact electrode and the oxidation resistance electrode. A highly elastic electrode made of a material having The first contact electrode is formed of any one of Ti, Cr, and Zr, and the highly elastic electrode is formed of any of Ir, Ru, Rh, W, Mo, Fe, Ni, and Co. A thin film capacitor is provided.
In order to achieve the above object, according to the present invention, in a thin film capacitor in which a lower electrode, a dielectric thin film, and an upper electrode are laminated on a substrate having a thickness of 2 μm or more and 100 μm or less, the lower electrode includes: A first contact electrode in contact with the substrate, an oxidation resistant electrode in contact with the dielectric thin film, and a Young higher than the oxidation resistance electrode provided between the first contact electrode and the oxidation resistant electrode. A highly elastic electrode made of a material having The first contact electrode is formed of any one of Ti, Cr, and Zr, and the highly elastic electrode is formed of any of Ir, Ru, Rh, W, Mo, Fe, Ni, and Co. A thin film resistor or an inductor or a composite passive component characterized in that both the thin film resistor and the inductor are formed on the same substrate is provided.
[0010]
In order to achieve the above object, according to the present invention,
In a thin film capacitor in which a lower electrode, a dielectric thin film, and an upper electrode are stacked on a substrate having a thickness of 2 μm or more and 100 μm or less, the lower electrode includes a first contact electrode that contacts the substrate, and the dielectric An oxidation-resistant electrode in contact with the thin film, a highly elastic electrode made of a material having a higher Young's modulus than the oxidation-resistant electrode, provided between the first contact electrode and the oxidation-resistant electrode, and the oxidation-resistant electrode; A second contact electrode is formed between the oxidation-resistant electrode and the highly elastic electrode, and the first and second contact electrodes are formed of any one of Ti, Cr, and Zr, and the highly elastic electrode Is formed of any one of Ir, Ru, Rh, W, Mo, Fe, Ni, and Co , And composite passive components including thin film capacitors.
And preferably, the film thickness of the highly elastic electrode is preferably 300 nm or more, more preferably 400 nm or more, or more than twice the film thickness of the dielectric thin film. Preferably, the highly elastic electrode is formed of any one of Ir, Ru, Rh, W, Mo, Fe, Ni, Co, and Ta. More preferably, a resin flexible substrate is used as the insulating substrate.
[0012]
In order to achieve the above object, according to the present invention, the substrate is in contact with the substrate having a thickness of 2 μm or more and 100 μm or less. Formed of Ti, Cr, or Zr Formed on the first contact electrode and the first contact electrode; Formed of any one of Ir, Ru, Rh, W, Mo, Fe, Ni, Co, Forming a lower electrode having a highly elastic electrode having a film thickness of 300 nm or more and an oxidation-resistant electrode made of a material having a Young's modulus lower than that of the highly elastic electrode formed on the highly elastic electrode; Forming a dielectric thin film on the lower electrode, forming an upper electrode on the dielectric thin film, patterning the upper electrode, patterning the dielectric thin film, and the lower electrode There is provided a method of manufacturing a thin film capacitor, characterized by comprising: patterning so as to occupy an area larger than that of the dielectric thin film.
In order to achieve the above object, according to the present invention, the substrate is in contact with the substrate having a thickness of 2 μm or more and 100 μm or less. Formed of Ti, Cr, or Zr Formed on the first contact electrode and the first contact electrode; Formed of any one of Ir, Ru, Rh, W, Mo, Fe, Ni, Co, Forming a lower electrode having a highly elastic electrode having a film thickness of 300 nm or more and an oxidation-resistant electrode made of a material having a Young's modulus lower than that of the highly elastic electrode formed on the highly elastic electrode; Forming a dielectric thin film on the lower electrode, forming an upper electrode on the dielectric thin film, patterning the upper electrode, patterning the dielectric thin film, and the lower electrode Patterning so as to occupy a larger area than the dielectric thin film, forming an insulating layer using a photosensitive resin or photosensitive glass, and patterning the insulating layer so as to cover the entire surface of the lower electrode. And a step of forming the adhesion layer of the extraction electrode and the thin film resistor with the same material, and a step of simultaneously forming the extraction electrode and the inductor with the same material. The method of manufacturing a composite passive components including a thin film capacitor characterized the door, is provided.
[0013]
In order to achieve the above object, according to the present invention, the thin film capacitor or a composite passive component including the thin film capacitor is embedded in a resin substrate, and the lower electrode of the thin film capacitor has a via hole reaching the thin film capacitor. Alternatively, the thin film capacitor is drawn out either through a through hole penetrating the thin film capacitor or a conductive pattern to which the thin film capacitor is fixed, and the upper electrode of the thin film capacitor penetrates the via hole reaching the thin film capacitor or the thin film capacitor. Each electrode of the thin film resistor and spiral inductor is drawn through either the through hole or the via hole reaching the thin film resistor and spiral inductor or the through hole penetrating the thin film resistor and spiral inductor. Wiring board with a built-in composite passive components including thin film capacitor and a thin film capacitor, characterized in that has been issued, is provided.
[0014]
[Action]
In the thin film capacitor of the present invention, a thick highly elastic electrode made of a high Young's modulus material is provided as a part of the lower electrode below the dielectric thin film. As a result, the stress generated when the dielectric thin film is formed at a temperature higher than the curing temperature of the resin can be relaxed. Such an effect can be expected from a film thickness of 300 nm or more, and the effect is more sure from 400 nm or more. However, it is not a good idea to make the film thickness thicker than 1.5 μm. This is because even if the thickness is more than a certain value, an improvement in the stress relaxation effect cannot be expected, and the film formation time becomes longer. Thus, it becomes possible to anneal the dielectric thin film at a high temperature without generating a high stress, so that a high capacitance density (approximately 30 pF / mm) is achieved. ² The above can be realized. In addition, by using a flexible base material of 2 μm or more and 100 μm or less, for example, 10 to 70 μm as a base material, it is damaged in the resin substrate manufacturing process in which the capacitor is embedded in the resin substrate with a thickness of 0.1 mm or less It is possible to provide a thin film capacitor without any problems. In the present invention, a substrate having a thickness of 2 to 100 μm is used, but the use of a substrate having a thickness of 100 μm or less is necessary for producing a capacitor having a thickness of 0.1 mm or less. This is because, when the substrate has a sufficient thickness and is strong, the necessity of using a highly elastic electrode required in the present invention is reduced. When a thin film capacitor is built in a wiring board, the thin film capacitor is often embedded using a prepreg. In that case, assuming that the thickness of the cured prepreg is about 0.1 mm, a base of 70 μm or less is used. It is more preferable to use a material. Further, a substrate having a thickness of 2 μm or less is insufficient in mechanical strength and difficult to handle during the manufacturing process, so that a greater thickness is required. In order to ensure the stability during the manufacturing process, it is more preferable to use a substrate having a thickness of 10 μm or more.
[0015]
In the thin film capacitor of the present invention, a lead electrode having a thickness of 1 μm or more, more preferably 2.5 μm or more is formed on the lower electrode and the upper electrode by electrolytic plating. Therefore, when the thin film capacitor is built in the resin substrate, the electrical connection between the electrode of the thin film capacitor and the Cu layer formed on the inner surface of the through hole can be ensured. In addition, if the thickness of the extraction electrode is less than 1 μm, there is a high risk that the electrical connection between the extraction electrode and the inner surface Cu plating of the through-through hole is lost in the thermal cycle test. It is effective to set the thickness to 1 μm or more. In this case, when a thick film electrode is formed on the thin film capacitor by electrolytic plating or the like, stress is further applied to the dielectric thin film, but this stress is also mitigated by using a highly elastic electrode for the lower electrode according to the present invention, The dielectric thin film can be prevented from being damaged.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
1A and 1B are a plan view and a sectional view showing a first embodiment of a thin film capacitor of the present invention. On a flexible substrate 1 made of resin or metal, preferably 2-100 μm thick, more preferably 10-70 μm, a lower electrode 5, a high dielectric constant thin film 8 made of an inorganic material, and an upper electrode 9 A capacitor is formed by stacking. The lower electrode 5 includes an adhesion electrode 2 provided to improve the adhesion of the flexible substrate 1, an oxidation-resistant electrode 4 made of a hardly oxidizable material in contact with the high dielectric constant thin film 8, and the oxidation-resistant electrode 4. And a highly elastic electrode 3 having a higher elastic modulus (Young's modulus) than that of the oxidation-resistant electrode 4 sandwiched between the close contact electrodes 2. The high elastic electrode 3 is an electrode provided to prevent the high dielectric constant thin film 8 from being damaged even when an external stress that causes deformation of the flexible substrate 1 is applied, and is preferably 300 nm or more. More preferably, the thickness is 400 nm or more. Moreover, in order to improve the adhesiveness of the highly elastic electrode 3 and the oxidation-resistant electrode 4, an adhesion layer can be interposed between them. The adhesion layer and the adhesion electrode can be formed using any one of Cr, Ti, and Zr.
[0017]
The thin film capacitor of the present invention is provided with an extraction electrode 7 and an extraction electrode 10 having a thickness of 1 μm or more, more preferably 2.5 μm or more, for connection to external wiring. Reference numeral 7 a in FIG. 1A denotes a contact portion of the extraction electrode 7 with respect to the upper electrode 9. In order to sufficiently insulate the extraction electrode 7 from the extraction electrode 10 and the lower electrode 5 electrically connected thereto, the area other than the contact area of the extraction electrodes 7 and 10 is covered with an insulating layer 6. Although not an essential requirement of the configuration of the present invention, a protective layer 11 having a thickness of 1 to 5 μm using a photosensitive resin is formed on the uppermost layer of the thin film capacitor. The protective layer 11 is provided with openings 11a and 11b so that a part of the extraction electrodes 7 and 10 is exposed. This opening is used to measure the capacitance of the thin film capacitor so that the probe of the measuring instrument is directly applied to the lead electrode of the thin film capacitor, and when the thin film capacitor is built in the wiring board, the conductive film of the wiring board is thinned. Used to allow contact with the lead electrode of the capacitor.
[0018]
A metal having an elastic modulus (Young's modulus) higher than Pt (Young's modulus E = 165 GPa) normally used for the oxidation-resistant electrode 4 is used for the highly elastic electrode 3 in FIG. Specific examples include Mo, W, Ru, Ir, and the like. However, the metal is not limited to the above metal as long as it has a higher elastic modulus (Young's modulus) than the oxidation-resistant electrode and has high conductivity. That is, Fe, Ni, Co, Ta, etc. can also be used. The oxidation resistant electrode 4 is made of Ru, RuO in addition to Pt. ₂ , IrO ₂ , Pd, Au, or the like may be used. The high dielectric constant thin film 8 includes barium strontium titanate ((Ba, Sr) TiO 2. _Three ), Strontium titanate (SrTiO) _Three ), Lead zirconate titanate (Pb (Zr, Ti) O) _Three ) Inorganic composite oxide having a perovskite structure such as titanium oxide (TiO 2) ₂ ), Tantalum oxide (Ta ₂ O _Five ) Etc. are used. Further, an adhesion layer made of Cr, Ti, Zr, or the like may be formed between the high dielectric constant thin film 8 and the upper electrode 9 in order to improve the adhesion between them. Further, the lead electrodes 7 and 10 are made of Cu, Ni, or the like suitable for being formed by a process capable of forming a thick film such as a plating method, and the insulating layer 6 is a photosensitive film that can be easily patterned. It is suitable to use a conductive resin. When the highly elastic electrode 3 itself is formed of an oxidation resistant material, the oxidation resistant electrode 4 is omitted and a dielectric thin film is formed on the highly elastic electrode 3 directly or via an adhesion layer. May be.
[0019]
FIGS. 2A and 2B are a plan view and a cross-sectional view showing a second embodiment of the thin film capacitor of the present invention. 2, parts that are the same as the parts of the first embodiment shown in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted. 1 is different from the thin film capacitor of the first embodiment shown in FIG. 1 in that the lower electrode 5 is electrically connected to the flexible substrate 1 in addition to the lower electrode 5 in contact with the high dielectric constant thin film 8. A lead electrode receiver 5a that is electrically insulated and has the same layer structure as that of the lower electrode 5 is formed, and the lead electrode 7 that extends from the upper electrode is extended to the lead electrode receiver 5a. As described above, the shape of the thin-film capacitor is larger than that of the thin-film capacitor shown in FIG. Although there is a demerit that the high-frequency characteristics are inferior due to the longer routing, when the extraction electrode 7 connected to the upper electrode 9 is pulled out directly above the high dielectric constant thin film 8, it is built into the wiring board. In addition, there is an advantage that through-holes that are inexpensive in the process can be used for electrical connection with the surface wiring layer. In addition, the extraction electrode 7 is connected to the extraction electrode receiver 5a as compared with the case where the extraction electrode 7 is simply extended on the flexible substrate 1 or the insulating layer 6, so that the extraction at the time of forming the through hole is performed. Electrode peeling can be prevented more effectively. Reference numerals 7 and 7b in FIG. 2A are contact portions for the upper electrode 9 of the extraction electrode 7 and the extraction electrode receiver 5a.
[0020]
FIG. 3 is a cross-sectional view showing a third embodiment of the thin film capacitor of the present invention. 3, parts that are the same as the parts of the first embodiment shown in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted. The difference from the thin film capacitor of the first embodiment shown in FIG. 1 of the present embodiment is that the flexible base 1 is provided with an opening, and the inside of the opening becomes the lead electrode 12 of the lower electrode 5. It is a point embedded by the material.
The flexible substrate 1 in which the extraction electrode 12 is embedded can be formed as follows. Conductive posts to be the lead electrodes 12 are formed on a rigid temporary substrate made of glass, silicon, sapphire, ceramic, metal, etc. by electrolytic plating or thick film printing, or a metal film is pasted on the temporary substrate. A conductive post is formed by etching, and a base material such as a polyimide varnish is applied and cured to form the flexible base material 1. After planarizing the surface by CMP or the like, a capacitor is formed thereon. After the capacitor is formed, the thin film capacitor is peeled off from the temporary substrate. Alternatively, the temporary substrate is removed by etching.
Another method for forming the flexible base material 1 in which the extraction electrode 12 is embedded is that after the capacitor is formed on the flexible base material 1, the base material is selectively etched from the back surface of the base material, or the base material is irradiated with laser light. Is selectively removed to form an opening, and conductive paint or solder is embedded in the opening. Alternatively, a conductive layer plug is formed in the opening by electrolytic plating.
[0021]
FIG. 4 is a cross-sectional view showing a second embodiment of the thin film capacitor of the present invention. 4, parts that are the same as the parts of the first and second embodiments shown in FIGS. 1 and 2 are given the same reference numerals, and redundant descriptions are omitted. This embodiment differs from the thin film capacitor of the first embodiment shown in FIG. 1 in that a high dielectric constant thin film 8 ′, a lower electrode 5 ′, a high dielectric constant thin film 8 ″, The upper electrode 9 'is laminated, the lower electrodes 5, 5' are connected in parallel, and the upper electrodes 9, 9 'are connected in parallel by the lead electrode 7. According to this embodiment, the upper electrode 9' is connected in parallel. Since the thickness of the capacitor of the present invention is substantially determined by the thickness of the flexible substrate 1 and the lead electrode, the thickness of the capacitor can be increased by employing a multilayer structure. The number of high dielectric constant thin films stacked in multiple layers may be 2 or 4 or more.
Also in the capacitors of the third and fourth embodiments shown in FIGS. 3 and 4, an insulating protective layer may be formed on the surface.
[0022]
FIGS. 5A and 5B are a plan view and a cross-sectional view showing a first embodiment of a composite passive component including a thin film capacitor of the present invention. In FIG. 5, parts that are the same as the parts of the first and second embodiments shown in FIGS. 1 and 2 are given the same reference numerals, and redundant descriptions are omitted. A thin film capacitor and a thin film resistor are formed on the same flexible substrate 1. On the left side of the figure, a thin film capacitor of the first embodiment shown in FIG. 1 with a contact electrode added is formed. That is, the contact electrode 14a is formed between the oxidation resistant electrode 6 of the upper electrode 9 or the lower electrode and the lead electrodes 7 and 10 formed of a thick film. The right side of the figure is a thin film resistor forming portion, and the thin film resistor 14b is made of the same material as the close contact electrode 14a and is formed simultaneously with the close contact electrode 14a. A lead electrode 15 is formed on the thin film resistor 14b. As shown in the first to fourth embodiments, the insulating protective layer 11 may be formed on the surface. In that case, openings 11 c and 11 d are opened on the extraction electrode 15 in the protective layer 11. Further, in FIG. 5, the thin film resistor 14b is described so that both ends of the thin film resistor 14b coincide with both ends of the extraction electrode 15. However, if the thin film resistor 14b and the extraction electrode 15 are in electrical contact, they coincide. It does not have to be. Here, the distance between the right end of the lower electrode 5 of the thin film capacitor and the left end of the thin film resistor 14b can be reduced to 20 μm.
FIG. 5 shows a form in which a thin film capacitor and a thin film resistor are formed on the same substrate. However, the thin film capacitor and the thin film inductor, or the thin film capacitor, the thin film resistor, and the thin film inductor are the same. It may be formed on a material.
[0023]
FIG. 6 is a cross-sectional view showing a second embodiment of a composite passive component including a thin film capacitor of the present invention. In FIG. 6, parts equivalent to those of the first embodiment of the composite passive component shown in FIG. In the present embodiment, a thin film capacitor and a spiral inductor are formed on the same flexible substrate 1. That is, the thin film capacitor of the first embodiment shown in FIG. 5 is formed on the left side of FIG. 6, and the spiral inductor 16 is formed on the right side. The spiral inductor 16 is made of the same material as that of the lower electrode 5 of the thin film capacitor, and is formed at the same time when the lower electrode 5 is patterned. A lead electrode 17 is formed on the spiral inductor 16. Note that the insulating protective layer 11 may be formed on the surface. In that case, the protective layer 11 is opened on the extraction electrode 17.
[0024]
FIG. 7 is a cross-sectional view showing a first embodiment of a wiring board incorporating the thin film capacitor of the present invention. The present embodiment relates to an example in which the thin film capacitor according to the present invention is incorporated in a multilayer wiring board. The multilayer wiring board with a built-in thin film capacitor shown in FIG. 7 is manufactured as follows. After the thin film capacitor 20a according to the present invention is fixed to the core layer 21 on which the wiring to be the inner layer pattern 22 is formed on both surfaces via the adhesive layer 23, prepregs are disposed on the upper and lower surfaces of the core layer 21 and pressed. -The prepreg cured layer 24 is formed by heating. Then, a through hole 25 penetrating the substrate is formed so as to penetrate the lead electrodes 7 and 10 of the thin film capacitor, a wiring pattern 26 is formed on the surface of the prepreg cured layer 24, and a wiring pattern is formed on the inner wall surface of the through hole. A Cu plating layer 26 is formed to connect 26 to the extraction electrodes 7 and 10 and the inner layer pattern 22 of the thin film capacitor 20a.
Instead of forming the wiring pattern by plating only by forming the prepreg cured layer 24, a copper foil is provided on the prepreg cured layer 24 when it is bonded to the core layer, or resin coated copper (RCC) A wiring pattern may be formed using the copper foil layer. As is clear from FIG. 7, it is essential that the thin film capacitor 20 a used in the present embodiment is thinner than the prepreg cured layer 24. Desirably, the thickness of the thin film capacitor is approximately 70% or less of the prepreg. Therefore, when the thickness of one prepreg layer is 0.1 mm, the allowable thickness of the thin film capacitor is 70 μm or less.
[0025]
FIG. 8 is a cross-sectional view showing a second embodiment of a wiring board incorporating the thin film capacitor of the present invention. The present embodiment relates to an example in which the thin film capacitor according to the present invention is built in a core substrate of a build-up substrate. The core substrate 30 is produced as follows. The thin film capacitor 20b according to the present invention is bonded to the core layer 21 having the wiring pattern to be the inner layer pattern 22 via the adhesive layer 23, and the prepreg is disposed on the upper and lower surfaces of the core layer 21, pressed and cured, and the prepreg A hardened layer 24 is formed. A through hole 25 that penetrates the core substrate is formed, and a via hole 28 that exposes the surface of the extraction electrodes 7 and 10 of the thin film capacitor 20b is formed. A wiring pattern 26 connected to the extraction electrodes 7 and 10 of the thin film capacitor 20b is formed via a Cu plating layer 29 formed on the inner wall surface of the via hole 28, and a Cu plating layer 27 is formed on the inner wall surface of the through hole 25. As a result, the wiring patterns 26 on the front and back surfaces of the substrate are electrically connected. When forming the prepreg cured layer 24, a copper foil may be provided thereon. Build-up layers 31 are formed on the front and back surfaces of the core substrate 30 thus manufactured. The buildup layer 31 is formed by forming the prepreg cured layer 32 and forming the via hole 33, and then performing the process of forming the Cu plating layer 34 covering the wiring pattern 35 and the inner wall surface of the via hole 33 one or more times. The
The build-up layer 31 is formed by forming a film by applying a thin insulating resin film, applying a varnish and curing, applying a photosensitive resin, exposing and developing, instead of forming the prepreg cured layer 32. At the same time, a method of forming a via hole may be used. Moreover, when forming the prepreg cured layer 32, you may make it provide copper foil on it.
[0026]
FIG. 9 is a cross-sectional view showing a third embodiment of a wiring board incorporating the thin film capacitor of the present invention. The present embodiment relates to an example in which the thin film capacitor according to the present invention is mounted in a flexible wiring board. The thin film capacitor 20a is fixed to the resin layer 41 formed of a resin film such as a polyimide film having a wiring pattern to be the inner layer pattern 42 via the adhesive layer 23, and a resin sheet is laminated thereon and thermocompression bonded. Thus, the resin layer 43 is formed. Thereafter, a through hole 44 penetrating the substrate is formed to form a wiring pattern 46 on the front and back surfaces of the substrate, and the wiring pattern 46 and the lead electrodes 7 and 10 and the inner layer pattern 42 of the thin film capacitor 20a are formed on the inner wall surface of the through hole 44. A Cu plating layer 45 to be connected is formed. The resin layer 43 may be formed by applying a varnish and curing it. Further, as the resin layer 41, a film having copper foil in advance on the side where the inner layer pattern 42 is not formed can be used. Furthermore, when forming the resin layer 43, you may make it form the resin layer with copper foil.
[0027]
In the present embodiment, a thin film capacitor is built in a flexible substrate made of resin layers 41 and 43 and having a thickness of 100 μm or less, and the thickness of each layer of the resin layer is less than about 50 μm. Therefore, it is desirable that the thickness of the thin film capacitor is about 35 μm or less in total thickness. Further, it is desirable that the resin constituting the resin layer 43 for embedding the thin film capacitor has thermoplasticity. However, if the thin film capacitor is not destroyed in the process of integrating the resin layer and the thin film capacitor, the resin layer 35 may be a thermosetting resin. Alternatively, the wiring pattern on the surface of the resin layer 43 and the lead electrodes 7 to 10 of the thin film capacitor may be electrically connected by via holes that do not penetrate the substrate.
[0028]
FIG. 10 is a cross-sectional view showing a fourth embodiment of a wiring board incorporating the thin film capacitor of the present invention. The present embodiment relates to an example in which a back electrode lead-out type thin film capacitor according to the present invention is mounted in a flexible wiring board. A thin film capacitor 20c is fixed on an inner layer pattern 42 formed on a resin layer 41 formed of a resin film such as a polyimide film via a conductive adhesive layer 23 made of solder, conductive paint, or the like. A resin sheet is laminated and thermocompression bonded to form a resin layer 43, and the thin film capacitor 20c is embedded. Then, a via hole 48 exposing the surface of the extraction electrode 7 of the thin film capacitor 20c is opened, and a through hole 44 penetrating the substrate is opened. Thereafter, a Cu plating layer 49 is formed on the inner wall surface of the via hole 48 and a wiring pattern 46 is formed on the front and back surfaces of the substrate by electrolytic plating, and between the wiring patterns 46 and between the wiring pattern 46 and the inner layer pattern 42 are connected to the inner wall surface of the through hole 44. A Cu plating layer 45 is formed. The resin layer 43 may be formed by applying a varnish and curing it. Further, as the resin layer 41, a film having copper foil in advance on the side where the inner layer pattern 42 is not formed can be used. Furthermore, when forming the resin layer 43, you may make it form the resin layer with copper foil.
[0029]
FIG. 11 is a cross-sectional view showing a first embodiment of a wiring board incorporating a composite component including a thin film capacitor of the present invention. The present embodiment relates to an example in which a composite part including a thin film capacitor according to the present invention is built in a multilayer wiring board. The multilayer wiring board with composite components shown in FIG. 11 is manufactured as follows. The composite component 50a formed on the same substrate as the thin film capacitor according to the present invention is fixed to the core layer 51, on which wiring to be the inner layer pattern 54 is formed on both surfaces, through the adhesive layer 55. Thereafter, prepregs are arranged on the upper and lower surfaces of the core layer 51, and the prepreg cured layer 52 is formed by applying pressure and heating. A through hole 56 penetrating the substrate is formed, and a via hole 58 is formed to expose the surfaces of the thin film capacitor lead electrodes 7 and 10 and the thin film resistor lead electrode 15. A wiring pattern 53 connected to the lead electrodes 7 and 10 of the thin film capacitor is formed through a Cu plating layer 59 formed on the inner wall surface of the via hole 58, and a Cu plating layer 57 is formed on the inner wall surface of the through hole 56. Thus, the front surface wiring of the wiring substrate and the inner layer or back surface wiring are electrically connected to each other, and these are electrically connected to the extraction electrode 15 of the thin film resistor. When forming the prepreg cured layer 52, a copper foil may be provided thereon. Similar to the first embodiment of the wiring board incorporating the thin film capacitor of the present invention, it is essential that the composite passive component including the thin film capacitor used in the present embodiment is thinner than the prepreg cured layer 52.
[0030]
【Example】
Next, examples of the present invention will be described in detail.
[Example 1]
After fixing a commercially available polyimide film (thickness: 50 μm) as a base film 63 to the stainless steel fixing frames 61 and 62 shown in FIG. 12, the film was introduced into a DC sputtering apparatus, and Cr, W, Ti, Pt were placed on the film. Were deposited in a film thickness of Cr: 20 nm, W: 500 nm, Ti: 20 nm, and Pt: 250 nm, respectively. Here, Cr is a close contact electrode (2 in FIG. 1), W is a highly elastic electrode (3 in FIG. 1), Ti is a close contact electrode (between 3 and 4 in FIG. 1), and Pt is an oxidation resistant electrode (in FIG. 1). Corresponds to 4). Strontium titanate (SrTiO) having a perovskite structure by RF sputtering on a Pt electrode _Three ) A thin film (8 in FIG. 1) was formed to a thickness of 200 nm, and further Pt was formed thereon to a thickness of 200 nm as an upper electrode (9 in FIG. 1) by DC sputtering. After film formation, annealing was performed at 400 ° C. Next, a resist film having an upper electrode pattern to be formed by photolithography was formed, and the Pt film was patterned by ion beam etching (IBE). Similarly, a resist film having a high dielectric constant dielectric film pattern to be formed by photolithography is formed, and SrTiO is formed by chemical etching. _Three The film was patterned. Further, a resist film was formed in a pattern of the lower electrode (5 in FIG. 1) by photolithography, and the lower electrode film (Pt, Ti, W, Cr film) was patterned by IBE method.
[0031]
Next, in order to insulate the lead electrode (7 in FIG. 1) and the lower electrode (5 in FIG. 1), which are electrically connected to the upper electrode (9 in FIG. 1), from the photosensitive resin made of epoxy resin. A conductive resin was applied and patterned by exposure and development to form an insulating layer (6 in FIG. 1) having a thickness of about 2 μm. Next, a plating underlayer was formed by DC sputtering on the entire surface in the order of about 20 nm of Ti and about 100 nm of Cu. The Ti layer is provided in order to improve the adhesion of the Cu film, and Cr or Zr can also be used outside for this purpose. Next, a resist film having an opening in the shape of an extraction electrode to be formed by photolithography is formed, and Cu is formed in the opening by 18 μm by electrolytic plating, and this is formed as an extraction electrode (7 and 10 in FIG. 1). did. After removing the resist film and removing the exposed plating base layer by etching, a photosensitive epoxy resin is applied to the entire top layer, and exposure and development are performed to form a protective layer (11 in FIG. 1) having a thickness of about 2 μm. did.
[0032]
Then, it removed from the fixed frames 61 and 62, cut | disconnected along the external shape, and was set as each thin film capacitor. FIG. 13 shows a view of the thin film capacitor manufactured in this way as viewed from above. From the top, only the protective layer 11 and the extraction electrodes 7 and 10 exposed in the openings 11a and 11b can be seen. The size of the openings 11a and 11b was 0.5 mm □. The dotted line in FIG. 13 shows the outer shape of the upper electrode 9, and the capacitance of the thin film capacitor is determined by this area and the thickness of the high dielectric constant dielectric thin film 8. The capacitance and dielectric loss of the thin film capacitor when the size of the upper electrode 9 of the thin film capacitor was changed in the range of 0.1 mm × 0.1 mm to 1 mm × 1 mm were measured with an LCR meter.
When the relative dielectric constant εr of the high dielectric constant thin film 8 was determined from the measured electrostatic capacitance by the formula (1), a numerical value of εr = 80 to 85 was obtained. A slightly higher εr was obtained when the effective area S was smaller. The dielectric loss was 0.008 at f = 1 kHz and 0.010 at f = 1 MHz.
From this result, it can be said that a relative dielectric constant εr almost equal to that formed on a rigid substrate such as a Si wafer is obtained, and the dielectric loss is also a practical value.
εr = Cd / ε ₀ S ... (1)
Where C is the capacitance (F), d is the thickness of the high dielectric constant thin film (m), ε ₀ Is dielectric in vacuum
Rate, S is the area of the upper electrode 9 (m ² ).
[0033]
[Example 2]
Similarly to Example 1, as shown in FIG. 12, after fixing a commercially available polyimide film (thickness 50 μm) to the fixed frames 61 and 62, it was introduced into a DC sputtering apparatus, and Cr, W, Ti, Pt was deposited in a film thickness of Cr: 20 nm, W: 1000 nm, Ti: 20 nm, and Pt: 250 nm, respectively. Here, Cr is a close contact electrode (2 in FIG. 2), W is a highly elastic electrode (3 in FIG. 2), Ti is a close contact electrode (between 3 and 4 in FIG. 2), and Pt is an oxidation resistant electrode (4 in FIG. 2). ). Lead lanthanum zirconate titanate having a perovskite structure by a sol-gel method on a Pt electrode ((Pb _0.94 La _0.06 ) (Zr _0.5 Ti _0.5 ) O _Three ) A thin film (8 in FIG. 2) was formed to a thickness of 200 nm, and further, Pt to be the upper electrode (9 in FIG. 2) was formed to a thickness of 200 nm by DC sputtering. After film formation, lead lanthanum zirconate titanate was annealed at 450 ° C. Next, a resist film having an upper electrode pattern to be formed by photolithography was formed, and the Pt film was patterned by ion beam etching (IBE). Similarly, a resist film was formed by photolithography, and a lead lanthanum zirconate titanate film was patterned by chemical etching. Further, a resist film is formed by photolithography, and the lower electrode film (Pt, Ti, W, Cr film) is patterned by the IBE method, and the lower electrode (5 in FIG. 2) and the extraction electrode receiver (5a in FIG. 2) are formed. It was created.
[0034]
The insulating layer (6 in FIG. 2), the extraction electrode (7 in FIG. 2, 10 in FIG. 2) and the protective layer (11 in FIG. 2) were formed in the same manner as described in Example 1. The capacitance and dielectric loss when the size of the upper electrode of the thin film capacitor is set to 0.1 mm × 0.1 mm to 1 mm × 1 mm in the same manner as in Example 1 are measured with an LCR meter, and the dielectric constant is determined according to the equation (1). When the rate εr was calculated, εr = 270 to 320. Although it is higher than the relative permittivity of the strontium titanate thin film of Example 1, it is far more than the relative permittivity (εr = 800 to 1000) of the lead lanthanum zirconate titanate thin film produced on a rigid substrate such as a Si wafer. Low. This is presumably due to the low annealing temperature. The dielectric loss was 0.02 at f = 1 kHz and 0.035 at f = 1 MHz.
[0035]
[Example 3]
This embodiment relates to the back electrode lead-out type capacitor shown in FIG. Ti / Cu is deposited on a silicon substrate by electron beam evaporation to form a plating underlayer, a resist film having an opening in the formation region of the extraction electrode 12 is formed by photolithography, and the extraction electrode 12 is formed by electrolytic plating. A conductive post having a thickness of 25 μm was formed. After removing the resist film and removing the exposed plating base layer, a flexible substrate 1 was formed by applying a polyimide varnish on the substrate by spin coating and performing predetermined drying and curing. The lead electrode 12 is preferably formed to be slightly thicker than the flexible substrate 1. Thereafter, the extraction electrode 12 was polished to eliminate the step between the extraction electrode 12 and the surface of the flexible substrate 1. On the flexible substrate 1 in which the extraction electrode 12 is embedded, the adhesion electrode 2 (Ti), the highly elastic electrode 3 (Ru), and the oxidation resistant electrode 4 (Pd) are respectively formed to a thickness of 50 nm, 400 nm, and 200 nm by sputtering. The lower electrode 5 was formed by depositing. Tantalum oxide (Ta) is deposited on the oxidation-resistant electrode 4 by CVD. ₂ O _Five ) To a thickness of 50 nm to form a high dielectric constant thin film 8. On top of that, a Pt film having a thickness of 150 nm was formed as the upper electrode 9 by sputtering. After the film formation, the Pt film to be the upper electrode 9 and the high dielectric constant thin film 8 are patterned by photolithography to form the insulating layer 6 and then drawn onto the upper electrode 9 using the same method as in the first embodiment. An electrode 7 was formed. Finally, the silicon substrate as a temporary substrate was peeled and removed, and the flexible base material was cut and separated to obtain individual capacitors.
[0036]
[Example 4]
The present embodiment relates to the multilayer capacitor shown in FIG. A polyimide film having a thickness of 30 μm to be the flexible substrate 1 was fixed on a silicon wafer using an adhesive having high heat resistance. In addition to silicon, any rigid substrate such as glass, sapphire, ceramic, or metal can be used. A lower electrode 5 is formed by depositing a contact electrode 2 (Ti), a highly elastic electrode 3 (W), and an oxidation-resistant electrode 4 (Pt) on a polyimide film to a thickness of 20 nm, 500 nm, and 250 nm, respectively, by sputtering. did. On a Pt electrode, lead zirconate titanate (Pb (Zr) having a perovskite structure as a high dielectric constant thin film 8 by a sol-gel method is used. _0.5 Ti _0.5 ) O _Three ) A thin film was formed to a thickness of 200 nm, patterned by photolithography, and further, Pt to be the upper electrode 9 was formed to a thickness of 200 nm by sputtering and patterned. For patterning the upper electrode 9, a photoetching method or a lift-off method can be used. Thereafter, a lead zirconate titanate thin film to be a high dielectric constant thin film 8 ′ is formed to a film thickness of 200 nm by a sol-gel method, patterned by photolithography, and then contact electrode 2 (Ti: 20 nm), acid resistance by sputtering. An electrode 4 (Pt: 250 nm) was deposited and patterned to form a lower electrode 5 '. For patterning the lower electrode 5 ', a photoetching method or a lift-off method can be used. Thereafter, a lead zirconate titanate thin film to be a high dielectric constant thin film 8 ″ is formed to a thickness of 200 nm by a sol-gel method, patterned by photolithography, and then Pt is formed to a thickness of 200 nm by sputtering. The upper electrode 9 'was formed by patterning, and the lower electrode layer was patterned to form the lower electrode 5 and the lead electrode receiver 5a. In this case, patterning may be performed by a lift-off method, and after annealing the lead zirconate titanate thin film at 450 ° C., the insulating layer 6 is formed using an epoxy-based photosensitive resin. After that, lead electrodes 7 and 10 mainly composed of Cu were formed using the same method as in Example 1. Finally, a flexible substrate was formed. The material was peeled from the silicon wafer and cut and separated into individual thin film capacitors.
[0037]
[Comparative example]
A thin film capacitor using a strontium titanate thin film as the high dielectric constant thin film 8 was manufactured by the same process as in Example 1. The difference from the first embodiment is the layer structure of the lower electrode 5. In the comparative example, Ti: 20 nm and Pt: 500 nm were used as the lower electrode. Here, Ti corresponds to the contact electrode (2 in FIG. 1), Pt corresponds to the oxidation-resistant electrode (4 in FIG. 1), and no electrode corresponding to the highly elastic electrode 3 is provided. When the strontium titanate was formed on the lower electrode 5 as the high dielectric constant thin film 8 and annealed, “wrinkles” of the dielectric thin film as shown in FIG. 14 were observed. Thereafter, the capacitance and dielectric loss of the thin film capacitor could be measured by the same process as in Example 1. As a result, 20 were measured and all of them were defective in the short mode. This is presumed that wrinkles were generated in the flexible substrate 1 due to the stress generated during the formation of the high dielectric constant thin film, and as a result, cracks and the like were generated in the high dielectric constant thin film 8 and shorted.
[0038]
[Example 5]
This embodiment relates to a method of manufacturing a composite passive component including the thin film capacitor of the present invention shown in FIG. 15-17 is sectional drawing of the order of the process which shows the manufacturing method. First, a polyimide varnish was applied onto the silicon wafer 1a shown in FIG. 15 (a) by a spin coat method and cured in a nitrogen atmosphere at 400 ° C. to form the flexible substrate 1 [FIG. 15 (b)]. . Subsequently, an adhesion layer, a highly elastic metal, and an oxidation resistant metal are sequentially deposited to form a lower electrode film 5b [FIG. 15 (c)], and a high dielectric constant thin film 8 is deposited [FIG. 15 (d)]. An upper electrode film 9a was formed [FIG. 15 (e)]. After patterning the upper electrode film 9a to form the upper electrode 9 [FIG. 16 (f)] and patterning the high dielectric constant thin film 8 [FIG. 16 (g)], the lower electrode film 5b is subsequently patterned to form the lower electrode 5 was formed [FIG. 16 (h)]. Then, the insulating layer 6 was formed with the epoxy-type photosensitive resin [FIG. 16 (i)]. The steps from the step of depositing the lower electrode film 5b to the formation of the insulating layer 6 (FIGS. 15C to 16I) are the same as those in the first embodiment. Next, a TiN film (thickness 50 nm) to be the contact electrode 14a and the thin film resistor 14b was deposited by a reactive sputtering method, and subsequently Cu (thickness 200 nm) was continuously formed by a normal DC sputtering method. Next, a resist film having an opening in the shape of an extraction electrode to be formed by photolithography is formed, and Cu is formed to a thickness of 12 to 18 μm by electrolytic plating in the opening to form extraction electrodes 7, 10, and 15. did. The resist film is removed, and the exposed Cu layer, which is the plating base, is removed using an etching solution that does not dissolve TiN (for example, sulfuric acid + hydrogen peroxide solution), and then a resist for forming a resistance pattern by photolithography. After the film was formed and the TiN film in the opening was removed by etching, the resist was stripped [FIG. 16 (j)]. Next, a photosensitive epoxy resin was applied to the entire uppermost layer, and exposure and development were performed to form a protective layer having a thickness of about 2 μm [FIG. 17 (k)]. Finally, the flexible base material on which the thin film capacitor and the thin film resistor were formed was peeled from the silicon wafer 1a [FIG. 17 (l), FIG. 17 (m)]. And it cut | disconnected to each composite passive component [FIG.17 (n)]. As an example, FIG. 18 shows a view of a composite passive component in which 10 thin film capacitors of 1000 pF and 1 thin film resistor of 50 kΩ are simultaneously formed as viewed from above. In FIG. 18, reference numeral 71 denotes a thin film capacitor portion, and 72 denotes a thin film resistor portion. The composite passive component had a size of 5.76 mm in length, 3.86 mm in width, and 40 μm in thickness (flexible base material to protective layer).
An inductor can be formed instead of or together with the thin film resistor. The inductor can be formed using a laminated film of a sputtered TiN layer and a Cu layer. Or you may make it form with the electrically conductive film containing the Cu plating layer which forms an extraction electrode.
[0039]
[Example 6]
19 and 20 are cross-sectional views in order of steps showing a method of manufacturing a composite passive component including the thin film capacitor of the present invention shown in FIG. Using the same method as in Example 5, the flexible substrate 1 is formed on the silicon wafer 1a, and the lower electrode film 5b made of an adhesion layer, a highly elastic metal, and an oxidation-resistant metal is formed. 8 was deposited to form an upper electrode film 9a [FIG. 19 (a)]. The upper electrode film 9a is patterned to form the upper electrode 9, the high dielectric constant thin film 8 is patterned, and then the lower electrode film 5b is patterned to form the lower electrode 5 and the spiral inductor 16 [FIG. ]. Thereafter, the insulating layer 6 having an opening in the lead electrode formation region of the thin film capacitor and the spiral inductor 16 was formed by an epoxy-based photosensitive resin [FIG. 19 (c)]. Next, a TiN film having a thickness of 50 nm and a Cu layer having a thickness of 200 nm were deposited by sputtering to form a base film 13 (FIG. 19D).
Next, a resist film 18 having an opening in the shape of an extraction electrode to be formed by photolithography is formed, and Cu is formed in a thickness of 12 to 18 μm by electrolytic plating in the opening, and the extraction electrodes 7 and 10 of the thin film capacitor are formed. Then, the lead electrode 17 of the spiral inductor 16 was formed [FIG. 20 (e)]. The resist film 18 was removed, and the exposed base film 13 was removed by etching [FIG. 20 (f)]. Next, a photosensitive epoxy resin was applied to the entire uppermost layer, and exposure and development were performed to form a protective layer 11 having a thickness of about 2 μm [FIG. 20 (g)]. Finally, the flexible substrate 1 on which the thin film capacitor and the spiral inductor 16 were formed was peeled from the silicon wafer 1a [FIG. 20 (h)].
A thin film resistor can be formed in place of or together with the spiral inductor. The thin film resistor can be formed by using the lower electrode film 5b made of a three-layer conductive film, using only the adhesion layer, or using the adhesion layer and the highly elastic metal film.
[0040]
[Example 7]
A wiring board incorporating the thin film capacitor produced in Example 2 was produced as follows. As shown in FIG. 7, a thin film capacitor 20a is attached to one surface of a core substrate 21 having a thickness of 0.4 to 0.6 mm in which wiring patterns are formed on both sides as a core substrate of a multilayer wiring substrate. And adhered. Next, a copper-coated prepreg or resin coated copper (RCC: resin coated copper) containing no glass cloth was disposed on the upper and lower surfaces of the core substrate and integrated by thermocompression bonding. Next, a through hole 25 penetrating the substrate is opened with a 0.3 to 0.35 mmφ drill, and then activation treatment, electroless plating, electrolytic plating, and selective etching are performed in accordance with a normal plated through hole forming method. Then, the wiring pattern 26 was formed, and the Cu plating layer 27 having a thickness of 18 to 30 μm was formed on the inner wall surface of the through hole 25. When the capacitance and dielectric loss of the thin film capacitor built in the substrate were measured with an LCR meter by applying probes to the wiring patterns 26 and 26 on the surface, the capacitance of the thin film capacitor before incorporation was 2250 pF and the dielectric loss was 0. What was 01 (f = 1 kHz, average of 20) was a capacitance of 2080 pF and a dielectric loss of 0.012 (both f = 1 kHz, average of 20 locations). It can be said that there is almost no difference in capacitance and dielectric loss between before and after mounting the substrate.
[0041]
[Example 8]
A multilayer build-up substrate incorporating the thin film capacitor produced in Example 1 was produced as follows. A core substrate 30 shown in FIG. 8 was produced by a method similar to the method for producing a multilayer wiring board described in Example 5. However, unlike the fifth embodiment, via holes 28 exposing the surfaces of the extraction electrodes 7 and 10 of the thin film capacitor 20a are opened by laser light, and the Cu plating layers 29 formed on the inner wall surfaces of the extraction holes 7 and 10 Electrical connection with the wiring pattern 26 is realized. Thus, since the lead electrode 10 of the thin film capacitor 20a is not directly above the high dielectric constant thin film 8 and the lower electrode 5, it is electrically connected to the wiring pattern 26 or the inner layer pattern 22 using a through-hole instead of a via hole. It does not matter if you let them. A photosensitive insulating resin is applied to the upper and lower surfaces of the core substrate 30 containing the thin film capacitor 20a, and exposure and development are performed to form an insulating layer (corresponding to the prepreg cured layer 32) having a via hole 33, and a Cu plating layer 34 is formed. Then, a wiring pattern 35 was formed to create a build-up layer for one layer. Thereafter, the build-up layer 31 was formed by repeating this process as many times as necessary, and a build-up substrate with a built-in thin film capacitor was produced.
[0042]
A probe was applied to the wiring patterns 35 and 35 on the surface of the build-up board, and the capacitance and dielectric loss of the thin film capacitor built in the board were measured with an LCR meter. The capacitance of the thin film capacitor before built-in was 880 pF, and the dielectric loss. Of 0.008 (f = 1 kHz, average of 20) was a capacitance of 850 pF and a dielectric loss of 0.01 (both f = 1 kHz, average of 20 locations). Even if a built-in thin film capacitor is built in the build-up board, it can be said that there is almost no difference in capacitance and dielectric loss before and after the built-in.
[0043]
[Example 9]
The thin film capacitor produced in Example 2 was built in the flexible wiring board by the following method. As shown in FIG. 9, the thin film capacitor 20a is bonded onto a polyimide film (resin layer 41) having a thickness of about 50 .mu.m in which a copper foil is provided on one side and a wiring pattern to be the inner layer pattern 42 is formed on the other side. A thermoplastic resin film having a thickness of 50 to 70 μm, which is fixed with an agent 23 and coated on one side with Cu, is laminated so that the surface not coated with Cu is covered with a thin film capacitor, and thermocompression bonded. The resin layer 43 was formed by integrating. A through hole 44 was opened with a drill, and then a wiring pattern 46 was formed on the front and back surfaces of the substrate by a normal plated through hole forming method, and a copper plating layer 45 was formed on the inner wall surface of the through hole 44. The thickness of the flexible substrate 1 serving as the base of the built-in thin film capacitor is 50 μm in Example 2, but is 20 μm here, so that the entire thickness of the thin film capacitor is 35 μm or less.
[0044]
The capacitance and dielectric loss of the built-in thin film capacitor were measured by applying a probe to the wiring patterns 46 and 46 on the substrate surface. Of the 20 locations measured, insulation failure occurred at 2 locations. This is because the flexible base material 1 of the thin film capacitor is thinner than that used in Examples 1 and 2 and the thickness of the resin layer 43 is thinner than the prepreg cured layer 24 in Examples 5 to 4, so that in the thermocompression bonding process. This is presumably because high stress was applied to the high dielectric constant thin film 8 of the thin film capacitor, resulting in dielectric breakdown. However, a substrate with a built-in capacitor free from insulation failure was obtained with a yield of 90%. The capacitance of the thin film capacitor before incorporation was 2250 pF and the dielectric loss was 0.01 (f = 1 kHz, average of 20), but after incorporation, the capacitance was 1960 pF and the dielectric loss was 0.012 (some F = 1 kHz, average of 18 locations). As a result, the capacitance decrease due to the built-in substrate was slightly larger than that of Example 5.
[0045]
Although preferred embodiments have been described above, the present invention is not limited to these embodiments, and appropriate modifications can be made without departing from the scope of the present invention. For example, in the embodiment, the insulating layer and the protective layer are formed using the photosensitive resin, but instead of this, the insulating layer and the protective layer may be formed using photosensitive glass. Alternatively, it may be formed of a non-photosensitive material.
[0046]
【The invention's effect】
Since the thin film capacitor of the present invention has an electrode layer made of a highly elastic material under the dielectric thin film, it is possible to reliably form a thin high dielectric constant dielectric thin film on a thin flexible substrate. Therefore, a thin and large-capacity thin film capacitor can be provided with high reliability. Therefore, according to the present invention, it is possible to reduce the thickness of the wiring board incorporating a large-capacity capacitor, and to provide a flexible substrate incorporating a large-capacitance capacitor. Further, since the thin film capacitor can be formed on the flexible substrate, the thin film capacitor can be prevented from being damaged when the thin film capacitor is mounted in the wiring board. In addition, since the lead electrode having a thickness of 1 μm or more is formed in the thin film capacitor of the present invention, it is possible to realize a through-hole connection with a low resistance and a high connection reliability that is not broken by a thermal cycle. In addition, the composite passive component including the thin film capacitor of the present invention and the manufacturing method thereof make it possible to form a large-capacity capacitor and a thin film resistor or thin film inductor on the same flexible substrate at a high density, and the composite passive component. It becomes possible to reduce the size of the wiring board containing the components.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view showing a first embodiment of a thin film capacitor of the present invention.
FIGS. 2A and 2B are a plan view and a cross-sectional view showing a second embodiment of the thin film capacitor of the invention. FIGS.
FIG. 3 is a cross-sectional view showing a third embodiment of a thin film capacitor of the present invention.
FIG. 4 is a cross-sectional view showing a fourth embodiment of a thin film capacitor of the present invention.
FIG. 5 is a cross-sectional view showing a first embodiment of a composite passive component including a thin film capacitor of the present invention.
FIG. 6 is a sectional view showing a second embodiment of a composite passive component including a thin film capacitor of the present invention.
FIG. 7 is a cross-sectional view showing a first embodiment of a wiring board with a built-in thin film capacitor according to the present invention.
FIG. 8 is a cross-sectional view showing a second embodiment of a wiring substrate with a built-in thin film capacitor according to the present invention.
FIG. 9 is a sectional view showing a third embodiment of a wiring board with a built-in thin film capacitor according to the present invention.
FIG. 10 is a sectional view showing a fourth embodiment of a wiring board with a built-in thin film capacitor according to the present invention.
FIG. 11 is a cross-sectional view showing a first embodiment of a wiring board with a built-in passive component including the thin film capacitor of the present invention.
12A and 12B are a top view and a cross-sectional view for illustrating a manufacturing process of a thin film capacitor of the invention.
FIG. 13 is a top view of a thin film capacitor formed according to Examples 1 and 2 of the present invention.
FIG. 14 is a metallographic micrograph showing a surface state after formation of a high dielectric constant thin film in a manufacturing process of a thin film capacitor of a comparative example.
FIGS. 15A and 15B are cross-sectional views in the order of steps showing a method for manufacturing a composite passive component according to Embodiment 5 of the present invention (No. 1); FIGS.
FIG. 16 is a cross-sectional view in the order of steps showing the method for manufacturing the composite passive component according to the fifth embodiment of the present invention (No. 2).
FIGS. 17A to 17C are cross-sectional views in the order of steps showing the method for manufacturing the composite passive component according to the fifth embodiment (No. 3). FIGS.
FIG. 18 is a top view of a composite passive component manufactured in Example 5 of the present invention.
FIG. 19 is a cross-sectional view in the order of steps showing a method for manufacturing a composite passive component according to Embodiment 6 of the present invention (part 1);
FIG. 20 is a cross-sectional view in order of steps showing the method for manufacturing a composite passive component according to the sixth embodiment of the present invention (part 2);
[Explanation of symbols]
1 Flexible substrate
1a Silicon wafer
2 Close contact electrode
3 High elasticity electrode
4 Oxidation resistant electrode
5 Lower electrode
5a Lead electrode holder
5b Lower electrode film
6 Insulation layer
7, 10, 12, 15, 17 Lead electrodes
7a, 7b Contact part
8 High dielectric constant thin film
9 Upper electrode
9a Upper electrode film
11 Protective layer
11a, 11b, 11c, 11d opening
13 Underlayer
14a Contact electrode
14b Thin film resistor
16 Spiral inductor
18 resist film
20a, 20b, 20c thin film capacitors
21, 51 Core layer
22, 42, 54 Inner layer pattern
23, 55 Adhesive layer
24, 32, 52 Prepreg cured layer
25, 44, 56 Through hole
26, 35, 46, 53 Wiring pattern
27, 29, 34, 45, 49, 57, 59 Cu plating layer
28, 33, 48, 58 Via hole
30 core substrate
31 Build-up layer
41, 43 Resin layer
47 Conductive adhesive layer
50a composite parts
61, 62 Fixed frame
63 Base film
71 Thin film capacitor part
72 Thin film resistor

Claims

In a thin film capacitor in which a lower electrode, a dielectric thin film, and an upper electrode are stacked on a substrate having a thickness of 2 μm or more and 100 μm or less, the lower electrode includes a first contact electrode that contacts the substrate, and the dielectric An oxidation-resistant electrode in contact with the thin film; and a highly elastic electrode made of a material having a higher Young's modulus than the oxidation-resistant electrode, provided between the first contact electrode and the oxidation-resistant electrode, The first contact electrode is formed of any one of Ti, Cr, and Zr, and the highly elastic electrode is formed of any of W, Mo, Fe, Ni, and Co , and the thickness of the highly elastic electrode is 300 nm. A thin film capacitor characterized by the above .

In a thin film capacitor in which a lower electrode, a dielectric thin film, and an upper electrode are stacked on a substrate having a thickness of 2 μm or more and 100 μm or less, the lower electrode includes a first contact electrode that contacts the substrate, and the dielectric An oxidation-resistant electrode in contact with the thin film; a high-elasticity electrode made of a material having a Young's modulus higher than that of the oxidation-resistant electrode provided between the first contact electrode and the oxidation-resistant electrode; and the oxidation-resistant electrode; A second contact electrode is formed between the high elastic electrode, the first and second contact electrodes are formed of any one of Ti, Cr, and Zr, and the high elastic electrode is W, Mo, A thin film capacitor formed of any one of Fe, Ni, and Co , wherein the highly elastic electrode has a thickness of 300 nm or more .

3. The thin film capacitor according to claim 1, wherein the upper electrode and the lower electrode are respectively drawn by an upper lead electrode and a lower lead electrode having a film thickness of 1 μm or more.

The upper lead electrode is drawn on a pseudo lower electrode in the same layer as the lower electrode formed on the base material and insulated from the lower electrode, and the lower lead electrode is directed upward from the lower electrode. The thin film capacitor according to claim 3 , wherein the thin film capacitor is drawn out.

A lower electrode and a pseudo lower electrode made of the same material as the lower electrode insulated from the lower electrode are formed on a substrate having a thickness of 2 μm or more and 100 μm or less, and a dielectric is formed on a partial region of the lower electrode. A thin film capacitor in which a thin film and an upper electrode are laminated, wherein an upper lead electrode having a thickness of 1 μm or more is drawn from the upper electrode to the pseudo lower electrode, and a lower lead electrode having a thickness of 1 μm or more is formed on the lower electrode. 3. The thin film capacitor according to claim 1, wherein the thin film capacitor is drawn upward from a region where the dielectric thin film is not formed.

The thin film capacitor according to claim 3 , wherein the lower lead electrode is formed by embedding an opening provided through the base material.

On the base material, on the lower electrode and the upper electrode, or on the base material, on the lower electrode, on the upper electrode and on the pseudo lower electrode, the upper lead electrode and the lower lead electrode An insulating layer having an opening is covered on the lead portion or on a lead portion between the upper lead electrode and the lower lead electrode and a connection portion between the upper lead electrode and the pseudo lower electrode. Item 6. The thin film capacitor according to any one of Items 3 to 5 .

Between the upper electrode and the upper lead electrode and between the lower electrode and the lower lead electrode, or between the upper electrode and the upper lead electrode, and between the pseudo lower electrode and the upper lead electrode. and wherein the third contact electrode between the lower electrode and the lower lead-out electrode is formed, according to claim 3, wherein the third contact electrode, wherein Ti, Cr, being formed by one of Zr The thin film capacitor in any one of 7 to 7 .

The upper electrode has a fourth contact electrode in contact with the dielectric film, and an upper main electrode formed in an upper layer of the fourth contact electrode, and the fourth contact electrode is Ti, Cr, Zr. thin film capacitor according to any one of claims 1 to 8, characterized in that it is formed by either.

The thin film capacitor according to any one of claims 1 to 9 , wherein the upper electrode or the upper main electrode is formed of any one of Pt, Au, Al, TiN, and TaN.

Thin film capacitor according to any one of claims 1 to 10, wherein the dielectric thin film is formed by a high dielectric constant material.

The thin film capacitor according to claim 11 , wherein the high dielectric constant material is made of an oxide having a perovskite structure.

Wherein the substrate, the thin film capacitor according to any one of claims 1 12, characterized in that it is constituted by a resin film or a metal film.

The thin film capacitor according to any one of claims 1 to 13 , wherein a laminated body of a dielectric thin film and a lower electrode or an electrode serving as an upper electrode is formed on the upper electrode.

Film capacitor according to any one of claims 1 to 14, characterized in that at least part of a surface the non-substrate side is covered by the surface protective film.

Composite passive component including a thin film capacitor as set forth in any of claims 1 to 15, the thin film resistors and / or inductors, the thin film capacitor but is characterized in that it is formed on the same substrate.

On a base material having a thickness of 2 μm or more and 100 μm or less, a first contact electrode formed of any one of Ti, Cr, and Zr in contact with the base material, and W formed on the first contact electrode , A high elastic electrode having a film thickness of 300 nm or more formed of any one of Mo, Fe, Ni, and Co , and a material having a Young's modulus lower than that of the high elastic electrode formed on the high elastic electrode A step of forming a lower electrode having an oxidation resistant electrode, a step of forming a dielectric thin film on the lower electrode, a step of forming an upper electrode on the dielectric thin film, and patterning the upper electrode And a step of patterning the dielectric thin film, and a step of patterning the lower electrode so as to occupy an area larger than that of the dielectric thin film. .

On a base material having a thickness of 2 μm or more and 100 μm or less, a first contact electrode formed of any one of Ti, Cr, and Zr in contact with the base material, and W formed on the first contact electrode , A high elastic electrode having a film thickness of 300 nm or more formed of any one of Mo, Fe, Ni, and Co , and a material having a Young's modulus lower than that of the high elastic electrode formed on the high elastic electrode A step of forming a lower electrode having an oxidation resistant electrode, a step of forming a dielectric thin film on the lower electrode, and an upper electrode patterned on the dielectric thin film by a selective etching method or a lift-off method Before or after forming the upper electrode, patterning the dielectric thin film, and patterning the lower electrode to occupy a larger area than the dielectric thin film. And a step of manufacturing the thin film capacitor.

19. The method of manufacturing a thin film capacitor according to claim 17 , wherein in the step of patterning the dielectric thin film, patterning is performed so that the patterned dielectric thin film protrudes from the upper electrode.

The method for manufacturing a thin film capacitor according to claim 17, wherein the above-described step is performed with the base material fixed to a fixed frame.

The thin film according to any one of claims 17 to 19 , wherein the above step is performed by bonding the base material on a rigid substrate or forming the base material on a rigid substrate. A method for manufacturing a capacitor.

Any said substrate is a resin substrate, the annealing temperature of the deposition temperature or the dielectric thin film of the dielectric thin film is, of claims 17 to 20, wherein the higher than curing temperature of said substrate A method for producing the thin film capacitor according to claim 1.

23. A thin film capacitor comprising the manufacturing method according to claim 17 , wherein a thin film resistor and / or an inductor is formed during or after the manufacturing process. A manufacturing method for composite passive components.

23. A thin film capacitor comprising the manufacturing method according to claim 17 , wherein a passive component is formed using a part or all of the conductive film constituting the lower electrode. A method of manufacturing a composite passive component.

23. A manufacturing method according to claim 17 , wherein the entire surface of the capacitor forming region excluding the lead electrode forming portion is covered with a photosensitive resin or photosensitive glass following the step of patterning the lower electrode. A method of manufacturing a composite passive component including a thin film capacitor, further comprising: forming an insulating layer as described above; and forming an adhesion layer of the extraction electrode and a thin film resistor with the same material.

A manufacturing method according to claim 17 , wherein the entire surface of the capacitor forming region excluding the lead electrode forming portion is formed using a photosensitive resin or photosensitive glass following the step of patterning the lower electrode. A step of forming an insulating layer so as to cover, a step of forming a base layer of the extraction electrode, and a step of forming the extraction electrode, wherein the extraction electrode and the inductor are simultaneously formed of the same material; A method of manufacturing a composite passive component including a thin film capacitor.

Composite passive components comprising thin film capacitors or thin-film capacitor as claimed in any of claims 1 to 16 is embedded in the resin substrate, the lower electrode of the thin film capacitor through a via hole or the thin film capacitor to reach the thin film capacitor The thin film capacitor is drawn through either a through hole or a conductive pattern to which the thin film capacitor is fixed, and the upper electrode of the thin film capacitor passes through either the via hole that reaches the thin film capacitor or the through hole that penetrates the thin film capacitor. A wiring board characterized by being drawn out through.

The composite passive component according to claim 16 is embedded in a resin substrate, and the lower electrode of the thin film capacitor is a via hole reaching the thin film capacitor, a through hole penetrating the thin film capacitor, or a conductive material to which the thin film capacitor is fixed. The upper electrode of the thin film capacitor is drawn through either a via hole that reaches the thin film capacitor or a through hole that penetrates the thin film capacitor, and is an electrode of a passive component other than the capacitor. Characterized in that the wiring board is drawn out through a through hole penetrating an electrode of a passive component other than a capacitor or a via hole reaching an electrode of a passive component other than a capacitor.

29. The wiring board according to claim 27 or 28 , wherein the thin film capacitor or the composite passive component is bonded to the resin substrate through an adhesive.

29. The wiring board according to claim 27 or 28 , wherein the thin film capacitor or the composite passive component is fixed to a conductive pattern formed on the resin substrate via a conductive adhesive or solder.

31. The wiring substrate according to claim 27 , wherein an inner layer pattern is formed in the resin substrate.

32. The wiring substrate according to claim 27, wherein the resin substrate is a flexible substrate.

33. The wiring board according to claim 27 , wherein one or more build-up wiring layers are formed on at least one main surface of the resin board.

The wiring board according to claim 33 , wherein the build-up wiring layer is formed using a prepreg cure layer or a varnish cure layer as an insulating layer.