JP4622367B2 - Electronic components - Google Patents

Description

  The present invention relates to an electronic component having a configuration in which a plurality of conductive pattern forming layers are stacked with an insulating layer interposed therebetween.

  FIG. 5A is a schematic cross-sectional view showing a configuration example of an electronic component. The electronic component 1 includes a substrate 2, a laminated portion 5 in which insulating layers 3 and conductive pattern 4 formation layers are alternately laminated on the substrate 2, and a substrate bonded to the upper side of the laminated portion 5. 6.

JP-A-9-289128

  The electronic component 1 shown in FIG. 5A can be manufactured as follows. For example, the insulating layer 3 is laminated on the upper surface of the substrate 2 using a film formation technique such as sputtering, vapor deposition, or screen printing, and the conductive pattern 4 is laminated on the insulating layer 3. Then, the insulating layer 3 and the formation layer of the conductive pattern 4 are alternately and sequentially formed so that the insulating layer 3 is stacked on the upper side, thereby forming the stacked portion 5. Then, after forming the laminated portion 5, the substrate 6 is bonded to the upper side of the laminated portion 5 while applying pressure. In this way, the electronic component 1 can be manufactured.

  By the way, the conductive pattern 4 is not laminated on the entire upper surface of the insulating layer 3 but is partially laminated on the upper surface of the insulating layer 3. When the insulating layer 3 is laminated, the upper surface of the insulating layer 3 is divided into a portion where the conductive pattern 4 is formed and a portion where the conductive pattern 4 is not formed. The height position will be different and the surface will be uneven.

  The upper surface of the laminated portion 5 formed by alternately laminating the insulating layers 3 and the conductive patterns 4 is an uneven surface as shown in the model cross-sectional view of FIG. In the bonding step of the stacked portion 5 and the substrate 6, the substrate 6 is disposed on the uneven surface of the stacked portion 5, and the stacked portion 5 and the substrate 6 are bonded while pressing the substrate 6 against the stacked portion 5. At this time, it is desirable that the pressing force from the substrate 6 side is uniformly applied to the entire laminated portion 5, but the pressing force from the substrate 6 side is not uniform due to the unevenness of the upper surface of the laminated portion 5. It will be concentrated on the part forming part. As a result, the following problems occur.

  That is, a part of the force F applied from the substrate 6 side to the convex portion forming portion of the laminated portion 5 directly receives the force from the substrate 6 side as shown by the arrow f in FIG. Escape to the recessed portion forming side of the laminated portion 5 not present. In a portion where such a force f is applied from a direction facing each other, an upward force as indicated by an arrow U in FIG. 5B is generated by applying the force f from the direction facing each other. . Due to this force U, there arises a problem that, for example, delamination such that the insulating layer 3 is peeled off from the conductive pattern 4 occurs, or interlayer adhesion is weakened. The delamination or degradation of interlayer adhesion adversely affects the electrical characteristics of the electronic component 1 and causes the electrical characteristics of the electronic component 1 to be degraded.

  Further, the electronic component 1 tends to be miniaturized, and with the miniaturization of the electronic component 1, the gap between the conductive patterns 4A and 4B arranged on the same layer surface is becoming narrower. For this reason, if the potentials of the conductive patterns 4A and 4B are different from each other, migration between the conductive patterns 4A and 4B occurs when the interlayer adhesion deteriorates or delamination occurs in the region between the conductive patterns 4A and 4B. This is likely to occur, the electrical characteristics of the electronic component 1 may be deteriorated, and the reliability of the electrical performance of the electronic component 1 may be reduced.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an electronic component that can improve the reliability of electrical characteristics.

In order to achieve the above object, the present invention has the following configuration as means for solving the above problems. That is, the present invention includes a laminated portion in which a plurality of conductive pattern forming layers are laminated and pressed through insulating layers, and a laminated portion in which conductive pattern forming layers and insulating layers are alternately laminated. Each of the upper and lower sides is an electronic component in which a substrate is bonded and arranged, and a plurality of conductive patterns having different potentials are arranged with a gap on the layer surface of at least one conductive pattern forming layer , On the layer surface of any conductive pattern forming layer in which a plurality of conductive patterns having different potentials are formed, the plurality of conductive patterns having different potentials are electrically disconnected from each other, and a plurality of conductive patterns are formed. of the conductive patterns, together they are conductively connected differently to a separate external connection electrodes of different conductive patterns potentials from one another potential, it different their potential The layer surface of the conductive pattern forming layer in which a plurality of conductive patterns are provided and the floating dummy pattern is provided not conductive patterns electrically connected to, the floating dummy patterns are different the potentials on the same layer plane It is characterized by being disposed and formed at a position between conductive patterns and at a position overlapping with a conductive pattern or a floating dummy pattern formed in another conductive pattern forming layer.

Further, according to the present invention, a conductive pattern or a floating dummy pattern is formed on each of the other conductive pattern forming layer portions overlapping with the floating dummy pattern, respectively, or disposed on the same conductive pattern forming layer. a plurality of conductive patterns and the floating dummy patterns are are formed from the same conductive material, and is characterized also that it is a pattern formed in the same step.

  According to the present invention, at least one conductive pattern forming layer is provided with a floating dummy pattern that is not electrically connected to the conductive pattern, and the floating dummy pattern is spaced on the layer surface of the same conductive pattern forming layer. The conductive pattern is arranged at a position between the conductive patterns having different electric potentials disposed between the conductive patterns and a floating dummy pattern formed on another conductive pattern forming layer. For example, when a floating dummy pattern is not provided between the conductive patterns, the insulating layer formed on the upper side of the conductive pattern forming layer is depressed at a gap position between the conductive patterns to form a recess. . On the other hand, by providing a floating dummy pattern between the conductive patterns, such a drop of the insulating layer can be suppressed, and unevenness of the insulating layer can be reduced. For this reason, the unevenness | corrugation of the upper surface of the laminated part formed by laminating | stacking an insulating layer and a conductive pattern formation layer alternately can be suppressed small. Thereby, when pressurizing a lamination part, the equalization of the pressurization pressure to a lamination part can be aimed at, and the problem of delamination resulting from pressurization nonuniformity can be prevented. For this reason, it is possible to prevent deterioration of the electrical characteristics of the electronic component due to delamination.

  In addition, when a portion having weak interlayer adhesion or a delamination occurs between conductive patterns having a potential difference due to uneven pressure applied to the laminated portion, the probability of occurrence of migration becomes very high. . On the other hand, in the present invention, the floating dummy pattern is provided between the conductive patterns having such a potential difference, and as described above, the applied pressure to the laminated portion can be equalized. Interlayer adhesion between patterns can be made good, and migration can be avoided. As a result, it is possible to suppress deterioration of the electrical characteristics of the electronic component due to migration, and to improve the reliability of the electronic component.

  Furthermore, by providing a structure in which conductive patterns or floating dummy patterns are formed in all other conductive pattern forming layer portions that overlap the floating dummy patterns, the unevenness on the top surface of the stacked portion is further reduced. And the problem of delamination as described above can be prevented more reliably.

  A configuration in which a plurality of conductive patterns and floating dummy patterns formed in the same conductive pattern forming layer are formed of the same conductive material and are formed in the same process, thereby providing a floating dummy pattern However, an increase in the manufacturing process can be avoided, and an increase in manufacturing cost can be suppressed. Furthermore, it is easy to increase the strength of the electronic component by the substrate by adopting a configuration in which the substrate is bonded and disposed on both the upper and lower sides of the stacked portion.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 1 shows a schematic exploded view of the electronic component of the first embodiment, and FIG. 2A shows an example of an external appearance of the electronic component of the first embodiment. 2 (b) shows a schematic cross-sectional view of the AA portion shown in FIG. 1, and FIG. 2 (c) shows a schematic cross-sectional view of the BB portion shown in FIG. ing.

  The electronic component 1 includes a substrate 2, a laminated portion 5 in which insulating layers 3 and conductive pattern 4 formation layers are alternately laminated on the substrate 2, and a substrate bonded to the upper side of the laminated portion 5. 6, external connection electrodes 7 and 8, and a floating dummy pattern 10 and a dummy terminal pattern 11.

  In the first embodiment, both the substrates 2 and 6 are made of the same material, and are made of a substrate previously selected from a magnetic substrate, a dielectric substrate, and an insulating substrate. Further, in the first embodiment, the conductive patterns 4A and 4B having two coil shapes (spiral shapes) are arranged in parallel with each other at an interval to form a conductive pattern forming layer. Such two conductive pattern forming layers are laminated and disposed via the insulating layer 3. The conductive patterns 4A formed in each conductive pattern forming layer and adjacent to each other in the stacking direction are connected in series by via holes 12 (12A) formed in the insulating layer 3 (3B) between the conductive pattern forming layers. One coil is formed. One end of this coil (the end Ta of the conductive pattern 4A on the lower layer) is connected to the external connection electrode 7A, and the other end of the coil (the end Tb of the upper conductive pattern 4A) is for external connection. The coil connected to the electrode 7B and composed of the two conductive patterns 4A can be electrically connected to the outside via the external connection electrodes 7 (7A, 7B).

  Also, the conductive patterns 4B formed in each conductive pattern forming layer and adjacent to each other in the stacking direction are connected in series by the via holes 12 (12B) formed in the insulating layer 3B in the same manner as the conductive patterns 4A. To form one coil. One end side of the coil (end portion Tc of the upper conductive pattern 4B) is connected to the external connection electrode 8A, and the other end side of the coil (end portion Td of the lower conductive pattern 4B) is for external connection. The coil connected to the electrode 8B and composed of the two conductive patterns 4B can be electrically connected to the outside via the external connection electrodes 8 (8A, 8B).

  In the first embodiment, the coil composed of the conductive pattern 4A and the coil composed of the conductive pattern 4B are connected to the external connection electrodes 7, 8, the conductive pattern 4A and the conductive pattern 4B have different potentials.

  The floating dummy pattern 10 is not connected to the conductive pattern 4 (4A, 4B) and is electrically floating. The floating dummy pattern 10 is a gap position between the conductive patterns 4A and 4B having different potentials formed in the same conductive pattern forming layer, and as shown in the model cross-sectional view of FIG. In the first embodiment, it is disposed at a position overlapping the floating dummy pattern 10 formed in another conductive pattern forming layer. The stacked arrangement of the floating dummy patterns 10 can suppress the drop of the insulating layer 3 in the gap between the conductive patterns 4A and 4B.

  The dummy terminal patterns 11 (11a to 11d) are formed at positions overlapping the end portions Ta to Td of the conductive pattern 4 connected to the external connection electrodes 7 and 8, respectively. That is, as shown in the model cross-sectional view of FIG. 2B, the dummy terminal pattern 11a is arranged at a position overlapping the end portion Ta of the conductive pattern 4A on the lower side of the stack connected to the external connection electrode 7A. The dummy terminal pattern 11b is arranged at a position overlapping the end portion Tb of the conductive pattern 4A on the upper side of the stack connected to the external connection electrode 7B. Similarly, the dummy terminal pattern 11c is arranged at a position overlapping the end portion Tc of the upper conductive pattern 4B connected to the external connection electrode 8A, and the dummy terminal pattern 11d is connected to the external connection electrode 8B. It is arranged at a position overlapping the end portion Td of the conductive pattern 4B on the lower side of the stacked layer.

  By providing such a dummy terminal pattern 11, it is possible to suppress the drop of the insulating layer 3 in the portions where the end portions Ta to Td of the conductive pattern 4 are formed, thereby contributing to the flattening of the upper surface of the stacked portion 5. In addition, it is possible to prevent problems such as an open failure of the external connection electrodes 7 and 8. The dummy terminal pattern 11 is connected to the external connection electrodes 7 and 8 and is applied with a voltage. Therefore, the dummy terminal pattern 11 is not electrically floating, and this point is significantly different from the floating dummy pattern 10. ing. The dummy terminal patterns 11a and 11b are connected to the external connection electrodes 7 (7A and 7B) in the same manner as the conductive patterns 4A adjacent to each other with a space on the same layer surface, and the dummy terminal patterns 11a and 11b. There is no potential difference between the conductive pattern 4A. Furthermore, the dummy terminal patterns 11c and 11d are connected to the external connection electrodes 8 (8A and 8B) in the same manner as the conductive patterns 4B adjacent to each other with a space on the same layer surface, and the dummy terminal patterns 11c and 11d. There is no potential difference between the conductive pattern 4B and the conductive pattern 4B.

The electronic component 1 shown in the first embodiment is configured as described above. Below, an example of the manufacturing process of the electronic component 1 of this 1st Embodiment is demonstrated. First, the substrate 2 is prepared, and the insulating layer 3 (3A) is laminated on the entire upper surface of the substrate 2. Examples of the constituent material of the insulating layer 3 include, for example, resin materials such as polyimide resin, epoxy resin, and benzocyclobutene resin, glass materials such as SiO ₂ , glass ceramics, and dielectrics. Before the insulating layer 3 (3A) is formed on the substrate 2, it is preferable that the upper surface of the substrate 2 is polished, for example, so that the surface roughness Ra of the substrate 2 is, for example, 0.5 μm or less. By polishing and smoothing the surface of the substrate 2 in this way, the adverse effect of the substrate surface roughness is exerted on the insulating layer 3 and the conductive pattern 4 which are laminated on the upper surface of the substrate 2. Can be prevented.

  The conductive pattern 4 (4A, 4B), the floating dummy pattern 10 (10A), and the dummy terminal pattern 11 (11b, 11c) are stacked on the upper side of the insulating layer 3A to produce a conductive pattern forming layer on the lower side of the stack. To do. These patterns 4, 10, and 11 can be formed as follows using, for example, a photolithography technique.

  For example, a conductor film is laminated and formed on the entire upper surface of the insulating layer 3A using a film formation technique (for example, a thin film formation technique such as sputtering or vapor deposition, or a thick film formation technique such as screen printing). The conductive film is a film of a conductive material constituting a pattern. Examples of the conductive material include, for example, metals such as Ag, Pd, Cu, and Al having excellent conductivity, and two or more of these metals. An alloy etc. are mentioned. By the way, the insulating material constituting the insulating layer 3 and the conductive material forming the patterns 4, 10, and 11 take into consideration workability and the adhesion between the insulating layer 3 and the patterns 4, 10, and 11. Is preferably selected and set.

  After the formation of the conductor film, a resist film is laminated on the entire upper surface of the conductor film, and a pattern forming mask is disposed above the resist film. Then, the resist film portion in the formation region of the patterns 4, 10, and 11 is irradiated with light such as ultraviolet rays through the mask to photocur the resist film portion. Thereafter, the uncured resist film portion is removed by development processing. As a result, the resist film is formed only in the formation regions of the patterns 4, 10, and 11. Thereafter, the conductive film portion where the resist film is not formed is removed by, for example, etching or the like, and the patterns 4, 10, and 11 are formed. Then, the resist film on the patterns 4, 10, and 11 is removed. By such a photolithography technique, a conductive pattern forming layer composed of the patterns 4, 10, and 11 can be produced.

  After the formation of the conductive pattern forming layer, the insulating layer 3 (3B) is laminated on the conductive pattern forming layer. Via holes 12 (12A, 12B) can be provided in the insulating layer 3 (3B) by using the following photolithography technique. For example, the insulating layer 3 (3B) made of a photosensitive insulating material is laminated on the conductive pattern forming layer. A mask for forming a via hole is arranged above the insulating layer 3B, and light such as ultraviolet rays is irradiated through the mask to a portion other than the via hole forming region to be photocured. Thereafter, only the uncured insulating layer portion is removed by development processing. Thereby, a hole for forming a via hole is formed in the insulating layer 3 (3B).

  After the formation of the insulating layer 3 (3B), the conductive pattern 4 (4A, 4B), the floating dummy pattern 10 (10B), and the dummy terminal pattern 11 (11a, 11d) are formed using, for example, the same photolithography technique as described above. Then, a conductive pattern forming layer is laminated on the insulating layer 3B. A part of the conductive material constituting the patterns 4, 10, and 11 enters the via hole forming hole of the insulating layer 3B to complete the via hole 12 (12A, 12B).

  After the formation of the conductive pattern formation layer, the insulating layer 3 (3C) is laminated on the upper side. In this way, the laminated portion 5 of the insulating layer 3 and the conductive pattern forming layer is laminated on the substrate 2. A substrate 6 is bonded to the upper side of the stacked portion 5. In this bonding step, for example, an adhesive such as a thermosetting polyimide resin is applied to the surfaces of the stacked portion 5 and the substrate 6 facing each other (that is, the upper surface of the stacked portion 5 and the back surface of the substrate 6). After that, the substrate 6 is disposed on the upper surface of the laminated portion 5 and, for example, heated in a state where the substrate 6 is relatively pressed against the laminated portion 5 in a vacuum or in an inert gas atmosphere. The part 5 is adhered. Then, after cooling, the pressurized state is released.

  By the way, although the process so far may be performed for each electronic component 1, in order to improve manufacturing efficiency, the laminated portion 5 is formed on the substrate 2 in the state of the parent substrate, and this laminated portion is formed. In many cases, a large number of electronic components 1 are manufactured at the same time by bonding and integrating the substrate 6 in the state of the parent substrate on the upper side of 5. In such a case, after the laminated body of the substrates 2 and 6 and the laminated portion 5 is formed, the laminated body is cut along the boundary line of each electronic component 1 and separated and divided for each electronic component 1.

  Thereafter, the external connection electrodes 7 and 8 are formed on the side surface of the electronic component 1 for each electronic component 1. The external connection electrodes 7 and 8 are formed on the side surface of the electronic component 1 by applying a conductive paste containing a conductive material such as Ag, Ab-Pd, Cu, NiCr, or NiCu, or by a film forming technique such as sputtering or vapor deposition. After the base electrode is formed on the base electrode, a metal film such as Ni, Sn, Sn—Pb or the like can be formed on the base electrode by, for example, wet electrolytic plating.

  In this way, the electronic component 1 can be manufactured.

  The second embodiment will be described below. In the description of the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and duplicate descriptions of common portions are omitted.

  The electronic component 1 according to the second embodiment is a common mode choke coil component, and has an external shape as shown in the schematic perspective view of FIG. As shown in the schematic exploded view, the substrate 2, the laminated portion 5 formed on the substrate 2, the substrate 6 formed on the laminated portion 5, and the external connection electrodes 7, 8, It is comprised.

  In the second embodiment, the substrates 2 and 6 are each made of a magnetic material. The stacked portion 5 includes an insulating layer 3A, a first conductive pattern forming layer in which the conductive pattern 4Aa is formed, an insulating layer 3B, and a second conductive pattern forming layer in which the conductive pattern 4Ab is formed. The insulating layer 3C, the third conductive pattern forming layer in which the conductive pattern 4Ba is formed, the insulating layer 3D, the fourth conductive pattern forming layer in which the conductive pattern 4Bb is formed, and the insulating layer 3E A structure in which layers are sequentially formed is provided.

  The conductive patterns 4Aa, 4Ab, 4Ba, and 4Bb each have a spiral shape. The conductive patterns 4Aa and 4Ab are stacked via an insulating layer 3B, and one end side of each of the conductive patterns 4Aa and 4Ab is connected to the external connection electrode 7A, and each of the conductive patterns 4Aa and 4Ab Both other end sides are connected to the external connection electrode 7B, and the conductive patterns 4Aa and 4Ab are connected in parallel. The conductive patterns 4Aa and 4Ab connected in parallel constitute, for example, a primary coil of a common mode choke coil, and the primary coil can be connected to the outside via the external connection electrodes 7A and 7B.

  The spiral inner ends of the conductive patterns 4Aa and 4Ab are electrically connected to each other through a via hole 12 formed in the insulating layer 3B. In addition, the conductive pattern 4Aa is electrically connected to the conductive pattern 4Ab through the via hole 12 of the insulating layer 3B in the middle of the conductive pattern 4Aa from one end side to the other end side, and the conduction current of the conductive pattern 4Ab is also conducted. There is a section.

  The conductive patterns 4Ba and 4Bb are the same as the conductive patterns 4Aa and 4Ab. One end sides of the conductive patterns 4Ba and 4Bb are both connected to the external connection electrode 8A, and the other end sides of the conductive patterns 4Ba and 4Bb are connected to each other. Are connected to the external connection electrode 8B, and the conductive patterns 4Ba and 4Bb are connected in parallel. The conductive patterns 4Ba and 4Bb connected in parallel constitute, for example, a secondary coil of a common mode choke coil, and the secondary coil can be connected to the outside via the external connection electrodes 8A and 8B. . Currents of different potentials are passed through the primary coil and the secondary coil of the common mode choke coil, respectively.

  In the second embodiment, the dummy terminal pattern 11 is provided in each of the third conductive pattern forming layer in which the conductive pattern 4Ba is formed and the fourth conductive pattern forming layer in which the conductive pattern 4Bb is formed. (11a, 11b) is formed. As shown in the model cross-sectional view of FIG. 4A, the dummy terminal pattern 11a is arranged at a position overlapping the end portions Ta of the conductive patterns 4Aa and 4Ab, and the dummy terminal pattern 11a corresponds to the external connection electrode 7A. This is a conductive pattern that is electrically connected to the substrate and is energized with current. The dummy terminal pattern 11b is disposed at a position overlapping the end portions Tb of the conductive patterns 4Aa and 4Ab, and the dummy terminal pattern 11b is electrically connected to the external connection electrode 7B and a conductive pattern through which current flows. It is made. The dummy terminal pattern 11a is for preventing the insulating layer 3 from dropping in the portions where the end portions Ta of the conductive patterns 4Aa and 4Ab are formed. Similarly, the dummy terminal pattern 11b is formed by the end portions Tb of the conductive patterns 4Aa and 4Ab. This is to prevent the insulating layer 3 from dropping in the formation portion.

  In the second embodiment, as described above, the dummy terminal patterns 11a and 11b are electrically connected to the external connection electrodes 7A and 7B, respectively, and the dummy terminal patterns 11 (11a and 11b). The conductive patterns 4 (4Ba, 4Bb) which are adjacent to each other on the same layer surface with the gap between them are electrically connected to the external connection electrodes 8A, 8B. Therefore, the dummy terminal patterns 11 (11a, 11b) and a potential difference between the conductive pattern 4 (4Ba, 4Bb). In the second embodiment, the floating dummy pattern 10 (10a, 10b) is disposed at a position between the dummy terminal pattern 11 and the conductive pattern 4 where the potential difference occurs. The floating dummy pattern 10 is not electrically connected to any conductive pattern of the dummy terminal pattern 11 and the conductive pattern 4 and is electrically floating. In addition, the floating dummy pattern 10 (10a, 10b) is not only provided at a position between the dummy terminal pattern 11 and the conductive pattern 4 having different potentials. In the second embodiment, FIG. As shown, the floating dummy pattern 10 or the conductive pattern (in this example, the end portions Ta and Tb of the conductive patterns 4Aa and 4Ab) formed in another conductive pattern forming layer is positioned to satisfy the condition of overlapping. Has been placed.

  Further, in the second embodiment, the first conductive pattern forming layer in which the conductive pattern 4Aa is formed and the second conductive pattern forming layer in which the conductive pattern 4Ab is formed have dummy terminals, respectively. Pattern 11 (11c, 11d) is formed. As shown in the model cross-sectional view of FIG. 4B, the dummy terminal pattern 11c is arranged at a position overlapping the end portions Tc of the conductive patterns 4Ba and 4Bb, and the dummy terminal pattern 11c is the external connection electrode 8A. Is electrically connected. The dummy terminal pattern 11d is disposed at a position overlapping the end portions Td of the conductive patterns 4Ba and 4Bb, and the dummy terminal pattern 11d is electrically connected to the external connection electrode 8B. The dummy terminal pattern 11c is for preventing the insulating layer 3 from dropping in the portions where the end portions Tc of the conductive patterns 4Ba and 4Bb are formed. Similarly, the dummy terminal pattern 11d is the end portion Td of the conductive patterns 4Ba and 4Bb. This is to prevent the insulating layer 3 from dropping in the formation portion.

  Similarly to the third and fourth conductive pattern forming layers, the first and second conductive pattern forming layers have floating dummy patterns 10 (10c and 10d) that are electrically floating, respectively, as shown in FIG. As shown in (b), the floating dummy in the position between the dummy terminal pattern 11 (11c, 11d) and the conductive pattern 4 (4Aa, 4Ab) where a potential difference occurs and in another conductive pattern forming layer. The pattern 10 or the conductive pattern (in the example shown, the conductive patterns 4Ba and 4Bb are arranged at positions overlapping with the ends Tc and Td).

  The electronic component 1 shown in the second embodiment can also be manufactured by the same manufacturing process as that of the electronic component 1 shown in the first embodiment. That is, the conductive pattern 4, the floating dummy pattern 10, and the dummy terminal pattern 11 can be formed with high positional accuracy and high accuracy by using photolithography technology, and the via hole 12 is provided in the insulating layer 3. be able to.

  The present invention is not limited to the first and second embodiments, and various embodiments can be adopted. For example, in each of the first and second embodiments, the conductive pattern 4 has a spiral shape (coil shape). Of course, the shape of the conductive pattern of the electronic component to which the present invention is applied is limited. For example, the present invention may be applied to an electronic component having a conductive pattern other than a coil shape such as a meander shape for forming an inductor or a square shape or a circular shape for forming a capacitor. it can.

  In the first embodiment, two conductive pattern formation layers are provided. In the second embodiment, four conductive pattern formation layers are provided. However, the number of conductive pattern formation layers is as follows. If it is two or more layers, it is not limited, and is appropriately set according to the specification and the like.

  Further, in each of the first and second embodiments, the floating dummy pattern 10 is located between conductive patterns having different potentials arranged side by side on the same layer surface, and in another conductive pattern forming layer. The conductive pattern or the floating dummy pattern is disposed at the position where it overlaps, but for example, only one conductive pattern is formed or only a plurality of conductive patterns with the same potential are formed. When the conductive pattern forming layer that is not included is included in the laminated portion 5, the floating dummy pattern 10 may be provided also in the conductive pattern forming layer.

  Further, in each of the first and second embodiments, the conductive pattern 4 or the floating dummy pattern 10 is formed in all other conductive pattern forming layer portions that overlap the floating dummy pattern 10. The conductive pattern 4 or the floating dummy pattern 10 may be formed only in the conductive pattern forming layer selected from all other conductive pattern forming layers overlapping the pattern 10.

1 is an exploded view schematically showing an electronic component according to a first embodiment. It is a model figure for demonstrating the characteristic structure of the electronic component of the example of 1st Embodiment. It is a figure for demonstrating the common mode choke coil which is an electronic component of the example of 2nd Embodiment. It is typical sectional drawing for demonstrating the specific component of the electronic component of the example of 2nd Embodiment. It is a figure for demonstrating the conventional problem.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electronic component 2, 6 Board | substrate 4 Conductive pattern 5 Lamination | stacking part 10 Floating dummy pattern 11 Dummy terminal pattern

Claims (3)

A plurality of conductive pattern forming layers are stacked and pressed with an insulating layer interposed therebetween, and are provided with a stacked portion, and the conductive pattern forming layer and the insulating layer are alternately stacked on the upper and lower sides of the stacked portion. In the electronic component in which the substrates are bonded and arranged , a plurality of conductive patterns having different potentials are disposed on the layer surface of the at least one conductive pattern forming layer with a gap therebetween . On the layer surface of any conductive pattern forming layer in which the conductive pattern is formed, the plurality of conductive patterns having different potentials are electrically disconnected from each other and are electrically connected to each other. different separate with are conductively connected to the external connection electrodes of different conductive patterns of potential potential to each other, a plurality of conductive patterns having different their potential The layer surface of the conductive pattern forming layer being kicked and floating dummy patterns which are not electrically conductive pattern and electrically connected is provided, the floating dummy patterns are located between the different conductive patterns of the potential on the same layer plane An electronic component characterized by being arranged and formed at a position overlapping a conductive pattern or a floating dummy pattern formed in another conductive pattern forming layer.   2. The electronic component according to claim 1, wherein a conductive pattern or a floating dummy pattern is formed in each of the other conductive pattern forming layer portions that overlap the floating dummy pattern.   The plurality of conductive patterns and floating dummy patterns arranged in the same conductive pattern formation layer are patterns formed of the same conductive material and manufactured in the same process. 2. Electronic component according to 2.

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