WO2006077630A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
WO2006077630A1
WO2006077630A1 PCT/JP2005/000586 JP2005000586W WO2006077630A1 WO 2006077630 A1 WO2006077630 A1 WO 2006077630A1 JP 2005000586 W JP2005000586 W JP 2005000586W WO 2006077630 A1 WO2006077630 A1 WO 2006077630A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
resin layer
solder
resin
forming
Prior art date
Application number
PCT/JP2005/000586
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English (en)
French (fr)
Inventor
Hiroyuki Kurata
Original Assignee
New Japan Radio Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co., Ltd. filed Critical New Japan Radio Co., Ltd.
Priority to PCT/JP2005/000586 priority Critical patent/WO2006077630A1/ja
Priority to JP2006520504A priority patent/JP4739198B2/ja
Priority to US11/630,000 priority patent/US7326638B2/en
Publication of WO2006077630A1 publication Critical patent/WO2006077630A1/ja

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Definitions

  • the present invention relates to a method for manufacturing a semiconductor device that can achieve small size, thinness, light weight, and low price. More specifically, a semiconductor device having a structure that can be directly mounted on a mother board or the like without using a lead frame or an interposer while having fine electrode terminals is obtained through a simple manufacturing process and at a low cost.
  • the present invention relates to a method for manufacturing a semiconductor device. Background art
  • a semiconductor chip 21 is die-bonded to a die pad 22 of a lead frame, and an electrode pad 21a and a lead 23 of a lead frame are connected by a gold wire 24. It is manufactured by forming the package 25 by wire bonding and molding with grease.
  • the electrode pads 21a around the semiconductor chip 21 are dispersed on the semiconductor chip 21 to form solder balls.
  • Chip size packages are being considered. That is, in the example shown in FIG. 16, a wiring (not shown) is formed on one surface of an interposer 26 that has a force such as a ceramic substrate, an organic material substrate such as polyimide, a film tape, and the like. Are connected to each other by wire bonding using a gold wire 24 or the like, and the external electrode 27 having a force such as a solder ball is formed on the back surface of the interposer 26 to connect the wiring to the semiconductor chip 21 side. This is a technology that coats with oil 25.
  • a solder bump 2 lb is formed on an electrode pad (not shown) without connecting the electrode pad 21a of the semiconductor chip 21 and the wiring by wire bonding, and the solder bump 21b is connected to the solder bump 21b. It directly connects the wiring of the poser 26, and the other configuration is the same as the example shown in FIG. 28 is a resin layer for fixing the semiconductor chip.
  • the electrode pads are provided around the semiconductor chip at intervals of about 100 to 200 ⁇ m.
  • the wiring of the circuit board on which the semiconductor device is mounted has an interval of about 0.5 mm, and even if the bump electrode is formed on the electrode pad of the semiconductor chip, it cannot be mounted directly on the circuit board.
  • a chip size package requires a force interposer that can be reduced in size and a connection process for connecting to it.
  • This interposer generally has a higher cost because it requires less distribution, that is, less production than a semiconductor device that uses a lead frame, and also requires fine molding.
  • the wire bonding between this interposer and the semiconductor chip is a one-by-one connection, so it is not possible to perform batch processing.
  • expensive equipment such as a stepper and resist coating / developing / exposure equipment is required. Therefore, the chip size package can realize a small size, a thin shape, and a light weight, but there is a problem that the cost is increased.
  • the present inventor disperses the electrode pad over the entire surface of the semiconductor chip by wiring on the surface of the semiconductor substrate on which the electronic circuit is formed, and electrolessly forms on the electrode pad.
  • a barrier metal layer is formed by a plating method, a solder core is formed thereon, a resin layer is formed on the entire surface, and then the solder core is exposed by grinding, and a solder bump is formed on the surface of the exposed solder core.
  • a method for manufacturing a small and thin semiconductor device by grinding and thinning the back surface of the semiconductor substrate to provide a force back surface resin layer is disclosed (see Patent Document 1).
  • Patent Document 1 Japanese Patent Laid-Open No. 2003-338515
  • the thickness of the backside resin layer varies by several tens / zm.
  • barrier meta By forming the metal layer by the above-mentioned electroless plating method, the vacuum deposition method can be easily formed with no waste of metal compared to the notching method, etc. Therefore, it is necessary to attach an insulating sheet to the back surface of the semiconductor substrate and remove the insulating sheet after the electroless plating is completed, and the process of attaching and removing the insulating sheet becomes complicated! There's a problem.
  • the present invention has been made in view of such a situation, and without using an interposer, the electrode interval is widened, and a noria metal is formed by an electroless plating method, while the semiconductor substrate is used for the electroless plating.
  • the special process of masking the back side with an insulating sheet can be omitted, and it is possible to reduce the cost while realizing a small, thin, and light weight by forming the desired thickness reliably.
  • An object is to provide a method for manufacturing a semiconductor device.
  • an electronic circuit is formed on a surface that is one surface of a semiconductor substrate, and electrode terminals of the electronic circuit are dispersed on the semiconductor substrate via wiring.
  • Forming a rearranged electrode pad by: (b) grinding the back side which is the other side of the semiconductor substrate; and (c) forming a first resin layer on the ground surface of the semiconductor substrate.
  • a step of forming a barrier metal layer on the electrode pad by electroless plating after forming the first resin layer and (e) a step of forming on the nore metal layer.
  • the first resin layer is thinly formed by attaching a resin sheet to the ground surface of the semiconductor substrate and curing the resin sheet. It is preferable because a resin layer having an accurate thickness can be formed.
  • the back surface of the semiconductor substrate is ground and thinned in the step before the electroless plating to form the first resin layer. Therefore, the metal film of the noria metal layer can be formed only on the electrode pad without forming the metal film of the noria metal layer on the back surface of the semiconductor substrate during electroless plating. As a result, for the electroless plating process, only the electrode pad portion that is necessary to form the bump electrode without interposing the wasteful process of covering the back surface of the semiconductor substrate with an insulating film and removing the insulating film after plating is used. A noria metal layer can be formed.
  • Electroless plating like electrolytic plating, forms a resist on a metal film provided by sputtering or the like on the entire surface, performs electrolytic plating, and then etches resist and unnecessary metal films. It can form without going through. Furthermore, since the back surface of the semiconductor substrate is covered with a shock-resistant resin layer, it is possible to prevent damage during transportation of the manufacturing process while being thin, and both surfaces of the semiconductor substrate are sandwiched between the resin layers. Therefore, warping of the wafer can be prevented. As a result, it is possible to manufacture at a low cost with a high yield by a very simple manufacturing process.
  • the first resin layer is formed by a method in which a resin sheet is attached and cured by heat treatment, a thin layer can be formed with a certain thickness, so that the target is achieved. With this thickness, a very thin semiconductor device can be obtained.
  • the thickness variation of the thickness is as large as several tens / zm, and a semiconductor device having an overall thickness of about 500 m is generated.
  • the first resin layer is formed from the resin sheet. The first resin layer can be thinned and formed with a constant thickness. As a result, it greatly contributes to manufacturing a very thin semiconductor device.
  • FIG. 1 is an explanatory view showing a manufacturing process of an embodiment of a manufacturing method according to the present invention.
  • FIG. 2 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
  • FIG. 3 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
  • FIG. 4 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
  • FIG. 5 is an explanatory diagram showing a manufacturing process of one embodiment of the manufacturing method according to the present invention and a detailed specific schematic diagram thereof.
  • FIG. 6 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
  • FIG. 7 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
  • FIG. 8 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
  • FIG. 9 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
  • FIG. 10 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
  • FIG. 11 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
  • FIG. 12 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
  • FIG. 13 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
  • FIG. 14 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
  • FIG. 15 is an explanatory diagram showing an example of a structure in a conventional semiconductor device.
  • FIG. 16 is an explanatory diagram showing an example of a structure in a conventional semiconductor device.
  • FIG. 17 is an explanatory diagram showing an example of a structure in a conventional semiconductor device.
  • FIG. 11-13 an electronic circuit is formed on a semiconductor substrate 1, and electrode terminals 2 of the electronic circuit are connected to the semiconductor substrate 1 via wirings 4.
  • the electrode pads 4a rearranged are formed by dispersing, and the back surface of the semiconductor substrate 1 is ground as shown in FIG.
  • FIG. A first resin layer 6 is formed on the back surface, and as shown in FIG. 6, a barrier metal layer 7 is formed on the electrode pad 4a by electroless plating, and a noria metal layer is formed as shown in FIG.
  • a solder core 8 is formed on the surface 7 by printing solder paste and heat-treating. As shown in FIG. 8, the resin core is printed on the surface side where the solder core 8 is formed. The second resin layer 9 is formed, and the second resin layer 9 is ground to expose the solder core 8 as shown in FIG. 9, and the exposed solder core 8 is exposed as shown in FIG. Furthermore, it is manufactured by forming solder bumps 10 by printing solder paste and performing heat treatment.
  • FIG. 1 a circuit element (not shown) such as a transistor or a diode is formed on a semiconductor substrate (WENO) 1 to form an electronic circuit, and an electrode terminal of the electronic circuit is formed on the surface thereof. 2 and an insulating film 3 is formed on the surface of the semiconductor substrate 1 to protect the circuit elements.
  • WENO semiconductor substrate
  • FIG. 1 10 one electrode terminal and a bump electrode provided to be connected to the electrode terminal are shown as an example. Is formed.
  • an electrode material having a force such as A1-Si (Si is 1 wt%) is formed to a thickness of about 3 ⁇ m by sputtering or the like, and a resist film (not shown) is provided for patterning.
  • a wiring 4 is formed that extends to a desired location to be connected to the electrode terminal 2 to form a bump electrode.
  • Bump electrode type which is the end of the wiring 4 mentioned above, with a covering layer 5 that has force such as Si N provided on the entire surface
  • Patterning is performed so that only the formation site is exposed. At this time, the rearranged electrode pad 4a with the wiring 4 exposed as the bump electrode formation location is spaced from the other rearranged electrode pad at a pitch of about 0 • 4 mm, and the size is about 150 m ⁇ . To form.
  • the back surface of the semiconductor substrate 1 is ground so that the thickness of the semiconductor substrate 1 becomes 150-350 / z m.
  • the semiconductor substrate 1 having a thickness of 630 m was ground to 200 ⁇ 15 / ⁇ ⁇ ) ⁇ :
  • a first resin layer 6 is prepared by attaching a resin sheet processed into a sheet of epoxy resin containing a filler.
  • a resin sheet processed into a sheet of epoxy resin containing a filler For example 5 It is formed on the entire back surface of the wafer with a thickness of about 0 ⁇ 10 / ⁇ ⁇ .
  • the thickness is about 50 ⁇ 5 m and it is made of a material that can be dissolved in an organic solvent such as acetone, and the resin sheet 6a is cut larger than the semiconductor wafer la,
  • the semiconductor substrate 1 is attached to the back surface of the wafer la in a wafer state by heating to, for example, about 70 ° C.
  • FIG. 5 (b) the thickness is about 50 ⁇ 5 m and it is made of a material that can be dissolved in an organic solvent such as acetone
  • acetone 18 is dropped from the surface side of the wafer la while the resin sheet 6a side is fixed to the spinner 17 and rotated as shown in FIG.
  • the resin sheet 6a protruding from the periphery of the wafer la is dissolved and removed.
  • the first resin layer 6 becomes 50 ⁇ A thickness of about 10 m is formed on the entire back surface of the wafer la.
  • a noria metal layer 7 is formed on the rearranged electrode pad 4a. Specifically, it was performed as follows. First, in order to improve the hydrophilicity of the surface of the rearranged electrode pad 4a, degreasing treatment was performed, and then the acid film deposited on the surface was removed with sulfuric acid or nitric acid. Thereafter, a Zn film was replaced on the surface. After removing the Zn film with nitric acid, the Zn film was replaced again to form a uniform Zn film on the surface of the electrode pad 4a. Next, 5-9 m of Ni was precipitated by a reduction reaction.
  • a barrier metal layer 7 was formed by forming a 0.03 / zm Au film by a substitution plating method.
  • the diameter of this noria metal layer 7 was 160 m.
  • the electrode pad 4a has a large etching amount when the first Zn is formed by substitution plating. Specifically, it was etched about 0.7 m. Therefore, it is necessary to provide the wiring 4 with a thickness of about 1 ⁇ m or more. When the thickness is 1 ⁇ m or less, the material of the electrode pad 4a may be melted and lost before the second formation of Zn, and Ni plating may not grow, which is not preferable.
  • a solder core 8 is formed on the surface of the barrier metal layer 7 by a printing method.
  • an epoxy resin containing filler is applied to the surface of the semiconductor substrate 1 (the surface on which the core 8 is formed) by a printing method under atmospheric pressure. Then, the second resin layer 9 is formed. At this time, a resin printing mask having open holes is formed except for the periphery of the wafer that defines the thickness of the second resin layer 9, which is the same as the height of the solder core 8. The thickness should be in the range of 150 / zm thicker than that. After printing, leave it in a vacuum atmosphere to defoam air bubbles that have been caught during printing. Then, the resin is cured at a high temperature.
  • the mask thickness used for printing is 250 / zm thicker than the solder core height, and defoamed by leaving it under a reduced pressure of 665Pa for 20 minutes using a lOOPa's viscosity resin. Did. Thereafter, the resin was cured by heat treatment at 100 ° C for 1 hour and 150 ° C for 2 hours. The thickness of the second resin layer 9 after curing was 250 ⁇ 50 / z m. It has been confirmed that the resin used can be used at a viscosity of 25, 200, 300, 600 Pa's.
  • the second resin layer 9 on the surface side of the semiconductor substrate 1 is ground to expose the solder core 8.
  • the grinding amount of the resin was set so that the grinding surface of the second resin layer 9 was 2Z3-1Z2 at the height of the solder core 8. Specifically, when the solder core 8 is 130 m high, the thickness of the second resin layer 9 (height of the solder core 8 after grinding) is 70-90 (80 ⁇ 10) / zm. Was ground. At this time, the diameter of the exposed solder core 8 was obtained in the range of 150 ⁇ 2 ⁇ .
  • a solder bump 10 is formed on the solder core 8 by a printing method.
  • the mask used for printing the solder paste is a solder mask whose ratio of (mask opening area) Z (mask wall surface area in the opening) is 1Z2 or more. It was strong to use.
  • reflow was performed by heat treatment at 260 ° C. for 10 seconds in an inert gas atmosphere having an oxygen concentration of 10 OO ppm or less.
  • a mask with an opening having a diameter of 250 m ⁇ and a thickness t of 100 ⁇ m was used as a mask, and printing was performed using a solder paste of Sn—Cu (Cu is 2 wt%).
  • the diameter of the solder mask opening is 250 m
  • the force that can confirm that the solder is transferred up to a thickness t of 125 ⁇ m is the same as the previous case 150 ⁇ m
  • the oxygen concentration during reflow was set to lOOOppm or more
  • the height of the solder bump 10 varied.
  • the solder core 8 diameter was 150 ⁇ 20 ⁇
  • the mask opening diameter was 250 ⁇
  • the mask thickness t was 100 m
  • the height of the solder bump 10 was in the range of 120 ⁇ 30 ⁇ m.
  • the model name is formed on the back surface of the wafer la (two chips are shown in FIG. 11), that is, on the exposed surface of the first resin layer 6.
  • Mark 11 such as. This marking is performed by a method such as printing or laser marking.
  • the same electronic circuits formed in large numbers on the wafer are diced at the boundary portions to form chips (individualized). Specifically, the back side of the wafer is attached to the dicing tape 12, and the chips are cut by the dicer 13. Even after cutting, the next process test can be performed with the dicing tape 12 still attached.
  • a tester probe 14 is brought into contact with the solder bump 10 to perform an electrical test.
  • a tester probe 14 is brought into contact with the solder bump 10 to perform an electrical test.
  • each chip is arranged on the dicing tape 12 while being electrically separated, as shown in FIG. Two or more chips can be tested simultaneously. Specifically, four chips could be tested simultaneously. Since multiple chips can be tested at the same time, the test index can be shortened and costs can be reduced. Of course, as usual, pick and press You can also test in place.
  • the interposer is used to widen the distance between the electrode pads by rearranging the electrode terminals using the wafer process on the surface of the semiconductor substrate. It is possible to obtain a very small semiconductor device of a chip size that can be directly mounted on a mother board. Moreover, the back surface of the semiconductor substrate is ground and thinned, the first resin layer is formed on the ground surface, and then the noria metal layer is formed by electroless plating before the solder core bumper bump is formed on the surface of the semiconductor substrate.
  • Al-Si (Si is 1 wt%) is used as the wiring 4 for rearranging the electrode terminals.
  • the film may be formed by vacuum deposition in addition to the sputtering method. Also, the process for forming the barrier metal layer 7 in FIG. 6 may be performed as follows.
  • the present invention can be applied to a semiconductor device used in an electronic device that is required to be light and thin in various electronic devices such as a portable device such as a mobile phone, a CD, a DVD, and a notebook personal computer.

Abstract

　半導体基板に電子回路を形成し、その電子回路の電極端子を半導体基板上で配線を介して分散することにより再配置された電極パッドを形成する。そして半導体基板の裏面を研削し、その研削面に第１の樹脂層を形成する。そして、電極パッド上に、無電解メッキ法によりバリアメタル層を形成し、その上にハンダコアを形成し、さらに樹脂を印刷することにより第２の樹脂層を形成した後に、第２の樹脂層を研削してハンダコアを露出させ、その上に、ハンダバンプを形成する。これにより、バリアメタル層を無電解メッキ法により形成しながら、無電解メッキのために半導体基板をマスクして、後に除去するという特別な工程を省くことができ、また、初期の工程で第１の樹脂層を設けているため、製造中の破損を防止でき、さらには樹脂シートにより第１の樹脂層を形成することにより、確実に所望の薄さとなり、小型、薄型、軽量化を実現しながら、コストを低減できる。

Description

明 細 書
半導体装置の製造方法
技術分野
[0001] 本発明は、小型、薄型、軽量、低価格を達成し得る半導体装置の製造方法に関す る。さらに詳しくは、微細な電極端子を有しながらリードフレームやインターポーザな どを用いないで、直接マザ一ボードなどにマウントすることができる構造の半導体装 置を簡単な製造工程で、しかも安価に得られる半導体装置の製造方法に関する。 背景技術
[0002] 半導体装置は、一般的には、たとえば図 15に示されるように、半導体チップ 21をリ ードフレームのダイパッド 22にダイボンディングし、電極パッド 21aとリードフレームの リード 23とを金線 24によりワイヤボンディングして、榭脂でモールドすることによりパッ ケージ 25を形成することにより製造されて 、る。
[0003] また、小型、薄型、軽量ィ匕を実現させる手段として、図 16または図 17に示されるよう に、半導体チップ 21周囲の電極パッド 21aを半導体チップ 21上に分散させてハンダ ボールを形成するチップサイズパッケージが考えられている。すなわち、図 16に示さ れる例は、セラミック基板、ポリイミドなどの有機材基板、フィルムテープなど力もなる インターポーザー 26の一面に配線（図示せず）を形成して半導体チップ 21の電極パ ッド 21aとその配線とを金線 24などを用いたワイヤボンディングにより接続し、そのィ ンターポーザー 26の裏面にその配線とそれぞれ接続してハンダボールなど力もなる 外部電極 27を形成し、半導体チップ 21側を榭脂 25により被覆する技術である。なお 、図 17に示される例は、半導体チップ 21の電極パッド 21aと配線との接続をワイヤボ ンデイングによらないで、電極パッド（図示せず）にハンダバンプ 2 lbを形成し、その ハンダバンプ 21bとインターポーザー 26の配線とを直接接合するもので、他の構成 は図 16に示される例と同じである。 28は半導体チップを固定する榭脂層である。
[0004] このようなインターポーザーを介在させることにより、半導体チップの周囲に非常に 狭い間隔で設けられている電極パッドを半導体チップの面積全体に分散させて回路 基板などに直接接続することを可能としている。すなわち、近年の半導体チップの高 集積化および小型化に伴い、その電極パッドは半導体チップの周囲に 100— 200 μ m程度の間隔で設けられている。しかし、半導体装置がマウントされる回路基板の配 線は、 0.5mm程度の間隔があり、半導体チップの電極パッドにバンプ電極を形成し ても直接回路基板にマウントすることができな 、が、このインターポーザーを介在させ ることにより、インターポーザー全体に電極を分散させることができるため、直接回路 基板にマウントすることができる。
[0005] 前述のように、チップサイズパッケージは小型化が可能である力 インターポーザー とそれに接続する接続工程が必要となる。このインターポーザーは、リードフレームを 使用する半導体装置に比べて、流通量、すなわち生産量が少なぐまた、微細な成 型が要求されるものもあるため、一般的にコストが高くなる。また、このインターポーザ 一と半導体チップとのワイヤボンディングは、ワンバイワンの接続であるため、一括処 理をすることができな 、し、一般的な電解工法によるメツキバンプは一括処理をするこ とができるものの、特にノリアメタルを形成する工程では、ステツパ装置、レジスト塗布 •現像 ·露光装置など高額な設備が必要となる。そのため、チップサイズパッケージは 、小型、薄型、軽量ィ匕を実現することができるが、コスト高になるという問題がある。
[0006] 一方、本発明者は、このような問題を解決するため、電子回路を形成した半導体基 板表面に配線で電極パッドを半導体チップの表面全体に分散させ、その電極パッド 上に無電解メツキ法によりバリアメタル層を形成して、その上にハンダコアを形成し、 表面全体に榭脂層を形成してから研削することによりハンダコアを露出させ、その露 出したハンダコアの表面にハンダバンプを形成すると共に、半導体基板裏面を研削 して薄くして力 裏面榭脂層を設けることにより小型で薄型の半導体装置を製造する 方法を開示して ヽる (特許文献 1参照)。
特許文献 1：特開 2003— 338515号公報
発明の開示
発明が解決しょうとする課題
[0007] しかし、このような方法によっても、たとえば裏面榭脂層を印刷法により塗布して硬 化させる方法で形成すると、裏面榭脂層の厚さのバラツキが、数十/ z m程度生じ、必 ずしも所望の値で薄型を達成することができないという問題がある。さらに、バリアメタ ル層を形成するのに、前述の無電解メツキ法で形成することにより、真空蒸着法ゃス ノ ッタリング法などに比べて金属の無駄がなく簡単に形成することができるが、半導 体基板も導電性であるため、半導体基板裏面に絶縁シートを貼り付け、無電解メツキ 終了後にその絶縁シートを除去しなければならず、その絶縁シートの貼り付けおよび 除去の工程が煩雑になると!、う問題がある。
[0008] 本発明は、このような状況に鑑みてなされたもので、インターポーザーを用いないで 、電極間隔を広げ、ノリアメタルを無電解メツキ法により形成しながら、無電解メツキの ために半導体基板裏面を絶縁シートでマスクする特別な工程を省くことができ、さら には確実に所望の厚さに形成して、小型、薄型、軽量ィ匕を実現しながら、コストを低 減することができる半導体装置の製造方法を提供することを目的とする。
課題を解決するための手段
[0009] 本発明による半導体装置の製造方法は、 (a)半導体基板の一面である表面に電子 回路を形成し、該電子回路の電極端子を前記半導体基板上で配線を介して分散す ることにより再配置された電極パッドを形成する工程と、（b)該半導体基板の他面で ある裏面側を研削する工程と、（c)該半導体基板の研削した面に第 1の榭脂層を形 成する工程と、（d)該第 1の榭脂層を形成した後に、前記電極パッド上に、無電解メッ キによりバリアメタル層を形成する工程と、 （e)該ノ リアメタル層上に、ハンダペースト を印刷し熱処理をすることにより、ハンダコアを形成する工程と、（f)前記半導体基板 の該ハンダコアを形成した表面側に第 2の榭脂層を形成する工程と、（g)該第 2の榭 脂層を研削して前記ハンダコアを露出させる工程と、 (h)前記露出したハンダコア上 に、さらにハンダペーストを印刷し熱処理をすることにより、ハンダバンプを形成する 工程とを含むことを特徴とする。
[0010] 前記 (c)工程を、前記半導体基板の研削した面に榭脂シートを貼り付け、該榭脂シ ートを硬化させることにより前記第 1の榭脂層を形成するのが、薄くて正確な厚さの榭 脂層を形成することができるため好ましい。
発明の効果
[0011] この方法を用いることにより、ノリアメタル層を無電解メツキ法により形成しながら、そ の無電解メツキ前の工程で半導体基板裏面を研削して薄くし、第 1の榭脂層を形成し ているため、無電解メツキの際に半導体基板裏面にもノ リアメタル層の金属被膜が形 成されることが無ぐ電極パッドのみにノリアメタル層の金属被膜を形成することがで きる。その結果、無電解メツキの工程のためにわざわざ絶縁膜で半導体基板裏面を 被覆して、メツキ後の絶縁膜を除去するという無駄な工程を挟むことなぐバンプ電極 を形成する必要な電極パッド部分のみにノリアメタル層を形成することができる。無 電解メツキは、電解メツキのように、全面にスパッタリングなどにより設けた金属膜にレ ジストを形成し、電解メツキを行い、その後、レジストや不要な金属膜をエッチングす るというような煩雑な工程を経ることなく形成することができる。さらに、衝撃に強い榭 脂層で半導体基板の裏面が被覆されているため、薄くしながら製造工程の搬送中な どにおける破損を防止することができると共に、半導体基板の両面が榭脂層により挟 まれるため、ウェハの反りを防止することができる。その結果、非常に簡単な製造工程 で歩留りが高ぐ安価に製造することができる。
[0012] さらに、第 1の榭脂層の形成を、榭脂シートを貼り付けて、熱処理により硬化させる 方法で行うことにより、薄い層で一定の厚さで形成することができるため、狙い通りの 厚さで非常に薄型の半導体装置を得ることができる。すなわち、印刷法により榭脂を 塗布して榭脂層を形成すると、その厚さのノ ラツキは数十/ z m程度と非常に大きなバ ラツキが生じ、全体の厚さが 500 m程度の半導体装置では、所望の厚さ以内という 薄型化を図っても、その寸法公差をオーバしてしまう場合も生じるが、本発明によれ ば、第 1の榭脂層を榭脂シートから形成しているため、その第 1の榭脂層を薄ぐかつ 、一定の厚さで形成することができる。その結果、非常に薄型の半導体装置を製造 するのに大きく寄与する。
図面の簡単な説明
[0013] [図 1]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 2]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 3]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 4]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 5]本発明による製造方法の一実施形態の製造工程、およびその詳細な具体的ェ 程図を示す説明図である。 [図 6]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 7]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 8]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 9]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 10]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 11]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 12]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 13]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 14]本発明による製造方法の一実施形態の製造工程を示す説明図である。
[図 15]従来の半導体装置における構造の一例を示す説明図である。
[図 16]従来の半導体装置における構造の一例を示す説明図である。
[図 17]従来の半導体装置における構造の一例を示す説明図である。
符号の説明
[0014] 1 半導体基板
2 電極端子
4 配線
4a 電極パッド
6 第 1の榭脂層
7 バリアメタル層
8 ハンダコア
9 第 2の榭脂層
10 ハンダバンプ
発明を実施するための最良の形態
[0015] つぎに、図面を参照しながら本発明の半導体装置の製造方法について説明をする 。本発明による半導体装置の製造方法は、まず、図 1一 3に示されるように、半導体 基板 1に電子回路を形成し、その電子回路の電極端子 2を半導体基板 1上で配線 4 を介して分散することにより再配置された電極パッド 4aを形成し、図 4に示されるよう に、半導体基板 1の裏面を研削する。そして、図 5に示されるように、半導体基板 1の 裏面に第 1の榭脂層 6を形成し、図 6に示されるように、その電極パッド 4a上に、無電 解メツキによりバリアメタル層 7を形成し、図 7に示されるように、ノリアメタル層 7上に、 ハンダペーストを印刷し熱処理をすることにより、ハンダコア 8を形成し、図 8に示され るように、半導体基板 1のハンダコア 8を形成した表面側に榭脂を印刷することにより 第 2の榭脂層 9を形成し、図 9に示されるように、第 2の榭脂層 9を研削してハンダコア 8を露出させ、図 10に示されるように、露出したハンダコア 8上に、さらにハンダぺー ストを印刷し熱処理をすることにより、ハンダバンプ 10を形成することにより製造する。
[0016] この半導体装置の製造方法について、具体例を交えて、さらに詳細に説明する。ま ず、図 1に示されるように、半導体基板 (ウエノ、） 1にトランジスタやダイオードなどの回 路素子（図示せず)を形成して電子回路を形成し、その表面に電子回路の電極端子 2を形成すると共に、半導体基板 1の表面に絶縁膜 3を形成して回路素子を保護して いる。この状態は、通常の半導体チップにする前のウェハの状態である。なお、図 1 一 10においては、 1個の電極端子およびその電極端子に接続して設けるバンプ電 極が 1個の例で示されている力 多数ある電極端子全てについて同時に同様の方法 でバンプ電極の形成が行われる。
[0017] つぎに、 A1- Si (Siが lwt%)など力もなる電極材料をスパッタ法などにより 3 μ m程 度の厚さに成膜して、図示しないレジスト膜を設けてパターユングすることにより、図 2 に示されるように、電極端子 2と接続してバンプ電極を形成する所望の場所まで延在 する配線 4を形成する。その後、図 3に示されるように、 CVD法などにより SiOまたは
2
Si Nなど力もなる被覆層 5を全面に設け、前述の配線 4の端部であるバンプ電極形
3 4
成場所のみが露出するようにパターニングする。この際、バンプ電極形成場所として 配線 4を露出させた再配置の電極パッド 4aは、他の再配置の電極パッドとの間隔が 0 •4mmピッチ程度となり、その大きさが 150 m φ程度となるように形成する。
[0018] つぎに、図 4に示されるように、半導体基板 1の厚さが 150— 350 /z mになるように、 半導体基板 1の裏面を研削する。具体的には、 630 m厚の半導体基板 1を研削し て、 200± 15 /ζ πι)ϊ:【こした。
[0019] ついで、図 5に示されるように、半導体基板 1の裏面側に、たとえばフイラ一入りェポ キシ榭脂をシート状に加工した榭脂シートを貼り付けて第 1の榭脂層 6を、たとえば 5 0 ± 10 /ζ πι程度の厚さで、ウェハの裏面全面に形成する。具体的には、たとえば図 5 Αに示されるように、厚さが 50 ± 5 m程度でアセトンなどの有機溶剤に溶解し得る 材料からなり、半導体ウェハ laより大きく榭脂シート 6aを切断し、半導体基板 1のゥェ ハ状態であるウェハ laの裏面に重ねて、たとえば 70°C程度に加熱することにより貼り 付ける。そして、図 5Bに示されるように、榭脂シート 6a側をスピナ一 17に固定して回 転させながら、ウェハ laの表面側からアセトン 18を滴下することにより、図 5Cに示さ れるように、ウェハ laの周囲からはみ出た榭脂シート 6aを溶解して除去する。その後 、たとえば 120°C程度で 8時間程度、さらに 175°C程度に昇温して 1.5時間程度の熱 処理をして、榭脂を硬化させることにより、第 1の榭脂層 6が 50 ± 10 m程度の厚さ で、ウェハ laの裏面全面に形成される。
[0020] つぎに、図 6に示されるように、再配置した電極パッド 4a上にノリアメタル層 7を形成 する。具体的にはつぎのように行った。まず、再配置した電極パッド 4a表面の親水性 改善のため、脱脂処理を行い、ついで、硫酸または硝酸により表面に付着した酸ィ匕 膜を除去した。その後、その表面に Zn膜を置換メツキした。硝酸によりこの Zn膜を一 且除去した後、再度 Zn膜を置換メツキし、電極パッド 4a表面に均一な Zn膜を形成し た。つぎに、還元反応により、 Niを 5— 9 m析出させた。さらに、 Ni表面の酸ィ匕を防 止するため、置換メツキ法により Au膜を 0.03 /z m形成することにより、バリアメタル層 7を形成した。なお、このノリアメタル層 7の直径は 160 mであった。ここで、電極パ ッド 4aは、 1回目の Znを置換メツキで形成する際のエッチング量が大きい。具体的に は、 0.7 m程度エッチングされた。したがって、配線 4の厚さを 1 μ m程度以上設け ることが必要である。 1 μ m以下の場合は、 2回目の Znを形成するまでに電極パッド 4 aの材料が溶けて無くなる場合が生じ、 Niメツキが成長しない場合が生じ、好ましくな い。
[0021] つぎに、図 7に示されるように、バリアメタル層 7の表面にハンダコア 8を印刷法によ り形成する。この場合のマスクとして、（マスクの開口面積 π ΐ:2) / (開口部におけるマ スク壁面面積 2 π rt) =rZ2tの比率が 1/2以上のハンダマスクを使用するのがよか つた。これは、（マスクの開口面積) Z (マスク壁面面積）が 1Z2より小さくなると、たと えばマスク開口の直径 2rが 250 μ ΐη φで、マスク厚 tを 200 μ mにした場合、マスク 壁面との接着力の方が大きぐマスクにハンダペーストが残っており、転写の再現性 が劣るためである。具体的には、直径が 250 m φの開口で、厚さ tが 100 μ mのマ スクを用い、 Sn-Cu (Cuが 2wt%)のハンダペーストを使用して印刷した。そして、酸 素濃度が lOOOppm以下の不活性ガス雰囲気で、 260°C、 10秒以上の熱処理をし てリフローした。ハンダマスクの開口の直径が 250 μ mのとき、マスク厚を変化させた 結果、厚さ tが 125 m (すなわち rZ2t=0.5)まではハンダが転写されることを確認 できた。また、リフロー時の酸素濃度が lOOOppm以上の場合、ハンダコア 8の高さに バラツキが生じた。ノ リアメタル層の直径が 160 μ ΐη φ、マスク開口の直径が 250 μ m φ、マスク厚 tが 100 μ mのとき、ハンダコア 8の高さは 130 ± 20 μ mの範囲で得ら れた。
[0022] つぎに、図 8に示されるように、半導体基板 1の表面 (ノ、ンダコア 8を形成した面)側 に、たとえばフイラ一入りエポキシ榭脂を大気圧下で印刷法により塗布して、第 2の榭 脂層 9を形成する。この際、第 2の榭脂層 9の厚さを規定するウェハ周囲を除いて開 ロ孔を形成した榭脂印刷マスクをつけて行うが、この榭脂印刷マスクは、ハンダコア 8 の高さと同じ厚さから、それより 150 /z m程度厚い範囲の厚さとする。印刷後、真空雰 囲気下に放置して印刷時に巻き込んだ気泡を脱泡する。その後、高温にして榭脂を 硬化させる。具体的には、印刷に用いるマスク厚をハンダコア高さより大きい 250 /z m 厚のものを使用し、 lOOPa ' sの粘度の榭脂を用いて 665Paの減圧下で、 20分間放 置して脱泡をした。その後、 100°Cで 1時間、 150°Cで 2時間の熱処理をして榭脂を 硬化させた。硬化後の第 2の榭脂層 9の厚さは 250 ± 50 /z mであった。なお、使用す る榭脂の粘度は、 25、 200、 300、 600Pa ' sでも使用できることが確認されている。
[0023] つぎに、図 9に示されるように、半導体基板 1の表面側の第 2の榭脂層 9を研削して 、ハンダコア 8を露出させる。榭脂の研削量は、第 2の榭脂層 9の研削面がハンダコア 8の高さの 2Z3— 1Z2となるように設定した。具体的には、 130 m高のハンダコア 8の場合に、第 2の榭脂層 9の厚さ (研削後のハンダコア 8の高さ）が 70— 90 (80 ± 1 0) /z mとなるように研削を行った。このとき、露出したハンダコア 8の直径は、 150 ± 2 Ο μ ηι φの範囲で得られた。
[0024] つぎに、図 10に示されるように、ハンダコア 8上にハンダバンプ 10を印刷法により形 成する。ここで、前述のハンダコア 8を形成する場合と同様に、ハンダペーストを印刷 する際に用いるマスクは、（マスクの開口面積) Z (開口部におけるマスク壁面面積） の比率が 1Z2以上のハンダマスクを使用するのがよ力つた。そして、酸素濃度が 10 OOppm以下の不活性ガス雰囲気で、 260°C、 10秒間の熱処理をしてリフローをした 。具体的には、マスクとして、直径が 250 m φの開口で、厚さ tが 100 μ mのマスク を用い、 Sn- Cu (Cuが 2wt%)のハンダペーストを使用して印刷した。ハンダマスク の開口の直径が 250 mのとき、マスク厚を変化させた結果、前述の場合と同様に、 厚さ tが 125 μ mまではハンダが転写されることを確認できた力 150 ^ mの厚さでは 、マスクにハンダが残っており、転写の再現性に劣った。また、リフロー時の酸素濃度 を lOOOppm以上にした場合、ハンダバンプ 10の高さにバラツキが生じた。ハンダコ ァ 8の直径が 150± 20 πι φ、マスク開口の直径が 250 πι φ、マスク厚 tが 100 mのとき、ハンダバンプ 10の高さは 120± 30 μ mの範囲で得られた。
[0025] つぎに、図 11に 123で示されるように、ウェハ la (図 11では 2個のチップ分が示さ れている）の裏面、すなわち第 1の榭脂層 6の露出面に型名などのマーク 11を付する 。このマーキングは、印刷またはレーザ刻印などの方法により行う。
[0026] つぎに、図 12に示されるように、ウェハに多数形成された同じ電子回路をそれぞれ その境界部でダイシングをしてチップ化 (個片化)する。具体的には、ウェハの裏面側 をダイシングテープ 12に貼着し、ダイサー 13によりチップ間を切断する。切断した後 も、ダイシングテープ 12に貼着したまま、次工程のテストを行うことができる。
[0027] その後、図 13に示されるように、ハンダバンプ 10にテスターのプローブ 14を接触さ せて、電気試験を行う。このように、梱包直前にテストを行なうことにより、ダイシング時 の不良も検出することができ、不良品の流出を完全に防止することができ、信頼性を 向上させることができる。また、このように、ダイシングテープ 12に貼着したままテスト を行うことにより、各チップは電気的には分離されながら、ダイシングテープ 12上に整 列しているため、図 13に示されるように、 2個以上のチップを同時にテストすることが できる。具体的には、 4個のチップを同時にテストすることができた。このように同時に 複数個のチップのテストを行うことができるため、テストインデックスを短くすることがで き、コストダウンを図ることができた。もちろん、従来通りピックアンドプレスによる 1個単 位でのテストをすることもできる。
[0028] 最後に、外観検査を行い、ダイシングテープカゝら分離されて完成した半導体装置 1 5を、図 14に示されるように、 1個ごとに収納できる凹部が形成されたキャリアテープ 1 6の凹部に収納し、キャリアテープ 16を梱包することにより、出荷できる状態になる。
[0029] 以上のように、本発明によれば、半導体基板表面にウェハのプロセスを用いて、電 極端子の再配置を行って電極パッドの間隔を広げて 、るため、インターポーザを用 いることなぐ直接マザ一ボードなどにマウントすることができるチップサイズの非常に 小型の半導体装置を得ることができる。しかも、半導体基板裏面を研削して薄くし、そ の研削面に第 1の榭脂層を形成してから、半導体基板表面にハンダコアゃノヽンダバ ンプを形成する前にノリアメタル層を無電解メツキにより形成し、さら〖こ、ハンダコアや ハンダバンプの形成を、印刷と加熱処理とにより行っているため、製造工程での破損 を防止しやすいと共に、無電解メツキのためのマスクをわざわざ形成することなぐ非 常に簡単な設備で、し力もウェハ単位で一括処理により製造することができる。その 結果、直接マザ一ボードなどにマウントすることができる、チップサイズ程度の小型、 薄型、軽量の半導体装置を非常に安価に得ることができる。さらに、第 1の榭脂層を 榭脂シートの貼り付けにより形成することにより、薄くて、かつ、寸法精度をシビアにす ることができ、非常に正確な薄型の半導体装置が得られる。
[0030] なお、前述の具体例では、電極端子を再配置するための配線 4として、 Al-Si(Siが lwt%)を用いる例であつたが、配線 4として、 Auまたは Cuを用いる場合には、この 膜を形成するのに、スパッタ法以外に真空蒸着で成膜してもよい。また、図 6のバリア メタル層 7の形成工程は以下のように行ってもょ 、。
[0031] まず、前述の例と同様に、再配置した電極パッド 4a表面の親水性改善のため、脱 脂処理を行い、ついで、硫酸または硝酸により表面に付着した酸化膜を除去する。 その後、電極パッド 4aの表面に、 Pdを置換メツキにより成膜する。つぎに、還元反応 により、 Niを 5— 9 μ m析出させる。さら〖こ、置換メツキ法により Au膜を 0.03 μ m形成 することにより、ノリアメタル層 7を形成する。なお、このバリアメタル層 7の直径は 160 mであった。ここで、配線 4は、半導体基板 1表面の凹凸により断線が生じる場合が あるので、 1 μ m以上の厚さに形成することが必要である。 産業上の利用可能性
本発明は、携帯電話機などの携帯機器、 CD、 DVD,ノート型パーソナルコンビュ ータなどの各種電子機器で軽薄短小化が要求される電子機器に用いられる半導体 装置に適用することができる。

Claims

請求の範囲
[1] (a)半導体基板の一面である表面に電子回路を形成し、該電子回路の電極端子を 前記半導体基板上で配線を介して分散することにより再配置された電極パッドを形 成する工程と、
(b)該半導体基板の他面である裏面側を研削する工程と、
(c)該半導体基板の研削した面に第 1の榭脂層を形成する工程と、
(d)該第 1の榭脂層を形成した後に、前記電極パッド上に、無電解メツキによりバリア メタル層を形成する工程と、
(e)該ノリアメタル層上に、ハンダペーストを印刷し熱処理をすることにより、ハンダコ ァを形成する工程と、
(f)前記半導体基板の該ハンダコアを形成した表面側に第 2の榭脂層を形成するェ 程と、
(g)該第 2の榭脂層を研削して前記ハンダコアを露出させる工程と、
(h)前記露出したノヽンダコア上に、さらにハンダペーストを印刷し熱処理をすることに より、ハンダバンプを形成する工程
とを含むことを特徴とする半導体装置の製造方法。
[2] 前記 (c)工程を、前記半導体基板の切削した面に榭脂シートを貼り付け、該榭脂シ ートを硬化させることにより前記第 1の榭脂層を形成する請求項 1記載の半導体装置 の製造方法。
[3] 前記 (c)工程を、前記半導体基板の切削した面に、有機溶液により溶解し得る榭脂 からなり、前記半導体基板より大きい榭脂シートを貼り付け、該榭脂シートが貼り付け られた前記半導体基板を回転させながら、該半導体基板の表面側から有機溶剤を 滴下させて、前記半導体基板と接着して ヽな 、部分の前記榭脂シートを溶解して除 去することにより、前記半導体基板の裏面全面に前記榭脂シートを貼り付け、該榭脂 シートを硬化させることにより前記第 1の榭脂層を形成する請求項 1記載の半導体装 置の製造方法。
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