Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
  • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0172—Manufacturing their gate conductors
  • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

• This invention relates to semiconductor device manufacturing, and in particular the manufacture of complementary metal-oxide-semiconductor (CMOS) FET devices. More particularly, the invention relates to formation of silicided metal gates in these devices.
• CMOS complementary metal-oxide-semiconductor
• the invention has utility in the field of semiconductor manufacturing.
• Gate structure 100 (often called a gate stack) is fabricated on the surface of substrate 1, which typically is a semiconductor wafer (e.g. Si, Ge, SiGe, as well as semiconductors over a buried insulator). Source and drain regions 22, 23 are formed near the surface of the wafer.
• Gate structure 100 includes conducting element 110 (typically polysilicon; p+ doped and n+ doped in PFETs and NFETs respectively) overlying dielectric layer 112. In present-day devices the equivalent oxide thickness of the gate dielectric has been reduced to less than 2 nm. At the same time, linewidths have been reduced so that the lateral extent of gate structure 100 is now in the sub- 65 ran range.
• silicided gate involves reacting a layer of metal with an underlying layer of silicon (polysilicon or amorphous silicon), which in turn is in contact with the gate dielectric.
• a substantial number of additional process steps are required as compared to fabrication of a conventional polysilicon gate.
• a typical silicide gate fabrication scheme requires chemical-mechanical polishing (CMP) or etching back of the polysilicon layer. These processes often fail to provide adequate uniformity (across the wafer) in the polysilicon thickness. This in turn results in low-quality silicided gates and low device yields.
• the present invention addresses the above-described need by providing a process in which the metal silicide gate is self-forming (that is, formed without the need for a separate metal/silicon reaction step). No CMP or etchback of the polysilicon is required, and in which only one additional step is used in comparison to the conventional polysilicon gate process.
• this is done by forming a first layer of a silicon material (which may be polysilicon or amorphous silicon) overlying the gate dielectric, forming a layer of metal on the first layer, and then forming a second layer of silicon material on the metal layer.
• At least one high-temperature (> 700 C) processing step is performed subsequent to forming those layers; this processing step is effective to form a first silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer.
• the thicknesses of the layers are such that in the first high-temperature processing step, at least a portion of the first layer and at least a portion of the second layer are reacted with the metal to form the silicide material.
• a second high-temperature processing step may be performed which is effective to form a second silicide layer from silicon in the second layer; the second silicide layer overlies the first silicide layer and in contact therewith. As a result of the high- temperature processes, substantially all of the silicon in the first layer is replaced by the silicide material.
• the first high-temperature processing step is an annealing step for source and drain portions of the FET device; alternatively, this step could be any of the other high temperature annealing steps performed in subsequent processing.
• the second high-temperature processing step is a silicidation process for source and drain portions of the FET device.
• the metal may be one of W, Ti, Pt, Ta, Nb, Hf and Mo. Substantially all of the silicon is reacted to form a silicide material, so that a fully silicided gate is produced.
• a second high-temperature processing step is effective to form a second silicide layer from silicon material in the second layer; this second silicide layer overlies a remaining portion of silicon in the second layer.
• a gate structure for an FET device which includes a gate dielectric on a substrate, a first layer of a first silicide overlying the gate dielectric and in contact therewith, and a second layer of a second silicide overlying the first silicide layer.
• the second layer is of the same material as silicide in source and drain regions of the FET.
• the gate structure may be fully silicided (that is, the material overlying the gate dielectric may consist essentially of silicide in the first and second layers).
• the gate structure may include a third layer of silicon between the first and second silicide layers.
• Figure 1 schematically illustrates a conventional CMOS structure including a polysilicon gate conductor.
• Figure 2 illustrates the deposition of dielectric, silicon and metal layers on a substrate, in accordance with an embodiment of the invention.
• Figure 3 illustrates a gate structure according to an embodiment of the invention, before formation of the source and drain regions.
• Figure 4A illustrates a gate structure according to an embodiment of the invention, after formation of a metal silicide in contact with the gate dielectric.
• Figure 4B illustrates a gate structure according to an alternate embodiment of the invention, after formation of a metal silicide in the first of two high-temperature processes.
• Figure 5 illustrates a completed gate structure along with source and drain regions, according to an embodiment of the invention.
• Figure 6 illustrates a completed gate structure along with source and drain regions, according to an alternate embodiment of the invention.
• FIG. 2 illustrates the sequence of deposition steps used to form the gate.
• the gate dielectric layer 2 is first formed on the substrate 1.
• Substrate 1 may be a wafer of bulk semiconductor (Si, Ge, SiGe, and the like) or semiconductor material on an insulator (oxide, nitride, oxynitride, and the like).
• Gate dielectric 2 may be oxide, oxynitride, a high-k material, ⁇ K> 2 , and the like.
• a thin layer 3 of silicon material is deposited on the gate dielectric, and a layer of metal 4 is then deposited thereon.
• the silicon material is polysilicon; the material may also be amorphous silicon.
• Metal layer 4 is chosen to be a metal having a thermally stable silicide, with the silicide being formed by a reaction at a high temperature (> 700 0 C); metals meeting this requirement include W, Ti, Pt, Ta, Nb, Hf and Mo.
• the thicknesses of layers 3 and 4 are chosen to ensure that the silicon material in layer 3 will be fully silicided during a high-temperature process which is performed later.
• the silicon in layer 3 may be doped before the deposition of metal layer 4, so that the subsequently formed silicide will have a work function appropriate for the type of device being fabricated (e.g. PFET or NFET).
• Another layer 5 of silicon material (polysilicon in this embodiment; alternatively amorphous silicon) is deposited on top of metal layer 4. It will be appreciated that in this embodiment of the invention, one extra deposition step is performed in comparison to the conventional gate fabrication process; that is, the silicon layer is deposited as two layers instead of a single layer.
• the substrate is then patterned using photoresist 10, and layers 3-5 are etched to define the gate structure.
• the result of these etching processes is shown in Figure 3.
• Further process steps are then performed, using techniques known in the art, to produce a gate structure including spacers 25 and source and drain regions 40.
• a typical process used at this point is a high-temperature activation anneal for the source and drain.
• the metal layer 4 reacts with the underlying layer 3 of silicon material to produce a silicide layer 30 (e.g. WSi x , TiSi x , PtSi x , TaSi x , NbSi x , HfSi x , MoSi x ).
• the thicknesses of silicon layer 3 and metal layer 4 are chosen so that the silicon material in layer 3 is folly silicided (that is, silicon layer 3 is replaced by a silicide layer). Accordingly, silicide 30 is in contact with gate dielectric 2, with unreacted silicon material from layer 5 over the silicide, as shown in Figure 4A.
• the first high-temperature process e.g.
• a remaining layer 33 of silicon material overlies the gate dielectric after the first high-temperature process, while the silicide layer 31 is a metal-rich phase of silicide.
• the silicon material in layer 33 is reacted to form a silicide material (the same material as in layer 30), so that layer 3 of silicon material is fully silicided after the second high-temperature process.
• a metal e.g. Ni, Co, Ti, Pt, and the like
• a further silicide-formation process is then performed to form conducting silicide regions 41 in the source and drain. This same process causes the silicon at the top of the gate to react with the metal to form a silicide region 50 in the upper portion of the gate (and also convert to a silicide the remaining silicon material in layer 33, if any).
• the resulting structure is shown in Figure 5.
• the silicide material in source/drain regions 41 and region 50 of the gate are the same; the silicide 30 m the lower portion of the gate may be either the same material as in region 50 or a different material. (There may also be a transition layer, with a mixture of silicide materials, between the lower silicide layer 30 and the upper silicide layer 50.)
• the originally-deposited silicon in the gate structure is therefore replaced by silicide material; that is, the gate structure is said to be fully silicided.
• a fully silicided gate is produced with only one additional deposition process step, but without the need for CMP or etching processes for the polysilicon layers.
• the silicidation of gate material occurs as a result of subsequent high-temperature processes; no separate processes are required to form the silicide layers in the gate.
• the thickness of silicon layer 5 is chosen so that the silicon material overlying silicide 30 is not completely converted to a silicide during the source/drain silicidation process. Accordingly, there will be three gate materials over the gate dielectric; silicide 30, silicon 55 and silicide 50 (which is the same silicide material as in the source/drain regions 41). This structure is shown in Figure 6.
• the gate fabrication process of the present invention is simpler than the conventional process, and permits automatic formation of self-aligned silicide gate conductors.
• the invention has utility in the field of semiconductor manufacturing and can be advantageously applied to all large scale integrated circuit chips, in all kinds of applications that include, communications, electronics, medical instrumentation, aerospace applications, and the like.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Thin Film Transistor (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=36653783

Family Applications (1)

Country Status (7)

Families Citing this family (7)

Citations (1)

Family Cites Families (10)

• 2005
  • 2005-01-13 US US10/905,629 patent/US7105440B2/en not_active Expired - Fee Related
• 2006
  • 2006-01-04 TW TW095100297A patent/TW200636920A/zh unknown
  • 2006-01-10 KR KR1020077015594A patent/KR20070095933A/ko not_active Ceased
  • 2006-01-10 EP EP06717971A patent/EP1856725A4/en active Pending
  • 2006-01-10 JP JP2007551329A patent/JP2008527743A/ja active Pending
  • 2006-01-10 CN CNB2006800014309A patent/CN100505187C/zh not_active Expired - Fee Related
  • 2006-01-10 WO PCT/US2006/000838 patent/WO2006076373A1/en not_active Ceased

Patent Citations (1)

Also Published As

Similar Documents

Legal Events