WO2006051790A1 - 駆動装置および駆動方法 - Google Patents
駆動装置および駆動方法 Download PDFInfo
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- WO2006051790A1 WO2006051790A1 PCT/JP2005/020469 JP2005020469W WO2006051790A1 WO 2006051790 A1 WO2006051790 A1 WO 2006051790A1 JP 2005020469 W JP2005020469 W JP 2005020469W WO 2006051790 A1 WO2006051790 A1 WO 2006051790A1
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- 238000000034 method Methods 0.000 title claims description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 36
- 239000000872 buffer Substances 0.000 description 27
- 238000010586 diagram Methods 0.000 description 22
- 230000000694 effects Effects 0.000 description 21
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 20
- 230000015556 catabolic process Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 2
- 101710179738 6,7-dimethyl-8-ribityllumazine synthase 1 Proteins 0.000 description 1
- 101710186608 Lipoyl synthase 1 Proteins 0.000 description 1
- 101710137584 Lipoyl synthase 1, chloroplastic Proteins 0.000 description 1
- 101710090391 Lipoyl synthase 1, mitochondrial Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
- G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Definitions
- the present invention relates to a driving apparatus and a driving method for sequentially outputting a plurality of output signals. More specifically, the present invention relates to a scanning line to which a plurality of display elements are connected in a display apparatus such as a liquid crystal display panel or an organic EL panel. The present invention relates to a driving device and a driving method for driving. Background art
- FIG. 29 is a block diagram showing a configuration of a conventional drive device (for example, JP 2000-98339 A).
- This device is used, for example, as a scanning line driver for a liquid crystal display panel.
- the conventional driving device has n (n is a positive integer) flip-flops FF— :! to FF—n, and n for level conversion of n outputs from the shift register 10.
- the n output buffers OB— :! to OB—n output n drive signals SXl to SXn.
- data (start pulse) is input from the terminal 11.
- Flip-flop FF-1 captures the start pulse according to the clock input to terminal 12.
- flip-flop FF-1 outputs a high-level signal for one pulse from terminal Y in synchronization with the rising edge of the clock.
- the data output from the terminal Q of the flip-flop FF-1 is input to the terminal D of the next-stage flip-flop FF-2.
- n flip-flops FF— :! to FF_n sequentially transfer data, and a high-level signal for one pulse from each terminal Y of n flip-flops FF_ :! to FF_n. Is output.
- n level shifters LS-1 to LS_n are level-converted by n level shifters LS-1 to LS_n into signals having an amplitude difference of VG G-VEE.
- these level-converted signals are buffered by n output buffers OB— :! to ⁇ B—n and output as n drive signals SXl to SXn.
- the n signals are sequentially output from the shift register 10, whereby the drive signals SXl to SXn are sequentially output.
- this driving device is used as a scanning line driver of a liquid crystal display panel, a plurality of scanning electrode lines are sequentially activated by these driving signals SXl to SXn, and the display screen of the liquid crystal display panel is vertical. Scanned in the direction.
- Patent Document 1 JP 2000-98339 A
- the driver IC of a liquid crystal display panel for a mobile phone is used.
- One chip is becoming mainstream. With the high definition of the liquid crystal display panel and the single driver IC chip, the chip area of the driver IC becomes very large and the cost of the liquid crystal display panel increases.
- the driver IC is equipped with a display controller, darling RAM, data driver, and scanning line driver. Therefore, the higher the definition, the larger the circuit scale. Therefore, the circuit area of the driver IC is generally reduced by miniaturizing the transistor in the semiconductor manufacturing process.
- the specification of the drive signal to be supplied to the liquid crystal display panel is determined by the characteristics of the liquid crystal display panel. For example, in order to drive a liquid crystal display element on a liquid crystal display panel for a mobile phone (generally, an element composed of a thin film transistor TFT and a liquid crystal capacitor), a driving voltage necessary for a scanning line driver is turned on. A drive signal having a potential difference in which the potential (VGG) is “about + 15V” and the off potential (VEE) force S is “about 15V” is required. Therefore, the scanning line driver that supplies the drive signal needs to be configured by a transistor having a withstand voltage corresponding to the drive signal. In this way, the transistor gate length is reduced. Since the breakdown voltage of the transistor is lowered by reducing the size, there is a limit to miniaturization of the transistor.
- an object of the present invention is to reduce the circuit scale of a driving device.
- the drive device includes first and second generation units, and (k X m) output circuits.
- the first generation unit sequentially changes the k first signals from the non-output state to the output state according to the first clock.
- k is a natural number.
- the second generation unit sequentially changes the m second signals from the non-output state to the output state according to the second clock.
- m is a natural number.
- the (k X m) output circuits are divided into k groups. Each of the k groups has m output circuits.
- the k first signals correspond to k gnoles.
- the m second signals correspond to m output circuits belonging to each of the k groups.
- each of the (k X m) output circuits When each of the (k X m) output circuits is in the output state when the first signal corresponding to the gnole to which the output circuit belongs is, the second signal corresponding to the self is in the output state. Is output.
- Each of the (k X m) output circuits when the first signal corresponding to the loop to which it belongs is in the non-output state, even if the second signal corresponding to itself is in the output state, The second signal is not output.
- (k X m) drive signals are sequentially output by combining a first generation unit having k outputs and a second generation unit having m outputs. .
- the number of outputs at the front stage of the drive device can be reduced.
- the circuit scale of the driving device can be reduced.
- the second generator generates the m second signals according to the second clock while any four of the k first signals are in an output state. Are sequentially switched from the non-output state to the output state.
- each of the (k X m) output circuits includes an output terminal, a first input terminal, a first switch, a second input terminal, and a second switch.
- the first input terminal receives a second signal corresponding to the output circuit.
- the first switch is connected between the output terminal and the first input terminal, and is turned on / off according to the state of the first signal corresponding to the output circuit.
- the second input terminal is a predetermined voltage corresponding to the non-output state of the second signal.
- the second switch is connected between the output terminal and the second input terminal, and is turned on / off according to the state of the first signal corresponding to the output circuit.
- the first generation unit includes k first flip-flops connected in series.
- the second generation unit includes m second flip-flops connected in series.
- the driving device further includes a logic circuit.
- the logic circuit is connected between the first generation unit and the (k X m) output circuits and receives a control signal from the outside.
- the logic circuit simultaneously sets all the k first signals from the first generation unit to the non-output state according to the presence or absence of the control signal.
- the driving device further includes a logic circuit.
- the logic circuit is connected between the second generation unit and the (k X m) output circuits and receives a control signal from the outside.
- the logic circuit simultaneously sets all the m number of second signals from the second generation unit to the non-output state according to the presence or absence of the control signal.
- the driving device further includes first and second selectors.
- the first selector is connected between the s-th first flip-flop and the (s + 1) -th first flip-flop from the top among the k first flip-flops.
- s is a natural number and l ⁇ s ⁇ (k —2).
- the second selector is connected between the t-th first flip-flop and the (t + 1) -th first flop flop from the top among the k first flip-flops.
- t is a natural number, s ⁇ t ⁇ (k_ l).
- the first and second selectors have first and second modes. In the first mode, the first selector outputs the output from the sth first flip-flop to the (s + 1) th first flip-flop.
- the second selector outputs the output from the t-th first flip-flop to the (t + 1) -th first flip-flop.
- the first selector outputs the output of the s-th first flip-flop output to the second selector.
- the second selector outputs the output from the first selector to the (t + 1) th first flip-flop.
- the output from the (k X m) output circuits can be limited by changing the operation mode of the selector. This makes it possible, for example, to display only a predetermined line on the liquid crystal display panel so that the image displayed on the predetermined line is not updated. That is, a partial display function can be realized.
- the driving device further includes a selection circuit having first and second modes.
- the selection circuit outputs the output from the y-th second flip-flop among the m second flip-flops as the y-th second signal, and the (y + 1) -th The output from the second flip-flop is output as the (y + 1) -th second signal.
- y is an odd natural number
- m is an even natural number
- the selection circuit outputs the output from the y-th second flip-flop at the same time as the y-th and (y + 1) -th second signals, and from the (y + 1) -th second flip-flop. Is not output.
- the driving device further includes a logic circuit.
- the logic circuit is connected between the first generation unit and the (k X m) output circuits and receives a control signal from the outside.
- the logic circuit simultaneously outputs all the k first signals from the first generation unit according to the presence or absence of a control signal.
- the drive device can output a plurality of drive signals simultaneously.
- the driving device further includes a logic circuit.
- the logic circuit is connected between the second generation unit and the (k X m) output circuits and receives a control signal from the outside.
- the logic circuit simultaneously outputs all the m second signals from the second generation unit according to the presence or absence of the control signal.
- the driving device includes a logic circuit.
- the logic circuit is connected between the first generator and the (k X m) output circuits, and operates according to the presence or absence of an external control signal.
- the control signal is shorter than the period from the time when one of the k second signals is in the output state until the next second signal is in the output state. Output only for a predetermined period.
- the logic circuit simultaneously sets all the k first signals from the first generation unit to the non-output state.
- the driving device includes a logic circuit.
- the logic circuit is connected between the second generation unit and the (k X m) output circuits, and operates according to the presence or absence of an external control signal.
- the control signal is output only for a predetermined period shorter than that period from the time when one of the k second signals is in the output state until the next second signal is in the output state. Is done.
- the logic circuit simultaneously sets all the m second signals from the second generation unit to the non-output state.
- the driving device includes a logic circuit.
- the logic circuit is connected between the first and second generation units and the (k X m) output circuits, and receives a control signal from the outside.
- the logic circuit simultaneously outputs all k first signals from the first generator according to the presence or absence of the control signal and outputs m signals from the second generator. All of the second signals are set to the output state simultaneously.
- a force S can be used to simultaneously activate all the gate lines of the display panel. As a result, the charge accumulated in the liquid crystal elements of the display panel can be discharged at once.
- each of the (k X m) output circuits receives a control signal from the outside.
- Each of the (k X m) output circuits further includes a selection unit.
- the selection unit outputs one of a predetermined voltage corresponding to the output state of the signal given to the output terminal and the second signal, depending on the presence or absence of a control signal.
- the driving method sequentially outputs drive signals from (k X m) output terminals divided into k gnoles.
- k and m are natural numbers.
- Each of the k groups has m output terminals.
- the k first signals corresponding to the k loops are sequentially changed from the non-output state to the output state.
- Second In accordance with the clock, m second signals corresponding to m output terminals included in each of k gnoles are sequentially changed from the non-output state to the output state.
- each of the (k X m) output terminals when the first signal corresponding to the group to which the output terminal belongs is in the output state, when the second signal corresponding to the output terminal is in the output state, The second signal is output from the output terminal as a drive signal.
- the second signal corresponding to the output terminal when the first signal corresponding to the group to which the output terminal belongs is in the non-output state, the second signal corresponding to the output terminal is in the output state. Even if it exists, the second signal is not output as a drive signal from the output terminal.
- (k X m) drive signals are sequentially output by combining the first generator having k outputs and the second generator having m outputs. . That is, the number of outputs at the front stage of the drive device can be reduced. As a result, the circuit scale of the driving device can be reduced.
- FIG. 1 is a block diagram showing an overall configuration of a drive device according to a first embodiment of the present invention.
- FIG. 2 is a circuit diagram showing an internal configuration of the output circuit shown in FIG.
- FIG. 3 is a timing chart for explaining the operation of the driving apparatus shown in FIG.
- FIG. 4 is a block diagram showing an overall configuration of a driving apparatus according to a second embodiment of the present invention.
- FIG. 5 is a timing chart for explaining the operation of the driving apparatus shown in FIG.
- FIG. 6 is a block diagram showing a modified example of the drive device shown in FIG.
- FIG. 7 is a block diagram showing a modified example of the drive device shown in FIG.
- FIG. 8 is a block diagram showing a modification of the drive device shown in FIG.
- FIG. 9 is a block diagram showing a modified example of the drive device shown in FIG.
- FIG. 10 is a block diagram showing a modification of the drive device shown in FIG.
- FIG. 11 is a block diagram showing an internal configuration of a signal generation unit used in the third embodiment of the present invention.
- FIG. 12 is a timing chart for explaining the operation of the driving apparatus according to the third embodiment of the present invention.
- FIG. 13 is a block diagram showing the overall configuration of the driving apparatus according to the fourth embodiment of the present invention.
- FIG. 14 is a timing chart for explaining the operation of the drive device shown in FIG.
- FIG. 15 is a block diagram showing a modification of the drive device shown in FIG.
- FIG. 16 is a block diagram showing an overall configuration of a driving apparatus according to a fifth embodiment of the present invention.
- FIG. 17 is a timing chart for explaining the operation of the drive device shown in FIG.
- FIG. 18 is a block diagram showing a modified example of the drive device shown in FIG.
- FIG. 19 is a block diagram showing a modified example of the drive device shown in FIG.
- FIG. 20 is a timing chart for explaining the operation of the drive device shown in FIG.
- FIG. 21 is a block diagram showing a modification of the drive device shown in FIG.
- FIG. 22 is a block diagram showing the overall configuration of the driving apparatus according to the sixth embodiment of the present invention.
- FIG. 23 is a timing chart for explaining the operation of the drive device shown in FIG.
- FIG. 24 is a block diagram showing a modification of the drive device shown in FIG.
- FIG. 25 is a block diagram showing the overall configuration of the driving apparatus according to the seventh embodiment of the present invention.
- FIG. 26 is a timing chart for explaining the operation of the drive device shown in FIG.
- FIG. 27 is a block diagram showing the overall configuration of the drive device according to the eighth embodiment of the present invention.
- FIG. 27 is a block diagram showing the overall configuration of the drive device according to the eighth embodiment of the present invention.
- FIG. 28 is a circuit diagram showing the internal configuration of the output circuit shown in FIG.
- FIG. 29 is a block diagram showing the overall configuration of a conventional drive device.
- FIG. 30 is a timing chart for explaining an operation by the drive device shown in FIG. 29.
- FIG. 1 shows a configuration of a driving apparatus according to the first embodiment of the present invention.
- This device is used, for example, as a scanning line driver for a liquid crystal display panel.
- This apparatus includes a drive signal input terminal 101, a clock input terminal 102, a reset signal input terminal 103, frequency dividing circuits 104 and 105, signal generation units 106 and 107, and an output unit 108.
- the drive signal input terminal 101 inputs an external drive signal (start pulse).
- the clock input terminal 102 inputs an external clock.
- the reset signal input terminal 103 inputs an external reset signal.
- the frequency dividing circuit 104 divides the start panel input to the drive signal input terminal 101 by a predetermined cycle.
- the frequency dividing circuit 105 divides the clock input to the clock input terminal 102 by a predetermined cycle.
- the signal generator 106 outputs k enable signals sl to sk (k is a natural number) according to the start panel without the frequency divided by the frequency divider circuit 104 and the clock frequency divided by the frequency divider circuit 105. To do.
- the signal generator 107 outputs m (m is a natural number) data signals bl to bm according to the start pulse input to the drive signal input terminal 101 and the clock input to the clock input terminal 102.
- the output unit 108 includes (k X m) output circuits.
- the (k X m) output circuits are divided into k groups Grl to Grk.
- Each of the groups Grl to Grk has m output circuits.
- m output circuits Xl to Xm belong to the group Grl.
- m output circuits Xm + 1 to X2m belong to group Gr2.
- m output circuits X (k- l) m + l to X km belongs to the group Grk.
- the k groups Grl to Grk correspond to the k enable signals si to sk.
- Group Grl corresponds to enable signal si.
- Gnolepe Gr2 corresponds to enable signal s2.
- Group Grk corresponds to enable signal sk.
- the m output circuits belonging to each of the groups Gr :! to Grk correspond to m data signals bl to b m.
- the output circuits XI, Xm + 1 and X (k_l) m + 1 correspond to the data signal bl.
- the output circuits X2, Xm + 2, X (k_l) m + 2 correspond to the data signal b2.
- the output circuits Xm, X2m, and Xkm correspond to the data signal bm.
- Each of the (k X m) output circuits outputs a drive signal according to the enable signal corresponding to the group to which the output circuit belongs and the data signal corresponding to the output circuit.
- the enable signals sl to s20 from the signal generation unit 106 are connected to 320 output circuits.
- the enable signal s1 is connected to the output circuits XI to X16 belonging to the gnoleop Grl.
- the enable signal s2 is connected to the output circuits X17 to X32 belonging to the gnole Gr2.
- the enable signal s20 is connected to the output circuits X305 to X320 belonging to the group Gr20 in exactly the same manner.
- Data signals bl to bl6 from the signal generation unit 107 are connected to 320 output circuits.
- the data signal bl is connected to the output circuit XI, X17,..., X305 having the smallest number among the 16 output circuits belonging to each of the groups Gr :! to Gr20.
- the data signal b2 is connected to the output circuit X2, X18,..., X306 having the second smallest number among the 16 output circuits belonging to each of the loops Gr :! to Gr20. Thereafter, the data signal bl6 is connected in the same manner to the output circuit X16, X32,..., X320 having the largest number among the 16 output circuits belonging to each of the groups Gr :! to Gr20.
- FIG. 2 shows the internal configuration of the output circuit shown in FIG.
- the output circuit includes an enable signal input terminal 120s, a data signal input terminal 120b, an off-voltage input terminal 121, an output terminal OUT, an inverter 123, and transistors MN124, MP124, and MN125.
- the enable signal input terminal 120s receives an enable signal corresponding to this output circuit.
- the data signal input terminal 120b receives a data signal corresponding to this output circuit.
- the off-voltage input terminal 121 receives the reference voltage VEE.
- the transistors MN124 and MP124 constitute a transfer gate.
- the transistor MN124 is connected between the data signal input terminal 120b and the output terminal OUT, and receives the signal from the enable signal input terminal 120s.
- Transistor MP124 is connected between data signal input terminal 120b and output terminal OUT, and receives a signal from inverter 123 at its gate.
- the transistor MN125 is connected between the off-voltage input terminal 121 and the output terminal OUT, and receives a signal from the inverter 123 at the gate.
- the system power supply voltage VDD is “1.8 V” and the system ground voltage VSS is “0 V”.
- the on-voltage VGG required to drive the thin film transistor of the liquid crystal display panel is “+ 15V” and the off-voltage VEE is “_15V”.
- the signal generation includes a shift register 116, k number of level shifters: LSa_l to Sa_k, and k output buffers OBa— :! to OBa—k.
- the shift register 116 includes k flip-flops FFa_ :! to FFa_k connected in series.
- Flip-flop FFa_ 1 Each of ⁇ FFa-k receives the start pulse from frequency divider 104 (or the output from output terminal Q of the previous flip-flop) at data terminal D and receives the clock from frequency divider 105 as the clock terminal CK is received and the reset signal from reset signal input terminal 103 is received at reset terminal R.
- the signal generation unit 107 includes a shift register 117, m level shifters LSb_1 to LSb_m, and m output buffers ⁇ Bb_1 to ⁇ Bb_m.
- the shift register 117 includes m flip-flops FFa_ :! to FFa_m connected in series. Each of the flip-flops FFb_l to FFb_k receives a start pulse from the drive signal input terminal 101 or an output from the output terminal Q of the preceding flip-flop at the data terminal D, and receives from the clock input terminal 102 The clock is received at the clock terminal CK, and the reset signal from the reset signal input terminal 103 is received at the reset terminal R.
- To LSb—m is the voltage required to drive the liquid crystal display element VGG, the output from the flip-flop corresponding to itself. — Convert to a signal with VEE amplitude.
- each of the frequency dividing circuit 104, the frequency dividing circuit 105, the flip-flops FFa— :! to FFa—k, and the flip-flops FFb— :! to FFb_m is composed of low-pressure transistors.
- Each is composed of a high voltage transistor.
- the breakdown voltage of the low breakdown voltage transistor may be about 3V, for example.
- the breakdown voltage of the high voltage transistor may be about 30V.
- the area of the high breakdown voltage transistor is larger than the area of the low breakdown voltage transistor.
- the signal generation unit 107 sequentially outputs the data signals bl to bm in synchronization with the clock pulse input to the clock input terminal 102 (sequentially). "High level”).
- the signal generator 106 outputs the enable signal si in synchronization with the clock divided by the frequency divider circuit 105.
- the frequency division cycle in the frequency divider circuit 105 is set so that m data signals sequentially become “high level” during a period when one enable signal is “high level”.
- the output circuits X :! to Xm belonging to the group Grl sequentially output the data signals bl to bm as drive signals.
- the drive signal has a “high level” ON voltage VGG and a “low level” OFF voltage VEE.
- the signal generator 107 sequentially outputs the data signals bl to bm again.
- the signal generator 106 outputs the next enable signal s2.
- the output circuits Xm + 1 to X2m belonging to the gnole Gr2 output the data signals bl to bm as drive signals.
- the output circuits X (k-l) m + 1 to Xkm output the data signals bl to bm as drive signals.
- the enable signal si is “high” for 16 cycles.
- Other enablers The signals s2 to s20 remain “low level”. Therefore, the output circuits X1 to X16 sequentially output drive signals.
- each of the output circuits X17 to X320 does not output a drive signal even if a data signal is input, since an enable signal corresponding to itself is not input.
- (k X m) drive signals are output. That is, the number of outputs at the front stage of the drive device can be reduced. This can reduce the circuit scale of the drive unit.
- the area (S106) of the signal generation unit 106, the area (S107) of the signal generation unit 107, and the area (S108) of the output unit 108 are as follows.
- the area (S ⁇ ) of the other part was “0.10 mm 2 ”.
- the total area (SSS) in the present embodiment is as follows.
- the conventional total area (SSS ′) is as follows.
- the total area (SSS) in this embodiment can be reduced to about 50% of the conventional total area (SS S ′).
- FIG. 4 shows the overall configuration of the driving apparatus according to the second embodiment of the present invention.
- This drive device includes a control signal input terminal 200 and a logic circuit 201 in addition to the drive device shown in FIG.
- the control signal input terminal 200 inputs an external control signal.
- the logic circuit 201 receives the control signal input from the control signal input terminal 200 from the shift register 116. Set all outputs to “low level”.
- Other configurations are the same as those in FIG.
- the logic circuit 201 includes k AND circuits 201— :! to 201-k. AND circuit 201— 1
- Each of .about.201-k receives the control signal input to the control signal input terminal 200 and the output from the flip-flop corresponding to itself.
- the AND circuit 201-1 receives the control signal and the output from the flip-flop FFa_l.
- each of the outputs from the shift register 116 corresponds to being not cut off by the logic circuit 201. Supplied to the level shifter. That is, the same operation as in FIG. 3 is executed.
- the enable signal s2 is not supplied to each of the output circuits Xm + 1 to X2m, even if the data signals b1 to bm are sequentially supplied to the output circuits Xm + 1 to X2m, the output circuits Xm + 1 to X2m The drive signal is not output from X 2m (it does not become “high level”).
- the driving force S is output while the control signal is input, and the driving signal is not output while the control signal is not input.
- the output of the drive signal can be limited by the control signal.
- the level shifter and the output buffer are stopped while the control signal is not input, power consumption can be reduced.
- the logic circuit 201 includes level shifters LSa — l ⁇ : LSa_k and an output buffer. The same effect can be obtained also when connected between OBa— :! to OBa—k.
- the logic circuit 201 includes a high voltage transistor.
- the same effect can be obtained when the logic circuit 201 is connected between the shift register 117 of the signal generation unit 107 and the level shifter LSb— :! to LSb—m. I can do it.
- the logic circuit 201 includes m AND circuits 201—! ⁇ 201 _m included.
- the same effect can be obtained when the logic circuit 201 is connected between the level shifter LSb— :! to LSb_m and the output buffer ⁇ Bb_ :! to ⁇ Bb_m.
- the logic circuit 201 includes a high voltage transistor.
- the logic circuit 201 is connected between the shift register 116 and the level shifter LSa_ :! to LSa_k, and between the shift register 117 and the level shifter LSb-1 to LSb-m.
- the logic circuit 201 includes AND circuits 201a- :! to 201a-k, 201b-: !!-201b-m.
- the level shifter and output buffer included in the other signal generation unit are stopped, so that power consumption can be further reduced.
- the logic circuit 201 includes level shifters LSa— :! to LSa—k and output buffers OBa— :! to OBa—k, and level shifters LSb— :! to LSb—m.
- the logic circuit 201 includes a high voltage transistor.
- FIG. 11 shows the internal configuration of the signal generation unit 106 of this embodiment.
- the signal generator 106 includes selectors 301 and 302 in addition to the signal generator shown in FIG. Other configurations are the same as those in FIG.
- the selector 301 is connected between the flip-flop FFa_1 and the flip-flop FFa_2.
- the selector 301 has a normal mode and a partial display mode. In the normal mode, the selector 301 supplies the output from the preceding flip-flop FFa_l to the succeeding flip-flop FFa-2. In the partial display mode, the selector 301 is connected to the system ground. Supply voltage VSS to flip-flop FFa-2.
- the selector 302 is connected between the flip-flop FFa— (k ⁇ 1) and the flip-flop FFa—k.
- the selector 302 has a normal mode and a partial display mode. In the normal mode, the selector 302 supplies the output of the preceding flip-flop FFa— (k_l) force to the subsequent flip-flop FFa_k. In the partial display mode, the selector 302 supplies the output from the flip-flop FFa-1 (the previous flip-flop of the selector 301) to the subsequent flip-flop FFa_k.
- one enable signal becomes “high level” in response to one start pulse, and data signals bl to bm are sequentially output.
- the enable signal sk In the partial display mode, the enable signal sk, not the enable signal s2, becomes "no level" after the enable signal si. Therefore, the drive signals are sequentially output from the output circuit X (k ⁇ l) m + 1 to Xkm instead of the output circuit Xm + 1 to X2m.
- the drive signal output by changing the operation mode of the selector. This makes it possible to display only a predetermined line on the liquid crystal display panel (or not to update the image displayed on the predetermined line). In other words, the partial display function can be realized. Furthermore, in the partial display mode, the flip-flops FFa-2 to FFa- (k-1) are stopped, so that power consumption can be reduced.
- the selector 301 has the ninth flip-flop FFa from the top.
- 9th and 10th flip-flop FFa Connected between 10 and selector 302 connected between 20th flip-flop FFa_20 and 21st flip-flop FFa_21 from the top.
- FIG. 13 shows the overall configuration of a drive apparatus according to the fourth embodiment of the present invention.
- This device includes a selection circuit 400 and a frequency dividing circuit 402 in addition to the driving device shown in FIG.
- the selection circuit 400 includes p selectors 401 _ 1 to 4 ( ⁇ _ ⁇ , where p is “k / 2”, where “k” is an even number). It is the same.
- Each of the selectors 401— :! to 401— ⁇ corresponds to two flip-flops and two shift registers.
- the selector 401-1 corresponds to two flip-flops FFb_l and FFb-2 and two shift registers LSb_l and LSb_2.
- Each of the selectors 401_l to 401_p has a normal mode and a two-line drive mode.
- selector 401—! Each of -401-p supplies the output from the first flip-flop corresponding to itself to the first level shifter corresponding to itself, and outputs the second flip-flop corresponding to itself to the second corresponding to itself.
- Supply to level shifter For example, the selector 401-1 supplies the output from the flip-flop FFb-1 to the level shifter LSb-1, and supplies the output to the output level shifter LSb-2 from the flip-flop FFb-2.
- each of the selectors 401- :! to 401-p supplies the output from the first flip-flop to the first level shifter and the second level shifter.
- the selector 401-1 supplies the output from the flip-flop FFb- 1 to the level shifters LSb- 1 and LSB- 2.
- the frequency divider circuit 402 has a normal mode and a two-line drive mode. In the normal mode, the frequency dividing circuit 402 outputs the start pulse input to the drive signal input terminal 101 as it is. In the 2-line drive mode, the frequency dividing circuit 402 divides the start pulse input to the drive signal input terminal 101 by a predetermined cycle.
- the shift register 117 receives the start pulse from the frequency divider circuit 402.
- the frequency dividing circuit 402 In the normal mode, the frequency dividing circuit 402 outputs the start pulse input to the drive signal input terminal 101 as it is.
- the selector 401-1 supplies the output of the flip-flop FFb-1 to the level shifter LSb-1, and supplies the output from the flip-flop FFb_2 to the level shifter LSb-2. Therefore, the same operation as shown in Fig. 3 is executed. It is.
- the shift register 117 inputs a start pulse (start panorace in which a period of “high level” is extended) divided by the frequency divider circuit 402. Further, since the output from the flip-flop FFb_1 is supplied to the level shifters L Sb-1 and LSb-2 by the selector 401_1, the data signals bl and b2 are output simultaneously. Therefore, each of the output circuits XI and X2 outputs a drive signal at the same time.
- a plurality of drive signals can be output simultaneously depending on the operation mode of the selector.
- a plurality of lines here, two lines
- This can reduce the resolution of the LCD panel.
- power consumption since the number of writing times by a data driver (not shown) of the liquid crystal display panel can be reduced, power consumption can be reduced.
- force N-line driving (N is a natural number) described for two-line driving can also be realized.
- N is a natural number
- each of the selectors is good if there is a one-to-one correspondence between N flip-flops and N level shifters.
- each selector may supply the output from the first flip-flop among the corresponding flip-flops to each of the N level shifters.
- selector 401— :! to 401—p force S level shifter LSb—1 to: LSb—m and output buffer OBb— :! to OBb-m are connected. If you are, you can get the same effect.
- each of the selectors 401— :! to 401—p corresponds to two shift registers and two output buffers.
- p selectors between flip-flops FFb_ :! to FFb_m and level shifter LSb— 1 to: LSB—m 403— :! ⁇ 403-p can also be provided.
- Each of ⁇ 403_p corresponds to an even-numbered flip-flop and a level shifter.
- each of the selectors 403— :! to 403-p supplies the output from the flip-flop corresponding to itself to the level shifter corresponding to itself.
- the selector 403-1 supplies the output from the flip-flop FFb_2 to the level shifter LSb-2.
- selector 403—! ⁇ 403 _p each is 2 la
- the system ground voltage VSS is supplied to the level shifter corresponding to the system ground voltage VSS. According to this, it is possible to prevent power consumption by the level shifter that is not required in the two-line drive mode.
- FIG. 16 shows the overall configuration of the drive apparatus according to the fifth embodiment of the present invention.
- This apparatus includes a control signal input terminal 500 and a logic circuit 501 in addition to the driving apparatus shown in FIG.
- the control signal input terminal 500 inputs an external control signal.
- the logic circuit 501 sets all k outputs from the shift register 116 to “high level” when the control signal input to the control signal input terminal 500 is “high level”.
- the other configurations are the same as in Fig. 1.
- the logic circuit 501 includes k OR circuits 501—! ⁇ Includes 501—k. ⁇ R circuit 501—! Each of ⁇ 501k receives the control signal input to the control signal input terminal 500 and the output from the corresponding flip-flop.
- the OR circuit 501-1 receives the control signal and the output from the flip-flop FFa-1.
- each of enable signals sl to sk from shift register 116 is supplied to the corresponding level shifter. That is, the same operation as that shown in FIG. 3 is executed.
- each of the enable signals sl to sk is supplied simultaneously to the corresponding m output circuits.
- the enable signals s2 to sk are also output.
- the data signal bl is output, not only the output circuit XI but also the output circuits Xm + 1 1,. That is, it belongs to the group Grl Not only the m output circuits but also the output circuits belonging to each of the other groups Gr2 to Grk simultaneously output drive signals at the same time.
- the drive signal is simultaneously output from the output circuit belonging to another group as well as the output circuit belonging to one group.
- a plurality of drive signals can be simultaneously output during a period in which the control signal is “high level”. It is also possible to set the divider circuit 104 so that the divider circuit 104 outputs the clock input to the drive signal input terminal 101 without dividing in the two-line drive mode. According to this, when displaying a solid image (an image with a uniform gradation number (for example, an image in which all pixels are “white”)) on the liquid crystal display panel, a data driver ( The ability to shorten the image writing time by (not shown) can be reduced.
- the logic circuit 501 includes a high-breakdown-voltage transistor.
- the logic circuit 501 includes m OR circuits 501—! ⁇ Includes 501—m.
- the logic circuit 501 includes m OR circuits 501—! ⁇ Includes 501—m.
- FIG. 20 when a control signal is input to the control signal input terminal 500 (“high level”), all the data signals bl to bm simultaneously become “noise level”. Therefore, all the power S of the output circuit to which the “high level” enable signal is input is outputted at the same time. For example, if the enable signal si is “noisy level”, all of the output circuits X :! to Xm simultaneously output drive signals.
- the same effect can be obtained when the logic circuit 501 is connected between the level shifter LSb— :! to LSb_m and the output buffer ⁇ Bb_ :! to ⁇ Bb_m.
- the logic circuit 501 includes a high-breakdown-voltage transistor.
- FIG. 22 shows the overall configuration of the drive apparatus according to the sixth embodiment of the present invention.
- This apparatus includes a control signal input terminal 600 and a logic circuit 601.
- the control signal input terminal 600 inputs a control signal from the outside.
- the logic circuit 601 sets all of the enable signals s:! To sk from the shift register 116 to “LOW LEVEL”.
- the logic circuit 601 has m NOR circuits 601—! ⁇ Includes 601_m.
- Each of the N0R circuit 601— :! to 601 — k receives a control signal input to the control signal input terminal 600 and a signal obtained by inverting the output from the flip-flop corresponding to itself.
- the N0R circuit 601_1 receives a control signal and a signal obtained by inverting the output from the flip-flop FFb_l.
- Other configurations are the same as those in FIG.
- each of the m outputs from the output buffer ⁇ Bb- :! to ⁇ Bb-m has a large rise time and fall time because the output buffer is composed of high voltage transistors.
- the waveform is distorted.
- the waveforms of the data signals bl to bm shown in FIG. 22 are obtained when the output from the shift register 117 is directly supplied to the level shifters LSb— :! to LSb-m.
- control signal becomes “high level”.
- the signal from the flip-flop FFb-l becomes “low level” and the data signal bl becomes “low level”, so that the drive signal of the output circuit XI and the drive signal thereof becomes “low level”.
- control signal becomes “low level”.
- data signal b2 becomes “noise level”
- the drive signal from the output circuit X2 becomes “noise level”.
- the control signal is “high” for a predetermined time shorter than that period during a period from when one data signal becomes “high level” until the next data signal becomes “high level”. "Level" is set.
- the logic circuit 601 includes a shift register 116 and a level shifter LSa — l ⁇ : L
- the logic circuit 601 has k N0R circuits 601—! ⁇ 601—includes k.
- FIG. 25 shows the overall configuration of the drive apparatus according to the seventh embodiment of the present invention.
- This device includes a control signal input terminal 700 and a logic circuit 701 in addition to the driving device shown in FIG. Other configurations are the same as those in FIG.
- the control signal input terminal 700 inputs an external control signal.
- the logic circuit 701 includes k OR circuits 701a- :! to 701a-k and m O-R circuits 701b- :! to 701b-m.
- Each of the OR circuits 701a- :! to 701a-k receives the control signal from the control signal input terminal 700 and the output from the flip-flop corresponding to itself.
- the OR circuit 701a-1 receives the control signal and the output from the flip-flop FFa-1.
- OR circuit 701b—! ... 701b-m each receive a control signal input terminal 700 and an output from a flip-flop corresponding thereto.
- the R circuit 701b_l receives the control signal and the output from the flip-flop FFb_l.
- each output from the shift register 116 is supplied to the corresponding level shifter, and the enable signal sl to sk Is output.
- each output from shift register 117 corresponds The data signals bl to bm are output to the level shifter. That is, the same operation as that shown in FIG. 3 is executed.
- the k OR circuits 701a_:! To 701a_k each output power and m ⁇ R
- the outputs of the circuits 701b_ :! to 701b_m are all “high level”. That is, the enable signals sl to sk from the signal generation unit 106 are all output at the same time, and the data signals bl to bm from the signal generation unit 107 are all output at the same time. As a result, drive signals are output simultaneously from all of the output circuits Xl to Xkm.
- all the gate lines of the display panel can be simultaneously activated.
- the charge accumulated in the liquid crystal element of the display panel can be discharged at once. Thereby, for example, it is possible to quickly turn off the display panel without disturbing the image on the display panel.
- FIG. 27 shows the overall configuration of the drive apparatus according to the eighth embodiment of the present invention.
- This device includes a control signal input terminal 800 in addition to the drive device shown in FIG.
- Each of the (k X m) output circuits Xl to Xkm receives a control signal input to the control signal input terminal 800.
- Other configurations are the same as those in FIG.
- FIG. 28 shows the internal configuration of the output circuit shown in FIG.
- the output circuit includes a selection unit 80 in addition to the output circuit shown in FIG.
- the selection unit 80 includes an input terminal 81, an inverter 82, transistors MN83, MP83, MN84, an output terminal OUT ′, and an on-voltage input terminal 85.
- the input terminal 81 inputs the control signal from the control signal input terminal 800.
- Transistors MN83 and MP83 constitute a transfer gate.
- the transistor MN83 is connected between the output terminal OUT and the output terminal OUT ′, and receives a control signal from the input terminal 81. Receive it.
- the transistor MP83 is connected between the output terminal OUT and the output terminal OUT ′, and receives the control signal inverted by the inverter 82 at the gate.
- the transistor MP84 is connected between the output terminal OUT ′ and the on-voltage input terminal 85, and receives a control signal from the input terminal 81 at its gate.
- the on-voltage input terminal 85 receives the on-voltage VGG.
- each of the output circuits Xl to Xkm outputs a drive signal in accordance with the enable signal and data signal corresponding to itself.
- all the gate lines of the display panel can be simultaneously activated. As a result, the charge accumulated in the liquid crystal element of the display panel can be discharged at once. As a result, the display panel can be quickly made full screen “black”.
- a shift register including a flip-flop and a frequency divider circuit are used as a circuit that sequentially outputs k signals and a circuit that sequentially outputs m signals.
- the power of the present invention is not limited to this.
- it may be configured by combining a counter and a decoder.
- the embodiments have been described with respect to the driving device for driving the scanning lines of the liquid crystal display panel, but the present invention is not limited to this.
- other display panels such as an organic EL panel can also be applied.
- the present invention can be applied to any device that performs active matrix driving.
- the present invention can be applied to a configuration in which signals are sequentially output to a plurality of output terminals in a single-chip semiconductor integrated circuit.
- the circuit area can be reduced, so that it is useful as a driving device and a driving method for driving a scanning line of a display device such as a liquid crystal display panel or an organic EL panel. It is.
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/585,512 US20090122040A1 (en) | 2004-11-10 | 2005-11-08 | Drive device and drive method |
JP2006544898A JPWO2006051790A1 (ja) | 2004-11-10 | 2005-11-08 | 駆動装置および駆動方法 |
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JP2004326563 | 2004-11-10 | ||
JP2004-326563 | 2004-11-10 |
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WO2006051790A1 true WO2006051790A1 (ja) | 2006-05-18 |
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PCT/JP2005/020469 WO2006051790A1 (ja) | 2004-11-10 | 2005-11-08 | 駆動装置および駆動方法 |
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US (1) | US20090122040A1 (ja) |
JP (1) | JPWO2006051790A1 (ja) |
CN (1) | CN100440307C (ja) |
WO (1) | WO2006051790A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009169384A (ja) * | 2008-01-17 | 2009-07-30 | Renei Kagi Kofun Yugenkoshi | フラットパネルディスプレイにおけるゲートドライバーの駆動装置 |
JP2011118052A (ja) * | 2009-12-01 | 2011-06-16 | Sony Corp | 表示装置及び駆動方法 |
Families Citing this family (2)
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TWI364022B (en) * | 2007-04-24 | 2012-05-11 | Raydium Semiconductor Corp | Scan driver |
CN101598966A (zh) * | 2008-06-06 | 2009-12-09 | 深圳富泰宏精密工业有限公司 | 显示双画面的触控装置及其控制方法 |
Citations (5)
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JPS6180226A (ja) * | 1984-09-28 | 1986-04-23 | Toshiba Corp | アクテイブ・マトリツクス駆動装置 |
JPH01267694A (ja) * | 1988-04-20 | 1989-10-25 | Hitachi Ltd | アクティブマトリクス方式の表示装置及びその走査回路と走査回路の駆動回路 |
JPH05313129A (ja) * | 1992-05-07 | 1993-11-26 | Fujitsu Ltd | 液晶表示装置 |
JP2000227784A (ja) * | 1998-07-29 | 2000-08-15 | Seiko Epson Corp | 電気光学装置の駆動回路および電気光学装置 |
JP2002215119A (ja) * | 2000-12-26 | 2002-07-31 | Hannstar Display Corp | ゲート制御線駆動回路及びゲート制御線駆動方法 |
Family Cites Families (3)
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TW440742B (en) * | 1997-03-03 | 2001-06-16 | Toshiba Corp | Flat panel display device |
US6437766B1 (en) * | 1998-03-30 | 2002-08-20 | Sharp Kabushiki Kaisha | LCD driving circuitry with reduced number of control signals |
JP3743503B2 (ja) * | 2001-05-24 | 2006-02-08 | セイコーエプソン株式会社 | 走査駆動回路、表示装置、電気光学装置及び走査駆動方法 |
-
2005
- 2005-11-08 JP JP2006544898A patent/JPWO2006051790A1/ja not_active Withdrawn
- 2005-11-08 WO PCT/JP2005/020469 patent/WO2006051790A1/ja active Application Filing
- 2005-11-08 CN CNB2005800059447A patent/CN100440307C/zh not_active Expired - Fee Related
- 2005-11-08 US US10/585,512 patent/US20090122040A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6180226A (ja) * | 1984-09-28 | 1986-04-23 | Toshiba Corp | アクテイブ・マトリツクス駆動装置 |
JPH01267694A (ja) * | 1988-04-20 | 1989-10-25 | Hitachi Ltd | アクティブマトリクス方式の表示装置及びその走査回路と走査回路の駆動回路 |
JPH05313129A (ja) * | 1992-05-07 | 1993-11-26 | Fujitsu Ltd | 液晶表示装置 |
JP2000227784A (ja) * | 1998-07-29 | 2000-08-15 | Seiko Epson Corp | 電気光学装置の駆動回路および電気光学装置 |
JP2002215119A (ja) * | 2000-12-26 | 2002-07-31 | Hannstar Display Corp | ゲート制御線駆動回路及びゲート制御線駆動方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009169384A (ja) * | 2008-01-17 | 2009-07-30 | Renei Kagi Kofun Yugenkoshi | フラットパネルディスプレイにおけるゲートドライバーの駆動装置 |
JP2011118052A (ja) * | 2009-12-01 | 2011-06-16 | Sony Corp | 表示装置及び駆動方法 |
Also Published As
Publication number | Publication date |
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JPWO2006051790A1 (ja) | 2008-05-29 |
CN1922650A (zh) | 2007-02-28 |
US20090122040A1 (en) | 2009-05-14 |
CN100440307C (zh) | 2008-12-03 |
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