WO2006043492A1 - 不揮発性記憶装置、不揮発性記憶装置の書込み方法及びコントローラ - Google Patents
不揮発性記憶装置、不揮発性記憶装置の書込み方法及びコントローラ Download PDFInfo
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- WO2006043492A1 WO2006043492A1 PCT/JP2005/019006 JP2005019006W WO2006043492A1 WO 2006043492 A1 WO2006043492 A1 WO 2006043492A1 JP 2005019006 W JP2005019006 W JP 2005019006W WO 2006043492 A1 WO2006043492 A1 WO 2006043492A1
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- memory
- transfer
- nonvolatile memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Definitions
- Non-volatile memory device non-volatile memory device writing method, and controller
- the present invention relates to a nonvolatile memory device using a semiconductor memory characterized by a data writing method, a nonvolatile memory device writing method, and a controller.
- a nonvolatile storage device equipped with a nonvolatile memory has been expanded as a memory card for digital cameras and mobile phones.
- a storage capacity of memory cards increases, its use expands from storage of small volumes such as data files and still images to video recording that requires a larger capacity.
- NAND type flash memory which is mainly used as a non-volatile memory of a memory card, has increased the capacity of a physical page as a data writing unit with an increase in the capacity.
- the flash memory of less than 128MB (bytes) mainly has a physical page capacity of 512B
- the flash memory of more than 128MB mainly has 2kB of physical pages.
- Patent Document 1 the writing speed is increased by providing a plurality of non-volatile memory write units.
- Patent Document 2 writing is realized by a buffer memory having a writing unit equal to or less than that of the nonvolatile memory.
- Patent Document 1 Japanese Patent Laid-Open No. 7-226095
- Patent Document 2 JP 2000-293427 A
- FIG. 1 is a timing chart at the time of data writing by the nonvolatile memory device.
- the host is a device that first transfers data to be written to the nonvolatile storage device in order to write data to the nonvolatile storage device.
- the upper part of Fig. 1 shows the transfer of write data from an external host to the buffer memory in the nonvolatile memory device.
- the host transfers data to the non-volatile storage device.
- data is temporarily stored in the buffer memory.
- the data transfer time is as follows.
- write data is transferred from the buffer memory to the flash memory in the nonvolatile memory device during a period of time T 2 to T 3.
- the middle part of FIG. 1 represents the transfer of write data from the buffer memory in the nonvolatile memory device to the flash memory in the nonvolatile memory device.
- the time required for data transfer is about the same as ⁇ 1 to ⁇ 2, for example, 164 sec.
- a data write command is issued to the flash memory at times T3 to T4, as shown in the operation of the flash memory in the nonvolatile memory device. This time is negligibly short compared to the data transfer time.
- the nonvolatile memory device of the present invention includes a nonvolatile memory having a plurality of independently writable physical pages, and a buffer memory that temporarily holds write data given from the outside And a controller for controlling writing to the non-volatile memory, the controller comprising the non-volatile memory
- the controller comprising the non-volatile memory
- the data to be written to the physical page of the nonvolatile memory may be data transferred from an external device.
- the waiting time from the start of data transfer to the buffer memory to the start of data transfer from the buffer memory to the nonvolatile memory is the amount of data transfer from the external device. It may be one transfer unit time or more.
- one transfer unit of the data transfer may be a data amount for one sector.
- the buffer memory may be composed of a plurality of volatile memories.
- the waiting time from the start of the data transfer to the buffer memory to the start of the data transfer from the buffer memory to the nonvolatile memory is the amount of data transfer from the external device. It may be one transfer unit time or more.
- one transfer unit of the data transfer may be data for one sector.
- the transfer start waiting time may be a time longer than a data transfer time to one of the buffer memories.
- the capacity of each buffer memory of the plurality of buffer memories may have a capacity that is an integral multiple of a data transfer unit transferred from the external device.
- the total capacity of the buffer memory may be equal to or larger than the storage capacity of a physical page that is a unit of writing to the nonvolatile memory.
- the buffer memory may be a dual-port RAM.
- the buffer memory may be a FIFO memory.
- the nonvolatile memory device writing method of the present invention temporarily holds a nonvolatile memory having a plurality of independently writable physical pages and externally supplied write data. And a controller for controlling writing to the non-volatile memory, wherein the data to be written to the non-volatile memory is transferred.
- the buffer memo The buffer memory power is transferred to the non-volatile memory earlier than the end of the data transfer, and after the transfer of the physical page unit to the non-volatile memory is completed, the non-volatile Data is written to the physical page of the volatile memory.
- the controller of the present invention provides a buffer memory that temporarily holds write data given from outside for writing to a non-volatile memory having a plurality of independently writable physical pages.
- the controller transfers the data to the buffer memory and temporarily holds it, and the transfer of the data is completed.
- the transfer from the buffer memory to the non-volatile memory is started early, and after the transfer in units of physical pages to the non-volatile memory is completed, data is written to the physical page of the non-volatile memory.
- Data that can be simultaneously written to the non-volatile memory is transferred to an external force non-volatile memory device, and at the same time, data is transferred from the buffer memory to the non-volatile memory inside the non-volatile memory device.
- the time required for data transfer can be shortened, and the writing performance of the nonvolatile memory device can be improved.
- FIG. 1 is a timing chart showing a method for writing data in a conventional nonvolatile memory device.
- FIG. 2 is a block diagram of a nonvolatile memory device according to Example 1 of the present invention.
- FIG. 3 is a conceptual diagram of a flash memory according to Embodiment 1 of the present invention.
- FIG. 4 is a conceptual diagram of a physical block of a flash memory according to Embodiment 1 of the present invention.
- FIG. 5 is a timing chart of a writing method according to Embodiment 1 of the present invention.
- FIG. 6 is a block diagram of a nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 7 is a timing chart of a writing method according to Embodiment 2 of the present invention.
- FIG. 8 is a block diagram of a nonvolatile memory device according to Embodiment 3 of the present invention.
- FIG. 9 is a timing chart of a writing method according to Embodiment 3 of the present invention.
- FIG. 10 is a block diagram of a nonvolatile memory device according to Embodiment 4 of the present invention.
- FIG. 11 is a timing chart of a writing method according to Embodiment 4 of the present invention.
- FIG. 2 is a schematic diagram illustrating the nonvolatile memory device according to the first embodiment and a host that reads data from and writes data to the nonvolatile memory device.
- a non-volatile storage device such as a memory card 101 A is connected to the host 102.
- the host 102 is a device for writing / reading data to / from the memory card 101A.
- a flash memory 111 which is a nonvolatile memory
- a controller 112A which controls the flash memory 111 in response to a write command and a read command from the host 102
- a buffer memory 113 which stores data from the host 102.
- the nota memory 113 is a volatile memory for temporarily storing data written to the flash memory 111 or read data from the flash memory 111 to the host 102.
- the nother memory 113 has a capacity of 2 kB corresponding to a physical page which is a general writing unit.
- FIG. 3 is a conceptual diagram showing the inside of the flash memory 111 of FIG.
- the flash memory 111 has a capacity of 128 MB, and there are 1024 physical blocks 201 (PB0 to PB1023) inside.
- the capacity of the data area of each physical block 201 is 128 kB.
- a physical block is the smallest erasure unit when erasing data.
- FIG. 4 is a conceptual diagram showing the inside of one physical block 201 of FIG.
- each physical block 201 there are 64 physical pages 301 (PP0 to PP63).
- Each physical page 30 The capacity of 1 data area is 2kB.
- a physical page is the smallest unit for writing data.
- Each physical page 301 consists of 4 sectors, for example, and 1 sector has a capacity of 512B.
- This data is for 4 sectors which are write data of the same capacity as the physical page 301 which is a unit of writing to the flash memory 103.
- the controller 112A starts data transfer from the buffer memory 113 to the flash memory 111 at an arbitrary time T3 after the time T2 when the transfer for one sector is completed.
- This data transfer rate is not necessarily the same as the transfer rate from the host 102 to the buffer to the memory 113, but the same example is shown here. Accordingly, the data held in the buffer memory 113 after time T4 is continuously transferred to the flash memory 111, and this transfer is completed at time T5.
- the controller 112A issues a write command between times T5 and T6, and performs a write process from time ⁇ 6 to time ⁇ 7.
- the time required for data transfer will be described.
- the time required to transfer 512 mm data from time 1 to time 2 is 512BZ4bitZ25MHz 41 ⁇ sec. Let this time be t.
- Host 102 starts the next 512B transfer from time T2. Therefore, the time T4 for ending the transfer of 2kB for 4 sectors is 164 seconds after the start time T1.
- Time T1 Time T4 is T.
- the waiting time d from the buffer memory 113 to the start of the transfer to the flash memory 111 is t or more and less than T. That is, T3 may be any timing from T2 to T4, but the data transfer time can be shortened as close as possible to ⁇ 2.
- the waiting time d may be the same as the time from T1 to ⁇ 2.
- the buffer memory 113 is transferred to the flash memory 111.
- Power to finish data transfer This time is also 164 sec.
- the controller 112A issues a command for writing the transferred data to the flash memory 111.
- This time is a force command issued between times T5 and T6.
- the time required to issue the command is short and negligible compared to 41 ⁇ sec, which is the data transfer time in 512B units.
- flash memory 111 Upon receiving a write command from controller 112A, flash memory 111 starts writing from time T6 and ends writing at time T7.
- the time required for this writing is long. Generally, it takes about 200 seconds.
- the time from the time T1 to the completion of writing at T7 is d + 164 / ⁇ s + 200 / ⁇ s.
- d is shorter than 164 sec, according to the present embodiment, data can be written in a shorter time than in the prior art, and the writing speed can be improved.
- the memory card 101B includes a controller 112B, a selector 121, nother memories 122 to 125, and a selector 126 in addition to the same flash memory 111 as in the first embodiment.
- the selector 121 switches the four buffer memories 122 to 125 when transferring data between the host 102 and the memory card 101B.
- the buffer memories 122 to 125 are volatile memories, each having a capacity of 512B, which is a data transfer unit from the host 102 and is also a sector unit.
- the selector 126 is connected between the buffer memories 122 to 125 and the flash memory 111, and selects one of the four buffer memories.
- the controller 112B switches the data transfer from the host 102 in units of 512B and holds it in the buffer memories 122 to 125 when data is written, and transfers the data in the buffer memory to the flash memory 111.
- the host 102 starts data transfer from time T1.
- the controller 112B first switches to the buffer memory 122 by the selector 121. Therefore, data is transferred to the buffer memory 122 from time T1 to T2.
- the controller 112B sequentially switches to the buffer memories 123, 124, and 125 to hold the data transferred by 512B.
- data transfer from the buffer memory 122 to the flash memory 111 is started from time T3 until time T4 when data transfer to the buffer memory 125 ends.
- the buffer memory 123, 124, 125 sequentially transfers the data to the flash memory 111, and the transfer ends at time T5.
- a write command is issued between times T5 and T6, and data writing is completed between time ⁇ 6 and time ⁇ 7.
- t, d, and T are the same as in Example 1.
- the time T3 is set between T2 and T4. In this way, as in the first embodiment, data can be written in a short time, and the writing speed can be improved.
- the memory card 101C has a controller 112C, a selector 131, nother memories 132 and 133, and a selector 134 in addition to the same flash memory 111 as in the first embodiment.
- the selector 131 switches the two buffer memories 132 and 133 when transferring data from the host 102 to the memory card 101C.
- the noffer memories 132 and 133 are volatile memories.
- each of the buffer memories 132 and 133 is assumed to have a capacity of lkB which is an integral multiple of the data transfer unit from the host 102, here twice.
- the selector 134 is connected between the buffer memories 132 and 133 and the flash memory 111 and selects one of them. Controller 112C switches lkB unit data transfer from host 102 when data is written The buffer memory 132 and 133 hold the data in the buffer memory and transfer the data in the buffer memory to the flash memory 111.
- the host 102 starts data transfer from time T1.
- the controller 112C first switches to the buffer memory 132 by the selector 131. Accordingly, lkB data is transferred to the buffer memory 132 from time T1 to time T2.
- time T2 switching to the buffer memory 133 is performed, and lkB data transfer is performed.
- Data transfer to the buffer memory 132 and the flash memory 111 is started from time T3 after time T2 until time T4 when data transfer to the buffer memory 133 ends.
- the data transfer of lkB is completed, the data transfer is further performed from the buffer memory 133 to the flash memory 111, and the transfer is completed at time T5.
- the memory card 101D has a controller 112D, a selector 141, nother memories 142 and 143, and a selector 144 in addition to the same flash memory 111 as in the first embodiment.
- the selector 141 switches between the two buffer memories 142 and 143 when data is transferred from the host 102 to the memory card 101D.
- Each of the buffer memories 142 and 143 is a volatile memory, and has a capacity of 512B, which is a data transfer unit from the host 102 and also a sector unit.
- a selector 144 is connected between the buffer memories 142 and 143 and the flash memory 111 and selects one of them.
- the controller 112D switches the data transfer in units of 512B from the host 102 when writing data, and stores them in the buffer memories 142 and 143 respectively. And the data in the buffer memory is transferred to the flash memory 111.
- the host 102 starts data transfer from time T1.
- the controller 11 2D first switches to the buffer memory 142 by the selector 141. Accordingly, 512 B data is transferred to the buffer memory 142 from time T1 to T2.
- the controller 112D switches the selectors 141 and 144 so that the data from the host 102 is transferred to the buffer memory 143 and the data in the buffer memory 142 is transferred to the flash memory 111. .
- the controller 112D switches the selectors 141 and 144 again, and the data from the host 102 is transferred to the buffer memory 142. At the same time, the data in the buffer memory 143 is transferred to the flash memory 111. After this data transfer is completed, the sector is switched in the same way.
- the controller 112D receives the write data from the host 102 while switching the buffer memory 142 and the buffer memory 143 with the selectors 141 and 144 as appropriate, and transfers the write data to the flash memory 111.
- the time required for the host 102 to write 2 kB of data to the memory card 101D is 41 ⁇ 5 ⁇ + 5 + 200 using the above-described interface.
- the writing speed can be improved as compared with the conventional nonvolatile memory device.
- the power of using a volatile memory as the noffer memory is preferably a first-in first-out buffer memory (FIFO memory).
- the nonvolatile memory device of the present invention even when using a nonvolatile memory having a large unit capable of performing batch writing, the time required for transferring write data can be shortened and writing can be performed at high speed. Can do. It is useful as a memory card controller for memory cards for the field of high-speed writing in non-volatile memory devices that will increase in capacity in the future, for example, portable video cameras.
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JP2004302593A JP2008021335A (ja) | 2004-10-18 | 2004-10-18 | 不揮発性記憶装置、不揮発性記憶装置の書込み方法およびコントローラ |
JP2004-302593 | 2004-10-18 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008041098A (ja) * | 2006-08-04 | 2008-02-21 | Samsung Electronics Co Ltd | メモリーカード及び該データ格納方法 |
JP2008112335A (ja) * | 2006-10-31 | 2008-05-15 | Tdk Corp | メモリコントローラ及びメモリコントローラを備えるフラッシュメモリシステム、並びにフラッシュメモリの制御方法 |
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US9606730B2 (en) * | 2012-05-04 | 2017-03-28 | Samsung Electronics Co., Ltd. | System and method including three dimensional nonvolatile memory device and random access memory |
KR102291803B1 (ko) | 2015-04-07 | 2021-08-24 | 삼성전자주식회사 | 불휘발성 메모리 시스템의 동작 방법, 및 그것을 포함하는 사용자 시스템의 동작 방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0756804A (ja) * | 1993-08-18 | 1995-03-03 | Toshiba Emi Ltd | データ記録再生装置 |
JPH1083345A (ja) * | 1996-09-09 | 1998-03-31 | Fujitsu Ltd | フラッシュ・メモリのデータ更新装置 |
JP2002288034A (ja) * | 2001-03-23 | 2002-10-04 | Mitsubishi Electric Corp | 半導体記憶装置とその読出し・書き込み方法 |
JP2003085034A (ja) * | 2001-09-12 | 2003-03-20 | Hitachi Ltd | 不揮発性記憶装置およびデータ格納方法 |
JP2003233529A (ja) * | 2002-02-07 | 2003-08-22 | Hitachi Ltd | メモリシステム |
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- 2005-10-17 WO PCT/JP2005/019006 patent/WO2006043492A1/ja active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0756804A (ja) * | 1993-08-18 | 1995-03-03 | Toshiba Emi Ltd | データ記録再生装置 |
JPH1083345A (ja) * | 1996-09-09 | 1998-03-31 | Fujitsu Ltd | フラッシュ・メモリのデータ更新装置 |
JP2002288034A (ja) * | 2001-03-23 | 2002-10-04 | Mitsubishi Electric Corp | 半導体記憶装置とその読出し・書き込み方法 |
JP2003085034A (ja) * | 2001-09-12 | 2003-03-20 | Hitachi Ltd | 不揮発性記憶装置およびデータ格納方法 |
JP2003233529A (ja) * | 2002-02-07 | 2003-08-22 | Hitachi Ltd | メモリシステム |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008041098A (ja) * | 2006-08-04 | 2008-02-21 | Samsung Electronics Co Ltd | メモリーカード及び該データ格納方法 |
JP2008112335A (ja) * | 2006-10-31 | 2008-05-15 | Tdk Corp | メモリコントローラ及びメモリコントローラを備えるフラッシュメモリシステム、並びにフラッシュメモリの制御方法 |
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