WO2006043346A1 - 半導体装置製造方法 - Google Patents
半導体装置製造方法 Download PDFInfo
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- WO2006043346A1 WO2006043346A1 PCT/JP2005/003761 JP2005003761W WO2006043346A1 WO 2006043346 A1 WO2006043346 A1 WO 2006043346A1 JP 2005003761 W JP2005003761 W JP 2005003761W WO 2006043346 A1 WO2006043346 A1 WO 2006043346A1
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- Prior art keywords
- metal
- current
- semiconductor device
- sic
- manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 238000010438 heat treatment Methods 0.000 claims abstract description 27
- 238000004544 sputter deposition Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 11
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000001771 vacuum deposition Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 12
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 18
- 239000010936 titanium Substances 0.000 description 7
- 238000005259 measurement Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Definitions
- the present invention relates to a method for manufacturing a semiconductor device such as a Schottky diode or a MESFET (Metal Semiconductor Field Effect Transistor) having a Schottky junction in which a semiconductor (SiC) and a metal are joined.
- a semiconductor device such as a Schottky diode or a MESFET (Metal Semiconductor Field Effect Transistor) having a Schottky junction in which a semiconductor (SiC) and a metal are joined.
- the method of the present invention is not limited to the manufacture of a semiconductor device having a Schottky junction, but can be applied to the case where an ohmic electrode is bonded to SiC.
- a Schottky junction is a junction between a semiconductor and a metal, and a potential barrier is generated due to the difference between the work functions of the two, thereby moving the carriers to the semiconductor force metal in the forward direction.
- a voltage is applied, a current flows, and when a voltage is applied in a direction in which carriers move from metal to semiconductor (reverse direction), the current does not flow.
- a Schottky-junction semiconductor metal junction has a rectifying action and can be used as a diode (Schottky diode).
- a field effect transistor (MESFET) using the semiconductor as a channel and the metal as a gate electrode can be formed.
- SiC Schottky diode power using SiC as a semiconductor has attracted attention because of its heat resistance and pressure resistance.
- SiC Schottky diodes are currently used as discrete devices, but are expected to become the basic elements of highly integrated circuits in the future.
- SiC Schottky diodes have been manufactured by depositing metal on a SiC substrate using a sputtering method or a vacuum evaporation method.
- simply depositing metal on the SiC substrate has the problem that the height of the potential barrier (barrier height) and current-voltage characteristics vary from device to device. This is thought to be due to the fact that the bonding state of SiC and metal differs from device to device, and that the work functions of SiC and metal change sensitively.
- Noria Height Since the value of is determined according to the application of the Schottky diode, it must be avoided that it varies.
- Non-Patent Document 1 describes that after depositing Ti (titanium) on a SiC substrate by sputtering, annealing is performed at 500 ° C.
- Patent Document 1 describes the purpose of improving the heat resistance of a Schottky electrode (metal).
- a SiC substrate is heated to a high temperature of 500 to 800 ° C., and a metal is deposited on the substrate by a vapor deposition method.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2000-106444 ([0011]-[0021], [0032])
- Non-Patent Document 1 D. Defives et al., “Electrical properties of non-uniform Ti / 4H-SiC Schottky junctions”, Materials' Science 'and' Engineering, (Switzerland), 1999, B61-62 395-401 (D. Denves et al., "Electrical characterization of inhomogeneous Ti / 4H- SiC Schottky contacts, Materials science and Engineering, 1999, Vol. B61-62, pp. 395-401)
- the problem to be solved by the present invention is that it is a simple process, but it is possible to reduce the variation of each element in the Noria height and current-voltage characteristics, and to improve the current-voltage characteristics.
- An object of the present invention is to provide a method of manufacturing a semiconductor device using SiC capable of controlling the value of Noria height.
- a method for manufacturing a semiconductor device according to the present invention to solve the above-mentioned problems is characterized in that a metal is deposited on a substrate while heating the SiC substrate to a predetermined temperature of 400 ° C or lower. Let's say.
- Such semiconductor devices include Schottky diodes and MESFETs.
- the thickness of the metal layer is preferably 10 mm or more.
- the SiC substrate when a metal is deposited on a SiC substrate, the SiC substrate is heated to 400 ° C or lower, so that the resulting Schottky diode has a higher height, current voltage, and voltage than when the heating is not performed. Variations in characteristics between elements are reduced. In addition, the slope of the current-voltage characteristic curve becomes larger. The reason for this is not specified, but one possible reason is that, for example, the moisture adsorbed on the substrate surface evaporates due to the heating, thereby cleaning the interface between the SiC and the metal.
- the heating temperature and the varian and itite there is a correlation between the heating temperature and the varian and itite.
- the Noriano and the Ito become higher as the heating temperature is increased in the temperature range of 400 ° C or lower.
- the heating temperature for obtaining the desired variano andite can be obtained in advance by a simple preliminary experiment.
- the method according to the present invention is characterized in that the SiC substrate is heated to 400 ° C or lower when the metal is deposited, and thereby various effects as described above can be obtained. Therefore, after that Whether or not annealing is to be performed does not have any effect on these effects. If it is necessary to simplify the manufacturing process of a semiconductor device, the annealing should be omitted. If you need to further improve the characteristics, you can do annealing.
- the annealing temperature may be the same as the conventional method (100 ° C-500 ° C).
- the metal includes, for example, any one of Ti, Ni, Mo, Au, or a combination of two or more, or any one of these, one or more, and other A combination of these metals can be used.
- a Schottky junction can be obtained.
- the bonded metal can be used as a normal electrode, and metal-SiC can be obtained by lowering the barrier height by the method of the present invention. The contact resistance between / J, can be reduced.
- sputtering As a method for depositing the metal, sputtering, vacuum deposition, MBE (molecular beam epitaxy), resistance wire heating, EB (electron beam) deposition, or the like can be used.
- MBE molecular beam epitaxy
- resistance wire heating As a method for depositing the metal, it is desirable to increase the degree of vacuum, that is, reduce the pressure (for example, 10 Pa or less).
- the present invention it is possible to reduce the variation of each device in the Noria height and current-voltage characteristics of the obtained semiconductor device. This improves the yield when manufacturing the semiconductor device. In addition, the slope of the current-voltage characteristic curve becomes larger, and the rectification characteristics are improved.
- the barrier height can be controlled by adjusting the heating temperature, a semiconductor device having the barrier height required by the consumer can be manufactured in a custom-made manner.
- FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor device manufacturing method according to the present invention.
- FIG. 2 is a cross-sectional view showing another embodiment of a semiconductor device manufacturing method according to the present invention.
- FIG. 3 is a graph showing the forward current voltage characteristics of the Schottky diode (without annealing) obtained by this example.
- FIG. 4 is a graph showing the ideal factor and the near height of the Schottky diode (without annealing) obtained by this example.
- FIG. 5 is a graph showing the reverse current voltage characteristics of the Schottky diode (without annealing) obtained by this example.
- FIG. 6 is a graph showing the forward current voltage characteristics of the Schottky diode (with annealing) obtained by this example.
- FIG. 7 is a graph showing ideal factors and barrier heights of Schottky diodes (with and without annealing) obtained by this example.
- the surface of the SiC substrate 11 made of n-type 4H-S1C semiconductor that has been epitaxially grown is cleaned.
- the RCA method is first used for cleaning, and then the SiC substrate 11 is heated in oxygen gas to form the oxide film 12 on the surface (a-1).
- the SiC substrate 11 is heated in oxygen gas to form the oxide film 12 on the surface (a-1).
- an electrode ohmic electrode
- the Ni electrode layer 13 was used as the ohmic electrode.
- This Ni electrode layer 13 is obtained by depositing Ni on the surface of the SiC substrate 11 without heating the SiC substrate 11 by a resistance wire heating vapor deposition method (bl), and then annealing the substrate at 1000 ° C in Ar gas. (b-2).
- metal layer 14 is formed by depositing Ti on the surface of SiC substrate 11 (on the opposite side of Ni electrode layer 13) using DC sputtering.
- (cl) devices were fabricated at three heating temperatures of 100 ° C, 200 ° C and 400 ° C for the purpose of investigating changes in Schottky diode characteristics due to the heating temperature at this time. did.
- the SiC substrate 11 was heated at the same temperature as when the metal layer 14 was formed, the A1 electrode layer 15 was formed by depositing A1 on the surface of the metal layer 14 using DC sputtering (c-2 ).
- a Schottky diode 10 was obtained in which the SiC substrate (semiconductor layer) 11 and the metal layer 14 having repulsive force were joined and sandwiched between the Ni electrode layer 13 and the A1 electrode layer 15.
- a Schottky diode 10 obtained by the above method was further annealed.
- the Schottky diode 10 was annealed at 500 ° C. in Ar gas.
- Fig. 3 shows a device fabricated without annealing after forming the metal layer 14 by the method of Fig. 1 and applying a voltage so that electrons move from the semiconductor layer 11 to the metal layer 14.
- the forward current-voltage characteristics are shown.
- the vertical axis is the current, and is expressed in linear scale in (a) and logarithmic scale in (b).
- the heating temperature when forming the metal layer 14 is 100 ° C, 200 ° C, and 400 ° C, and as a comparative example, the semiconductor layer 11 is not heated when the metal layer 14 is formed (the temperature of the substrate). Shows an example of a room temperature (24 ° C) device.
- the devices with heating temperatures of 100 ° C and 200 ° C have a larger slope of the current-voltage curve in the voltage region where the current changes abruptly than the device of the comparative example. This means that the characteristics of the Schottky diode are improved by heating when the metal layer 14 is formed.
- the slope of the current-voltage curve of the device with a heating temperature of 400 ° C is slightly larger than that of the device of the comparative example.
- Fig. 4 shows the results of obtaining the nore height and the ideal factor for the forward current-voltage characteristic force using a thermionic model.
- the ideal factor is an index indicating how far the junction between the semiconductor and the metal is away from the ideal state. The closer to this value S1, the more the slope of the current-voltage curve in the voltage region where the current changes abruptly. Large, meaning that the joint is close to the ideal state.
- the measurement results for a plurality of elements are shown for each heating temperature, and the variation in characteristics for each element is shown.
- FIG. 4 shows that the element that heated the semiconductor layer 11 when forming the metal layer 14 was closer to the ideal factor force than the element that was not heated, that is, the junction was closer to the ideal state.
- Ma Noriano and Ito increase as the heating temperature increases. This indicates that the barrier height can be controlled by the heating temperature when the metal layer 14 is formed.
- the element that has been heated has a smaller ideality factor, and the variation power S of the Varian and Ito than the element that has not been heated. That is, by manufacturing a Schottky diode using the method of the present invention, variation in device quality is reduced and yield is improved. Small variation is also advantageous in controlling the barrier height value.
- Fig. 5 shows the reverse current-voltage characteristics (leakage current characteristics) when a voltage is applied in the direction opposite to that in the measurement of Fig. 3 for the element that was annealed after formation of the metal layer 14. The measurement results are shown.
- the element heated when forming the metal layer 14 has a leakage current force S1—two orders of magnitude smaller than the element not heated, and the diode rectification characteristics are good.
- FIG. 6 shows the results of forward voltage and current measurement performed on an element that was annealed at a temperature of 500 ° C. after the metal layer 14 was formed.
- the current on the vertical axis is expressed in linear scale in (a) and in logarithmic scale in (b).
- Figure 7 shows the results of performing forward voltage and current measurements for a number of devices obtained at the same heating temperature (100 ° C and 200 ° C), and determining the barrier height and ideal factor.
- This figure also shows the result of finding the nore height and ideal factor of the element that was not annealed (same as in Figure 4). From Fig. 7, it can be seen that the ideal factor ⁇ approaches, that is, the junction approaches the ideal state by performing the seal.
- annealing is getting higher by performing annealing. Therefore, it is desirable that annealing be performed when the device is manufactured with a high Norano and Ito.
- annealing can be omitted if the manufacturing process is to be simplified, and annealing is sometimes performed when the junction is brought closer to an ideal state.
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2004305334A JP2006120761A (ja) | 2004-10-20 | 2004-10-20 | 半導体装置製造方法 |
JP2004-305334 | 2004-10-20 |
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PCT/JP2005/003761 WO2006043346A1 (ja) | 2004-10-20 | 2005-03-04 | 半導体装置製造方法 |
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WO (1) | WO2006043346A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009094392A (ja) | 2007-10-11 | 2009-04-30 | Mitsubishi Electric Corp | 炭化珪素半導体装置の製造方法 |
JP2010068008A (ja) * | 2009-12-24 | 2010-03-25 | Mitsubishi Electric Corp | 炭化珪素ショットキバリアダイオードの製造方法 |
JP5598015B2 (ja) | 2010-02-23 | 2014-10-01 | 株式会社デンソー | ショットキーバリアダイオードを備えた炭化珪素半導体装置およびその製造方法 |
JP5455973B2 (ja) | 2011-05-27 | 2014-03-26 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
JP5966556B2 (ja) * | 2012-04-18 | 2016-08-10 | 富士電機株式会社 | 半導体デバイスの製造方法 |
JP2014053393A (ja) * | 2012-09-06 | 2014-03-20 | Sumitomo Electric Ind Ltd | ワイドギャップ半導体装置およびその製造方法 |
JP5738376B2 (ja) * | 2013-10-02 | 2015-06-24 | 三菱電機株式会社 | 炭化珪素ショットキバリアダイオードの製造方法 |
JP7505402B2 (ja) | 2020-12-25 | 2024-06-25 | 株式会社デンソー | 炭化珪素半導体ウェハおよび炭化珪素半導体装置の製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000101100A (ja) * | 1998-09-17 | 2000-04-07 | Toshiba Corp | 半導体装置 |
JP2000106444A (ja) * | 1998-07-31 | 2000-04-11 | Sanyo Electric Co Ltd | ショットキー電極、ショットキー電極の形成方法、半導体素子、及び半導体素子の製造方法 |
JP2002261295A (ja) * | 2001-03-05 | 2002-09-13 | Shikusuon:Kk | ショットキーダイオード、pn接合ダイオード、pin接合ダイオード、および製造方法 |
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2004
- 2004-10-20 JP JP2004305334A patent/JP2006120761A/ja active Pending
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- 2005-03-04 WO PCT/JP2005/003761 patent/WO2006043346A1/ja active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000106444A (ja) * | 1998-07-31 | 2000-04-11 | Sanyo Electric Co Ltd | ショットキー電極、ショットキー電極の形成方法、半導体素子、及び半導体素子の製造方法 |
JP2000101100A (ja) * | 1998-09-17 | 2000-04-07 | Toshiba Corp | 半導体装置 |
JP2002261295A (ja) * | 2001-03-05 | 2002-09-13 | Shikusuon:Kk | ショットキーダイオード、pn接合ダイオード、pin接合ダイオード、および製造方法 |
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