WO2006042519A1 - Verfahren zur herstellung von submikronstrukturen - Google Patents
Verfahren zur herstellung von submikronstrukturen Download PDFInfo
- Publication number
- WO2006042519A1 WO2006042519A1 PCT/DE2005/001852 DE2005001852W WO2006042519A1 WO 2006042519 A1 WO2006042519 A1 WO 2006042519A1 DE 2005001852 W DE2005001852 W DE 2005001852W WO 2006042519 A1 WO2006042519 A1 WO 2006042519A1
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- WIPO (PCT)
- Prior art keywords
- film
- substrate
- shadow mask
- mask
- energy
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 26
- 230000000873 masking effect Effects 0.000 claims abstract description 16
- 239000002245 particle Substances 0.000 claims description 6
- 238000005286 illumination Methods 0.000 claims description 2
- 239000006249 magnetic particle Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 description 28
- 239000002070 nanowire Substances 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 239000002086 nanomaterial Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 230000035508 accumulation Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 230000032798 delamination Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- 101100346656 Drosophila melanogaster strat gene Proteins 0.000 description 1
- 238000001015 X-ray lithography Methods 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 210000001520 comb Anatomy 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
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- 239000011224 oxide ceramic Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
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- 238000002360 preparation method Methods 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
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- 238000001338 self-assembly Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02603—Nanowires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
Definitions
- the invention relates to the production of submicron structures, in particular of electronic components with dimensions ranging from a few nanometers to a few micrometers, which have sub-micron subcomponents (for example electrodes).
- Such structures generally consist of a plurality of over- and / or juxtaposed accumulations of material on a substrate, the dimension of such accumulation being in at least one dimension in the submicron range, such as thin films, nanowires or quantum dots.
- the materials from which the individual aggregates are formed vary from elemental metals to semiconductors and metal oxide ceramics to organic compounds, e.g. functional or chemically stable polymers.
- Nanowires also: quantum wires
- Such wires offer the possibility of producing highly sensitive sensors, catalytically active surfaces or optically transparent electrical conductors.
- the article ADELUNG, R. et al. Nature Materials, Vol. 3, June 2004, p. 375-379 describes a relatively simple way of bringing a nanostructure, in particular a nanowire, onto a substrate, the latter following a microscopic preselection.
- the substrate is first wet-chemically coated or by vapor deposition, e.g. with a brittle oxide film or a polymer, and then cracks are selectively generated in this layer, which extend to the substrate.
- vapor deposition metal atoms are finally brought onto the substrate with the cracked film, wherein wire-shaped metal accumulations can form directly on the substrate only in the region of the cracks
- wire-shaped metal accumulations can form directly on the substrate only in the region of the cracks
- even more complex nanowire networks can be produced, eg a rectangular grid.
- the article presented method is also suitable for the simultaneous use of multiple materials, for example for the production of alloy wires made of elemental metals.
- the article presented method is also suitable for the simultaneous use of multiple materials, for example for the production of alloy wires made of elemental metals.
- one wishes to create two metal wires extending parallel to one another and electrically insulated from one another they will have a distance of several 100 nanometers from each other in accordance with the structuring possibilities limited to the microscale.
- US 4,525,919 provides a combination of epitaxial growth of the mask and selective etching to expose the substrate in a defined area. Such measures are complicated to control, time-consuming and thus hardly suitable for mass production.
- a masking material is now used in which cracks can easily be caused, which only weakly haf ⁇ tet on the substrate and tends especially to form a tensile stress on the mask surface. This is the case, for example, when the individual particles of the mask layer at the interface with the substrate are forced to assume a greater distance from each other than in the volume of the mask material. The mask layer then contracts with increasing layer thickness, preferably at the surface, if permitted. However, this has the consequence that, in the event of cracking down to the substrate, forces arise in the masking film, which promote the partial winding of the film in the immediate vicinity of a crack.
- a sufficiently thick film will detach from the crack and lift (delamination). This occurs at both opposite edges of the film along the crack, but remains limited to a near area around the crack, ie the film only rises locally.
- Both the extent of delamination and the crack width can be controlled via the material parameters of the thin film, such as the film thickness, interfacial adhesion and stress.
- a material can also be specifically influenced, for example by tempering or irradiation. Examples which may be mentioned are amorphous carbon or tem- pered photoresist (PMMA), which has become brittle.
- FIG. 1 shows a sketch of the shadow mask produced according to the invention for the production of nanostructures
- Fig. 2 shows the principle and a realized example of parallel nanowires (scanning electron micrograph);
- nanoscale field effect transisitors nanoscale field effect transisitors
- FIG. 5 illustrates an embodiment of the invention in which a) first the mask film is removed along defined lines and then b) a shadow mask analogous to FIG. 1 is created by cracking along the film curvature.
- a relatively narrow passage opening is formed at some distance from the substrate over a much wider, exposed substrate surface. It is a particular advantage of the method that the rolling-up masking film binds contaminants to the substrate surface in general and lifts them off.
- the "work surface" on which nanostructures are to be produced has to a certain extent the maximum cleanliness immediately after film detachment and has ideal dimensions in order to produce extremely sharp edge edges, since the mask is in the (sub) micrometer range above the Work surface is located.
- Reference numeral 10 designates the cavity for structuring, reference numeral 12 the delaminated thin film, 14 the substrate.
- the shadow mask formed by delamination allows the use of all known advantages of the shadow mask technique.
- different materials can be introduced at variable angles in order to produce mixed substances or those having gradients in the composition.
- the problem described above parallel, separated wires is treatable, as shown in FIG. 2.
- Two materials A and B are successively placed on the work surface under substantially different entry angles and, if necessary, leave a gap uncovered.
- the scanning electron micrograph shows a realization of two rather thick wires.
- the underlying masking layer is usually much thicker than, for example, the material layers A and B, which are formed during nanowire formation.
- the deposit can be additional
- Reference numeral 16 denotes metal A, 18 metal B (nanowires).
- control of the forces in the mask film is preferably to be designed in such a way that the force effect from the outside on the film can be controlled as desired and can take place without the additional input of material.
- a simple possibility lies in the addition of magnetic particles to the masking material, which can be aligned in the applied film by an external magnetic field. If the opposite edges of the cracked film are e.g. repel magnetically, the shadow mask is opened further.
- the mask material particles which exhibit high thermal expansion or shrinkage when energized or which exhibit a change in the extent of light emission e.g. the azobenzenes used in rewritable CDs. It may be expedient to arrange them in a masked manner and selectively in certain layers of the mask, in particular on the surface. If, for example, the mask surface expands under illumination in the first place, the opening width of the shadow mask decreases again.
- nano-FET nanoscale field-effect transistor
- FIG. 3 a shows substrate and masking film (here with crack and detachment) in side elevation and top view.
- FIG. The top view reveals that the film extends only over a middle region of the substrate; two substrate edges have been left free by covering when applying the mask.
- one of the previously left free substrate edges is covered with a temporary mask, and metal is projected at an angle through the shadow mask. ke brought to the substrate. The result is parallel, separate wires in the shadow space of the mask, each of which has electrical contact with one of the two metallized areas on the substrate edge. These contact surfaces act as leads to the nanowires, which can be bonded by conventional techniques.
- Fig. 3 d) and e) show the large-area deposition of a semiconductor material 20 and the removal of the mask layer.
- the substrate remains with the edge contacts, two nanowire metal electrodes ("source” and “drain”) and an intermediate semiconductor nanowire, as illustrated in FIG. 3 f).
- the nano-FET is completed in FIG. 3 g) by first placing an insulator layer 22 and finally a metal layer 24 (not a nanowire) across the nanowire array.
- the latter is the gate electrode, whose potential controls the charge carrier density in the semiconductor wire.
- FIG. 4 shows yet another interesting variant of the production of sub-micron structures with shadow masks.
- an ion beam By means of an ion beam, parts of the substrate are removed by sputtering, and trench-like structures are created.
- ion bombardment can take place at defined angles and for defined periods of time in order to precisely control the morphology of the trenches.
- the mask layer must be insensitive to the particle beam 26 (atoms, photons, electrons, etc.).
- the present invention remedy this by teaching to systematically promote and exploit an already existing effect - namely the crack formation and detachment of films, which are often regarded as disturbing.
- the order of these steps is immaterial to the result, as illustrated by FIG.
- the mask is applied to an initially heated substrate (eg, silicon, 150 ° C.) and then quenched (eg by liquid nitrogen vapor deposition), bulges form along the weakest points in the film, the film being simultaneously detached from the substrate (FIG 5 a)).
- a very brittle mask will already form cracks in the region of the smallest radii of curvature when the curvature is formed, that is to say on the curvature combs (FIG. 5 b)). Otherwise you can still convey the cracking even after the film detachment by additional tension.
- the course of the bulges can, in principle, just like the course of tear patterns, be controlled by pre-structuring the mask on the microscale (see ADELUNG, R. et al., Nature materials, Vol. 3, June 2004, pp. 375-379 for examples).
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Materials Engineering (AREA)
- Inorganic Chemistry (AREA)
- Physical Vapour Deposition (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/666,013 US7718349B2 (en) | 2004-10-22 | 2005-10-17 | Method for producing submicron structures |
EP05804015A EP1803148A1 (de) | 2004-10-22 | 2005-10-17 | Verfahren zur herstellung von submikronstrukturen |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004051662A DE102004051662B3 (de) | 2004-10-22 | 2004-10-22 | Verfahren zur Herstellung von Submikronstrukturen |
DE102004051662.6 | 2004-10-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006042519A1 true WO2006042519A1 (de) | 2006-04-27 |
Family
ID=35811536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2005/001852 WO2006042519A1 (de) | 2004-10-22 | 2005-10-17 | Verfahren zur herstellung von submikronstrukturen |
Country Status (4)
Country | Link |
---|---|
US (1) | US7718349B2 (de) |
EP (1) | EP1803148A1 (de) |
DE (1) | DE102004051662B3 (de) |
WO (1) | WO2006042519A1 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007059750A1 (de) * | 2005-11-28 | 2007-05-31 | Christian-Albrechts-Universität Zu Kiel | Verfahren zur erzeugung einer mehrzahl regelmässig angeordneter nanoverbindungen auf einem substrat |
EP3366639A1 (de) | 2017-02-28 | 2018-08-29 | Evonik Degussa GmbH | Verfahren zur herstellung strukturierter schichten |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7749784B2 (en) * | 2005-12-30 | 2010-07-06 | Ming-Nung Lin | Fabricating method of single electron transistor (SET) by employing nano-lithographical technology in the semiconductor process |
KR102421575B1 (ko) * | 2017-12-01 | 2022-07-18 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법 |
CN112047296B (zh) * | 2020-09-18 | 2022-07-29 | 南开大学 | 一种光控基底热膨胀实现双向原子开关的方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4525919A (en) * | 1982-06-16 | 1985-07-02 | Raytheon Company | Forming sub-micron electrodes by oblique deposition |
RU2094902C1 (ru) * | 1994-02-11 | 1997-10-27 | Институт физики полупроводников СО РАН | Способ изготовления субмикронных и нанометровых элементов твердотельных приборов |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6897009B2 (en) * | 1999-11-29 | 2005-05-24 | Trustees Of The University Of Pennsylvania | Fabrication of nanometer size gaps on an electrode |
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2004
- 2004-10-22 DE DE102004051662A patent/DE102004051662B3/de not_active Expired - Fee Related
-
2005
- 2005-10-17 US US11/666,013 patent/US7718349B2/en not_active Expired - Fee Related
- 2005-10-17 WO PCT/DE2005/001852 patent/WO2006042519A1/de active Application Filing
- 2005-10-17 EP EP05804015A patent/EP1803148A1/de not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4525919A (en) * | 1982-06-16 | 1985-07-02 | Raytheon Company | Forming sub-micron electrodes by oblique deposition |
RU2094902C1 (ru) * | 1994-02-11 | 1997-10-27 | Институт физики полупроводников СО РАН | Способ изготовления субмикронных и нанометровых элементов твердотельных приборов |
Non-Patent Citations (4)
Title |
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ADELUNG R ET AL: "Strain-controlled growth of nanowires within thin-film cracks", NATURE MATERIALS NATURE PUBLISHING GROUP UK, vol. 3, no. 6, June 2004 (2004-06-01), pages 375 - 379, XP002369949, ISSN: 1476-1122 * |
GOROKHOV E B ET AL: "STRESS GENERATION AND RELAXATION IN PASSIVATING FILMS AND ITS NEW APPLICATION IN NANOLITOGRAPHY", MATERIALS SCIENCE FORUM, AEDERMANNSFDORF, CH, vol. 185-188, 21 August 1994 (1994-08-21), pages 129 - 141, XP008024100, ISSN: 0255-5476 * |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2007059750A1 (de) * | 2005-11-28 | 2007-05-31 | Christian-Albrechts-Universität Zu Kiel | Verfahren zur erzeugung einer mehrzahl regelmässig angeordneter nanoverbindungen auf einem substrat |
EP3366639A1 (de) | 2017-02-28 | 2018-08-29 | Evonik Degussa GmbH | Verfahren zur herstellung strukturierter schichten |
WO2018158037A1 (de) | 2017-02-28 | 2018-09-07 | Evonik Degussa Gmbh | Verfahren zur herstellung strukturierter schichten |
Also Published As
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EP1803148A1 (de) | 2007-07-04 |
DE102004051662B3 (de) | 2006-04-20 |
US20080090181A1 (en) | 2008-04-17 |
US7718349B2 (en) | 2010-05-18 |
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