WO2006022024A1 - Processus de production de dispositif semi-conducteur - Google Patents

Processus de production de dispositif semi-conducteur Download PDF

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Publication number
WO2006022024A1
WO2006022024A1 PCT/JP2004/012450 JP2004012450W WO2006022024A1 WO 2006022024 A1 WO2006022024 A1 WO 2006022024A1 JP 2004012450 W JP2004012450 W JP 2004012450W WO 2006022024 A1 WO2006022024 A1 WO 2006022024A1
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WO
WIPO (PCT)
Prior art keywords
mold
die pad
resin
pad portion
semiconductor device
Prior art date
Application number
PCT/JP2004/012450
Other languages
English (en)
Japanese (ja)
Inventor
Masakazu Sakano
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2004/012450 priority Critical patent/WO2006022024A1/fr
Publication of WO2006022024A1 publication Critical patent/WO2006022024A1/fr

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
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Definitions

  • the present invention relates to a semiconductor device manufacturing technique, and in particular, an external connection terminal is disposed on a mounting surface of a mold resin for sealing a semiconductor chip, and a die pad is formed on the other surface of the mold resin.
  • the present invention relates to a technique that is effective when applied to the manufacture of a semiconductor device having a package structure with exposed portions.
  • the QFN forms external connection terminals by exposing a part of each of the multiple leads that are electrically connected to the semiconductor chip via bonding wires from the bottom surface (mounting surface) of the mold resin. It is a package that is mounted by soldering the terminals to the electrodes (foot prints) on the wiring board. Such a package structure is advantageous for high-density mounting because the mounting area can be reduced compared to QFP (Quad Flat Package), etc., in which the lead constituting the external connection terminal is pulled out from the side of the mold resin. It is. Disclosure of the invention
  • a semiconductor chip is mounted on the die pad part of the lead frame, the semiconductor chip and the lead are connected by a wire, and then the lead frame is attached to the mold Then, the semiconductor chip is sealed with resin, and then unnecessary portions of the lead frame exposed to the outside of the mold resin are cut and removed.
  • the mold is composed of an upper mold and a lower mold, and usually the surface of the mold exposed in the cavity is subjected to a satin finish.
  • the satin finish is a process of forming a large number of fine irregularities on the surface of the mold by physical treatment or chemical treatment, and thereby forming minute irregularities on the surface of the mold resin.
  • the surface of the mold resin that seals the semiconductor chip is made into a satin finish.
  • resin packages such as QFN and QFP seal the semiconductor chip with an organic resin with low thermal conductivity, so the heat generated from the semiconductor chip is difficult to dissipate to the outside.
  • a resin package that seals a semiconductor chip that generates a large amount of heat such as a semiconductor chip on which a high-frequency circuit is formed
  • the thermal resistance of the package is reduced by exposing the die pad part to the surface of the mold resin. It is being reduced.
  • the force QFN has an external connection terminal on the bottom surface of the mold resin. Therefore, when the die pad part is exposed to the outside from the bottom surface (mounting surface) of the mold resin, the force QFN is placed in a region facing the die pad part on the surface of the wiring board. Wiring cannot be arranged, and wiring layout design becomes difficult, especially on high-density mounting wiring boards.
  • Q F N it is required to improve the mounting density of the wiring board and improve the heat dissipation of the package by exposing the die pad portion from the upper surface of the mold tree.
  • a QFN To manufacture a QFN with the die pad exposed from the top surface of the mold resin, first mount the semiconductor chip on the die pad of the lead frame, and then wire the bonding pad of the semiconductor chip and the lead of the lead frame. Then, connect the lead frame to the mode die. Then, a thin resin sheet is laid on the surface of the lower mold, and the lead frame is placed on the resin sheet. At this time, the lead frame is arranged with the one surface (main surface) opposite to the one side (main surface) of the die pad portion on which the semiconductor chip is mounted facing upward, and the lead is brought into contact with the resin sheet.
  • the upper mold and the lower mold are separated so that the back surface (upper surface) of the die pad portion is the upper surface of the mold resin.
  • the lead that has bite into the resin sheet is exposed to the outside from the bottom surface of the mold resin.
  • a thin resin sheet is laid on both surfaces of the upper mold and the lower mold, and a resin sheet is interposed between the die pad and the upper mold.
  • a resin sheet is interposed between the die pad and the upper mold.
  • the upper die is provided with a gate runner that supplies molten resin and an air vent that exhausts excess air inside the body.
  • the upper mold has a more complicated structure than the lower mold, and if a resin sheet is laid on the upper mold, the resin sheet may be twisted.
  • the molding method that spreads the resin sheet on both the upper and lower molds not only complicates the mold structure but also increases the cost of the resin sheet. There are disadvantages to invite.
  • An object of the present invention is to manufacture a semiconductor device having a package structure in which external connection terminals are arranged on the lower surface (mounting surface) of a mold resin for sealing a semiconductor chip, and the die pad portion is exposed on the upper surface of the mold resin. At the same time, it is an object of the present invention to provide a technique capable of reducing the amount of resin barrier adhering to the surface of the die pad portion.
  • Another object of the present invention is to provide a technique capable of reducing the manufacturing time of a semiconductor device.
  • Another object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor device.
  • the present invention includes a die pad portion, a semiconductor chip mounted on one surface of the die pad portion, a plurality of leads arranged to surround the die pad portion, and each of the plurality of leads.
  • a plurality of wires that are electrically connected to the semiconductor chip are sealed with a mold resin,
  • a part of each of the plurality of leads is exposed from the mounting surface of the monored resin, thereby forming a plurality of external connection terminals,
  • each of the plurality of leads formed on the lead frame and the semiconductor chip are connected with wires. Electrically connecting, and
  • step (c) After the step (b), the lead frame is attached to a mold composed of an upper mold and a lower mold, and the other surface of the die pad portion is brought into contact with the surface of the upper mold. Contacting a part of each of the plurality of leads with a resin sheet laid on the lower mold;
  • FIG. 1 is a plan view showing the upper surface of Q F N according to one embodiment of the present invention.
  • FIG. 2 is a plan view showing the lower surface of Q F N according to one embodiment of the present invention.
  • Fig. 3 is a cross-sectional view of Q F N along the line AA in Fig. 1.
  • FIG. 4 is a side view of a QFN according to an embodiment of the present invention.
  • FIG. 5 is a plan view of a lead frame used for manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 6 is a plan view of a lead frame showing a method of manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 7 is a fragmentary cross-sectional view of a lead frame showing a method of manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 8 is a plan view of a lead frame showing a method of manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 9 is a cross-sectional view of the main part of the lead frame showing the method of manufacturing QFN according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view of a principal part of a mold showing a method for manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 11 is a cross-sectional view of a principal part of a mold showing a method for manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 12 is a sectional view of an essential part of a mold showing a method for producing QFN according to another embodiment of the present invention.
  • FIG. 13 is a cross-sectional view of a principal part of a mold showing a method for producing QFN according to another embodiment of the present invention.
  • FIG. 14 is a cross-sectional view of a principal part of a mold showing a method for producing QFN according to another embodiment of the present invention.
  • FIG. 15 is a cross-sectional view of the QFN formed by the mold shown in FIG.
  • FIG. 16 is a cross-sectional view of the QFN formed by the mold shown in FIG.
  • FIG. 17 is a cross-sectional view of a QFN formed by the mold shown in FIG.
  • FIG. 18 is a cross-sectional view of QFN, which is another embodiment of the present invention.
  • FIG. 19 is a cross-sectional view of a principal part of a mold showing a method for producing QFN according to another embodiment of the present invention.
  • FIG. 1 and 2 are plan views of the Q F N according to the present embodiment.
  • FIG. 1 shows the upper surface side
  • FIG. 2 shows the lower surface (mounting surface) side.
  • Fig. 3 is a cross-sectional view along line AA in Fig. 1, and
  • Fig. 4 is a side view of this Q F N.
  • Q F N (1 A) of the present embodiment is a surface mount type resin package in which one semiconductor chip (hereinafter simply referred to as a chip) 2 is sealed with a mold resin 3.
  • Chip 2 is mounted (adhered) on one side of metal die pad part 4 (chip mounting part, tab) and placed at the center of mold resin 3.
  • the back side of chip 2 and the die pad part The surface of 4 is bonded by an adhesive 7.
  • a plurality of bonding pads 8 are formed on the periphery of the main surface of the chip 2 (the surface on which the integrated circuit is formed).
  • the die pad portion 4 is formed integrally with the die pad portion 4 and supported by four suspension leads 5 extending in the direction of the corner portion of the mold resin 3.
  • the shape of the die pad portion 4 shown in the figure is a quadrangle, but other shapes (for example, a circle) may be used. Further, the size of the die pad portion 4 may be smaller than the size of the chip 2.
  • each lead 6 (the end closer to the chip 2) and the bonding pad 8 on the main surface of the chip 2 are electrically connected via an Au wire 9.
  • the other end of each lead 6 is exposed to the outside from the bottom surface (mounting surface) force of the mold resin 3 and constitutes an external connection terminal of Q F N (1 A).
  • P d (palladium) plating is applied to the surfaces of the lead 6, the suspension lead 5 and the die pad portion 4.
  • the feature of the QFN (1 A) of this embodiment is that the other surface (back surface) opposite to the one surface (main surface) of the die pad 4 on which the chip 2 is mounted is exposed from the upper surface of the mold resin 3 to the outside. It is at an exposed point.
  • the external connection terminal (lead 6) is arranged on the lower surface of the mold resin 3 in the QFN (1 A). For this reason, if the back surface of the die pad part 4 is exposed to the outside from the lower surface (mounting surface) force of the mold resin 3, it becomes impossible to place wiring in a region facing the die pad part 4 on the surface of the wiring board. Wiring layout design is difficult for a high density mounting wiring board. Therefore, the QFN (1 A) of the present embodiment exposes the die pad portion 4 from the upper surface of the mold resin 3 to improve the mounting density of the wiring board and reduce the thermal resistance of the package.
  • the top surface (the surface where the die pad portion 4 is exposed) and the side surface of the mold resin 3 are not subjected to a matte finish, and are flat. It is in the point. Mold resin 3 having such a flat surface is molded using a mold whose surface is mirror-finished.
  • pear finish means that many fine irregularities are formed on the surface of molds by physical treatment (sand blasting, shot blasting, electric discharge machining, laser irradiation, etc.) or chemical treatment (etching, etc.) This process is also called squirrel processing.
  • the size of the unevenness (depth of recess or height of protrusion) formed by the satin finish is such that marks such as letters and symbols can be printed on the surface of the mold resin 3 using ink. Size, usually 10 m ⁇ l
  • mirror finishing generally means that the surface of a mold or the like is not subjected to the above-mentioned matte finish and is finished to a flat surface without unevenness. In this embodiment, This includes the case of forming extremely fine irregularities of less than 1.0 ⁇ .
  • the process of molding the mold resin 3 using a mold that has undergone mirror finishing will be described later.
  • a mark 10 indicating the manufacturer, product number, mouth number, etc. is stamped on the periphery of the upper surface of the mold resin 3.
  • there are two methods for forming marks on the surface of a resin package a printing method using an ink and a laser marking method.
  • the QFN (1 A) of this embodiment has a flat top surface of the mold resin 3. Therefore, in the printing method, the adhesion between the mold tree 3 and the ink is poor. Therefore, the mark 10 above is a laser marker that can be engraved on a flat surface. Engraved by the King method.
  • FIG. 5 is a plan view of a lead frame used for manufacturing the above Q F N (1 A).
  • the lead frame 11 is made of a metal plate made of Cu, Cu alloy or Fe-Ni alloy or the like with a thickness of about 1 2 5 / zm to 200 ⁇ m. Patterns such as lead 5 and lead 6 are repeatedly formed. That is, the lead frame 11 has a multiple structure in which a plurality of (for example, three) chips 2 can be mounted.
  • the lead frame 11 1 is formed by punching a metal plate with a press or etching to form a pattern such as a die pad portion 4, a suspended lead 5, a lead 6, and the like, and then P on the entire surface of these patterns. Manufactured by applying d-stick. When Pd plating is applied to the entire surface of the lead frame 11, the process of selectively applying the plating to the surface of the lead 6 and the surface of the die pad portion 4 is not necessary.
  • FIG. 10 is a cross-sectional view showing a part of the mold 20 (an area corresponding to about one Q F N).
  • This mold 20 is composed of an upper mold 2 OA and a lower mold 20 B, and the surface of the upper mold 2 OA exposed in the cavity 21 is mirror-finished. .
  • a thin resin sheet 22 is laid on the surface of the lower mold 20 B, and the resin sheet 22 is placed on the resin sheet 22.
  • the lead frame 11 1 is arranged with the back surface of the die pad 4 (the surface opposite to the surface on which the chip 2 is mounted) facing upward, and the lead 6 is brought into contact with the resin sheet 22.
  • the lead 6 and the resin sheet 2 2 are sandwiched between the upper mold 2 OA and the lower mold 20 B, and the back surface (upper surface) of the die pad 4 is brought into contact with the surface of the upper mold 2 OA.
  • the lead 6 is bitten into the resin sheet 22 by the pressing force of the upper mold 2 OA and the lower mold 20 B.
  • the upper mold 2 OA surface is The surface of the upper mold 2 OA and the die pad portion 4 are in intimate contact with each other because the surface is not flat.
  • the back surface (upper surface) of the die pad portion 4 is exposed to the outside from the upper surface of the monored resin 3, and the lead 6 that has digged into the resin sheet 22. Is exposed to the outside from the bottom surface of the mold resin 3.
  • the lead 6 is formed so as to protrude from the mold lumber 3 because it digs into the lunar month sheet 22 laid on the surface of the lower mold 20 B.
  • the upper mold 2 OA and the die pad part 4 are in intimate contact with each other, so that the molten resin injected into the cavity 21 is the surface of the upper mold 2 OA and the die pad part. It is difficult to enter the gap with 4. Therefore, the amount of resin burrs adhering to the back surface (upper surface) of the die pad portion 4 exposed from the mold resin 3 is reduced.
  • the lead frame 11 taken out from the mold 20 is transported to a water jet type deburring device, and foreign matter is removed by spraying high pressure water onto the surface of the mold resin 3. .
  • the resin burrs adhering to the surface of the die pad portion 4 exposed from the upper surface of the mold resin 3 are also removed at the same time.
  • the manufacturing method of the present embodiment since only a small amount of resin burr adheres to the surface of the die pad portion 4, even if a resin burr occurs, the resin can be promptly ejected by high-pressure water injection. Deburring can be removed, eliminating the need for deburring by electrolysis. Therefore, the deterioration of the lead 6 exposed to the outside of the monored resin 3 and the Pd plating applied to the surface of the die pad portion 4 are also reduced.
  • the cleaning process in this embodiment is also performed to improve the appearance of the resin package.
  • the QFN (1 A) of the present embodiment shown in FIGS. 1 to 4 is completed through a testing process and an appearance inspection process.
  • the entire surface of the upper mold 2 OA exposed in the cavity 21 is mirror-finished.
  • the entire surface of the upper mold 2 OA exposed in the cavity 21 is mirror-finished.
  • the surfaces of the upper mold 20 A Only the area that contacts the back surface (upper surface) of the die pad part 4 may be mirror-finished and the other areas may be textured.
  • the molten resin injected into the cavity 21 is difficult to enter the gap between the upper mold 2 OA and the die pad part 4, the resin burrs adhering to the surface of the die pad part 4 exposed from the mold resin 3 can be prevented. The amount of can be reduced.
  • the Q F N (1 A) molded by the upper mold 2 O A has a structure in which the surface of the mold resin 3 where the die pad portion 4 is exposed is subjected to a matte finish.
  • the mark 10 can be engraved by either the laser marking method or the printing method.
  • the degree of freedom in the marking process is improved.
  • the side surface of the mold resin 3 is also satin, so when the lead frame 11 that has completed the molding process is taken out from the mold 20 force, the mold resin 3 and the upper mold 20 A Release property is improved.
  • the upper die 20 A shown in FIG. 13 is mirror-finished only in the area that contacts the back surface (upper surface) of the die pad 4, as with the upper die 20 A shown in FIG.
  • the area that contacts the back surface of the die pad part 4 protrudes more inside the cavity 21 than the other areas, and the upper die near the outer periphery of the die pad part 4 2 A step is formed on the surface of OA.
  • the cross-sectional view of QFN (1 A) molded with such an upper mold 2 OA is shown in FIG. 16, and the mirror resin is applied to the surface of the mold resin 3 where the die pad portion 4 is exposed. Further, the structure has a step at the periphery of the die pad portion 4.
  • the surface of the upper mold 2 O A shown in FIG. 14 is obtained by applying a mirror finish to the area in contact with the upper surface of the mold resin 3 and applying a matte finish to the area in contact with the side surface of the mold resin 3.
  • the molten resin injected into the cavity 21 is difficult to enter the gap between the upper mold 2 OA and the die pad part 4, the resin burrs adhering to the surface of the die pad part 4 exposed from the mold resin 3 can be prevented. The amount of can be reduced.
  • the mark 10 is engraved by a laser one marking method.
  • the side surface of the mold resin 3 is satin, the releasability between the mold tree 3 and the upper mold 2 O A is improved.
  • the step as shown in FIG. 13 on the surface of the upper mold 20 A shown in FIG. 14, the amount of resin burr generated on the surface of the die pad portion 4 can be further reduced. Can do.
  • the cross-sectional view of QFN (1 A) molded by such an upper mold 2 OA is mirror-finished on the surface of the mold resin 3 where the die pad portion 4 is exposed.
  • the side is structured with satin finish.
  • the QFN structure in which the area of the die pad portion 4 is larger than the area of the chip 2 has been described.
  • the area of the die pad portion 4 is smaller than the area of the chip 2
  • the present invention may be applied.
  • the possibility that the resin burr covers the entire surface of the die pad part 4 as described above is when the area of the die pad part 4 is larger than the area of the chip 2. Compared to higher. If the entire surface of the die pad 4 is covered with resin burrs, it will be difficult to remove the resin burrs even if the deburring process is performed. . However, by molding the mold resin 3 using the mold 20 as in the first and second embodiments, it is possible to suppress the resin burrs from adhering to the back surface (upper surface) of the die pad portion 4.
  • the present invention may be applied to the case of using a collective mold mold that cuts the resin and the lead frame 11 and separates the QFN (1 A).
  • the present invention may be applied to a lead-frame type lead frame in which A 1 is formed on Cu.

Abstract

Un QFN (1A) possède une structure telle que la surface arrière d'un tampon de matrice (4), sur lequel est fixé une puce (2), est exposée à l'extérieur de la surface supérieure d'une résine de moulage (3). Cette résine de moulage (3) est munie de surfaces supérieure et latérale n’ayant pas été soumises à une finition mate. La résine de moulage (3), disposant de ces surfaces plates, est moulée à l'aide d'une matrice (20), disposant d'une matrice supérieure (20A), dont les surfaces exposées à une cavité (21) bénéficient d’une finition en miroir.
PCT/JP2004/012450 2004-08-24 2004-08-24 Processus de production de dispositif semi-conducteur WO2006022024A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2004/012450 WO2006022024A1 (fr) 2004-08-24 2004-08-24 Processus de production de dispositif semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2004/012450 WO2006022024A1 (fr) 2004-08-24 2004-08-24 Processus de production de dispositif semi-conducteur

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WO2006022024A1 true WO2006022024A1 (fr) 2006-03-02

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000236060A (ja) * 1999-02-16 2000-08-29 Matsushita Electronics Industry Corp 半導体装置
JP2002134676A (ja) * 2000-09-15 2002-05-10 Samsung Techwin Co Ltd リードフレーム及びそれを備えた半導体パッケージ、並びにその半導体パッケージの製造方法
JP2003243600A (ja) * 2001-12-14 2003-08-29 Hitachi Ltd 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000236060A (ja) * 1999-02-16 2000-08-29 Matsushita Electronics Industry Corp 半導体装置
JP2002134676A (ja) * 2000-09-15 2002-05-10 Samsung Techwin Co Ltd リードフレーム及びそれを備えた半導体パッケージ、並びにその半導体パッケージの製造方法
JP2003243600A (ja) * 2001-12-14 2003-08-29 Hitachi Ltd 半導体装置およびその製造方法

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