WO2006022024A1 - Process for producing semiconductor device - Google Patents

Process for producing semiconductor device Download PDF

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Publication number
WO2006022024A1
WO2006022024A1 PCT/JP2004/012450 JP2004012450W WO2006022024A1 WO 2006022024 A1 WO2006022024 A1 WO 2006022024A1 JP 2004012450 W JP2004012450 W JP 2004012450W WO 2006022024 A1 WO2006022024 A1 WO 2006022024A1
Authority
WO
WIPO (PCT)
Prior art keywords
mold
die pad
resin
pad portion
semiconductor device
Prior art date
Application number
PCT/JP2004/012450
Other languages
French (fr)
Japanese (ja)
Inventor
Masakazu Sakano
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2004/012450 priority Critical patent/WO2006022024A1/en
Publication of WO2006022024A1 publication Critical patent/WO2006022024A1/en

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Definitions

  • the present invention relates to a semiconductor device manufacturing technique, and in particular, an external connection terminal is disposed on a mounting surface of a mold resin for sealing a semiconductor chip, and a die pad is formed on the other surface of the mold resin.
  • the present invention relates to a technique that is effective when applied to the manufacture of a semiconductor device having a package structure with exposed portions.
  • the QFN forms external connection terminals by exposing a part of each of the multiple leads that are electrically connected to the semiconductor chip via bonding wires from the bottom surface (mounting surface) of the mold resin. It is a package that is mounted by soldering the terminals to the electrodes (foot prints) on the wiring board. Such a package structure is advantageous for high-density mounting because the mounting area can be reduced compared to QFP (Quad Flat Package), etc., in which the lead constituting the external connection terminal is pulled out from the side of the mold resin. It is. Disclosure of the invention
  • a semiconductor chip is mounted on the die pad part of the lead frame, the semiconductor chip and the lead are connected by a wire, and then the lead frame is attached to the mold Then, the semiconductor chip is sealed with resin, and then unnecessary portions of the lead frame exposed to the outside of the mold resin are cut and removed.
  • the mold is composed of an upper mold and a lower mold, and usually the surface of the mold exposed in the cavity is subjected to a satin finish.
  • the satin finish is a process of forming a large number of fine irregularities on the surface of the mold by physical treatment or chemical treatment, and thereby forming minute irregularities on the surface of the mold resin.
  • the surface of the mold resin that seals the semiconductor chip is made into a satin finish.
  • resin packages such as QFN and QFP seal the semiconductor chip with an organic resin with low thermal conductivity, so the heat generated from the semiconductor chip is difficult to dissipate to the outside.
  • a resin package that seals a semiconductor chip that generates a large amount of heat such as a semiconductor chip on which a high-frequency circuit is formed
  • the thermal resistance of the package is reduced by exposing the die pad part to the surface of the mold resin. It is being reduced.
  • the force QFN has an external connection terminal on the bottom surface of the mold resin. Therefore, when the die pad part is exposed to the outside from the bottom surface (mounting surface) of the mold resin, the force QFN is placed in a region facing the die pad part on the surface of the wiring board. Wiring cannot be arranged, and wiring layout design becomes difficult, especially on high-density mounting wiring boards.
  • Q F N it is required to improve the mounting density of the wiring board and improve the heat dissipation of the package by exposing the die pad portion from the upper surface of the mold tree.
  • a QFN To manufacture a QFN with the die pad exposed from the top surface of the mold resin, first mount the semiconductor chip on the die pad of the lead frame, and then wire the bonding pad of the semiconductor chip and the lead of the lead frame. Then, connect the lead frame to the mode die. Then, a thin resin sheet is laid on the surface of the lower mold, and the lead frame is placed on the resin sheet. At this time, the lead frame is arranged with the one surface (main surface) opposite to the one side (main surface) of the die pad portion on which the semiconductor chip is mounted facing upward, and the lead is brought into contact with the resin sheet.
  • the upper mold and the lower mold are separated so that the back surface (upper surface) of the die pad portion is the upper surface of the mold resin.
  • the lead that has bite into the resin sheet is exposed to the outside from the bottom surface of the mold resin.
  • a thin resin sheet is laid on both surfaces of the upper mold and the lower mold, and a resin sheet is interposed between the die pad and the upper mold.
  • a resin sheet is interposed between the die pad and the upper mold.
  • the upper die is provided with a gate runner that supplies molten resin and an air vent that exhausts excess air inside the body.
  • the upper mold has a more complicated structure than the lower mold, and if a resin sheet is laid on the upper mold, the resin sheet may be twisted.
  • the molding method that spreads the resin sheet on both the upper and lower molds not only complicates the mold structure but also increases the cost of the resin sheet. There are disadvantages to invite.
  • An object of the present invention is to manufacture a semiconductor device having a package structure in which external connection terminals are arranged on the lower surface (mounting surface) of a mold resin for sealing a semiconductor chip, and the die pad portion is exposed on the upper surface of the mold resin. At the same time, it is an object of the present invention to provide a technique capable of reducing the amount of resin barrier adhering to the surface of the die pad portion.
  • Another object of the present invention is to provide a technique capable of reducing the manufacturing time of a semiconductor device.
  • Another object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor device.
  • the present invention includes a die pad portion, a semiconductor chip mounted on one surface of the die pad portion, a plurality of leads arranged to surround the die pad portion, and each of the plurality of leads.
  • a plurality of wires that are electrically connected to the semiconductor chip are sealed with a mold resin,
  • a part of each of the plurality of leads is exposed from the mounting surface of the monored resin, thereby forming a plurality of external connection terminals,
  • each of the plurality of leads formed on the lead frame and the semiconductor chip are connected with wires. Electrically connecting, and
  • step (c) After the step (b), the lead frame is attached to a mold composed of an upper mold and a lower mold, and the other surface of the die pad portion is brought into contact with the surface of the upper mold. Contacting a part of each of the plurality of leads with a resin sheet laid on the lower mold;
  • FIG. 1 is a plan view showing the upper surface of Q F N according to one embodiment of the present invention.
  • FIG. 2 is a plan view showing the lower surface of Q F N according to one embodiment of the present invention.
  • Fig. 3 is a cross-sectional view of Q F N along the line AA in Fig. 1.
  • FIG. 4 is a side view of a QFN according to an embodiment of the present invention.
  • FIG. 5 is a plan view of a lead frame used for manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 6 is a plan view of a lead frame showing a method of manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 7 is a fragmentary cross-sectional view of a lead frame showing a method of manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 8 is a plan view of a lead frame showing a method of manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 9 is a cross-sectional view of the main part of the lead frame showing the method of manufacturing QFN according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view of a principal part of a mold showing a method for manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 11 is a cross-sectional view of a principal part of a mold showing a method for manufacturing a QFN according to an embodiment of the present invention.
  • FIG. 12 is a sectional view of an essential part of a mold showing a method for producing QFN according to another embodiment of the present invention.
  • FIG. 13 is a cross-sectional view of a principal part of a mold showing a method for producing QFN according to another embodiment of the present invention.
  • FIG. 14 is a cross-sectional view of a principal part of a mold showing a method for producing QFN according to another embodiment of the present invention.
  • FIG. 15 is a cross-sectional view of the QFN formed by the mold shown in FIG.
  • FIG. 16 is a cross-sectional view of the QFN formed by the mold shown in FIG.
  • FIG. 17 is a cross-sectional view of a QFN formed by the mold shown in FIG.
  • FIG. 18 is a cross-sectional view of QFN, which is another embodiment of the present invention.
  • FIG. 19 is a cross-sectional view of a principal part of a mold showing a method for producing QFN according to another embodiment of the present invention.
  • FIG. 1 and 2 are plan views of the Q F N according to the present embodiment.
  • FIG. 1 shows the upper surface side
  • FIG. 2 shows the lower surface (mounting surface) side.
  • Fig. 3 is a cross-sectional view along line AA in Fig. 1, and
  • Fig. 4 is a side view of this Q F N.
  • Q F N (1 A) of the present embodiment is a surface mount type resin package in which one semiconductor chip (hereinafter simply referred to as a chip) 2 is sealed with a mold resin 3.
  • Chip 2 is mounted (adhered) on one side of metal die pad part 4 (chip mounting part, tab) and placed at the center of mold resin 3.
  • the back side of chip 2 and the die pad part The surface of 4 is bonded by an adhesive 7.
  • a plurality of bonding pads 8 are formed on the periphery of the main surface of the chip 2 (the surface on which the integrated circuit is formed).
  • the die pad portion 4 is formed integrally with the die pad portion 4 and supported by four suspension leads 5 extending in the direction of the corner portion of the mold resin 3.
  • the shape of the die pad portion 4 shown in the figure is a quadrangle, but other shapes (for example, a circle) may be used. Further, the size of the die pad portion 4 may be smaller than the size of the chip 2.
  • each lead 6 (the end closer to the chip 2) and the bonding pad 8 on the main surface of the chip 2 are electrically connected via an Au wire 9.
  • the other end of each lead 6 is exposed to the outside from the bottom surface (mounting surface) force of the mold resin 3 and constitutes an external connection terminal of Q F N (1 A).
  • P d (palladium) plating is applied to the surfaces of the lead 6, the suspension lead 5 and the die pad portion 4.
  • the feature of the QFN (1 A) of this embodiment is that the other surface (back surface) opposite to the one surface (main surface) of the die pad 4 on which the chip 2 is mounted is exposed from the upper surface of the mold resin 3 to the outside. It is at an exposed point.
  • the external connection terminal (lead 6) is arranged on the lower surface of the mold resin 3 in the QFN (1 A). For this reason, if the back surface of the die pad part 4 is exposed to the outside from the lower surface (mounting surface) force of the mold resin 3, it becomes impossible to place wiring in a region facing the die pad part 4 on the surface of the wiring board. Wiring layout design is difficult for a high density mounting wiring board. Therefore, the QFN (1 A) of the present embodiment exposes the die pad portion 4 from the upper surface of the mold resin 3 to improve the mounting density of the wiring board and reduce the thermal resistance of the package.
  • the top surface (the surface where the die pad portion 4 is exposed) and the side surface of the mold resin 3 are not subjected to a matte finish, and are flat. It is in the point. Mold resin 3 having such a flat surface is molded using a mold whose surface is mirror-finished.
  • pear finish means that many fine irregularities are formed on the surface of molds by physical treatment (sand blasting, shot blasting, electric discharge machining, laser irradiation, etc.) or chemical treatment (etching, etc.) This process is also called squirrel processing.
  • the size of the unevenness (depth of recess or height of protrusion) formed by the satin finish is such that marks such as letters and symbols can be printed on the surface of the mold resin 3 using ink. Size, usually 10 m ⁇ l
  • mirror finishing generally means that the surface of a mold or the like is not subjected to the above-mentioned matte finish and is finished to a flat surface without unevenness. In this embodiment, This includes the case of forming extremely fine irregularities of less than 1.0 ⁇ .
  • the process of molding the mold resin 3 using a mold that has undergone mirror finishing will be described later.
  • a mark 10 indicating the manufacturer, product number, mouth number, etc. is stamped on the periphery of the upper surface of the mold resin 3.
  • there are two methods for forming marks on the surface of a resin package a printing method using an ink and a laser marking method.
  • the QFN (1 A) of this embodiment has a flat top surface of the mold resin 3. Therefore, in the printing method, the adhesion between the mold tree 3 and the ink is poor. Therefore, the mark 10 above is a laser marker that can be engraved on a flat surface. Engraved by the King method.
  • FIG. 5 is a plan view of a lead frame used for manufacturing the above Q F N (1 A).
  • the lead frame 11 is made of a metal plate made of Cu, Cu alloy or Fe-Ni alloy or the like with a thickness of about 1 2 5 / zm to 200 ⁇ m. Patterns such as lead 5 and lead 6 are repeatedly formed. That is, the lead frame 11 has a multiple structure in which a plurality of (for example, three) chips 2 can be mounted.
  • the lead frame 11 1 is formed by punching a metal plate with a press or etching to form a pattern such as a die pad portion 4, a suspended lead 5, a lead 6, and the like, and then P on the entire surface of these patterns. Manufactured by applying d-stick. When Pd plating is applied to the entire surface of the lead frame 11, the process of selectively applying the plating to the surface of the lead 6 and the surface of the die pad portion 4 is not necessary.
  • FIG. 10 is a cross-sectional view showing a part of the mold 20 (an area corresponding to about one Q F N).
  • This mold 20 is composed of an upper mold 2 OA and a lower mold 20 B, and the surface of the upper mold 2 OA exposed in the cavity 21 is mirror-finished. .
  • a thin resin sheet 22 is laid on the surface of the lower mold 20 B, and the resin sheet 22 is placed on the resin sheet 22.
  • the lead frame 11 1 is arranged with the back surface of the die pad 4 (the surface opposite to the surface on which the chip 2 is mounted) facing upward, and the lead 6 is brought into contact with the resin sheet 22.
  • the lead 6 and the resin sheet 2 2 are sandwiched between the upper mold 2 OA and the lower mold 20 B, and the back surface (upper surface) of the die pad 4 is brought into contact with the surface of the upper mold 2 OA.
  • the lead 6 is bitten into the resin sheet 22 by the pressing force of the upper mold 2 OA and the lower mold 20 B.
  • the upper mold 2 OA surface is The surface of the upper mold 2 OA and the die pad portion 4 are in intimate contact with each other because the surface is not flat.
  • the back surface (upper surface) of the die pad portion 4 is exposed to the outside from the upper surface of the monored resin 3, and the lead 6 that has digged into the resin sheet 22. Is exposed to the outside from the bottom surface of the mold resin 3.
  • the lead 6 is formed so as to protrude from the mold lumber 3 because it digs into the lunar month sheet 22 laid on the surface of the lower mold 20 B.
  • the upper mold 2 OA and the die pad part 4 are in intimate contact with each other, so that the molten resin injected into the cavity 21 is the surface of the upper mold 2 OA and the die pad part. It is difficult to enter the gap with 4. Therefore, the amount of resin burrs adhering to the back surface (upper surface) of the die pad portion 4 exposed from the mold resin 3 is reduced.
  • the lead frame 11 taken out from the mold 20 is transported to a water jet type deburring device, and foreign matter is removed by spraying high pressure water onto the surface of the mold resin 3. .
  • the resin burrs adhering to the surface of the die pad portion 4 exposed from the upper surface of the mold resin 3 are also removed at the same time.
  • the manufacturing method of the present embodiment since only a small amount of resin burr adheres to the surface of the die pad portion 4, even if a resin burr occurs, the resin can be promptly ejected by high-pressure water injection. Deburring can be removed, eliminating the need for deburring by electrolysis. Therefore, the deterioration of the lead 6 exposed to the outside of the monored resin 3 and the Pd plating applied to the surface of the die pad portion 4 are also reduced.
  • the cleaning process in this embodiment is also performed to improve the appearance of the resin package.
  • the QFN (1 A) of the present embodiment shown in FIGS. 1 to 4 is completed through a testing process and an appearance inspection process.
  • the entire surface of the upper mold 2 OA exposed in the cavity 21 is mirror-finished.
  • the entire surface of the upper mold 2 OA exposed in the cavity 21 is mirror-finished.
  • the surfaces of the upper mold 20 A Only the area that contacts the back surface (upper surface) of the die pad part 4 may be mirror-finished and the other areas may be textured.
  • the molten resin injected into the cavity 21 is difficult to enter the gap between the upper mold 2 OA and the die pad part 4, the resin burrs adhering to the surface of the die pad part 4 exposed from the mold resin 3 can be prevented. The amount of can be reduced.
  • the Q F N (1 A) molded by the upper mold 2 O A has a structure in which the surface of the mold resin 3 where the die pad portion 4 is exposed is subjected to a matte finish.
  • the mark 10 can be engraved by either the laser marking method or the printing method.
  • the degree of freedom in the marking process is improved.
  • the side surface of the mold resin 3 is also satin, so when the lead frame 11 that has completed the molding process is taken out from the mold 20 force, the mold resin 3 and the upper mold 20 A Release property is improved.
  • the upper die 20 A shown in FIG. 13 is mirror-finished only in the area that contacts the back surface (upper surface) of the die pad 4, as with the upper die 20 A shown in FIG.
  • the area that contacts the back surface of the die pad part 4 protrudes more inside the cavity 21 than the other areas, and the upper die near the outer periphery of the die pad part 4 2 A step is formed on the surface of OA.
  • the cross-sectional view of QFN (1 A) molded with such an upper mold 2 OA is shown in FIG. 16, and the mirror resin is applied to the surface of the mold resin 3 where the die pad portion 4 is exposed. Further, the structure has a step at the periphery of the die pad portion 4.
  • the surface of the upper mold 2 O A shown in FIG. 14 is obtained by applying a mirror finish to the area in contact with the upper surface of the mold resin 3 and applying a matte finish to the area in contact with the side surface of the mold resin 3.
  • the molten resin injected into the cavity 21 is difficult to enter the gap between the upper mold 2 OA and the die pad part 4, the resin burrs adhering to the surface of the die pad part 4 exposed from the mold resin 3 can be prevented. The amount of can be reduced.
  • the mark 10 is engraved by a laser one marking method.
  • the side surface of the mold resin 3 is satin, the releasability between the mold tree 3 and the upper mold 2 O A is improved.
  • the step as shown in FIG. 13 on the surface of the upper mold 20 A shown in FIG. 14, the amount of resin burr generated on the surface of the die pad portion 4 can be further reduced. Can do.
  • the cross-sectional view of QFN (1 A) molded by such an upper mold 2 OA is mirror-finished on the surface of the mold resin 3 where the die pad portion 4 is exposed.
  • the side is structured with satin finish.
  • the QFN structure in which the area of the die pad portion 4 is larger than the area of the chip 2 has been described.
  • the area of the die pad portion 4 is smaller than the area of the chip 2
  • the present invention may be applied.
  • the possibility that the resin burr covers the entire surface of the die pad part 4 as described above is when the area of the die pad part 4 is larger than the area of the chip 2. Compared to higher. If the entire surface of the die pad 4 is covered with resin burrs, it will be difficult to remove the resin burrs even if the deburring process is performed. . However, by molding the mold resin 3 using the mold 20 as in the first and second embodiments, it is possible to suppress the resin burrs from adhering to the back surface (upper surface) of the die pad portion 4.
  • the present invention may be applied to the case of using a collective mold mold that cuts the resin and the lead frame 11 and separates the QFN (1 A).
  • the present invention may be applied to a lead-frame type lead frame in which A 1 is formed on Cu.

Abstract

A QFN (1A) has such a structure that the rear surface of a die pad part (4) on which a chip (2) is mounted is exposed to the outside from the upper surface of a mold resin (3). The mold resin (3) has flat upper and side surfaces which have not been subjected to mat finish. The mold resin (3) having such flat surfaces is molded using a die (20) having an upper die (20A) whose surface exposed to a cavity (21) is mirror-finished.

Description

半導体装置の製造方法 技術分野 Manufacturing method of semiconductor device
本発明は、 半導体装置の製造技術に関し、 特に、 半導体チップを封止するモー ルド樹脂の実装面に外部接続端子を配置し、 モールド樹脂の他の面にダイパッ ド 明  The present invention relates to a semiconductor device manufacturing technique, and in particular, an external connection terminal is disposed on a mounting surface of a mold resin for sealing a semiconductor chip, and a die pad is formed on the other surface of the mold resin.
部を露出させたパッケージ構造を有する半導体装置の製造に適用して有効な技 術に関するものである。 田 The present invention relates to a technique that is effective when applied to the manufacture of a semiconductor device having a package structure with exposed portions. Rice field
背景技術 Background art
リードフレームに搭載された半導体チップをモールド樹脂からなる封止体によ つて封止した樹脂パッケージの一種に QFN(Quad Flat Non-leaded package)が ある （例えば特開 200 1— 1 8941 0号公報、 特許第 307229 1号公報 など)。  One type of resin package in which a semiconductor chip mounted on a lead frame is sealed with a sealing body made of mold resin is QFN (Quad Flat Non-leaded package) (for example, JP-A-2001-189410). Patent No. 307229 1).
上記 QFNは、 ボンディングワイヤを介して半導体チップと電気的に接続され た複数のリードのそれぞれの一部をモールド樹脂の下面 （実装面） から露出させ て外部接続端子を構成し、 これらの外部接続端子を配線基板の電極 （フッ トプリ ント） に半田付けすることによって実装されるパッケージである。 このようなパ ッケージ構造は、 外部接続端子を構成するリ一ドをモールド樹脂の側面から外側 に引き出した QF P (Quad Flat Package)などに比べて実装面積を小さくできる ので、 高密度実装に有利である。 発明の開示  The QFN forms external connection terminals by exposing a part of each of the multiple leads that are electrically connected to the semiconductor chip via bonding wires from the bottom surface (mounting surface) of the mold resin. It is a package that is mounted by soldering the terminals to the electrodes (foot prints) on the wiring board. Such a package structure is advantageous for high-density mounting because the mounting area can be reduced compared to QFP (Quad Flat Package), etc., in which the lead constituting the external connection terminal is pulled out from the side of the mold resin. It is. Disclosure of the invention
一般に、 Q FNや QFPなどの樹脂パッケージを製造するには、 リードフレー ムのダイパッド部上に半導体チップを実装し、 半導体チップとリードとをワイヤ で接続した後、 リードフレームをモールド金型に装着して半導体チップを樹脂封 止し、 その後、 モールド樹脂の外部に露出したリードフレームの不要部分を切断 、 除去する。 上記モールド金型は、 上金型と下金型とで構成され、 通常、 キヤビティ内に露 出した金型の表面には、 梨地加工が施される。 梨地加工とは、 物理的処理や化学 的処理によって、 金型の表面に多数の微細な凹凸を形成する処理であり、 これに よって、 モールド樹脂の表面に微細な凹凸を形成する。 In general, to manufacture resin packages such as QFN and QFP, a semiconductor chip is mounted on the die pad part of the lead frame, the semiconductor chip and the lead are connected by a wire, and then the lead frame is attached to the mold Then, the semiconductor chip is sealed with resin, and then unnecessary portions of the lead frame exposed to the outside of the mold resin are cut and removed. The mold is composed of an upper mold and a lower mold, and usually the surface of the mold exposed in the cavity is subjected to a satin finish. The satin finish is a process of forming a large number of fine irregularities on the surface of the mold by physical treatment or chemical treatment, and thereby forming minute irregularities on the surface of the mold resin.
半導体チップを封止するモールド樹脂の表面を梨地にするのは、  The surface of the mold resin that seals the semiconductor chip is made into a satin finish.
( a ) モールド樹脂の表面に、 製造者、 品番、 ロット番号などを示すインクマー クを刻印する際、 インクの密着性を向上させる。  (a) Improve ink adhesion when marking the ink mark indicating the manufacturer, product number, lot number, etc. on the surface of the mold resin.
( b ) 金型の表面の微細な傷などがモールド樹脂の表面に転写され難くする。 (b) It makes it difficult to transfer fine scratches on the mold surface to the surface of the mold resin.
( c ) モールド樹脂の外観に高級感を付与する、 などの理由からである。 (c) This is because the appearance of the mold resin is given a high-class feeling.
また、 Q F Nや Q F Pなどの樹脂パッケージは、 熱伝導性の小さい有機樹脂に よつて半導体チップを封止するので、 半導体チップから発生した熱が外部に放散 され難い。 その対策として、 高周波回路が形成された半導体チップのように、 発 熱量の大きい半導体チップを封止する樹脂パッケージの場合は、 モールド樹脂の 表面にダイパッド部を露出させることによって、 パッケージの熱抵抗を低減する ことが行われている。  In addition, resin packages such as QFN and QFP seal the semiconductor chip with an organic resin with low thermal conductivity, so the heat generated from the semiconductor chip is difficult to dissipate to the outside. As a countermeasure, in the case of a resin package that seals a semiconductor chip that generates a large amount of heat, such as a semiconductor chip on which a high-frequency circuit is formed, the thermal resistance of the package is reduced by exposing the die pad part to the surface of the mold resin. It is being reduced.
モールド樹脂の表面にダイパッド部を露出させる方式には、 モールド樹脂の下 面 （実装面） から露出させる方式と、 上面 （実装面とは反対側の面） から露出さ せる方式とがある。 ところ力 Q F Nは、 モールド樹脂の下面に外部接続端子が 配置されるため、 ダイパッド部をモールド樹脂の下面 （実装面） から外部に露出 させた場合、 配線基板の表面のダイパッド部と対向する領域に配線を配置するこ とができなくなり、 特に高密度実装用配線基板においては、 配線のレイアウト設 計が困難になる。  There are two methods to expose the die pad on the surface of the mold resin: one from the lower surface (mounting surface) of the mold resin and the other from the upper surface (surface opposite to the mounting surface). However, the force QFN has an external connection terminal on the bottom surface of the mold resin. Therefore, when the die pad part is exposed to the outside from the bottom surface (mounting surface) of the mold resin, the force QFN is placed in a region facing the die pad part on the surface of the wiring board. Wiring cannot be arranged, and wiring layout design becomes difficult, especially on high-density mounting wiring boards.
従って、 Q F Nの場合は、 モールド樹月旨の上面からダイパッ ド部を露出させる ことによって、 配線基板の実装密度を向上させると共に、 パッケージの放熱性を 向上させることが要求される。  Therefore, in the case of Q F N, it is required to improve the mounting density of the wiring board and improve the heat dissipation of the package by exposing the die pad portion from the upper surface of the mold tree.
モールド樹脂の上面からダイパッド部を露出させた Q F Nを製造するには、 ま ず、 リードフレームのダイパッド部上に半導体チップを実装した後、 半導体チッ プのボンディングパッドと、 リードフレームのリードとをワイヤで結線し、 次に 、 このリードフレームをモード金型に装着する。 そして、 下金型の表面に薄い樹脂シートを敷き、 この樹脂シートの上にリード フレームを載置する。 このとき、 リードフレームは、 半導体チップが実装された ダイパッド部の一面 （主面） と反対側の他面 （裏面） を上に向けて配置し、 リー ドを樹脂シートに接触させる。 そしてこの状態で、 リードと樹脂シートとを上金 型と下金型とで挟み付けると、 ダイパッド部の裏面 （上面） が上金型の表面に接 触すると共に、 上金型と下金型との押圧力によってリードが樹脂シー卜の中に食 レ、込む。 To manufacture a QFN with the die pad exposed from the top surface of the mold resin, first mount the semiconductor chip on the die pad of the lead frame, and then wire the bonding pad of the semiconductor chip and the lead of the lead frame. Then, connect the lead frame to the mode die. Then, a thin resin sheet is laid on the surface of the lower mold, and the lead frame is placed on the resin sheet. At this time, the lead frame is arranged with the one surface (main surface) opposite to the one side (main surface) of the die pad portion on which the semiconductor chip is mounted facing upward, and the lead is brought into contact with the resin sheet. In this state, when the lead and the resin sheet are sandwiched between the upper mold and the lower mold, the back surface (upper surface) of the die pad part contacts the surface of the upper mold, and the upper mold and the lower mold The lead is bitten into the resin sheet by the pressing force.
次に、 この状態でキヤビティ内に溶融樹脂を注入してモールド樹脂を成形した 後、 上金型と下金型とを分離することにより、 ダイパッド部の裏面 （上面） がモ 一ルド樹脂の上面から外部に露出すると共に、 樹脂シートの中に食い込んでいた リ一ドがモールド樹脂の下面から外部に露出する。  Next, after the molten resin is injected into the cavity in this state to mold the mold resin, the upper mold and the lower mold are separated so that the back surface (upper surface) of the die pad portion is the upper surface of the mold resin. The lead that has bite into the resin sheet is exposed to the outside from the bottom surface of the mold resin.
リードは樹月旨シートに隙間なく食い込むため、 リードと樹月旨シー卜との間に樹 脂が入り込むことがないことから、 モールド樹脂の下面 （実装面） から露出させ 形成される外部接続端子の表面に樹脂が付着することがない。  Since the lead bites into the woody effect sheet without any gaps, resin does not enter between the lead and the woody effect sheet, so the external connection terminals that are formed by exposing from the bottom surface (mounting surface) of the mold resin The resin does not adhere to the surface.
ところが、 上記した成形工程では、 リードフレームを金型に装着してダイパッ ド部の裏面 （上面） を上金型の表面に接触させた時、 梨地加工による上金型の表 面の微細な凹凸に起因してダイパッド部と上金型との間に微細な隙間が生じる。 そのため、 キヤビティ内に溶融樹脂を注入すると、 溶融樹脂がこの隙間に入り込 む結果、 リードフレームを金型から取り出した際に、 モールド樹脂から露出した ダイパッド部の表面にレジンフラッシュと呼ばれる樹脂パリが大量に付着して しまうこと力 本発明者の検討によって明らかになった。  However, in the molding process described above, when the lead frame is mounted on the mold and the back surface (upper surface) of the die pad is brought into contact with the surface of the upper mold, fine irregularities on the surface of the upper mold by matte processing Due to this, a fine gap is generated between the die pad portion and the upper mold. Therefore, when molten resin is injected into the cavity, the molten resin enters this gap. As a result, when the lead frame is removed from the mold, a resin Paris called a resin flash is formed on the surface of the die pad exposed from the mold resin. The ability to adhere in large quantities was clarified by the study of the present inventors.
一般に、 成形工程で発生するこの種の樹脂バリを除去するパリ取り（deflash) 方法としては、 モ一ルド樹脂の表面に高圧水を噴射するウォータージエツト方式 が用いられる。 また、 樹脂バリの量が多いとき、 あるいは樹脂バリがウォーター ジェット方式だけでは除去することが困難な場合には、 ウォータージェットの前 処理として、 モールド樹脂を薬液に浸漬する電解方式が併用される。  In general, as a deflash method for removing this type of resin burr generated in the molding process, a water jet method in which high-pressure water is sprayed onto the surface of the mold resin is used. In addition, when the amount of resin burrs is large, or when resin burrs are difficult to remove by the water jet method alone, an electrolysis method in which the mold resin is immersed in a chemical solution is used as a pretreatment for the water jet.
し力 し、 ダイパッド部の表面に樹脂パリが大量に付着した場合は、 ノ リ取りに 多くの時間が掛かってしまう。 特に、 Q F Nのような小型のパッケージの場合は 、 ダイパッド部の表面全体が樹脂バリで覆われてしまうので、 上記したバリ取り 方法では除去が困難である。 また、 ダイパッド部に半導体チップを実装する工程 に先立ってリードフレームの表面全体に P d (パラジウム） などのメツキを施し ておく、 いわゆる先付けメツキ方式のリードフレームに上記のようなバリ取り方 法を適用すると、 モールド樹脂の外部に露出したリードやダイパッド部の表面の メツキがダメージを受け、 半田メツキの濡れ性が低下するという問題も生じる。 さらに、 ダイパッド部の表面に付着した樹脂バリの一部がリ一ドフレームの搬送 中に剥離して異物の原因となる場合もある。 However, if a large amount of resin paris adheres to the surface of the die pad part, it takes a lot of time to remove the glue. In particular, in the case of a small package such as QFN, the entire surface of the die pad part is covered with resin burrs. This method is difficult to remove. Also, prior to the process of mounting the semiconductor chip on the die pad part, the surface of the lead frame is subjected to plating such as Pd (palladium). If applied, the lead exposed to the outside of the mold resin and the surface of the die pad will be damaged, and the wettability of the solder will deteriorate. In addition, some of the resin burrs adhering to the surface of the die pad part may be peeled off during transport of the lead frame, causing foreign matter.
ダイパッド部の表面に樹脂バリが付着するのを防ぐ方法として、 例えば上金型 と下金型の両面に薄い樹脂シートを敷き、 ダイパッド部と上金型との間に樹脂シ ートを介在させる方法もある。 このようにすると、 ダイパッド部が樹脂シートの 中に食い込むので、 ダイパッド部と樹脂シートとの間に溶融樹脂が入り込むこと はない。  As a method for preventing resin burrs from adhering to the surface of the die pad, for example, a thin resin sheet is laid on both surfaces of the upper mold and the lower mold, and a resin sheet is interposed between the die pad and the upper mold. There is also a method. If it does in this way, since a die pad part bites into a resin sheet, molten resin does not enter between a die pad part and a resin sheet.
し力 し、 上金型には溶融樹脂を供給するゲートランナーやキヤビディ内の余分 な空気を排気するためのエアベント等が設けられている。 そのため、 上金型は下 金型に比べ複雑な構造のため、 上金型に樹脂シートを敷くと、 その樹脂シートが よれてしまう可能性がある。 上金型と下金型の両面に樹脂シ一トを敷く成形方法 は、 金型の構造が複雑ィヒするのみならず、 樹脂シートのコスト増加をもたらすの で、 Q F Nの製造コストの増加を招く不利益がある。  On the other hand, the upper die is provided with a gate runner that supplies molten resin and an air vent that exhausts excess air inside the body. For this reason, the upper mold has a more complicated structure than the lower mold, and if a resin sheet is laid on the upper mold, the resin sheet may be twisted. The molding method that spreads the resin sheet on both the upper and lower molds not only complicates the mold structure but also increases the cost of the resin sheet. There are disadvantages to invite.
本発明の目的は、 半導体チップを封止するモールド樹脂の下面 （実装面） に外 部接続端子を配置し、 モールド樹脂の上面にダイパッド部を露出させたパッケ一 ジ構造を有する半導体装置の製造に際し、 ダイパッド部の表面に付着する樹脂バ リの量を低減することのできる技術を提供することにある。  An object of the present invention is to manufacture a semiconductor device having a package structure in which external connection terminals are arranged on the lower surface (mounting surface) of a mold resin for sealing a semiconductor chip, and the die pad portion is exposed on the upper surface of the mold resin. At the same time, it is an object of the present invention to provide a technique capable of reducing the amount of resin barrier adhering to the surface of the die pad portion.
また、 本発明の他の目的は、 半導体装置の製造時間を低減することのできる技 術を提供することにある。  Another object of the present invention is to provide a technique capable of reducing the manufacturing time of a semiconductor device.
また、 本発明の他の目的は、 半導体装置の製造コストを安価にすることのでき る技術を提供することにある。  Another object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor device.
本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記述および添 付図面から明らかになるであろう。  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、 代表的なものの概要を簡単に説明すれば 、 次のとおりである。 Of the inventions disclosed in this application, a brief summary of typical ones will be given. , It is as follows.
本発明は、 ダイパッド部と、 前記ダイパッド部の一面に実装された半導体チッ プと、 前記ダイパッド部の周囲を囲むように配置された複数本のリードと、 前記 複数本のリ一ドのそれぞれと前記半導体チップとを電気的に接続する複数本の ワイヤとがモールド樹脂によって封止され、  The present invention includes a die pad portion, a semiconductor chip mounted on one surface of the die pad portion, a plurality of leads arranged to surround the die pad portion, and each of the plurality of leads. A plurality of wires that are electrically connected to the semiconductor chip are sealed with a mold resin,
前記複数本のリ一ドのそれぞれの一部が、 前記モーノレド樹脂の実装面から露出 されることによって、 複数の外部接続端子が構成され、  A part of each of the plurality of leads is exposed from the mounting surface of the monored resin, thereby forming a plurality of external connection terminals,
前記ダイパッド部の一面と反対側の他面が、 前記モールド樹脂の前記実装面と は反対側の面から露出されたパッケージ構造を有する半導体装置の製造方法で あって、  A method of manufacturing a semiconductor device having a package structure in which the other surface opposite to the one surface of the die pad part is exposed from the surface opposite to the mounting surface of the mold resin,
( a ) 前記ダイパッド部と前記複数本のリードとが形成されたリードフレームを 用意する工程と、  (a) preparing a lead frame in which the die pad portion and the plurality of leads are formed;
( b ) 前記リードフレームに形成された前記ダイパッド部の一面に、 前記半導体 チップを実装した後、 前記リードフレームに形成された前記複数本のリードのそ れぞれと前記半導体チップとをワイヤで電気的に接続する工程と、  (b) After mounting the semiconductor chip on one surface of the die pad portion formed on the lead frame, each of the plurality of leads formed on the lead frame and the semiconductor chip are connected with wires. Electrically connecting, and
( c ) 前記工程 （b ) の後、 上金型と下金型とからなる金型に前記リードフレー ムを装着し、 前記ダイパッド部の他面を前記上金型の表面に接触させると共に、 前記複数本のリードのそれぞれの一部を、 前記下金型の上に敷かれた樹脂シート に接触させる工程と、  (c) After the step (b), the lead frame is attached to a mold composed of an upper mold and a lower mold, and the other surface of the die pad portion is brought into contact with the surface of the upper mold. Contacting a part of each of the plurality of leads with a resin sheet laid on the lower mold;
( d ) 前記工程 （c ) の後、 前記金型のキヤビティ内に溶融樹脂を供給すること によって、 前記モールド樹月旨を成形する工程とを有し、  (d) after the step (c), by supplying molten resin into the mold cavity, forming the mold tree effect,
前記キヤビティ内に露出した前記上金型の表面全体が鏡面処理されているもの である。 図面の簡単な説明  The entire surface of the upper mold exposed in the cavity is mirror-finished. Brief Description of Drawings
図 1は、 本発明の一実施の形態である Q F Nの上面を示す平面図である。 図 2は、 本発明の一実施の形態である Q F Nの下面を示す平面図である。 図 3は、 図 1の A— A線に沿った Q F Nの断面図である。  FIG. 1 is a plan view showing the upper surface of Q F N according to one embodiment of the present invention. FIG. 2 is a plan view showing the lower surface of Q F N according to one embodiment of the present invention. Fig. 3 is a cross-sectional view of Q F N along the line AA in Fig. 1.
図 4は、 本発明の一実施の形態である Q F Nの側面図である。 図 5は、 本発明の一実施の形態である Q FNの製造に用いるリードフレームの 平面図である。 FIG. 4 is a side view of a QFN according to an embodiment of the present invention. FIG. 5 is a plan view of a lead frame used for manufacturing a QFN according to an embodiment of the present invention.
図 6は、 本発明の一実施の形態である Q FNの製造方法を示すリードフレーム の平面図である。  FIG. 6 is a plan view of a lead frame showing a method of manufacturing a QFN according to an embodiment of the present invention.
図 7は、 本発明の一実施の形態である Q FNの製造方法を示すリードフレーム の要部断面図である。  FIG. 7 is a fragmentary cross-sectional view of a lead frame showing a method of manufacturing a QFN according to an embodiment of the present invention.
図 8は、 本発明の一実施の形態である Q FNの製造方法を示すリードフレーム の平面図である。  FIG. 8 is a plan view of a lead frame showing a method of manufacturing a QFN according to an embodiment of the present invention.
図 9は、 本発明の一実施の形態である Q FNの製造方法を示すリードフレーム の要部断面図である。  FIG. 9 is a cross-sectional view of the main part of the lead frame showing the method of manufacturing QFN according to one embodiment of the present invention.
図 1 0は、 本発明の一実施の形態である Q FNの製造方法を示す金型の要部断 面図である。  FIG. 10 is a cross-sectional view of a principal part of a mold showing a method for manufacturing a QFN according to an embodiment of the present invention.
図 1 1は、 本発明の一実施の形態である Q FNの製造方法を示す金型の要部断 面図である。  FIG. 11 is a cross-sectional view of a principal part of a mold showing a method for manufacturing a QFN according to an embodiment of the present invention.
図 1 2は、 本発明の他の実施の形態である Q FNの製造方法を示す金型の要部 断面図である。  FIG. 12 is a sectional view of an essential part of a mold showing a method for producing QFN according to another embodiment of the present invention.
図 1 3は、 本発明の他の実施の形態である Q FNの製造方法を示す金型の要部 断面図である。  FIG. 13 is a cross-sectional view of a principal part of a mold showing a method for producing QFN according to another embodiment of the present invention.
図 1 4は、 本発明の他の実施の形態である Q FNの製造方法を示す金型の要部 断面図である。  FIG. 14 is a cross-sectional view of a principal part of a mold showing a method for producing QFN according to another embodiment of the present invention.
図 1 5は、 図 1 2に示す金型により成形された Q FNの断面図である。  FIG. 15 is a cross-sectional view of the QFN formed by the mold shown in FIG.
図 1 6は、 図 1 3に示す金型により成形された Q FNの断面図である。  FIG. 16 is a cross-sectional view of the QFN formed by the mold shown in FIG.
図 1 7は、 図 1 4に示す金型により成形された QFNの断面図である。  FIG. 17 is a cross-sectional view of a QFN formed by the mold shown in FIG.
図 1 8は、 本発明の他の実施の形態である Q FNの断面図である。  FIG. 18 is a cross-sectional view of QFN, which is another embodiment of the present invention.
図 1 9は、 本発明の他の実施の形態である Q FNの製造方法を示す金型の要部 断面図である。 発明を実施するための最良の形態  FIG. 19 is a cross-sectional view of a principal part of a mold showing a method for producing QFN according to another embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施の形態を図面に基づいて詳細に説明する。 なお、 実施の形 態を説明するための全図において、 同一の機能を有するものには同一の符号を付 し、 その繰り返しの説明は省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The form of implementation In all the drawings for explaining the state, the same reference numerals are given to those having the same function, and repeated explanation thereof is omitted.
(実施の形態 1 )  (Embodiment 1)
図 1および図 2は、 本実施の形態の Q F Nの平面図であり、 図 1は上面側、 図 2は下面 （実装面） 側をそれぞれ示している。 また、 図 3は、 図 1の A— A線に 沿った断面図、 図 4は、 この Q F Nの側面図である。  1 and 2 are plan views of the Q F N according to the present embodiment. FIG. 1 shows the upper surface side, and FIG. 2 shows the lower surface (mounting surface) side. Fig. 3 is a cross-sectional view along line AA in Fig. 1, and Fig. 4 is a side view of this Q F N.
本実施の形態の Q F N ( 1 A) は、 1個の半導体チップ （以下、 単にチップと いう） 2をモールド樹脂 3で封止した表面実装型の樹脂パッケージである。 チッ プ 2は、 金属製のダイパッド部 4 (チップ搭載部、 タブ） の一面に実装 （接着） された状態でモールド樹脂 3の中央部に配置されており、 .チップ 2の裏面とダイ パッド部 4の表面とは、 接着剤 7によって接着されている。 チップ 2の主面 （集 積回路が形成された面） の周辺部には、 複数のボンディングパッド 8が形成され ている。 図 1〜図 4には示さないが、 ダイパッド部 4は、 これと一体に形成され 、 モールド樹脂 3のコーナー部方向に延在する 4本の吊りリード 5によって支持 されている。 なお、 図に示すダイパッド部 4の形状は四角形であるが、 それ以外 の形状 （例えば円形） であってもよい。 また、 ダイパッド部 4のサイズは、 チッ プ 2のサイズより小さくてもよい。  Q F N (1 A) of the present embodiment is a surface mount type resin package in which one semiconductor chip (hereinafter simply referred to as a chip) 2 is sealed with a mold resin 3. Chip 2 is mounted (adhered) on one side of metal die pad part 4 (chip mounting part, tab) and placed at the center of mold resin 3. The back side of chip 2 and the die pad part The surface of 4 is bonded by an adhesive 7. A plurality of bonding pads 8 are formed on the periphery of the main surface of the chip 2 (the surface on which the integrated circuit is formed). Although not shown in FIGS. 1 to 4, the die pad portion 4 is formed integrally with the die pad portion 4 and supported by four suspension leads 5 extending in the direction of the corner portion of the mold resin 3. The shape of the die pad portion 4 shown in the figure is a quadrangle, but other shapes (for example, a circle) may be used. Further, the size of the die pad portion 4 may be smaller than the size of the chip 2.
チップ 2が実装されたダイパッド部 4の周囲には、 複数本のリード 6がほぼ等 間隔に配置されている。 各リード 6の一端部 （チップ 2に近い方の端部） と、 チ ップ 2の主面のボンディングパッド 8とは、 A uワイヤ 9を介して電気的に接続 されている。 一方、 各リード 6の他端部側は、 モールド樹脂 3の下面 （実装面） 力 ら外部に露出し、 Q F N ( 1 A) の外部接続端子を構成している。 図示は省略 するが、 リード 6、 吊りリード 5およびダイパッド部 4のそれぞれの表面には、 P d (パラジウム） メツキが施されている。 Q F N ( 1 A) を配線基板に実装す る際には、 配線基板の電極と Q F N ( 1 A) の各リード 6とを半田を介して電気 的に接続するが、 上記 P dメツキは、 半田の濡れ性を向上させるために形成され る。  Around the die pad portion 4 on which the chip 2 is mounted, a plurality of leads 6 are arranged at almost equal intervals. One end of each lead 6 (the end closer to the chip 2) and the bonding pad 8 on the main surface of the chip 2 are electrically connected via an Au wire 9. On the other hand, the other end of each lead 6 is exposed to the outside from the bottom surface (mounting surface) force of the mold resin 3 and constitutes an external connection terminal of Q F N (1 A). Although not shown, P d (palladium) plating is applied to the surfaces of the lead 6, the suspension lead 5 and the die pad portion 4. When QFN (1 A) is mounted on the wiring board, the wiring board electrode and each lead 6 of QFN (1 A) are electrically connected via solder. It is formed to improve the wettability.
本実施の形態の Q F N ( 1 A) の特徴は、 チップ 2が実装されたダイパッド部 4の一面 （主面） とは反対側の他面 （裏面） をモールド樹脂 3の上面から外部に 露出させた点にある。 前述したように、 Q F N ( 1 A) は、 モ一ルド樹脂 3の下 面に外部接続端子 （リード 6 ) が配置される。 そのため、 ダイパッド部 4の裏面 をモールド樹脂 3の下面 （実装面） 力 ら外部に露出させた場合、 配線基板の表面 のダイパッド部 4と対向する領域に配線を配置することができなくなり、 特に高 密度実装用配線基板においては、 配線のレイアウト設計が困難になる。 そこで、 本実施の形態の Q F N ( 1 A) は、 モールド樹脂 3の上面からダイパッド部 4を 外部に露出させ、 配線基板の実装密度を向上させると共に、 パッケージの熱抵抗 を低減させている。 The feature of the QFN (1 A) of this embodiment is that the other surface (back surface) opposite to the one surface (main surface) of the die pad 4 on which the chip 2 is mounted is exposed from the upper surface of the mold resin 3 to the outside. It is at an exposed point. As described above, the external connection terminal (lead 6) is arranged on the lower surface of the mold resin 3 in the QFN (1 A). For this reason, if the back surface of the die pad part 4 is exposed to the outside from the lower surface (mounting surface) force of the mold resin 3, it becomes impossible to place wiring in a region facing the die pad part 4 on the surface of the wiring board. Wiring layout design is difficult for a high density mounting wiring board. Therefore, the QFN (1 A) of the present embodiment exposes the die pad portion 4 from the upper surface of the mold resin 3 to improve the mounting density of the wiring board and reduce the thermal resistance of the package.
また、 本実施の形態の Q F N ( 1 A) の他の特徴は、 モールド樹脂 3の上面 （ ダイパッド部 4が露出している面） と側面とに梨地加工が施されておらず、 平坦 な面になっている点にある。 このような平坦な面を有するモールド樹脂 3は、 表 面が鏡面加工された金型を使って成形される。  In addition, another feature of the QFN (1 A) of the present embodiment is that the top surface (the surface where the die pad portion 4 is exposed) and the side surface of the mold resin 3 are not subjected to a matte finish, and are flat. It is in the point. Mold resin 3 having such a flat surface is molded using a mold whose surface is mirror-finished.
一般に、 梨地加工 （梨地処理） とは、 物理的処理 （サンドブラスト、 ショット ブラスト、 放電加工、 レーザー照射など） あるいは化学的処理 （エッチングなど ) によって、 金型などの表面に多数の微細な凹凸を形成する処理であり、 シボ加 ェとも呼ばれている。 梨地加工によって形成される凹凸の大きさ （凹部の深さ、 あるいは凸部の高さ） は、 モールド樹脂 3の表面にインクを使って文字や記号な どのマークを印刷することが可能な程度の大きさであり、 通常は、 1 0 m〜l In general, pear finish (pear finish) means that many fine irregularities are formed on the surface of molds by physical treatment (sand blasting, shot blasting, electric discharge machining, laser irradiation, etc.) or chemical treatment (etching, etc.) This process is also called squirrel processing. The size of the unevenness (depth of recess or height of protrusion) formed by the satin finish is such that marks such as letters and symbols can be printed on the surface of the mold resin 3 using ink. Size, usually 10 m ~ l
5 μ πι程度である。 About 5 μπι.
一方、 鏡面加工 （鏡面処理） とは、 一般に、 金型などの表面に上記のような梨 地加工を施さず、 凹凸のない平坦な面に仕上げることをいうが、 本実施の形態で は、 1 . 0 μ ΐη未満の極めて微細な凹凸を形成する場合も含まれる。 鏡面加工が 施された金型を使ってモールド樹脂 3を成形する工程については、 後述する。 図 1に示すように、 モールド樹脂 3の上面の周辺部には、 製造者、 品番、 口ッ ト番号などを示すマーク 1 0が刻印されている。 一般に、 樹脂パッケージの表面 にマークを形成する方法として、 ィンクを用いた印刷方法とレーザーマーキング 法とがあるが、 本実施の形態の Q F N ( 1 A) は、 モ一ルド樹脂 3の上面が平坦 になっているので、 印刷方法ではモールド樹月旨 3とィンクとの密着性が乏しくな る。 そこで、 上記マーク 1 0は、 平坦な面にもマークを刻印できるレーザーマー キング法によって刻印されている。 On the other hand, mirror finishing (mirror finishing) generally means that the surface of a mold or the like is not subjected to the above-mentioned matte finish and is finished to a flat surface without unevenness. In this embodiment, This includes the case of forming extremely fine irregularities of less than 1.0 μΐη. The process of molding the mold resin 3 using a mold that has undergone mirror finishing will be described later. As shown in FIG. 1, a mark 10 indicating the manufacturer, product number, mouth number, etc. is stamped on the periphery of the upper surface of the mold resin 3. In general, there are two methods for forming marks on the surface of a resin package: a printing method using an ink and a laser marking method. The QFN (1 A) of this embodiment has a flat top surface of the mold resin 3. Therefore, in the printing method, the adhesion between the mold tree 3 and the ink is poor. Therefore, the mark 10 above is a laser marker that can be engraved on a flat surface. Engraved by the King method.
図 5は、 上記 Q F N ( 1 A) の製造に用いるリードフレームの平面図である。 このリードフレーム 1 1は、 C u、 C u合金または F e — N i合金などからなる 厚さ 1 2 5 /z m〜2 0 0 μ m程度の金属板からなり、 前述したダイパッド部 4、 吊りリード 5、 リード 6などのパターンが繰り返し形成された構成になっている 。 すなわち、 リードフレーム 1 1は、 複数個 （例えば 3個） のチップ 2を搭載で きる多連構造を有している。 このリードフレーム 1 1は、 金属板をプレスで打ち 抜いたり、 エッチングしたりすることによって、 ダイパッド部 4、 吊りリード 5 、 リード 6などのパターンを形成し、 その後、 これらのパターンの表面全体に P dメツキを施すことによって製造される。 リードフレーム 1 1の表面全体に一括 して P dメツキを施した場合は、 リード 6の表面やダイパッド部 4の表面に選択 的にメツキを施す工程が不要となる。  FIG. 5 is a plan view of a lead frame used for manufacturing the above Q F N (1 A). The lead frame 11 is made of a metal plate made of Cu, Cu alloy or Fe-Ni alloy or the like with a thickness of about 1 2 5 / zm to 200 μm. Patterns such as lead 5 and lead 6 are repeatedly formed. That is, the lead frame 11 has a multiple structure in which a plurality of (for example, three) chips 2 can be mounted. The lead frame 11 1 is formed by punching a metal plate with a press or etching to form a pattern such as a die pad portion 4, a suspended lead 5, a lead 6, and the like, and then P on the entire surface of these patterns. Manufactured by applying d-stick. When Pd plating is applied to the entire surface of the lead frame 11, the process of selectively applying the plating to the surface of the lead 6 and the surface of the die pad portion 4 is not necessary.
上記リードフレーム 1 1を使って Q F N ( 1 A) を組み立てるには、 まず、 図 6および図 7に示すように、 A g (銀） ペーストなどの接着剤 7を使ってダイパ ッド部 4上にチップ 2を接着した後、 図 8および図 9に示すように、 周知のボー ルボンディング装置を使って、 チップ 2のボンディングパッド 8と、 リードフレ —ム 1 1のリード 6とを A uワイヤ 9で電気的に接続 （結線） する。  To assemble QFN (1 A) using the above lead frame 1 1, first, as shown in Fig. 6 and Fig. 7, use adhesive 7 such as Ag (silver) paste on die pad 4 After bonding chip 2 to the chip, use well-known ball bonding equipment to connect chip 2 bonding pad 8 and lead frame 1 1 lead 6 to Au wire 9 as shown in Figs. 8 and 9. Electrically connect (connect) with.
次に、 上記リードフレーム 1 1を図 1 0に示す金型 2 0に装着する。 図 1 0は 、 金型 2 0の一部 （Q F N約 1個分の領域） を示す断面図である。 この金型 2 0 は、 上金型 2 O Aと下金型 2 0 Bとで構成されており、 キヤビティ 2 1内に露出 した上金型 2 O Aの表面には、 鏡面加工が施されている。  Next, the lead frame 11 is mounted on a mold 20 shown in FIG. FIG. 10 is a cross-sectional view showing a part of the mold 20 (an area corresponding to about one Q F N). This mold 20 is composed of an upper mold 2 OA and a lower mold 20 B, and the surface of the upper mold 2 OA exposed in the cavity 21 is mirror-finished. .
上記金型 2 0を使ってチップ 2を樹脂封止するには、 まず、 下金型 2 0 Bの表 面に薄い樹脂シ—ト 2 2を敷き、 この樹脂シ一ト 2 2の上にリードフレーム 1 1 を載置する。 リードフレーム 1 1は、 ダイパッド部 4の裏面 （チップ 2が実装さ れた面と反対側の面） を上に向けて配置し、 リ一ド 6を樹脂シ一ト 2 2に接触さ せる。 そして、 この状態でリード 6と樹脂シート 2 2とを上金型 2 O Aと下金型 2 0 Bとで挟み付け、 ダイパッド部 4の裏面 （上面） を上金型 2 O Aの表面に接 触させると共に、 上金型 2 O Aと下金型 2 0 Bとの押圧力によって、 リード 6を 樹脂シート 2 2の中に食い込ませる。 このとき、 上金型 2 O Aの表面は、 梨地加 ェされていない平坦な面となっているので、 上金型 2 O Aの表面とダイパッド部 4とが密に接触する。 In order to resin-seal the chip 2 using the above mold 20, first, a thin resin sheet 22 is laid on the surface of the lower mold 20 B, and the resin sheet 22 is placed on the resin sheet 22. Place the lead frame 1 1. The lead frame 11 1 is arranged with the back surface of the die pad 4 (the surface opposite to the surface on which the chip 2 is mounted) facing upward, and the lead 6 is brought into contact with the resin sheet 22. In this state, the lead 6 and the resin sheet 2 2 are sandwiched between the upper mold 2 OA and the lower mold 20 B, and the back surface (upper surface) of the die pad 4 is brought into contact with the surface of the upper mold 2 OA. At the same time, the lead 6 is bitten into the resin sheet 22 by the pressing force of the upper mold 2 OA and the lower mold 20 B. At this time, the upper mold 2 OA surface is The surface of the upper mold 2 OA and the die pad portion 4 are in intimate contact with each other because the surface is not flat.
次に、 この状態でキヤビティ 2 1内に溶融樹脂を注入してモールド樹脂 3を成 形した後、 上金型 2 O Aと下金型 2 0 Bとを分離する。 これにより、 図 1 1に示 すように、 ダイパッド部 4の裏面 （上面） がモ一ノレド樹脂 3の上面から外部に露 出すると共に、 樹脂シ一ト 2 2の中に食い込んでいたリード 6がモールド樹脂 3 の下面から外部に露出する。 また、 リード 6は下金型 2 0 Bの表面に敷かれた樹 月旨シート 2 2の中に食い込んでいるので、 モールド樹月旨 3から突出して形成され る。  Next, in this state, molten resin is injected into the cavity 21 to form the mold resin 3, and then the upper mold 2OA and the lower mold 20B are separated. As a result, as shown in FIG. 11, the back surface (upper surface) of the die pad portion 4 is exposed to the outside from the upper surface of the monored resin 3, and the lead 6 that has digged into the resin sheet 22. Is exposed to the outside from the bottom surface of the mold resin 3. In addition, the lead 6 is formed so as to protrude from the mold lumber 3 because it digs into the lunar month sheet 22 laid on the surface of the lower mold 20 B.
前述したように、 本実施の形態では、 上金型 2 O Aとダイパッド部 4とが密に 接触するので、 キヤビティ 2 1内に注入された溶融樹脂は、 上金型 2 O Aの表面 とダイパッド部 4との隙間に入り難い。 従って、 モールド樹脂 3から露出したダ ィパッド部 4の裏面 （上面） に付着する樹脂バリの量が低減される。  As described above, in the present embodiment, the upper mold 2 OA and the die pad part 4 are in intimate contact with each other, so that the molten resin injected into the cavity 21 is the surface of the upper mold 2 OA and the die pad part. It is difficult to enter the gap with 4. Therefore, the amount of resin burrs adhering to the back surface (upper surface) of the die pad portion 4 exposed from the mold resin 3 is reduced.
一方、 リード 6は、 下金型 2 0 Bの表面に敷かれた樹脂シート 2 2の中に食い 込んでいるので、 リード 6と樹脂シート 2 2との間に溶融樹脂が入り込むことは ない。 従って、 モールド樹脂 3から露出したリード 6の表面に樹脂バリが発生す ることはない。  On the other hand, since the lead 6 bites into the resin sheet 22 laid on the surface of the lower mold 20 B, the molten resin does not enter between the lead 6 and the resin sheet 22. Therefore, no resin burr is generated on the surface of the lead 6 exposed from the mold resin 3.
次に、 金型 2 0から取り出したリードフレーム 1 1をウォータージヱット方式 のバリ取り装置に搬送し、 モールド樹脂 3の表面に高圧水を噴射することによつ て、 異物を除去する。 このとき、 モールド樹脂 3の上面から露出したダイパッド 部 4の表面に付着している樹脂バリも同時に除去される。 本実施の形態の製造方 法によれば、 ダイパッド部 4の表面には、 僅かな量の樹脂バリしか付着しないの で、 たとえ樹脂バリが発生しても高圧水の噴射によつて速やかに樹脂バリを除去 することができ、 電解方式によるバリ取り作業が不要となる。 従って、 モーノレド 樹脂 3の外部に露出したリード 6やダイパッド部 4の表面に施された P dメツキ の劣化も低減される。 また、 本実施の形態における洗浄工程は、 樹脂パッケージ の外観を良くするためにも行う。  Next, the lead frame 11 taken out from the mold 20 is transported to a water jet type deburring device, and foreign matter is removed by spraying high pressure water onto the surface of the mold resin 3. . At this time, the resin burrs adhering to the surface of the die pad portion 4 exposed from the upper surface of the mold resin 3 are also removed at the same time. According to the manufacturing method of the present embodiment, since only a small amount of resin burr adheres to the surface of the die pad portion 4, even if a resin burr occurs, the resin can be promptly ejected by high-pressure water injection. Deburring can be removed, eliminating the need for deburring by electrolysis. Therefore, the deterioration of the lead 6 exposed to the outside of the monored resin 3 and the Pd plating applied to the surface of the die pad portion 4 are also reduced. In addition, the cleaning process in this embodiment is also performed to improve the appearance of the resin package.
その後、 モールド樹脂 3の上面の周辺部にレーザ一マーキング法でマーク 1 0 を刻印し、 続いて、 モールド樹脂 3の外部に露出したリードフレーム 1 1の不要 箇所を切断してパッケージを個片化した後、 テスティング工程および外観検査ェ 程を経ることによって、 前記図 1〜図 4に示す本実施の形態の Q F N ( 1 A) が 完成する。 Thereafter, a mark 10 is engraved on the periphery of the upper surface of the mold resin 3 by a laser marking method, and then the lead frame 1 1 exposed outside the mold resin 3 is not required. After cutting the part and dividing the package into individual pieces, the QFN (1 A) of the present embodiment shown in FIGS. 1 to 4 is completed through a testing process and an appearance inspection process.
(実施の形態 2 )  (Embodiment 2)
前記実施の形態 1では、 キヤビティ 2 1内に露出した上金型 2 O Aの表面全体 に鏡面加工を施したが、 例えば図 1 2に示すように、 上金型 2 0 Aの表面のうち 、 ダイパッド部 4の裏面 （上面） と接触する領域のみに鏡面加工を施し、 他の頜 域に梨地加工を施してもよい。  In the first embodiment, the entire surface of the upper mold 2 OA exposed in the cavity 21 is mirror-finished. For example, as shown in FIG. 12, among the surfaces of the upper mold 20 A, Only the area that contacts the back surface (upper surface) of the die pad part 4 may be mirror-finished and the other areas may be textured.
この場合も、 キヤビティ 2 1内に注入された溶融樹脂は、 上金型 2 O Aとダイ パッド部 4との隙間に入り難いので、 モールド樹脂 3から露出したダイパッド部 4の表面に付着する樹脂バリの量を低減することができる。  Also in this case, since the molten resin injected into the cavity 21 is difficult to enter the gap between the upper mold 2 OA and the die pad part 4, the resin burrs adhering to the surface of the die pad part 4 exposed from the mold resin 3 can be prevented. The amount of can be reduced.
このような上金型 2 O Aにより成形された Q F N ( 1 A) は、 図 1 5に示すよ うに、 モールド樹脂 3においてダイパッド部 4が露出する面には梨地加工が施さ れた構造となる。  As shown in FIG. 15, the Q F N (1 A) molded by the upper mold 2 O A has a structure in which the surface of the mold resin 3 where the die pad portion 4 is exposed is subjected to a matte finish.
一方、 この場合は、 モールド樹脂 3の上面が梨地になるので、 レーザーマ一キ ング方式と印刷方式のいずれの方法でもマーク 1 0を刻印することが可能となり On the other hand, in this case, since the upper surface of the mold resin 3 is textured, the mark 10 can be engraved by either the laser marking method or the printing method.
、 マーキング工程の自由度が向上する。 The degree of freedom in the marking process is improved.
また、 この場合は、 モールド樹脂 3の側面も梨地になるので、 モールド工程が 完了したリードフレーム 1 1を金型 2 0力 ら取り出す際、 モールド樹月旨 3と上金 型 2 0 Aとの離型性が向上する。  In this case, the side surface of the mold resin 3 is also satin, so when the lead frame 11 that has completed the molding process is taken out from the mold 20 force, the mold resin 3 and the upper mold 20 A Release property is improved.
図 1 3に示す上金型 2 0 Aは、 前記図 1 2に示す上金型 2 0 Aと同様、 ダイパ ッド部 4の裏面 （上面） と接触する領域のみに鏡面加工を施し、 他の領域に梨地 加工を施したものであるが、 さらに、 ダイパッド部 4の裏面と接触する領域を他 の領域よりもキヤビティ 2 1の内側に突出させ、 ダイパッド部 4の外周部近傍の 上金型 2 O Aの表面に段差を形成している。  The upper die 20 A shown in FIG. 13 is mirror-finished only in the area that contacts the back surface (upper surface) of the die pad 4, as with the upper die 20 A shown in FIG. In addition, the area that contacts the back surface of the die pad part 4 protrudes more inside the cavity 21 than the other areas, and the upper die near the outer periphery of the die pad part 4 2 A step is formed on the surface of OA.
このような段差を設けた場合は、 キヤビティ 2 1内に注入された溶融樹脂が段 差部の狭い隙間を通過する際に熱を奪われ易くなるので、 樹脂の硬化が促進され る。 この結果、 モールド樹脂 3により成形された Q F N ( 1 A) は、 ダイパッド の周辺部のみ段差部の狭い隙間を設けた分だけ樹脂封止される。 これにより、 ダ ィパッド部 4と上金型 2 0 Aとの隙間に溶融樹脂が入り込み難くなるので、 ダイ パッド部 4の表面に発生する樹脂バリの量をさらに低減することができる。 この ような段差は、 前記実施の形態 1で使用した上金型 2 0 A、 または図 1 2に示す ような上金型 2 O Aに形成してもよレ、。 In the case where such a step is provided, since the molten resin injected into the cavity 21 is likely to lose heat when passing through a narrow gap in the stepped portion, curing of the resin is promoted. As a result, the QFN (1 A) molded with the mold resin 3 is resin-sealed by the amount of narrow gaps in the stepped portions only at the periphery of the die pad. As a result, Since the molten resin does not easily enter the gap between the pad portion 4 and the upper mold 20A, the amount of resin burrs generated on the surface of the die pad portion 4 can be further reduced. Such a step may be formed in the upper mold 20A used in the first embodiment or the upper mold 2OA as shown in FIG.
このような上金型 2 O Aにより成形された Q F N ( 1 A) の断面図は、 図 1 6 に示すように、 モールド樹脂 3においてダイパッド部 4が露出する面には鏡面加 ェが施され、 さらにダイパッド部 4の周辺部において段差を有した構造となる。 図 1 4に示す上金型 2 O Aの表面は、 モールド樹脂 3の上面と接触する領域に 鏡面加工を施し、 モールド樹脂 3の側面と接触する領域に梨地加工を施したもの である。  The cross-sectional view of QFN (1 A) molded with such an upper mold 2 OA is shown in FIG. 16, and the mirror resin is applied to the surface of the mold resin 3 where the die pad portion 4 is exposed. Further, the structure has a step at the periphery of the die pad portion 4. The surface of the upper mold 2 O A shown in FIG. 14 is obtained by applying a mirror finish to the area in contact with the upper surface of the mold resin 3 and applying a matte finish to the area in contact with the side surface of the mold resin 3.
この場合も、 キヤビティ 2 1内に注入された溶融樹脂は、 上金型 2 O Aとダイ パッド部 4との隙間に入り難いので、 モールド樹脂 3から露出したダイパッド部 4の表面に付着する樹脂バリの量を低減することができる。  Also in this case, since the molten resin injected into the cavity 21 is difficult to enter the gap between the upper mold 2 OA and the die pad part 4, the resin burrs adhering to the surface of the die pad part 4 exposed from the mold resin 3 can be prevented. The amount of can be reduced.
この場合は、 モールド樹脂 3の上面が平坦になるので、 マーク 1 0は、 レーザ 一マーキング方式によって刻印する。 また、 モールド樹脂 3の側面が梨地になる ので、 モールド樹月旨 3と上金型 2 O Aとの離型性が向上する。 なお、 図 1 4に示 す上金型 2 0 Aの表面に、 前記図 1 3に示すような段差を形成することにより、 ダイパッド部 4の表面に発生する樹脂バリの量をさらに低減することができる。 このような上金型 2 O Aにより成形された Q F N ( 1 A) の断面図は、 図 1 7 に示すように、 モールド樹脂 3においてダイパッド部 4が露出する面には鏡面加 ェが施され、 側面は梨地加工が施された構造となる。  In this case, since the upper surface of the mold resin 3 becomes flat, the mark 10 is engraved by a laser one marking method. In addition, since the side surface of the mold resin 3 is satin, the releasability between the mold tree 3 and the upper mold 2 O A is improved. Further, by forming the step as shown in FIG. 13 on the surface of the upper mold 20 A shown in FIG. 14, the amount of resin burr generated on the surface of the die pad portion 4 can be further reduced. Can do. As shown in FIG. 17, the cross-sectional view of QFN (1 A) molded by such an upper mold 2 OA is mirror-finished on the surface of the mold resin 3 where the die pad portion 4 is exposed. The side is structured with satin finish.
(実施の形態 3 )  (Embodiment 3)
前記実施の形態 1では、 ダイパッド部 4の面積がチップ 2の面積よりも大きい Q F N構造について説明したが、 例えば図 1 8に示すように、 ダイパッド部 4の 面積がチップ 2の面積よりも小さい場合に、 本発明を適用してもよい。  In the first embodiment, the QFN structure in which the area of the die pad portion 4 is larger than the area of the chip 2 has been described. However, for example, as shown in FIG. 18, the area of the die pad portion 4 is smaller than the area of the chip 2 In addition, the present invention may be applied.
ダイパッド部 4の面積がチップ 2の面積よりも小さいと、 上記したように樹脂 バリがダイパッド部 4の表面全体を覆う可能性が、 ダイパッド部 4の面積がチッ プ 2の面積よりも大きい場合に比べ高くなる。 ダイパッド部 4の表面全体を樹脂 バリで覆われてしまうと、 バリ取り工程を行っても樹脂バリの除去が困難となる 。 しかし、 実施形態 1および 2のような金型 2 0によりモールド樹脂 3を成形す ることで、 ダイパッド部 4の裏面 （上面） に樹脂バリが付着するのを抑制するこ とができる。 If the area of the die pad part 4 is smaller than the area of the chip 2, the possibility that the resin burr covers the entire surface of the die pad part 4 as described above is when the area of the die pad part 4 is larger than the area of the chip 2. Compared to higher. If the entire surface of the die pad 4 is covered with resin burrs, it will be difficult to remove the resin burrs even if the deburring process is performed. . However, by molding the mold resin 3 using the mold 20 as in the first and second embodiments, it is possible to suppress the resin burrs from adhering to the back surface (upper surface) of the die pad portion 4.
(実施の形態 4 )  (Embodiment 4)
前記実施の形態 1〜 3では、 チップ 2を 1個ずつ封止する金型 2 0を使用した 力 例えば図 1 9に示すように、 複数のチップ 2を一括して樹脂封止し、 その後 、 樹脂およびリードフレーム 1 1を切断して Q F N ( 1 A) を個片化する一括モ ールド方式の金型を使用する場合に、 本発明を適用してもよい。  In the first to third embodiments, the force using the mold 20 for sealing the chips 2 one by one, for example, as shown in FIG. 19, the plurality of chips 2 are collectively sealed with resin, The present invention may be applied to the case of using a collective mold mold that cuts the resin and the lead frame 11 and separates the QFN (1 A).
以上、 本発明者によってなされた発明を実施の形態に基づき具体的に説明した 力 本発明は前記実施の形態に限定されるものではなく、 その要旨を逸脱しない 範囲で種々変更可能であることはいうまでもない。  The above has specifically described the invention made by the present inventor based on the embodiments. The present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
前記実施の形態では、 Q F Nの製造に適用した場合について説明したが、 一般 に、 半導体チップを封止するモールド樹脂の実装面に外部接続端子を配置し、 モ ールド樹脂の他の面にダイパッド部を露出させる樹脂パッケージの製造に広く適 用することができる。  In the above-described embodiment, the case where the present invention is applied to the manufacture of QFN has been described. In general, external connection terminals are arranged on a mounting surface of a mold resin for sealing a semiconductor chip, and a die pad portion is formed on the other surface of the mold resin. It can be widely applied to the production of resin packages that expose the surface.
前記実施の形態では、 リードフレームに P dメツキを施した場合について説明 したが、 C uに A 1を形成する後付けメツキ方式のリードフレームに適用しても よい。  In the above-described embodiment, the case where the lead frame is subjected to Pd plating has been described. However, the present invention may be applied to a lead-frame type lead frame in which A 1 is formed on Cu.
また、 前記実施の形態では、 上金型の表面において、 少なくともダイパッド部 4の裏面 （上面） と接触する部分は鏡面加工されている場合について説明したが 、 梨地加工を施した上金型を適用しても、 その梨地加工によって形成される凹凸 の大きさを小さくすれば、 樹脂パリの発生は多少ではあるが抑制できる。 上金型 の表面全体を梨地加工で形成することで、 鏡面加工で形成するよりも金型の製造 コストを低減できる。 し力 し、 上金型の表面全体を梨地加工にする場合、 ダイパ ッド部 4の裏面 （上面） と上金型の表面とを密にできないため、 樹脂バリは発生 することから、 モールド樹月旨 3を成形後の洗浄工程は必要である。 さらに説明す ると、 同じサイズのダイパッドに対して、 例えば凹凸の大きさが 5 μ πΐと 1 5 μ mの上金型により成形した場合、 凹凸の大きさが小さい方がダイパッド部の裏面 (上面） 全体は樹脂バリで覆われ難くなる。 産業上の利用可能性 In the above embodiment, the case where at least the portion in contact with the back surface (upper surface) of the die pad part 4 is mirror-finished on the surface of the upper mold has been described. However, if the size of the irregularities formed by the matte finish is reduced, the occurrence of resin paris can be suppressed to some extent. By forming the entire surface of the upper mold with a satin finish, the manufacturing cost of the mold can be reduced compared with forming with a mirror finish. If the entire upper surface of the upper mold is processed into a satin finish, the resin burrs are generated because the back surface (upper surface) of the die pad part 4 and the surface of the upper mold cannot be made dense. A washing process after molding the moon 3 is necessary. To explain further, when the same size die pad is formed with an upper mold with 5 μππΐ and 15 μm, for example, the unevenness is smaller on the back of the die pad ( Upper surface) The entire surface is difficult to be covered with resin burrs. Industrial applicability
半導体チップを封止するモールド樹脂の実装面に外部接続端子を配置し、 モー ルド樹脂の他の面にダイパッド部を露出させたパッケージ構造を有する Q F N (Q uad Flat Non-leaded package)などの製造に適用することができる。  Manufacturing of QFN (Quad Flat Non-leaded package) etc., which has a package structure in which the external connection terminals are placed on the mounting surface of the mold resin that seals the semiconductor chip and the die pad part is exposed on the other surface of the mold resin Can be applied to.

Claims

1 . ダイパッド部と、 前記ダイパッド部の一面に実装された半導体チップと、 前 記ダイパッド部の周囲を囲むように配置された複数本のリードと、 前記複数本の リ一ドのそれぞれと前記半導体チップとを電気的に接続する複数本のワイヤとが モールド樹脂によって封止され、 1. a die pad part; a semiconductor chip mounted on one surface of the die pad part; a plurality of leads arranged so as to surround the periphery of the die pad part; and each of the plurality of leads and the semiconductor A plurality of wires that electrically connect the chip are sealed with mold resin,
前記複数本のリ一ドのそれぞ請れの一部が、 前記モールド樹脂の実装面から露出 されることによって、 複数の外部接続端子が構成され、  A plurality of external connection terminals are configured by exposing a part of each of the plurality of leads from the mounting surface of the mold resin,
前記ダイパッド部の一面と反対側の他の面が、 前記モールド樹脂の前記実装面と は反対側の面から露出されたパッケージ構造を有する半導体装置の製造方法であ つて、 囲  A manufacturing method of a semiconductor device having a package structure in which another surface opposite to one surface of the die pad portion is exposed from a surface opposite to the mounting surface of the mold resin,
( a ) 前記ダイパッド部と前記複数本のリードとが形成されたリードフレームを 用意する工程と、  (a) preparing a lead frame in which the die pad portion and the plurality of leads are formed;
( b ) 前記リードフレームに形成された前記ダイパッド部の一面に、 前記半導体 チップを実装した後、 前記リードフレームに形成された前記複数本のリードのそ れぞれと前記半導体チップとをワイャで電気的に接続する工程と、  (b) After mounting the semiconductor chip on one surface of the die pad portion formed on the lead frame, each of the plurality of leads formed on the lead frame and the semiconductor chip are wired. Electrically connecting, and
( c ) 前記工程 （b ) の後、 上金型と下金型とからなる金型に前記リードフレー ムを装着し、 前記ダイパッド部の他面を前記上金型の表面に接触させると共に、 前記複数本のリ一ドのそれぞれの一部を、 前記下金型の上に敷かれた樹脂シ一ト に接触させる工程と、  (c) After the step (b), the lead frame is attached to a mold composed of an upper mold and a lower mold, and the other surface of the die pad portion is brought into contact with the surface of the upper mold. Contacting a part of each of the plurality of leads with a resin sheet laid on the lower mold;
( d ) 前記工程 （c ) の後、 前記金型のキヤビティ内に溶融樹脂を供給すること によって、 前記モールド樹脂を成形する工程とを有し、  (d) after the step (c), by supplying a molten resin into the mold cavity, forming the mold resin,
前記キヤビティ内に露出した前記上金型の表面全体が鏡面処理されていること を特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device, wherein the entire surface of the upper mold exposed in the cavity is mirror-finished.
2 . 前記工程 （d ) の後、 前記モールド樹脂の前記実装面とは反対側の面に、 レ 一ザ一マークを刻印する工程をさらに有することを特徴とする請求項 1記載の半 導体装置の製造方法。  2. The semiconductor device according to claim 1, further comprising a step of marking a laser mark on a surface of the mold resin opposite to the mounting surface after the step (d). Manufacturing method.
3 . 前記工程 （b ) に先立って、 前記リードフレームの表面にメツキを施すこと を特徴とする請求項 1記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the surface of the lead frame is plated prior to the step (b).
4 . 前記メツキは、 P dメツキであることを特徴とする請求項 3記載の半導体装 置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 3, wherein the plating is a Pd plating.
5 . 前記工程 （d ) の後、 前記モールド樹脂の表面に高圧水を噴射することによ つて、 前記ダイパッド部の他面に付着した樹脂バリを除去する工程をさらに有す ることを特徴とする請求項 1記載の半導体装置の製造方法。  5. After the step (d), the method further comprises a step of removing resin burrs adhering to the other surface of the die pad portion by spraying high pressure water onto the surface of the mold resin. The method for manufacturing a semiconductor device according to claim 1.
6 . 前記キヤビティ内に露出した前記上金型の表面全体は、 凹凸を有し、 前記凹 凸の大きさは 1 . 0 μ πι未満であることを特徴とする請求項 1記載の半導体装置 の製造方法。  6. The entire surface of the upper mold exposed in the cavity has irregularities, and the size of the irregularities is less than 1.0 μππι. Production method.
7 . ダイパッド部と、 前記ダイパッド部の一面に実装された半導体チップと、 前 記ダイパッド部の周囲を囲むように配置された複数本のリードと、 前記複数本の リ一ドのそれぞれと前記半導体チップとを電気的に接続する複数本のワイャとが モールド樹脂によって封止され、  7. A die pad part, a semiconductor chip mounted on one surface of the die pad part, a plurality of leads arranged so as to surround the die pad part, each of the plurality of leads, and the semiconductor A plurality of wires that electrically connect the chip are sealed with mold resin,
前記複数本のリ一ドのそれぞれの一部が、 前記モールド樹脂の実装面から露出 されることによって、 複数の外部接続端子が構成され、  By exposing a part of each of the plurality of leads from the mounting surface of the mold resin, a plurality of external connection terminals are configured,
前記ダイパッド部の一面と反対側の他面が、 前記モールド樹脂の前記実装面と は反対側の面から露出されたパッケージ構造を有する半導体装置の製造方法であ つて、  A manufacturing method of a semiconductor device having a package structure in which the other surface opposite to the one surface of the die pad portion is exposed from the surface opposite to the mounting surface of the mold resin,
( a ) 前記ダイパッド部と前記複数本のリードとが形成されたリードフレームを 用意する工程と、  (a) preparing a lead frame in which the die pad portion and the plurality of leads are formed;
( b ) 前記リードフレームに形成された前記ダイパッド部の一面に、 前記半導体 チップを実装した後、 前記リ一ドフレームに形成された前記複数本のリ一ドのそ れぞれと前記半導体チップとをワイャで電気的に接続する工程と、  (b) After mounting the semiconductor chip on one surface of the die pad portion formed on the lead frame, each of the plurality of leads formed on the lead frame and the semiconductor chip Electrically connecting the two with a wire,
( c ) 前記工程 （b ) の後、 上金型と下金型とからなる金型に前記リードフレー ムを装着し、 前記ダイパッド部の他面を前記上金型の表面に接触させると共に、 前記複数本のリ一ドのそれぞれの一部を、 前記下金型の上に敷かれた樹脂シート に接触させる工程と、  (c) After the step (b), the lead frame is attached to a mold composed of an upper mold and a lower mold, and the other surface of the die pad portion is brought into contact with the surface of the upper mold. Contacting a part of each of the plurality of leads with a resin sheet laid on the lower mold; and
( d ) 前記工程 （c ) の後、 前記金型のキヤビティ内に溶融樹脂を供給すること によって、 前記モールド樹月旨を成形する工程とを有し、  (d) after the step (c), by supplying molten resin into the mold cavity, forming the mold tree effect,
前記キヤビティ内に露出した前記上金型の表面のうち、 前記ダイパッド部の他 面に接触する領域は鏡面処理され、 他の領域は梨地処理されていることを特徴と する半導体装置の製造方法。 Of the surface of the upper mold exposed in the cavity, other than the die pad portion A method for manufacturing a semiconductor device, characterized in that a region in contact with the surface is mirror-finished and the other region is satin-finished.
8 . 前記キヤビティ内に露出した前記上金型の表面のうち、 前記ダイパッド部の 他面と接触する領域は、 前記他の領域よりも前記キヤビティの内側に突出してい ることを特徴とする請求項 7記載の半導体装置の製造方法。  8. Of the surface of the upper mold exposed in the cavity, a region in contact with the other surface of the die pad portion protrudes inside the cavity from the other region. 8. A method for producing a semiconductor device according to 7.
9 . 前記工程 （d ) の後、 前記モールド樹脂の前記実装面とは反対側の面に、 ィ ンクマークを刻印する工程をさらに有することを特徴とする請求項 7記載の半導 体装置の製造方法。  9. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of marking an ink mark on a surface of the mold resin opposite to the mounting surface after the step (d). Method.
1 0 . 前記工程 （b ) に先立って、 前記リードフレームの表面にメツキを施すこ とを特徴とする請求項 7記載の半導体装置の製造方法。  10. The method of manufacturing a semiconductor device according to claim 7, wherein the surface of the lead frame is plated prior to the step (b).
1 1 . 前記工程 （d ) の後、 前記モールド樹脂の表面に高圧水を噴射することに よって、 前記ダイパッド部の他面に付着した樹脂バリを除去する工程をさらに有 することを特徴とする請求項 7記載の半導体装置の製造方法。  11. After the step (d), the method further includes a step of removing resin burrs adhering to the other surface of the die pad portion by spraying high pressure water onto the surface of the mold resin. 8. A method for manufacturing a semiconductor device according to claim 7.
1 2 . 前記キヤビティ内に露出した前記上金型の表面のうち、 前記ダイパッド部 の他面に接触する領域は、 他の領域よりも平坦度が高いことを特徴とする請求項 12. The region of the upper die surface exposed in the cavity that contacts the other surface of the die pad portion has higher flatness than the other region.
7記載の半導体装置の製造方法。 8. A method for producing a semiconductor device according to 7.
1 3 . ダイパッド部と、 前記ダイパッド部の一面に実装された半導体チップと、 前記ダイパッド部の周囲を囲むように配置された複数本のリードと、 前記複数本 のリードのそれぞれと前記半導体チップとを電気的に接続する複数本のワイャと がモールド樹脂によって封止され、  13. A die pad part, a semiconductor chip mounted on one surface of the die pad part, a plurality of leads arranged to surround the die pad part, each of the plurality of leads, and the semiconductor chip A plurality of wires that electrically connect the two are sealed with mold resin,
前記複数本のリ一ドのそれぞれの一部が、 前記モールド樹脂の実装面から露出 されることによって、 複数の外部接続端子が構成され、  By exposing a part of each of the plurality of leads from the mounting surface of the mold resin, a plurality of external connection terminals are configured,
前記ダイパッド部の一面と反対側の他面が、 前記モールド樹脂の前記実装面と は反対側の面から露出されたパッケージ構造を有する半導体装置の製造方法であ つて、  A manufacturing method of a semiconductor device having a package structure in which the other surface opposite to the one surface of the die pad portion is exposed from the surface opposite to the mounting surface of the mold resin,
( a ) 前記ダイパッド部と前記複数本のリードとが形成されたリードフレームを 用意する工程と、  (a) preparing a lead frame in which the die pad portion and the plurality of leads are formed;
( b ) 前記リードフレームに形成された前記ダイパッド部の一面に、 前記半導体 チップを実装した後、 前記リードフレームに形成された前記複数本のリ一ドのそ れぞれと前記半導体チップとをワイャで電気的に接続する工程と、 ( C ) 前記工程 （b ) の後、 上金型と下金型とからなる金型に前記リードフレー ムを装着し、 前記ダイパッド部の他面を前記上金型の表面に接触させると共に、 前記複数本のリードのそれぞれの一部を、 前記下金型の上に敷かれた樹脂シート に接触させる工程と、 (b) After mounting the semiconductor chip on one surface of the die pad portion formed on the lead frame, the plurality of leads formed on the lead frame. A step of electrically connecting each of the semiconductor chips and the semiconductor chip with a wire; and (C) after the step (b), mounting the lead frame on a die composed of an upper die and a lower die. A step of bringing the other surface of the die pad portion into contact with the surface of the upper mold, and contacting a part of each of the plurality of leads with a resin sheet laid on the lower mold;
( d ) 前記工程 （c ) の後、 前記金型のキヤビティ内に溶融樹脂を供給すること によって、 前記モールド樹月旨を成形する工程とを有し、  (d) after the step (c), by supplying molten resin into the mold cavity, forming the mold tree effect,
前記キヤビティ内に露出した前記上金型の表面のうち、 前記モールド樹脂の前 記実装面とは反対側の面に接触する領域は鏡面処理され、 前記モールド樹脂の側 面に接触する領域は梨地処理されていることを特徴とする半導体装置の製造方法  Of the surface of the upper mold exposed in the cavity, the region that contacts the surface opposite to the mounting surface of the mold resin is mirror-finished, and the region that contacts the side surface of the mold resin is satin. Process for manufacturing a semiconductor device characterized in that it is processed
1 4 . 前記工程 （d ) の後、 前記モールド樹脂の前記実装面とは反対側の面に、 レーザーマークを刻印する工程をさらに有することを特徴とする請求項 1 3記載 の半導体装置の製造方法。 14. The method of manufacturing a semiconductor device according to claim 13, further comprising a step of marking a laser mark on a surface of the mold resin opposite to the mounting surface after the step (d). Method.
1 5 . 前記工程 （b ) に先立って、 前記リードフレームの表面にメツキを施すこ とを特徴とする請求項 1 3記載の半導体装置の製造方法。  15. The method for manufacturing a semiconductor device according to claim 13, wherein the surface of the lead frame is subjected to plating prior to the step (b).
1 6 . 前記キヤビティ内に露出した前記上金型の表面のうち、 前記ダイパッド部 の他面と接触する領域は、 他の領域よりも前記キヤビティの内側に突出している ことを特徴とする請求項 1 3記載の半導体装置の製造方法。  16. Of the surface of the upper mold exposed in the cavity, a region in contact with the other surface of the die pad portion protrudes more inside the cavity than the other region. 13. A method for manufacturing a semiconductor device according to 3.
1 7 . 前記キヤビティ内に露出した前記上金型の表面のうち、 前記モールド樹脂 の前記実装面とは反対側の面に接触する領域は、 前記モールド樹脂の側面に接触 する領域よりも平坦度が高いことを特徴とする請求項 1 3記載の半導体装置の製 造方法。  17. Of the surface of the upper mold exposed in the cavity, the area that contacts the surface of the mold resin opposite to the mounting surface is flatter than the area that contacts the side surface of the mold resin. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the semiconductor device is high.
1 8 . ダイパッド部と、 前記ダイパッド部の一面に実装された半導体チップと、 前記ダイパッド部の周囲を囲むように配置された複数本のリードと、 前記複数本 のリ一ドのそれぞれと前記半導体チップとを電気的に接続する複数本のワイヤと がモールド樹脂によって封止され、  18. A die pad portion, a semiconductor chip mounted on one surface of the die pad portion, a plurality of leads arranged so as to surround the die pad portion, and each of the plurality of leads and the semiconductor A plurality of wires that electrically connect the chip are sealed with mold resin,
前記複数本のリ一ドのそれぞれの一部が、 前記モールド樹脂の実装面から露出 されることによって、 複数の外部接続端子が構成され、 前記ダイパッド部の一面と反対側の他面が、 前記モールド樹脂の前記実装面と は反対側の面から露出されたパッケージ構造を有する半導体装置の製造方法であ つて、 By exposing a part of each of the plurality of leads from the mounting surface of the mold resin, a plurality of external connection terminals are configured, A manufacturing method of a semiconductor device having a package structure in which the other surface opposite to the one surface of the die pad portion is exposed from the surface opposite to the mounting surface of the mold resin,
( a ) 前記ダイパッド部と前記複数本のリードとが形成されたリードフレームを 用意する工程と、  (a) preparing a lead frame in which the die pad portion and the plurality of leads are formed;
( b ) 前記リードフレームに形成された前記ダイパッド部の一面に、 前記半導体 チップを実装した後、 前記リードフレームに形 された前記複数本のリ一ドのそ れぞれと前記半導体チップとをワイャで電気的に接続する工程と、  (b) After mounting the semiconductor chip on one surface of the die pad portion formed on the lead frame, each of the plurality of leads formed on the lead frame and the semiconductor chip. Electrically connecting with wires;
( c ) 前記工程 （b ) の後、 上金型と下金型とからなる金型に前記リードフレー ムを装着し、 前記ダイパッド部の他面を前記上金型の表面に接触させると共に、 前記複数本のリ一ドのそれぞれの一部を、 前記下金型の上に敷かれた樹脂シート に接触させる工程と、  (c) After the step (b), the lead frame is attached to a mold composed of an upper mold and a lower mold, and the other surface of the die pad portion is brought into contact with the surface of the upper mold. Contacting a part of each of the plurality of leads with a resin sheet laid on the lower mold; and
( d ) 前記工程 （c ) の後、 前記金型のキヤビティ内に溶融樹脂を供給すること によって、 前記モールド樹脂を成形する工程とを有し、  (d) after the step (c), by supplying a molten resin into the mold cavity, forming the mold resin,
前記キヤビティ内に露出した前記上金型の表面のうち、 前記モールド樹脂の前 記実装面とは反対側の面に接触する領域は、 他の領域よりも平坦度が高いことを 特徴とする半導体装置の製造方法。  Of the surface of the upper mold exposed in the cavity, a region in contact with the surface opposite to the mounting surface of the mold resin has higher flatness than other regions. Device manufacturing method.
1 9 . 前記キヤビティ内に露出した前記上金型の表面のうち、 前記ダイパッド部 の他面と接触する領域は、 前記他の領域よりも前記キヤビティの内側に突出して いることを特徴とする請求項 1 8記載の半導体装置の製造方法。  19. Of the surface of the upper mold exposed in the cavity, a region in contact with the other surface of the die pad portion protrudes inside the cavity from the other region. Item 18. A method for manufacturing a semiconductor device according to Item 18.
2 0 . 前記工程 （d ) の後、 前記モールド樹脂の前記実装面とは反対側の面に、 インクマークを刻印する工程をさらに有することを特徴とする請求項 1 8記載の 半導体装置の製造方法。  20. The method of manufacturing a semiconductor device according to claim 18, further comprising a step of marking an ink mark on a surface of the mold resin opposite to the mounting surface after the step (d). Method.
2 1 . 前記工程 （b ) に先立って、 前記リードフレームの表面にメツキを施すこ とを特徴とする請求項 1 8記載の半導体装置の製造方法。  21. The method of manufacturing a semiconductor device according to claim 18, wherein the surface of the lead frame is plated prior to the step (b).
2 2 . 前記工程 （d ) の後、 前記モールド樹脂の表面に高圧水を噴射することに よって、 前記ダイパッド部の他面に付着した樹脂バリを除去する工程をさらに有 することを特徴とする請求項 1 8記載の半導体装置の製造方法。  2 2. After the step (d), the method further comprises a step of removing resin burrs adhering to the other surface of the die pad portion by spraying high-pressure water onto the surface of the mold resin. The method for manufacturing a semiconductor device according to claim 18.
PCT/JP2004/012450 2004-08-24 2004-08-24 Process for producing semiconductor device WO2006022024A1 (en)

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PCT/JP2004/012450 WO2006022024A1 (en) 2004-08-24 2004-08-24 Process for producing semiconductor device

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WO2006022024A1 true WO2006022024A1 (en) 2006-03-02

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000236060A (en) * 1999-02-16 2000-08-29 Matsushita Electronics Industry Corp Semiconductor device
JP2002134676A (en) * 2000-09-15 2002-05-10 Samsung Techwin Co Ltd Lead frame, semiconductor package provided therewith, and manufacturing method of the semiconductor package
JP2003243600A (en) * 2001-12-14 2003-08-29 Hitachi Ltd Semiconductor device and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000236060A (en) * 1999-02-16 2000-08-29 Matsushita Electronics Industry Corp Semiconductor device
JP2002134676A (en) * 2000-09-15 2002-05-10 Samsung Techwin Co Ltd Lead frame, semiconductor package provided therewith, and manufacturing method of the semiconductor package
JP2003243600A (en) * 2001-12-14 2003-08-29 Hitachi Ltd Semiconductor device and method of manufacturing the same

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