JP2006279088A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a production yield of a semiconductor device suitable for multiple pins. <P>SOLUTION: The semiconductor device is provided with a semiconductor chip having a plurality of electrodes on its principal plane, a plurality of leads electrically connected to the plurality of electrodes of the semiconductor chip, respectively, and a sealing body made of resin sealing the semiconductor chip and the plurality of leads, wherein the plurality of leads include a first lead, which are exposed at a mounting surface of the sealing body made of resin and which have first external terminals located at the side of the sealing body made of resin and a second lead adjacent to the first lead which are exposed at the mounting surface of the sealing body made of resin and which have second external terminals located at the side of the semiconductor chip as to the first external terminal, the first lead and the second lead adhered to the semiconductor chip and fixed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device having an external connection terminal on the back surface (mounting surface) of a resin sealing body.

  As a semiconductor device for sealing a semiconductor chip with a resin sealing body, various package structures have been proposed and put into practical use. For example, Japanese Patent Application Laid-Open No. 11-330343 discloses a semiconductor device called a QFN (Quad Flatpack Non-Leaded Package) type. This QFN type semiconductor device has a package structure in which an external connection portion (external terminal portion) formed on a lead electrically connected to an electrode of a semiconductor chip is exposed from the back surface (mounting surface) of the resin sealing body. Therefore, it is compared with a semiconductor device called a QFP (Quad Flatpack Package) type package structure in which leads electrically connected to the electrodes of the semiconductor chip protrude from the side surface of the resin sealing body and are bent into a predetermined shape. Thus, the planar size can be reduced.

  The QFN type semiconductor device is manufactured by an assembly process using a lead frame. For example, in the case of a package structure in which a semiconductor chip is mounted on a die pad, the semiconductor chip is mainly mounted on a die pad (also referred to as a tab) supported via a suspension lead on the frame body of the lead frame, and then the electrode of the semiconductor chip And a lead supported on the frame body of the lead frame via a tie bar (also referred to as a dam bar) by a bonding wire, and thereafter, a semiconductor chip, a lead, a die pad, a suspension lead and a bonding wire are sealed with a resin. It is manufactured by sealing with a stationary body and then cutting and separating leads, tie bars, suspension leads and the like from the frame body of the lead frame. One end side of the bonding wire is connected to the electrode of the semiconductor chip, and the other end side is connected to the main surface on the opposite main surface and back surface of the lead. The main surface of the lead is covered with a resin sealing body, and the back surface is exposed from the back surface of the resin sealing body on the opposite main surface and back surface (mounting surface).

  The resin sealing body of the QFN type semiconductor device is formed by a transfer molding method (transfer molding method) suitable for mass production. The resin molding is formed by the transfer molding method so that the semiconductor chip, lead, die pad, suspension lead, bonding wire, etc. are located inside the mold cavity (resin sealing body forming part). This is done by positioning the lead frame between the upper mold and the lower mold of the mold and then injecting resin into the cavity of the mold.

  By the way, in the package structure in which the external connection portion configured on the lead is exposed from the back surface of the resin sealing body, the lead frame is positioned on the molding die so that the external connection portion of the lead contacts the lower mold of the molding die, After that, it can be obtained by pressurizing and injecting resin into the cavity of the molding die. In this case, since the adhesion between the lower mold and the external connection part of the lead is low inside the cavity, the lower mold and the external The resin is likely to enter between the connection portions, and the external connection portion is likely to be covered with a thin resinous resin body (resin burr).

  Therefore, in the manufacture of the QFN type semiconductor device, generally, a resin sheet (resin film) is interposed between the lower mold of the molding die and the lead frame so that the external connection portion of the lead is in contact with the resin sheet. A technique (hereinafter referred to as a sheet mold technique) is employed in which a lead frame is positioned in a molding die and then a resin is injected under pressure into the cavity of the molding die. In the case of this sheet molding technique, since the adhesiveness between the resin sheet and the external connection part of the lead is high inside the cavity, it is possible to suppress the problem that the external connection part is covered with the resin burr. The sheet mold technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-274195.

JP 11-330343 A JP-A-11-274195

  However, in the QFN type semiconductor device, the following problems arise when trying to increase the number of terminals (increase the number of pins) as the LSI formed on the semiconductor chip has higher functionality and higher performance.

  In order to increase the number of terminals, it is necessary to miniaturize the leads, but the external connection portion is also miniaturized as the leads are miniaturized. The area of the external connection portion cannot be made very small because a predetermined area is required to ensure reliability during mounting. Therefore, when trying to increase the number of pins without changing the package size, the number of terminals cannot be increased so much, so that a large number of pins cannot be achieved.

  Therefore, in order to secure the area of the external connection part and increase the number of pins without changing the package size, the width of the external connection part of the lead is selectively widened and the arrangement of the external connection part is made in a staggered arrangement. Is effective. However, in such a case, in the molding process, the external connection portion located on the semiconductor chip side is far from the clamping portion of the molding die that clamps the other end side of the lead from the vertical direction, so the resin sheet and the outside of the lead Adhesiveness with a connection part falls and it becomes easy to generate | occur | produce the malfunction that an external connection part will be covered with a resin burr | flash. Such a defect becomes a factor of reducing the manufacturing yield of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device suitable for increasing the number of pins.

  The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

Means (1): The semiconductor device of the present invention comprises a semiconductor chip having a plurality of electrodes arranged on the main surface;
A plurality of leads electrically connected to a plurality of electrodes of the semiconductor chip, and
A resin sealing body for sealing the semiconductor chip and the plurality of leads;
The plurality of leads are exposed from a mounting surface of the resin sealing body, and have a first lead having a first external connection portion located on a side surface of the resin sealing body, and the first lead A second lead that is adjacent to the second lead and has a second external connection portion that is exposed from the mounting surface of the resin sealing body and is located closer to the semiconductor chip than the first external connection portion. Including lead,
The first and second leads are bonded and fixed to the semiconductor chip.

Means (2): The manufacture of the semiconductor device of the present invention includes the following steps.
The first and second leads adjacent to each other, the first external connection portion provided on the first lead, and the lead provided on the second lead and more than the first external connection portion And a first mold having a first clamp part and a cavity connected to the first clamp part on a first mating surface, and a lead frame having a second external connection part located on one end side ,
Preparing a mold having a second mold having a second clamp portion facing the first clamp portion on a second match surface facing the first mating surface;
Bonding and fixing one end side of the first and second leads to a semiconductor chip;
Electrically connecting a plurality of electrodes arranged on the main surface of the semiconductor chip and the first and second leads, respectively;
The other end side opposite to the one end side of the first and second leads is sandwiched from above and below by the first and second clamp portions, and the first and second leads and the second mating surface Injecting resin into the cavity in a state where the first and second external connection portions are in contact with a resin sheet disposed between the semiconductor chip, the first lead, and the second lead The process of resin sealing.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the present invention, it is possible to improve the manufacturing yield of a semiconductor device suitable for increasing the number of pins.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

(Embodiment 1)
In the first embodiment, an example in which the present invention is applied to a SON (Small Out-line Non-Leaded Package) type semiconductor device will be described.

FIG. 1 is a plan view showing the external appearance (main surface side) of the semiconductor device of Embodiment 1.
FIG. 2 is a plan view (bottom view) showing the appearance (back side) of the semiconductor device according to the first embodiment.
FIG. 3 is a plan view showing the internal structure (back side) of the semiconductor device of Embodiment 1;
4 is an enlarged cross-sectional view of a part of FIG.
5 is a cross-sectional view showing the internal structure of the semiconductor device according to the first embodiment ((a) is a cross-sectional view taken along the line AA in FIG. 3, and (b) is a cross-sectional view taken along the line BB in FIG. ),
FIG. 6 is an enlarged cross-sectional view of a part of FIG.

  As shown in FIGS. 1 to 5, the semiconductor device 1a according to the present embodiment includes one semiconductor chip 2, first and second lead groups including a plurality of leads 4, a plurality of bonding wires 7, and a resin. The package structure has a sealing body 8. The semiconductor chip 2, the leads 4 of the first and second lead groups, the plurality of bonding wires 7, and the like are sealed with a resin sealing body 8.

  As shown in FIGS. 3 and 5, the semiconductor chip 2 has a rectangular planar shape that intersects the thickness direction, and is, for example, a rectangle in this embodiment. Although not limited to this, the semiconductor chip 2 mainly includes a semiconductor substrate, a plurality of transistor elements formed on the main surface of the semiconductor substrate, and an insulating layer and a wiring layer on the main surface of the semiconductor substrate. A multilayer wiring layer stacked in a plurality of stages and a surface protective film (final protective film) formed so as to cover the multilayer wiring layer are configured. The insulating layer is made of, for example, a silicon oxide film. The wiring layer is formed of a metal film such as aluminum (Al), an aluminum alloy, copper (Cu), or a copper alloy. The surface protective film is formed of, for example, a multilayer film in which an inorganic insulating film and an organic insulating film such as a silicon oxide film or a silicon nitride film are stacked.

  The semiconductor chip 2 has a main surface (circuit forming surface) 2x and a back surface 2y positioned on opposite sides, and a memory made of, for example, a DRAM (Dynamic Random Access Memory) as an integrated circuit on the main surface 2x side of the semiconductor chip 2. A circuit is formed. This memory circuit is mainly composed of transistor elements formed on the main surface of the semiconductor substrate and wirings formed on the multilayer wiring layer.

  A plurality of electrodes 2 a are disposed on the main surface 2 x of the semiconductor chip 2. The plurality of electrodes 2a are arranged along one of the two center lines of the main surface 2a of the semiconductor chip 2 (in this embodiment, the center line in the same direction as the long side direction of the semiconductor chip 2). It is a central array. The plurality of electrode pads 2a are formed in the uppermost wiring layer of the multilayer wiring layers of the semiconductor chip 2, and are exposed through bonding openings formed in the surface protective film of the semiconductor chip 2 corresponding to the respective electrodes 2a. ing.

  As shown in FIGS. 1, 2, and 5, the resin sealing body 8 has a rectangular planar shape that intersects the thickness direction, and is, for example, a rectangle in this embodiment. The resin sealing body 8 has a main surface 8 x and a back surface (mounting surface) 8 y located on opposite sides, and the planar size of the resin sealing body 8 is larger than the planar size of the semiconductor chip 2.

  For the purpose of reducing the stress, the resin sealing body 8 is formed of, for example, a biphenyl resin to which a phenolic curing agent, silicone rubber, filler, and the like are added. The resin sealing body 8 is formed by a transfer molding method suitable for mass production. The transfer molding method uses a molding die having a pot, a runner, an inflow gate, a cavity and the like, and forms a resin sealing body by injecting resin into the cavity through the runner and the inflow gate from the pot. It is. In the present embodiment, a sheet mold technique for forming the resin sealing body 8 using a resin sheet is employed.

  As shown in FIGS. 3 to 5, each lead 4 of the first lead group is arranged along one long side of two long sides located on opposite sides of the semiconductor chip 2, and Each lead 4 of the lead group is arranged along the other long side of the semiconductor chip 2. One long side of the semiconductor chip 2 is located on the same side as one side face 8b of two side faces (8a, 8b) located on opposite sides of the resin sealing body 8, and the other length of the semiconductor chip 2 is placed. The side is located on the same side as the other side surface 8 a of the resin sealing body 8.

  Each lead 4 of the first lead group extends so as to cross the outer periphery of the main surface 2x of the semiconductor chip 2, one end side is bonded and fixed to the semiconductor chip 2, and the other end side is one side of the resin sealing body 8. It is arrange | positioned at the side surface 8a side. Each lead 4 of the second lead group extends so as to cross the outer periphery of the main surface 2x of the semiconductor chip 2, one end side is bonded and fixed to the semiconductor chip 2, and the other end side is the other side of the resin sealing body 8. It is arrange | positioned at the side surface 8b side. In the present embodiment, one end side of each lead 4 of the first and second lead groups is arranged along the arrangement direction of the plurality of electrodes 2a, and the insulating chip 3 made of resin is interposed between the leads 4 of the semiconductor chip 2. It is adhesively fixed to the main surface 2x. The other end side of each lead 4 of the first and second lead groups is arranged along the longitudinal direction (the same direction as the long side of the semiconductor chip) of the side surfaces (8a, 8b) of the resin sealing body 8. ing.

  The plurality of electrodes 2a of the semiconductor chip 2 are electrically connected to the respective leads 4 of the first and second lead groups. In the present embodiment, the electrical connection between the electrode 2 a of the semiconductor chip 2 and the lead 4 is performed by the bonding wire 7, and one end side of the bonding wire 7 is connected to the electrode 2 a of the semiconductor chip 2. The end side is connected to one end side of the lead 4. As the bonding wire 7, for example, a gold (Au) wire is used. As a method for connecting the wires 7, for example, a nail head bonding (ball bonding) method using ultrasonic vibration in combination with thermocompression bonding is used.

  In the first and second lead groups, the plurality of leads 4 include a first lead 4a and a second lead 4b adjacent to each other. The first lead 4 a is configured to have a first external connection portion 5 a that is exposed from the back surface of the resin sealing body 8 and is located on the side surface side of the resin sealing body 8. The second lead 4b is exposed from the back surface 8y of the resin sealing body 8, and is closer to the semiconductor chip 2 than the first external connection portion 5a, in other words, the lead 4 is closer to the first external connection portion 5a. It has the structure which has the 2nd external connection part 5b located in the one end side. The first lead 4a and the second lead 4b are alternately and repeatedly arranged along the longitudinal direction of the resin sealing body 8 (long side direction of the semiconductor chip). That is, in the first and second lead groups, the first lead 4a having the first external connection portion 5a and the second lead 4b having the second external connection portion 5b are alternately and repeatedly arranged in one direction. It has a configuration.

  As shown in FIG. 2, first and second terminal groups including a plurality of external connection portions 5 are arranged on the back surface 8 y of the resin sealing body 8. Each external connection portion 5 of the first terminal group is disposed along the longitudinal direction of the resin sealing body 8 on the first side surface 8a side of the resin sealing body 8, and each external connection portion of the second terminal group. 5 is arrange | positioned along the longitudinal direction of the resin sealing body 8 at the 2nd side surface 8b side of the resin sealing body 8. As shown in FIG. In the first and second terminal groups, the plurality of external connection portions 5 include a first external connection portion 5a located on the side surface (8a, 8b) side of the resin sealing body 8 and the first external connection portion. And the second external connection portion 5b positioned farther from the side surface of the resin sealing body 8 than 5a, and the first and second external connection portions (5a, 5b) are arranged in the longitudinal direction of the resin sealing body 8 ( The semiconductor chips are alternately and repeatedly disposed along the long side direction of the semiconductor chip. That is, the first and second terminal groups have a staggered arrangement in which the first external connection portion 5a and the second external connection portion 5b are repeatedly arranged along one direction.

  As shown in FIG. 6, the plurality of leads 4 (4a, 4b) includes a first portion 4m1 extending on the main surface 2x of the semiconductor chip 2, and the resin sealing body 8 from the first portion 4m1. The second portion 4m2 is bent to the back surface 8y side, and the third portion 4m3 extends from the second portion 4m2 toward the side surface of the resin sealing body 8.

  As shown in FIGS. 3 to 5, the first and second external connection portions (5 a, 5 b) are arranged around the semiconductor chip 2, respectively, as the third thirds of the first and second leads (4 a, 4 b). The portion 4m3 is provided.

  As shown in FIGS. 5 and 6, the external connection portions (5 a, 5 b) 5 are formed integrally with the leads (4 a, 4 b), and the thickness of the external connection portion 5 is the third part of the lead 4. It is thicker than 4m3. In the present embodiment, the thickness of the external connection portion 5 is, for example, about 125 μm to 150 μm, and the thickness of the lead 4 other than the external connection portion 5, that is, the thickness at other portions is, for example, about 65 μm to 75 μm.

  Although not shown in detail, the external connection portion 5 protrudes outward from the back surface 8y of the resin sealing body 8, and the tip portion thereof is covered with a solder layer (plating layer) 9 formed by, for example, a plating method or a printing method. It has been broken. The semiconductor device 1a of this embodiment is mounted by soldering these external connection portions 5 to electrodes (footprints, lands, pads) of the wiring board.

  As shown in FIG. 4, the width 5W of the external connection portion (5a, 5b) 5 is wider than the width 4W of the third portion 4m3 of the lead (4a, 4b) 4. The interval 5S between the first external connection portion 5a and the second external connection portion 5b is an interval 4S between the third portion 4m3 of the first lead 4a and the third portion 4m3 of the second lead 4b. It is narrower than. The distance L2 from the side surface (8a, 8b) of the resin sealing body 8 to the second external connection portion 5b is from the side surface (8a, 8b) of the resin sealing body 8 to the first external connection portion 5a. It is longer than the distance L1. In the present embodiment, the width 5W is about 300 μm, for example, and the width 4W is about 200 μm, for example. The interval 5S is, for example, about 100 μm, and the interval 4S is, for example, about 300 μm. The distance L2 is about 0.8 mm, for example, and the distance L1 is about 0.1 mm, for example.

  The semiconductor device 1a of this embodiment has a package structure in which a plurality of external connection portions 5 exposed from the back surface 8y of the resin sealing body 8 are arranged in a staggered arrangement along the longitudinal direction of the resin sealing body 8. By adopting such a package structure, it is possible to secure the area of the external connection portion 5 necessary for ensuring the reliability at the time of mounting and to miniaturize the lead 4, so that the package size is not changed. The number of pins can be increased.

  Next, a lead frame used for manufacturing the semiconductor device 1a will be described with reference to FIGS.

FIG. 7 is a plan view showing a part of the lead frame;
FIG. 8 is an enlarged plan view of a part of FIG.
FIG. 9 is a cross-sectional view showing a part of the lead frame ((a) is a cross-sectional view along the first lead, and (b) is a cross-sectional view along the second lead).

  As shown in FIG. 7, the lead frame LF1 has a multiple structure in which a plurality of product forming regions 11 partitioned by the frame body 10 are arranged in the longitudinal direction of the lead frame LF1. As shown in FIGS. 8 and 9, first and second lead groups each including a plurality of leads 4 including the first and second leads (4 a and 4 b) are arranged in each product formation region 11. Yes. In the present embodiment, the product formation region 11 has a rectangular planar shape. The first and second lead groups are disposed facing each other and spaced apart from each other in the short side direction of the product formation region 11. Each lead 4 of the first and second lead groups is arranged along the long side direction of the product formation region 11. In the first and second lead groups, adjacent leads 4 are connected via a tie bar 12. Further, a plating layer 6 is provided on the bonding surface on one end side of each of the plurality of leads 4, and an insulating property extending along the long side direction of the product formation region 11 on the surface opposite to the bonding surface. Tape 3 is affixed. The other end side of each of the plurality of leads 4 is connected to the frame body 10.

  In order to manufacture the lead frame LF1, first, a metal plate made of Cu, Cu alloy, Fe—Ni alloy or the like having a plate thickness of about 125 μm to 150 μm is prepared, and one side of the portion where the lead 4 is to be formed is a photoresist film. Cover with. Further, the portions where the external connection portion 5 is formed are covered with a photoresist film on both sides. In this state, the metal plate is etched with a chemical solution, and the thickness of the metal plate in the region where one side is covered with the photoresist film is reduced to, for example, about half (65 μm to 75 μm) (half etching). By etching in this way, the metal plate in the region not covered with the photoresist film on both sides disappears completely, and the lead having a thickness of about 65 μm to 75 μm is formed in the region covered on one side with the photoresist film. 4 is formed. Further, since the metal plate in the region where both surfaces are covered with the photoresist film is not etched by the chemical solution, the protruding external connection portion 5 having the same thickness (125 μm to 150 μm) as before the etching is formed. Next, the photoresist film is removed, and then a plated layer 6 is formed on the bonding surface on one end side of the lead 4, and then the lead 4 is subjected to bending processing, whereby the lead frame LF1 shown in FIGS. Is completed.

  Next, a molding die used for manufacturing the semiconductor device 1a will be described with reference to FIGS.

FIG. 11 is a cross-sectional view taken along the first lead in the molding process during the manufacturing process of the semiconductor device 1a.
12 is an enlarged cross-sectional view of a part of FIG.
FIG. 13 is a cross-sectional view taken along the second lead in the molding process during the manufacturing process of the semiconductor device 1a.
FIG. 14 is an enlarged cross-sectional view of a part of FIG.

  As shown in FIGS. 11 to 14, the molding die 20 is not limited to this, but has an upper die 21 and a lower die 22 which are divided into upper and lower parts, and further, a pot, a cull part, a runner, and a resin injection gate. , Cavity 23, air vent and the like. The upper mold 21 has a first clamping portion 21a on the first mating surface, a cavity 23 connected to the first clamp portion 21a, a runner having one end side connected to the cavity 23 via a resin injection gate, The lower die 22 has a cull portion connected to the other end side of the runner, a pot portion connected to the cull portion, and an air vent connected to the cavity 23. The second clamp portion 22a faces the first clamp portion. The cavity 23 is configured to be recessed from the first clamp portion 21 a of the upper mold 21 in the depth direction of the upper mold 21. The planar shape of the cavity 23 is a square shape, which is a rectangle in this embodiment.

  In the formation of the resin sealing body by the sheet molding technique, the upper mold 21 of the molding die 20 is placed so that the resin sheet (resin film) 24 is positioned between the lower die 22 of the molding die 20 and the lead frame LF1. The lead frame LF1 is positioned between the lower mold 22 and then the resin is pressurized and injected from the pot into the cavity 23 through the cull part, the runner and the resin injection gate. In the sheet molding technique, since a thermosetting resin is generally used, a heat-resistant resin sheet that can withstand the temperature at the time of forming the resin sealing body is used as the resin sheet 24. Further, in order to obtain a stand-off package structure, it is necessary to bite the external connection portion 5 of the lead 4 into the resin sheet 24 by the clamping force (clamping force) of the molding die 20. A flexible resin sheet (flexible resin sheet) 24 that can be easily crushed is used.

  Next, the manufacture of the semiconductor device 1a will be described with reference to FIGS.

  FIG. 10 is a cross-sectional view ((a) is a cross-sectional view in the die bonding step, and (b) is a cross-sectional view in the wire bonding step) during the manufacturing process of the semiconductor device 1a.

  First, the lead frame LF1 shown in FIGS. 7 to 9 is prepared, and then, as shown in FIG. 10A, the semiconductor chip 2 is bonded and fixed to the lead frame LF1. The lead frame LF1 and the semiconductor chip 2 are bonded and fixed by bonding and fixing one end side (first portion 4m1) of the lead 4 to the main surface 2x of the semiconductor chip 2 with the insulating tape 3 interposed. .

  Next, as shown in FIG. 10B, the plurality of electrodes 2 a arranged on the main surface 2 x of the semiconductor chip 2 and the plurality of leads 4 are electrically connected by a plurality of bonding wires 7, respectively. One end side of the bonding wire 7 is connected to the electrode 2 a of the semiconductor chip 2, and the other end side is connected to the plating layer 6 provided on the bonding surface on one end side of the lead 4.

  Next, the molding die 20 shown in FIGS. 11 to 14 is prepared, and then the lead frame LF1 is positioned between the upper die 21 and the lower die 22 of the molding die 20 as shown in FIG.

The positioning of the lead frame LF1 is performed in a state where the resin sheet 24 is interposed between the lead frame LF1 and the mating surface of the lower mold 22.
The lead frame LF1 is positioned in a state where the semiconductor chip 2, the bonding wire 7 and the like are positioned inside the cavity 23.

  The lead frame LF1 is positioned by sandwiching the other end of the lead (4a, 4b) 4 between the first clamp portion 21a of the upper die 21 and the second clamp portion 22a of the lower die 22 from the vertical direction. 4a, 4b) 4 and the resin sheet 24 disposed between the second mating surface of the lower mold 22 and the external connection portions (5a, 5b) 5 are in contact with each other.

  Next, with the lead frame LF1 positioned as described above, for example, a thermosetting resin is injected under pressure from the pot of the molding die 20 into the cavity 23 through the cull portion, the runner, and the resin injection gate. The sealing body 8 is formed. The semiconductor chip 2, the plurality of leads 4, the plurality of bonding wires 7, etc. are sealed with a resin sealing body 8.

  In this step, the stand-off package in which the external connection portion 5 is exposed from the back surface 8y of the resin sealing body 8 and the external connection portion 5 protrudes outward from the back surface 8y of the resin sealing body 8 is almost completed.

  Next, the resin sheet 24 attached to the lead frame LF1 is peeled off, the lead frame LF1 is taken out from the molding die 20, and then a curing process for promoting the hardening of the resin sealing body 8 is performed, and then the tie bar 12 is separated. The semiconductor device 1a of the present embodiment is almost completed by performing a cutting process for cutting, a cutting process for separating the leads 4 from the frame body 10, and the like.

  In the molding process during the manufacturing process of the semiconductor device according to the present embodiment, a sheet molding technique in which the resin sheet 24 is disposed between the lead frame LF1 and the lower mold 22 of the molding die 20 is adopted, and the lead 4 is attached to the resin sheet 24. The other end side of the lead 4 is sandwiched between the clamp part 21a of the upper die 21 and the clamp part 22a of the lower die 22 in the vertical direction with the external connection part 5 in contact therewith. In this way, the external connection portion 5 of the lead 4 presses the resin sheet 24 by the pressing force of the molding die 20 (upper die 21 and lower die 22), so that the distal end portion of the external connection portion 5 is against the resin sheet 24. Bite. As a result, after the resin is injected into the cavity 23 to form the resin sealing body 8, when the lead frame LF 1 is taken out from the molding die 20, the distal end portion of the external connection portion 5 that bites into the resin sheet 24 is removed. It protrudes from the back surface 8y of the resin sealing body 8 to the outside.

  Further, when the lead frame LF1 is pressed by the clamping force of the molding die 20, an upward force acts on one end side that is the tip side of the lead 4 by the spring force of the metal plate constituting the lead frame LF1. Therefore, when the plurality of external connection portions 5 are arranged in a staggered arrangement as in this embodiment, the lead 4 (4a) in which the external connection portion 5 (5a) is formed at a position close to the other end side of the lead 4 The lead 4 (4b) in which the external connection portion 5 (5b) is formed at a position farther from the other end side of the lead 4 than the external connection portion 5a is different from the force by which the external connection portion 5 presses the resin sheet 24. Occurs. That is, the external connection portion 5b formed on the lead 4b has a weaker force for pressing the resin sheet 24 than the external connection portion 5a formed on the lead 4a. As a result, the external connection part 5b farther from the clamp part of the molding die 20 than the external connection part 5a has a problem that the adhesiveness with the resin sheet 24 is lowered and the external connection part 5b is covered with the resin burr. It becomes easy to do.

  On the other hand, in the present embodiment, resin sealing is performed in a state where one end side of the lead 4 is bonded and fixed to the main surface 2x of the semiconductor chip 2. By sealing the resin in such a state, the warping of the lead 4 caused by pressing the lead frame LF1 by the clamping force of the molding die 20 can be suppressed, so the pressing force of the external connection portion 5b that presses the resin sheet 24 Can be suppressed. Therefore, since the adhesiveness between the external connection portion 5b far from the clamp portion of the molding die 20 and the resin sheet 24 can be secured, it is possible to suppress the occurrence of a problem that the external connection portion 5b is covered with the resin burr. As a result, the manufacturing yield of the semiconductor device 1a can be improved.

(Embodiment 2)
FIG. 15 is a cross-sectional view of the semiconductor device according to the second embodiment ((a) is a cross-sectional view taken along the first lead, and (b) is a cross-sectional view taken along the second lead),
FIG. 16 is a cross-sectional view taken along the first lead in the molding process during the manufacturing process of the semiconductor device according to the second embodiment;
FIG. 17 is a cross-sectional view taken along the second lead in the molding process during the manufacturing process of the semiconductor device according to the second embodiment.

  As shown in FIG. 15, the semiconductor device 1b according to the second embodiment has basically the same configuration as that of the first embodiment, and the following configuration is different.

  That is, the semiconductor device 1a of the first embodiment has a package structure in which the back surface 2y of the semiconductor chip 2 is covered with the resin of the resin sealing body 8, but the semiconductor device 1b of the second embodiment has a semiconductor structure. The package structure is such that the back surface 2 y of the chip 2 is exposed from the main surface 8 x of the resin sealing body 8, in other words, the package structure is such that the back surface 2 y of the semiconductor chip 2 is not covered with the resin of the resin sealing body 8.

  In such a package structure, as shown in FIGS. 16 and 17, in the molding process, the back surface 2 y of the semiconductor chip 2 is resin-sealed while being in contact with the inner wall surface of the cavity 23 facing the back surface 2 y. can get.

  Even in such a package structure, the same effects as those of the above-described embodiment can be obtained.

  In the present embodiment, one end of the lead 4 is bonded and fixed to the main surface 2x of the semiconductor chip 2, and the resin sealing is performed with the back surface 2y of the semiconductor chip 2 in contact with the inner wall surface of the cavity 23. By sealing the resin in such a state, the warping of the lead 4 caused by pressing the lead frame LF1 with the clamping force of the molding die 20 can be further suppressed, so that the external connection portion 5b is covered with the resin burr. The occurrence of such problems can be further suppressed.

(Embodiment 3)
FIG. 18 is a cross-sectional view of the semiconductor device of the third embodiment ((a) is a cross-sectional view along the first lead, and (b) is a cross-sectional view along the second lead).

  As shown in FIG. 18, the semiconductor device 1c of the third embodiment has basically the same configuration as that of the first embodiment described above, and the following configurations are different.

  That is, in the semiconductor device 1a of the first embodiment, the package structure in which the main surface 2x of the semiconductor chip 2 is located on the back surface 8y side of the resin sealing body 8, in other words, the back surface 2y of the semiconductor chip 2 and the resin sealing body. 8 has a package structure in which the back surface 8y is located on the same side, but in the semiconductor device 1b of the third embodiment, the back surface 2y of the semiconductor chip 2 is located on the back surface 8y side of the resin sealing body 8. In other words, the package structure is such that the back surface 2y of the semiconductor chip 2 and the back surface 8y of the resin sealing body 8 are located on the same side. Also in such a semiconductor device 1c, the same effect as in the first embodiment can be obtained.

(Embodiment 4)
The fourth embodiment is an example in which the present invention is applied to a semiconductor device in which two semiconductor chips are sealed with one resin sealing body.

  19 and 20 are cross-sectional views ((a), (b), (c)) showing the manufacturing process of the semiconductor device of this embodiment.

  In the semiconductor device 1d of this embodiment, as shown in FIG. 20C, two semiconductor chips 2 having the same structure are stacked with their back surfaces facing each other, and the two semiconductor chips 2 are sealed with one resin. The package structure is sealed with the body 8. Since the semiconductor device 1d of this embodiment is manufactured by superimposing two lead frames having the same lead pattern, the upper structure and the lower structure are formed with the mating surface of the two semiconductor chips 2 as a boundary. It is almost symmetrical.

  A plurality of leads 4 are arranged along one long side of one of the two long sides located on opposite sides of one semiconductor chip 2 (upper side in the drawing), and the other A plurality of leads 4 are arranged along the other long side on the long side. One side of the plurality of leads 4 on one long side is bonded and fixed to the main surface of one semiconductor chip 2 with the insulating tape 3 interposed therebetween, and the other end side is disposed on the side surface 8 a side of the resin sealing body 8. ing. The plurality of leads 4 on the other long side are bonded and fixed at one end side to the main surface of one semiconductor chip 2 with the insulating tape 3 interposed therebetween, and the other end side is disposed on the side surface 8b side of the resin sealing body 8. ing.

  A plurality of leads 4 are arranged along one long side of one of the two long sides located on opposite sides of the other semiconductor chip 2 (lower side in the figure), On the other long side, a plurality of leads 4 are arranged along the other long side. One side of the plurality of leads 4 on one long side is bonded and fixed to the main surface of one semiconductor chip 2 with the insulating tape 3 interposed therebetween, and the other end side is disposed on the side surface 8 a side of the resin sealing body 8. ing. The plurality of leads 4 on the other long side are bonded and fixed at one end side to the main surface of the other semiconductor chip 2 with the insulating tape 3 interposed therebetween, and the other end side is disposed on the side surface 8b side of the resin sealing body 8. ing.

  A plurality of external connection portions 5 are arranged on the main surface of the resin sealing body 8. A plurality of external connection portions 5 are also arranged on the back surface of the resin sealing body 8. These external connection parts 5 have a staggered arrangement similar to that of the first embodiment. Therefore, the semiconductor device 1d of the present embodiment can be mounted on the wiring board with the main surface or the back surface of the resin sealing body 8 as a mounting surface. Also, the same two semiconductor devices 1d can be stacked and mounted in the vertical direction.

  The lead 4 of the present embodiment is different in shape from the lead 4 of the first embodiment described above. The lead 4 of the first embodiment has a shape having two bent portions, but the lead 4 of the present embodiment has a shape having four bent portions. Therefore, the lead 4 of the present embodiment is bent to the first portion extending on the main surface of the semiconductor chip 2 and the mounting surface (main surface or back surface) side of the resin sealing body 8 from the first portion. A second part; a third part extending from the second part toward the side surface of the resin sealing body 8; a fourth part bent from the third part toward the semiconductor chip 2; and the fourth part. And a fifth portion extending from the portion toward the side surface of the resin sealing body 8. The external connection portion 5 is provided in the third portion, as in the first embodiment.

  The fifth portion of the upper lead 4 is electrically and mechanically connected to the corresponding fifth portion of the lower lead 4.

  Next, the manufacture of the semiconductor device 1d will be described with reference to FIGS.

  First, two lead frames having the same lead pattern are prepared, and the semiconductor chip 2 is bonded and fixed to one and the other lead frames. As shown in FIG. 19A, the lead frame and the semiconductor chip 2 are bonded and fixed by bonding and fixing one end of the lead 4 to the main surface of the semiconductor chip 2 with an insulating tape 3 interposed therebetween. .

  Next, in one and the other lead frames, the electrodes of the semiconductor chip 2 and the leads 4 are electrically connected by bonding wires 7 as shown in FIG. The connection between the lead 4 of one lead frame and the electrode of the semiconductor chip 2 is reverse-bonded so that the routing of the wire 7 is opposite to the connection between the lead 4 of the other lead frame and the electrode of the semiconductor chip 2. To do.

  Next, as shown in FIG. 19C and FIG. 20A, the semiconductor chip 2 of one lead frame and the back surface of the semiconductor chip 2 of the other lead frame face each other. The lead frames are overlapped, and then the fifth portion of the lead 4 of one lead frame and the fifth portion of the lead 4 of the other lead frame are electrically and mechanically connected. The lead 4 is connected by laser welding, for example.

  Next, as shown in FIG. 20B, the two semiconductor chips 2, the leads 4 of one and the other lead frames, the bonding wires 7 and the like are sealed with resin to form a resin sealing body 8. The resin sealing body 8 is formed by using the same sheet molding technique as in the first embodiment. However, in the case of the present embodiment, a resin sheet is interposed between the lower mold of the molding die and the lead frame, and between the upper mold of the molding die and the lead frame. As a result, a package is formed in which a plurality of external connection portions 5 are arranged in a staggered manner on the main surface and the back surface of the resin sealing body 8.

  Next, the resin sheet attached to the lead frame is peeled off, and the lead frame is taken out from the molding die. Thereafter, as shown in FIG. The solder layer 9 is formed on the substrate, and then a curing process for promoting the hardening of the resin sealing body 8 is performed. Then, a cutting process for separating the tie bars of the two lead frames, and a cutting process for separating the leads 4 from the frame body Etc., the semiconductor device 1d of the present embodiment is almost completed.

  Thus, since the semiconductor device 1d of this embodiment has a package structure in which the two semiconductor chips 2 are sealed with one resin sealing body 8, high-density mounting is possible.

  Moreover, since the semiconductor device 1d of the present embodiment has a package structure in which a plurality of external connection portions 5 are arranged in a staggered manner on the main surface and the back surface of the resin sealing body 8, the resin sealing body 8 The main surface or the back surface can be mounted on the wiring board as a mounting surface. Further, since the same two semiconductor devices 1d can be stacked and mounted in the vertical direction, higher-density mounting is possible.

(Embodiment 5)
The fifth embodiment is an example in which a semiconductor device in which two semiconductor chips are stacked is manufactured by a through mold method.

  21 to 23 are cross-sectional views ((a) and (b)) showing the manufacturing process of the semiconductor device of the fifth embodiment.

  First, two multiple lead frames having the same lead pattern are prepared, and then the die bonding process and the wire bonding process similar to those of the fourth embodiment are performed. Thereafter, as shown in FIG. The semiconductor chip 2 of one lead frame and the semiconductor chip 2 of the other lead frame face each other, and the one and other lead frames are overlapped.

  Next, as shown in FIG. 21B, the two lead frames and the lower die of the molding die 30 are overlapped between the two lead frames and the upper die 31 of the molding die 30. The resin sheet 24 is interposed between the upper and lower lead frames 32 and 32, respectively. In the two lead frames of this embodiment, a plurality of product formation regions are arranged in a matrix. Therefore, also in the molding die 30, a plurality of cavities 33 are arranged in a matrix corresponding to the product formation region of the lead frame. In the molding die 30, a resin injection gate 34 is provided for each row of a plurality of cavities, and the resin injection gate 34 is connected to the first-stage cavities 33 in each row. The adjacent cavities 33 in each row are connected by a through gate 35 (see FIG. 22A).

  Next, resin is pressurized and injected into the cavity 33 from the pot of the molding die 30 through the runner, the resin injection gate 34, etc., and as shown in FIG. The resin sealing body 8 is formed by sealing the lead 4 of the lead frame, the bonding wire 7 and the like with resin.

  Next, as shown in FIG. 22B, the two lead frames are taken out from the molding die 30, and then the fifth portion of the lead 4 of one lead frame and the second lead frame of the other lead frame. 5 is electrically and mechanically connected. The lead 4 is connected by laser welding, for example.

  Next, as shown in FIG. 23A, a curing process is performed in which a solder layer 9 is formed at the tip of the external connection portion 5 exposed from the resin sealing body 8, and then the curing of the resin sealing body 8 is promoted. 23, the cutting process for separating the tie bars of the two lead frames, the cutting process for separating the leads 4 from the frame body, and the like are performed, so that the semiconductor device 1e of this embodiment shown in FIG. Almost complete.

  Thus, also in this embodiment, the same effect as the above-mentioned Embodiment 4 is acquired.

(Embodiment 6)
The sixth embodiment is an example in which a semiconductor device in which two semiconductor chips are stacked is manufactured by a batch molding method.

24 to 25 are cross-sectional views ((a), (b), (c)) showing the manufacturing process of the semiconductor device of this embodiment,
FIG. 26 is a cross-sectional view showing the internal structure of the semiconductor device of this embodiment.

  In the semiconductor device 1g of the sixth embodiment, the planar size of the main surface and the back surface of the resin sealing body 8 is substantially the same, and the side surface of the resin sealing body 8 is substantially perpendicular to the main surface and the back surface. It has become. In the manufacture of the semiconductor device 1g of the present embodiment, the batch molding method is adopted. Therefore, as will be described in detail later, the semiconductor device 1g seals the semiconductor chips respectively mounted in the plurality of product formation regions of the lead frame with a single resin sealing body, and then the lead frame and the resin. It is manufactured by dividing the sealing body into product formation regions.

  Manufacture of the semiconductor device 1g of the present embodiment will be described with reference to FIGS.

  First, two multiple lead frames having the same lead pattern are prepared, and then the die bonding process and the wire bonding process similar to those of the fourth embodiment are performed. Thereafter, as shown in FIG. The semiconductor chip 2 of one lead frame and the semiconductor chip 2 of the other lead frame face each other, and the one and other lead frames are overlapped. At this time, the fifth portion of the lead 4 of one lead frame and the fifth portion of the lead 4 of the other lead frame are electrically and mechanically connected using a solder material or a conductive adhesive. To do.

  Next, as shown in FIG. 24B, the two lead frames overlapped with the upper die 41 of the molding die 40 and the lower die of the molding die 40 are placed as shown in FIG. With the resin sheet 24 interposed between the two lead frames 42, the two lead frames overlapped are positioned between the upper mold 31 and the lower mold 32 of the molding die 30. In the two lead frames of this embodiment, a plurality of product formation regions are arranged in a matrix. The molding die 40 according to the present embodiment includes a cavity 43 in which a plurality of product formation regions of the lead frame can be arranged collectively.

  Next, a resin is pressurized and injected into the cavity 43 from the pot of the molding die 40 through a runner, a resin injection gate 44, etc., and as shown in FIG. The resin sealing body 8 is formed by sealing the lead 4 of the lead frame, the bonding wire 7 and the like with resin.

  Next, two lead frames are taken out from the molding die 40, and then, as shown in FIG. 25B, a solder layer 9 is formed on the tip of the external connection portion 5 exposed from the resin sealing body 8. Thereafter, as shown in FIG. 25C, the two lead frames and the resin sealing body 8 are divided into product formation regions, whereby the semiconductor device 1g of this embodiment is almost completed.

  Thus, also in this embodiment, the same effect as the above-mentioned Embodiment 4 is acquired.

(Embodiment 7)
FIG. 27 is a cross-sectional view showing the internal structure of the semiconductor device of this embodiment.

  As shown in FIG. 27, the semiconductor device 1h of the present embodiment has basically the same configuration as that of the above-described sixth embodiment, and the following configuration is different.

  That is, the semiconductor device 1h according to the sixth embodiment has a package structure in which a plurality of external connection portions 5 are arranged in a staggered manner on the main surface and the back surface of the resin sealing body 8, but the semiconductor device according to the present embodiment. 1h has a package structure in which a plurality of external connection portions 5 are arranged in a staggered manner only on the back surface side of the resin sealing body 8. The semiconductor device 1h having such a package structure is manufactured by a batch molding method using a lead frame that does not have the external connection portion 5 as the lead 4 as one of the two lead frames. Also in the semiconductor device 1h of the present embodiment, the same effects as those of the first embodiment can be obtained.

(Embodiment 8)
FIG. 28 is a cross-sectional view showing the internal structure of the semiconductor device of this embodiment.

  The semiconductor device 1j of the present embodiment has a package structure in which one semiconductor chip 2 is sealed with one resin sealing body 8. The semiconductor device 1j of this embodiment is manufactured by a batch molding method using one lead frame. Also in the semiconductor device 1j of the present embodiment, the same effect as that of the first embodiment can be obtained.

(Embodiment 9)
FIG. 29 is a cross-sectional view showing the internal structure of the semiconductor device of this embodiment.

  The semiconductor device 1k of the present embodiment is a package in which two semiconductor chips (2, 50) having different structures are stacked with their back surfaces facing each other, and the two semiconductor chips are sealed with one resin sealing body 8. In addition, only a back surface side of the resin sealing body 8 has a package structure in which a plurality of external connection portions 5 are arranged in a staggered manner. The electrode of the semiconductor chip 50 is electrically connected to a lead 51 having a shape different from that of the lead 4 via a bonding wire, and the lead 51 is electrically and mechanically connected to a fifth portion of the lead 4. . Also in this embodiment, high-density mounting is possible.

(Embodiment 10)
FIG. 30 is a cross-sectional view showing the internal structure of the semiconductor device of this embodiment.

  As shown in FIG. 30, the semiconductor device 1m of the present embodiment has basically the same configuration as that of the ninth embodiment, and the following configurations are different.

  In other words, the semiconductor chip 50 is bonded and fixed to the lead 51 extended between the semiconductor chip 50 and the semiconductor chip 2 with an insulating adhesive interposed therebetween. Also in this embodiment, high-density mounting is possible.

(Embodiment 11)
FIG. 31 is a cross-sectional view showing the internal structure of the semiconductor device of this embodiment.

  As shown in FIG. 31, the semiconductor device 1n of the present embodiment has basically the same configuration as that of the ninth embodiment, and the following configurations are different.

  That is, the electrodes arranged on the main surface of the semiconductor chip 50 and the leads 51 are electrically and mechanically connected by the conductive bumps 52 interposed therebetween. Also in this embodiment, high-density mounting is possible.

Embodiment 12
FIG. 32 is a cross-sectional view showing a schematic configuration of the module of the present embodiment;
FIG. 33 is a cross-sectional view showing a first mounting method for mounting a semiconductor device in manufacturing the module of the present embodiment;
34 and 35 are cross-sectional views showing a second mounting method for mounting a semiconductor device in manufacturing the module of this embodiment.

  The module (electronic device) of this embodiment is mounted on the wiring board 53 in a state where two semiconductor devices 1g are stacked one above the other. In the lower semiconductor device 1g, the external connection portion 5 on the back surface of the resin sealing body 8 is electrically and mechanically connected to the electrode 54 of the wiring board 53 with the solder layer 9 interposed therebetween. The external connection portion 5 on the main surface is electrically and mechanically connected to the external connection portion 5 disposed on the back surface of the resin sealing body 8 of the upper semiconductor device 1g with the solder layer 9 interposed.

  The two semiconductor devices 1g are mounted in the manufacture of the module. There are the following two methods for mounting the two semiconductor devices 1g.

First implementation method:
As shown in FIG. 33, two semiconductor devices 1g are stacked one above the other and placed on the wiring board 53, and then the solder layer 9 is melted and mounted. In this case, materials having the same melting point are used as the solder layer 9 on the back surface side and the main surface side of the lower semiconductor device 1g and the solder layer 9 on the back surface side of the upper semiconductor device 1g.

Second implementation method:
As shown in FIG. 34, the lower semiconductor device 1g is mounted first, and then, as shown in FIG. 35, the upper semiconductor device 1g is mounted on the lower semiconductor device 1g. In this case, the solder layer 9 on the main surface side of the lower semiconductor device 1g and the solder layer 9 on the back surface side of the upper semiconductor device 1g have a melting point higher than that of the solder layer 9 on the back surface side of the lower semiconductor device 1g. A material with a high value is used.

  Thus, since the semiconductor device 1g has a package structure in which a plurality of external connection portions 5 are arranged in a staggered manner on the main surface and the back surface of the resin sealing body 8, the same two semiconductor devices 1g are arranged. The modules can be stacked and mounted in the vertical direction, and the module can be mounted with high density.

  In the present embodiment, an example in which the same two semiconductor devices 1g are stacked has been described. However, when two semiconductor devices are stacked, the upper semiconductor device is illustrated in FIG. 27 as the semiconductor device 1h or FIG. The semiconductor device 1j may be used.

  Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

It is a top view which shows the external appearance (main surface side) of the semiconductor device which is Embodiment 1 of this invention. It is a top view (bottom view) which shows the external appearance (back surface side) of the semiconductor device which is Embodiment 1 of this invention. It is a top view which shows the internal structure (back surface side) of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing to which a part of FIG. 3 was expanded. Sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 1 of this invention ((a) is sectional drawing which follows the AA line of FIG. 3, (b) is sectional drawing which follows the BB line of FIG. 3) It is. It is sectional drawing to which a part of Fig.5 (a) was expanded. It is a top view which shows a part of lead frame used in manufacture of the semiconductor device which is Embodiment 1 of this invention. It is the top view which expanded a part of FIG. Sectional drawing which shows a part of lead frame used in manufacture of the semiconductor device which is Embodiment 1 of this invention ((a) is sectional drawing which follows 1st lead | read | reed, (b) is sectional drawing which follows 2nd lead | read | reed) Figure). FIG. 4 is a cross-sectional view ((a) is a cross-sectional view in a die bonding process, and (b) is a cross-sectional view in a wire bonding step) during a manufacturing process of a semiconductor device according to Embodiment 1 of the present invention. In the molding process in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention, it is sectional drawing which follows a 1st lead | read | reed. It is sectional drawing to which a part of FIG. 11 was expanded. In the molding process in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention, it is sectional drawing which follows a 2nd lead | read | reed. It is sectional drawing to which a part of FIG. 13 was expanded. FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention ((a) is a cross-sectional view taken along a first lead, and (b) is a cross-sectional view taken along a second lead). In the molding process in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention, it is sectional drawing which follows a 1st lead | read | reed. In the molding process in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention, it is sectional drawing which follows a 2nd lead | read | reed. FIG. 7 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention ((a) is a cross-sectional view taken along a first lead, and (b) is a cross-sectional view taken along a second lead). It is sectional drawing ((a), (b), (c)) which shows the manufacturing process of the semiconductor device which is Embodiment 4 of this invention. It is sectional drawing ((a), (b), (c)) which shows the manufacturing process of the semiconductor device which is Embodiment 4 of this invention. It is sectional drawing ((a), (b)) which shows the manufacturing process of the semiconductor device which is Embodiment 5 of this invention. It is sectional drawing ((a), (b)) which shows the manufacturing process of the semiconductor device which is Embodiment 5 of this invention. It is sectional drawing ((a), (b)) which shows the manufacturing process of the semiconductor device which is Embodiment 5 of this invention. It is sectional drawing ((a), (b)) which shows the manufacturing process of the semiconductor device which is Embodiment 6 of this invention. It is sectional drawing ((a), (b), (c)) which shows the manufacturing process of the semiconductor device which is Embodiment 6 of this invention. It is sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 6 of this invention. It is sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 7 of this invention. It is sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 8 of this invention. It is sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 9 of this invention. It is sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 10 of this invention. It is sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 11 of this invention. It is sectional drawing which shows schematic structure of the module which is Embodiment 12 of this invention. It is sectional drawing which shows the 1st mounting method of a semiconductor device in manufacture of the module which is Embodiment 12 of this invention. It is sectional drawing which shows the 2nd mounting method of a semiconductor device in manufacture of the module which is Embodiment 12 of this invention. It is sectional drawing which shows the 2nd mounting method of a semiconductor device in manufacture of the module which is Embodiment 12 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a, 1b, 1c, 1d, 1f, 1g, 1h, 1j, 1k, 1m, 1n ... Semiconductor device, 2 ... Semiconductor chip, 2x ... Main surface (circuit formation surface), 2y ... Back surface, 3 ... Insulating tape (Insulating film), 4 ... lead, 4a ... first lead, 4b ... second lead, 5 ... external connection portion (external terminal portion), 5a ... first external connection portion, 5b ... second external Connection portion, 6 ... plating layer, 7 ... bonding wire, 8 ... resin sealing body, 8a, 8b ... side surface, 8x ... main surface, 8y ... back surface (mounting surface), 9 ... solder layer (plating layer), LF1 ... Lead frame, 10 ... frame main body, 11 ... product forming region, 12 ... tie bar, 20 ... molding die, 21 ... upper die, 21a ... first clamp portion, 22 ... lower die, 22a ... second clamp portion, 23 ... cavity, 24 ... resin sheet.

Claims (19)

A first lead; a second lead adjacent to the first lead; a first external connection provided on the first lead; provided on the second lead; and the first lead Preparing a lead frame having a second external connection portion located on one end side of the lead with respect to the external connection portion;
A first mold having a first clamping portion on the first mating surface and a cavity connected to the first clamping portion; a first clamping portion on a second mating surface facing the first mating surface; Providing a mold having a second mold having a second clamp portion facing each other;
Bonding and fixing one end side of the first and second leads to a semiconductor chip;
Electrically connecting a plurality of electrodes arranged on the main surface of the semiconductor chip and the first and second leads, respectively;
The other end side opposite to the one end side of the first and second leads is sandwiched from above and below by the first and second clamp portions, and the first and second leads and the second mating surface Injecting resin into the cavity in a state where the first and second external connection portions are in contact with a resin sheet disposed between the semiconductor chip, the first lead, and the second lead A step of resin sealing;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
One end of each of the first and second leads is bonded and fixed to the main surface of the semiconductor chip. In the manufacturing method of the semiconductor device according to claim 1,
The first and second leads extend across an outer peripheral side of the semiconductor chip;
The method of manufacturing a semiconductor device, wherein the first and second external connection portions are provided in portions of the first and second leads around the semiconductor chip. In the manufacturing method of the semiconductor device according to claim 1,
The first and second leads include a first portion extending on a main surface of the semiconductor chip, a second portion bent from the first portion to the second mating surface, and the first lead A third portion extending from the two portions toward the first and second clamp portions,
The method of manufacturing a semiconductor device, wherein the first and second external connection portions are provided in a third portion of each of the first and second leads. In the manufacturing method of the semiconductor device according to claim 4,
A method of manufacturing a semiconductor device, wherein a first portion of each of the first and second leads is bonded and fixed to a main surface of a semiconductor chip. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor device manufacturing method, wherein a main surface of the semiconductor chip faces the resin sheet. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein a back surface opposite to the main surface of the semiconductor chip is in contact with an inner wall surface of the cavity. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein a back surface opposite to a main surface of the semiconductor chip faces the resin sheet. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the first and second external connection portions are wider than the third portions of the first and second leads. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the first and second external connection portions are thicker than the first and second leads. In the manufacturing method of the semiconductor device according to claim 1,
An electrical connection between the electrode of the semiconductor chip and the first and second leads is performed by a bonding wire. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor chip is formed in a square shape in a plane shape intersecting the thickness direction thereof,
The method for manufacturing a semiconductor device, wherein the plurality of electrodes are arranged in a central arrangement along one of the two center lines of the main surface of the semiconductor chip. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first and second leads are bonded and fixed to the semiconductor chip via an insulating tape. (A) A step of preparing a lead frame having first and second leads provided with a first end and a second end facing the first end and including an external connection portion. When,
(B) preparing a semiconductor chip having a plurality of electrodes arranged on the main surface;
(C) bonding the semiconductor chip to the lead frame so that the first end of each of the first and second leads is fixed to the main surface of the semiconductor chip;
(D) After the step (c), the lead frame including the semiconductor chip is arranged such that the first end of each of the semiconductor chip and the first and second leads has an upper mold and a lower mold. Placing the second end side of each of the first and second leads between the upper mold and the lower mold of the molding die, and placing the first and second leads in a cavity defined by a mold;
(E) A resin sealing body that injects resin into the cavity of the molding die by a transfer molding method and seals the first end of each of the semiconductor chip and the first and second leads. Forming a step;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 14,
After the step (b) and before the step (c), the first end of each of the first and second leads and the plurality of electrodes of the semiconductor chip are connected to a plurality of bonding wires. A method for manufacturing a semiconductor device, comprising the step of electrically connecting through a semiconductor device. In the manufacturing method of the semiconductor device according to claim 14,
The method of manufacturing a semiconductor device, wherein the second end of each of the first and second leads is disposed outside the semiconductor chip. In the manufacturing method of the semiconductor device according to claim 14,
In the step (d), after disposing a resin sheet between the lead frame and the lower mold of the molding die, the external connection portions of the first and second leads are bitten into the resin sheet. A method of manufacturing a semiconductor device comprising the step of sandwiching the second end side of each of the first and second leads between the upper mold and the lower mold of the molding die. In the manufacturing method of the semiconductor device according to claim 14,
After the step (e), the external connection portion of each of the first and second leads is exposed from the back surface of the resin sealing body. In the manufacturing method of the semiconductor device according to claim 14,
After the step (e), the external connection portion of each of the first and second leads protrudes from the back surface of the resin sealing body.

Images