JP2001298144A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2001298144A JP2001298144A JP2000111466A JP2000111466A JP2001298144A JP 2001298144 A JP2001298144 A JP 2001298144A JP 2000111466 A JP2000111466 A JP 2000111466A JP 2000111466 A JP2000111466 A JP 2000111466A JP 2001298144 A JP2001298144 A JP 2001298144A
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- Prior art keywords
- semiconductor device
- resin
- islands
- lead
- semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に、底面端子型の半導体装置に適
用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a technology effective when applied to a bottom terminal type semiconductor device.
【０００２】[0002]
【従来の技術】半導体集積回路装置では、微細化の進展
によって、より多くの回路を単一の半導体チップに搭載
する高集積化が進められている。しかしながら、半導体
集積回路を構成する全ての素子を単一チップに集積した
場合には、モデルチェンジ等に伴う些細な仕様変更の度
に、集積回路の再設計を行なうこととなり、迅速な対応
が困難となる。そこで、こうした軽微な変更に対応する
ために、トランジスタ等回路素子の一部を集積化せずに
実装基板上で半導体集積回路に外付けする構成とし、こ
の外付けする回路素子を変えることによって、同一の半
導体集積回路装置を用いたままで軽微な変更に対応する
方法が採用されている。2. Description of the Related Art In semiconductor integrated circuit devices, with the advance of miniaturization, high integration of mounting more circuits on a single semiconductor chip has been promoted. However, if all the elements that make up a semiconductor integrated circuit are integrated on a single chip, the integrated circuit must be redesigned every time a small specification change occurs due to a model change or the like, making it difficult to respond quickly. Becomes Therefore, in order to cope with such minor changes, a configuration is adopted in which a part of circuit elements such as transistors are externally mounted on a semiconductor integrated circuit on a mounting board without being integrated, and by changing the externally mounted circuit elements, A method of coping with minor changes while using the same semiconductor integrated circuit device is adopted.
【０００３】そして、半導体分野においては、顧客実装
面積・容積縮小を目的とした個別半導体装置の薄型化・
小型化が常に求められている。こうした単体の回路素子
にも小型化が求められており、例えば単体のトランジス
タでは、顧客要求により外形寸法１００６（平面形状１
ｍｍ×０．６ｍｍ）、或いは外形寸法０８０４（平面形
状０．８ｍｍ×０．４ｍｍ）といった微小な半導体装置
が求められている。In the field of semiconductors, individual semiconductor devices have been reduced in thickness to reduce customer mounting area and volume.
Miniaturization is always required. Such a single circuit element is also required to be reduced in size. For example, in the case of a single transistor, an external dimension 1006 (planar shape 1
mm × 0.6 mm) or a small semiconductor device having an outer dimension of 0804 (a planar shape of 0.8 mm × 0.4 mm) is demanded.
【０００４】こうした半導体装置を製造する方法として
は、例えば、特開平１１‐１０２９２４号公報に、セラ
ミック又はガラスエポキシ樹脂の基板を用い、トランス
ファーモールド方式またはポッティング方式によって樹
脂封止を行ない、封止後にダイシングにより切断・分離
して個別の半導体装置を形成する技術が記載されてい
る。As a method of manufacturing such a semiconductor device, for example, Japanese Patent Application Laid-Open No. H11-102924 discloses a method in which a ceramic or glass epoxy resin substrate is used, and resin sealing is performed by a transfer molding method or a potting method. A technique is described in which individual semiconductor devices are cut and separated by dicing to form individual semiconductor devices.
【０００５】この技術では、半導体装置は、多層のセラ
ミック基板の上面に形成された搭載部に、半導体素子の
ダイボンディングを行い、半導体素子の電極パッドとセ
ラミック基板の電極端子とをボンディングワイヤにより
接続し、前記電極端子が基板の底面に形成された外部端
子と基板の内部配線によって接続され、半導体素子、基
板の上面及び内側面、ボンディングワイヤを樹脂を用い
た封止体によって封止してある。In this technique, a semiconductor device performs die bonding of a semiconductor element on a mounting portion formed on an upper surface of a multilayer ceramic substrate, and connects an electrode pad of the semiconductor element to an electrode terminal of the ceramic substrate by a bonding wire. The electrode terminals are connected to external terminals formed on the bottom surface of the substrate by internal wiring of the substrate, and the semiconductor element, the upper surface and the inner surface of the substrate, and the bonding wires are sealed by a sealing body using a resin. .
【０００６】この半導体装置の製造方法では、複数の半
導体装置の基板が行列状に複数連続して形成されてお
り、個々の半導体装置のダイボンディング・ワイヤボン
ディングが行なわれた後に、基板上面の複数の半導体素
子及びボンディングワイヤ等を樹脂により一括して封止
した後、ダイシングを用いて夫々切断し個別半導体装置
を形成する。In this method of manufacturing a semiconductor device, a plurality of substrates of a plurality of semiconductor devices are continuously formed in a matrix, and after die bonding and wire bonding of each semiconductor device are performed, a plurality of substrates on the upper surface of the substrate are formed. After the semiconductor elements and the bonding wires are collectively sealed with a resin, they are individually cut using dicing to form individual semiconductor devices.
【０００７】この技術では、モールド時のゲート寸法に
係らず、個別半導体の外形寸法の縮小が可能となる。し
かし、セラミック基板のコストが従来のＣｕ、４２アロ
イ等を材料としたリードフレームに比べて高価であり、
加えて基板表面には、金等の高価なメッキを導体として
施さなければならないので製造原価が上昇する。また、
セラミックは焼結材料の為、セラミック基板の焼成工程
にて、焼成後の収縮誤差及び反りの問題が生じ、基板の
歩留まり向上に限界がある等のデメリットが有り、更
に、この結果、基板不具合部に不良処置（マーキング
等）を施し、ダイボンディング時には不良部分にダイボ
ンドを行なわないように工夫する等の処理が増加するこ
ととなる。According to this technique, the outer dimensions of the individual semiconductor can be reduced irrespective of the gate dimensions at the time of molding. However, the cost of the ceramic substrate is higher than that of a conventional lead frame made of Cu, 42 alloy, or the like.
In addition, expensive plating such as gold must be applied to the surface of the substrate as a conductor, which increases the manufacturing cost. Also,
Since ceramic is a sintered material, in the firing process of the ceramic substrate, there are disadvantages such as shrinkage error and warping after firing, and there is a limit in improving the yield of the substrate. In such a case, the number of processes such as performing a defect treatment (such as marking) on the substrate and devising not to perform die bonding on the defective portion during die bonding increases.
【０００８】また、セラミック基板を用いた場合、セラ
ミックが脆性をもっているために、上下金型により挟持
しクランプ圧力を付加した時点で、若干の基板の反りに
よっても破損するおそれがあるので、従来方式である金
型を用いたスルーモールド方式の採用は困難であり、レ
ジンを塗布する等の別方法を用いる必要がある。レジン
を塗布する場合、塗布の厚み及び平坦度の制御が難しく
なる等の問題点が残っている。更に、基板上面を一括し
て樹脂封止する為、樹脂の収縮作用により分割前に大き
な反りを生ずる。更には、ダイシング方法等に依って切
削切断したパッケージの側面（セラミックと樹脂との接
合界面）より水分が進入し、完成品の長期信頼性に影響
を及ぼす可能性が有る等の問題点が、発明者等により明
らかとなった。Further, when a ceramic substrate is used, since the ceramic is brittle, there is a possibility that even when the substrate is clamped by upper and lower molds and a clamping pressure is applied, the substrate may be broken even by a slight warpage of the substrate. It is difficult to adopt a through-mold method using a mold, and it is necessary to use another method such as applying a resin. When applying the resin, there remain problems such as difficulty in controlling the thickness and flatness of the application. Further, since the upper surface of the substrate is collectively sealed with a resin, a large warpage occurs before the division due to the shrinkage of the resin. Further, there is a problem that moisture enters from a side surface (joining interface between ceramic and resin) of the package cut and cut by a dicing method or the like, which may affect long-term reliability of a finished product. It became clear by the inventors.
【０００９】他に、例えば特開平１０‐３１３０８２公
報には、リードフレームに複数の半導体素子を搭載し、
トランスファーモールド方式又はポッティング方式を用
いて一括樹脂封止し、ダイシングによって個別の半導体
装置に切断・分離する方法が開示されている。In addition, for example, Japanese Patent Application Laid-Open No. 10-313082 discloses that a plurality of semiconductor elements are mounted on a lead frame,
A method has been disclosed in which a resin is collectively sealed using a transfer molding method or a potting method, and cut and separated into individual semiconductor devices by dicing.
【００１０】しかしながらこの方法では、基板上面を一
括して樹脂封止する為、比較的広い面積を１つのキャビ
ティとして封止することとなり、封止後に樹脂が硬化す
る際の収縮作用による応力によって、樹脂の分割前に大
きな大きな反りやねじれが生じてしまう。加えて、半導
体素子の搭載されるアイランド下面及びリード電極下面
が、半導体装置下面に露出する為、個別半導体装置の封
止体としては封止体下面部の絶縁範囲を広くすることが
難しい。その結果として、実装基板の回路設計時にアイ
ランド下面及びリード電極下面と配線との電気的ショー
トを回避する配慮が必要となる。半導体装置の下に位置
する基板領域に配線を通すことが難しくなり、回路設計
の自由度が低下する。また、搭載する半導体素子がパッ
ケージ寸法に近くなるに連れて、アイランド寸法を大き
くする必要があり、アイランド部とリード電極との距離
を十分に確保することが次第に困難となる。However, in this method, since the upper surface of the substrate is collectively sealed with a resin, a relatively large area is sealed as one cavity. Before splitting the resin, large and large warpage or twisting occurs. In addition, since the lower surface of the island and the lower surface of the lead electrode on which the semiconductor element is mounted are exposed on the lower surface of the semiconductor device, it is difficult to widen the insulation range of the lower surface of the sealing body for the individual semiconductor device. As a result, it is necessary to take care to avoid an electrical short between the lower surface of the island and the lower surface of the lead electrode and the wiring when designing the circuit of the mounting board. It becomes difficult to pass wiring through the substrate region located below the semiconductor device, and the degree of freedom in circuit design is reduced. Further, as the semiconductor element to be mounted becomes closer to the package size, it is necessary to increase the island size, and it becomes increasingly difficult to secure a sufficient distance between the island portion and the lead electrode.
【００１１】更に、前記半導体装置外形の一部は、封止
体の絶縁材料が硬化した後に切断された面によって構成
されるため、切断面からの水分の進入による個別半導体
装置の封止信頼性低下という問題が残っている。また、
個別半導体装置に切断する際の作業性及び切断精度に関
して充分な検討が為されていない等の問題点も有る。Further, since a part of the outer shape of the semiconductor device is constituted by a surface cut after the insulating material of the sealing body is cured, the sealing reliability of the individual semiconductor device due to the ingress of moisture from the cut surface. The problem of decline remains. Also,
There is also a problem that workability and cutting accuracy in cutting into individual semiconductor devices have not been sufficiently studied.
【００１２】[0012]
【発明が解決しようとする課題】こうした問題点を踏ま
えて、本発明者等は、個々の半導体装置に用いられるア
イランド或いはリードの組を複数組一体に形成したリー
ドフレームに、複数の半導体素子のダイボンディングを
行ない、複数の半導体素子を列毎に一つのキャビティと
して一体に封止体をモールドし、前記キャビティ及びリ
ードフレームを切断して、個別の半導体装置に分離する
技術を発明し、特願平１１‐１９９８９７号として出願
した。In view of these problems, the present inventors have developed a plurality of semiconductor elements on a lead frame integrally formed with a plurality of sets of islands or leads used for individual semiconductor devices. Invented a technology of performing die bonding, integrally molding a sealing body with a plurality of semiconductor elements as one cavity for each column, cutting the cavity and the lead frame, and separating the semiconductor devices into individual semiconductor devices. Filed as Hei 11-199897.
【００１３】この技術では、個別の半導体装置に分離す
る際に、キャビティの樹脂とリードフレームの金属をダ
イシングブレードを用いて同時に切断しているが、切断
時の応力によって金属と樹脂との接合面に亀裂の生じる
ことがある。この亀裂が大きい場合には半導体素子の接
合界面又はワイヤボンディング接合部に達し不良品とな
り、亀裂が小さい場合にも温度サイクル・吸湿等の影響
によって経時的に半導体装置の信頼性を低下させること
がある。According to this technique, the resin of the cavity and the metal of the lead frame are simultaneously cut using a dicing blade when the semiconductor device is separated into individual semiconductor devices. Cracks may occur. If the crack is large, it may reach the bonding interface of the semiconductor element or the wire bonding joint, resulting in a defective product. Even if the crack is small, the reliability of the semiconductor device may decrease over time due to the effects of temperature cycling, moisture absorption, etc. is there.
【００１４】また、ダイシングブレードによって金属を
切断する場合には、特に銅等の比較的軟らかい金属の場
合には、切断面にダレと通称される上下方向への変形が
生じ、この変形が底面に設けられる外部電極の端部に生
じた場合には、電極面の平坦度が低下し、実装不良を生
じることがある。In the case of cutting a metal with a dicing blade, particularly in the case of a relatively soft metal such as copper, a vertical deformation called a sag occurs on the cut surface, and this deformation is generated on the bottom surface. When it occurs at the end of the external electrode provided, the flatness of the electrode surface is reduced, and a mounting failure may occur.
【００１５】また、用いるブレードは樹脂と金属とを併
せて切断するのでブレードを何れかに最適化することが
できないため、銅等の比較的軟らかい金属をリードフレ
ームに用いた場合等には、この切断の際にブレードに金
属の目づまりが生じることがあり、場合によっては、こ
うした目づまりによって分離工程の進捗が影響を受ける
ことがある。Further, since the blade to be used cuts the resin and the metal together, the blade cannot be optimized to any one. Therefore, when a relatively soft metal such as copper is used for the lead frame, this blade is not used. During cutting, the blades may become clogged with metal, and in some cases, such clogging may affect the progress of the separation process.
【００１６】本発明の課題は、こうした問題を解決し、
微小な半導体装置の封止体を比較的容易に低コストで行
ない得る技術の更なる信頼性及び生産性の向上を図るこ
とにある。An object of the present invention is to solve such problems.
It is an object of the present invention to further improve the reliability and productivity of a technique capable of relatively easily sealing a small semiconductor device at low cost.
【００１７】本発明の前記ならびにその他の課題と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１８】[0018]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.
【００１９】アイランドに固定した半導体素子とリード
とを接続し封止体によって封止した半導体装置におい
て、前記アイランド或いはリードが封止体底面にて露出
して半導体装置の外部端子となり、このアイランド或い
はリードの外端部が、前記封止体の相対する２側面に露
出し、前記２側面と直交する他の２側面には露出してい
ない構成とする。In a semiconductor device in which a semiconductor element fixed to an island and a lead are connected and sealed by a sealing body, the island or the lead is exposed at the bottom surface of the sealing body and becomes an external terminal of the semiconductor device. The outer ends of the leads are exposed on two opposite sides of the sealing body and are not exposed on the other two sides orthogonal to the two sides.
【００２０】また、その製造方法では、個々の半導体装
置に用いられるアイランド或いはリードの組を行列状に
複数組設け、行方向に隣接するアイランド或いはリード
を連続させて一体に形成したリードフレームを用意し、
このリードフレームの各アイランドに夫々半導体素子の
ダイボンディングを行ない、前記夫々の半導体素子と前
記リードとを電気的に接続し、半導体素子、アイランド
及びリードを封止する前記封止体を、列毎に複数を一体
に一つのキャビティとして樹脂モールドし、前記封止体
の列間の樹脂及びリードフレームをプレス切断し、前記
封止体の行間のキャビティをブレード切断して個別の半
導体装置に分離する。In the manufacturing method, a plurality of sets of islands or leads used in individual semiconductor devices are provided in a matrix, and a lead frame is formed by integrally forming adjacent islands or leads in a row direction. And
The semiconductor element is die-bonded to each of the islands of the lead frame, the respective semiconductor elements are electrically connected to the leads, and the sealing element for sealing the semiconductor elements, the islands, and the leads is provided for each column. A plurality of resin molds are integrally formed as one cavity, the resin and the lead frame between the columns of the sealing body are press-cut, and the cavities between the rows of the sealing body are cut into blades to be separated into individual semiconductor devices. .
【００２１】かかる本発明によれば、半導体素子寸法に
近似した半導体装置（ＣＳＰ：チップサイズパッケー
ジ）に関し、個別半導体素子搭載基板として金属材料を
用いたリードフレームの使用が可能となり、セラミック
基板を用いた場合より安価に製造することができる。According to the present invention, a semiconductor device (CSP: chip size package) having dimensions similar to those of a semiconductor element can be used as a substrate for mounting an individual semiconductor element by using a lead frame using a metal material. It can be manufactured cheaper than it would be.
【００２２】また、半導体装置下面に、絶縁層を樹脂モ
ールド方法により形成したことにより、実装基板上に形
成された回路配線との電気的短絡を防止することができ
る。Further, since the insulating layer is formed on the lower surface of the semiconductor device by the resin molding method, it is possible to prevent an electrical short circuit with the circuit wiring formed on the mounting substrate.
【００２３】また、リードフレームをプレス切断するの
で、前記ダイシングによるダレの発生を防止することが
できるので、実装不良の発生を防止することができる。Further, since the lead frame is press-cut, the occurrence of sagging due to the dicing can be prevented, so that the occurrence of defective mounting can be prevented.
【００２４】更に、ブレードを用いた切断では樹脂のみ
を切断するので、用いるブレードを樹脂の切断に最適化
することが可能となり、切断を円滑に進捗させることが
できる。Furthermore, in cutting using a blade, only the resin is cut, so that the blade to be used can be optimized for cutting the resin, and the cutting can proceed smoothly.
【００２５】加えて、複数の半導体素子を列毎に一つの
キャビティとして樹脂封止することによって、熱または
樹脂の収縮作用による反りを防止しつつ、仕上がり寸法
精度の良い個別半導体装置を提供することが可能とな
る。In addition, it is possible to provide an individual semiconductor device having a high finished dimensional accuracy while preventing warpage due to heat or resin shrinkage action by sealing a plurality of semiconductor elements as one cavity for each column with resin. Becomes possible.
【００２６】[0026]
【発明の実施の形態】以下、本発明の実施の形態を説明
する。なお、実施の形態を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。Embodiments of the present invention will be described below. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
【００２７】（実施の形態１）図１は本発明の一実施の
形態である半導体装置を封止体を透過して示す斜視図で
あり、図２は本発明の一実施の形態である半導体装置を
示す斜視図及びその底面の投影図である。(Embodiment 1) FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention through a sealing body, and FIG. 2 is a semiconductor device according to an embodiment of the present invention. FIG. 2 is a perspective view showing the apparatus and a projection view of a bottom surface thereof.
【００２８】本実施の形態の半導体装置では、単結晶シ
リコン等の半導体基板にＦＥＴ等の所定の素子を形成し
た半導体素子１を、例えば金等のロー材によってアイラ
ンド２に固定し、半導体素子１とリード３とをボンディ
ングワイヤ４によって接続してある。半導体素子１をダ
イボンディングするアイランド２には下面部内方及び外
方に凹部が設けられ、リード３には下面部外方に凹部が
設けられている。In the semiconductor device according to the present embodiment, a semiconductor element 1 in which a predetermined element such as an FET is formed on a semiconductor substrate such as single crystal silicon is fixed to an island 2 by a brazing material such as gold. And the lead 3 are connected by a bonding wire 4. An island 2 for die-bonding the semiconductor element 1 is provided with concave portions inside and outside the lower surface, and a lead 3 is provided with concave portions outside the lower surface.
【００２９】半導体素子１、アイランド２、リード３の
上面及び側面、ボンディングワイヤ４は、例えばエポキ
シ樹脂にフィラを混入させた封止樹脂を用いた封止体５
によって封止され、前記下面部の凹部も封止体５によっ
て覆われており、アイランド２及びリード３の外端部の
下面或いは角部には凹部が設けられている。アイランド
２の上面と半導体素子１の裏面電極とは導電性の接続が
されており、アイランド２の下面及びリード３の下面が
封止体５の底面から選択的に露出して半導体装置の外部
電極となる。The semiconductor element 1, the island 2, the upper and side surfaces of the leads 3, and the bonding wires 4 are made of a sealing body 5 using a sealing resin in which a filler is mixed into an epoxy resin, for example.
The concave portion on the lower surface is also covered with the sealing body 5, and a concave portion is provided on the lower surface or the corner of the outer end of the island 2 and the lead 3. The upper surface of the island 2 and the back electrode of the semiconductor element 1 are electrically conductively connected, and the lower surface of the island 2 and the lower surface of the lead 3 are selectively exposed from the bottom surface of the sealing body 5 so that the external electrode of the semiconductor device is exposed. Becomes
【００３０】封止体５の短手方向に沿った側面（以下、
短側面という）下部にはわずかに張出した平坦部５ａが
形成されており、この平坦部５ａではアイランド２及び
リード３の端部上面及び外端部が露出しているが、アイ
ランド２或いはリード３の端部は、封止体５の長手方向
に沿った側面（以下、長側面という）には露出していな
い。A side surface (hereinafter, referred to as a lateral direction) of the sealing body 5 along the lateral direction.
A slightly protruding flat portion 5a is formed at a lower portion (referred to as a short side surface). In this flat portion 5a, the upper surface and the outer end of the end of the island 2 and the lead 3 are exposed. Are not exposed on a side surface (hereinafter, referred to as a long side surface) of the sealing body 5 along the longitudinal direction.
【００３１】封止体５から露出して外部電極となるアイ
ランド２の部分及びリード３の部分の厚さは、封止体５
から露出しないアイランド２の部分及びリード３の部分
の厚さよりも厚い構造となっており、アイランド２の下
面内方に凹部を形成し、樹脂封止を行うことによって半
導体装置の下面部電極間の絶縁層を広げることが可能と
なり、実装基板の回路配線との電気的短絡防止ができ
る。この結果、半導体装置実装基板設計時、パッケージ
下面絶縁部に回路配線を配置することが可能となり、実
装基板の縮小化に寄与することができる。The thickness of the part of the island 2 and the part of the lead 3 exposed from the sealing body 5 and serving as external electrodes is
It has a structure thicker than the thickness of the part of the island 2 and the part of the lead 3 which are not exposed from the outside. The insulating layer can be expanded, and electrical short-circuit with the circuit wiring on the mounting board can be prevented. As a result, at the time of designing a semiconductor device mounting board, it is possible to arrange circuit wiring in the insulating portion on the lower surface of the package, which can contribute to downsizing of the mounting board.
【００３２】また、アイランド２とリード３との下面部
外方に凹部を設け、外端の下面を夫々内側に後退させる
ことによって、半導体装置の底面では、アイランド２及
びリード３の電極として機能する露出面が封止体５と同
一平面となり、かつその周囲が封止体５によって囲まれ
ている。このため外部電極はアイランド２及びリード３
の露出面に施されたメッキの厚さ分周囲の封止体５から
均等に浮き出た形状となり、ハンダ付け等による実装基
板への実装を確実に行なうことができる。Further, a concave portion is provided outside the lower surface of the island 2 and the lead 3 and the lower surface of the outer end is retreated inward, thereby functioning as an electrode of the island 2 and the lead 3 on the bottom surface of the semiconductor device. The exposed surface is flush with the sealing body 5, and the periphery thereof is surrounded by the sealing body 5. Therefore, the external electrodes are the island 2 and the lead 3
The shape becomes evenly protruded from the surrounding sealing body 5 by the thickness of the plating applied to the exposed surface, and the mounting to the mounting board by soldering or the like can be reliably performed.
【００３３】続いて、本実施の形態の半導体装置の製造
方法について、図３乃至図１４を用いて説明する。Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.
【００３４】図３は本実施の形態の半導体装置の製造に
用いられるリードフレームを示す平面図であり、図４は
図３中のａ部を拡大して示す平面図及び縦断面図であ
る。リードフレーム６には、図４中に破線にて示す封止
体５形成領域毎に、個別の半導体装置となる夫々のアイ
ランド２及びリード３が、行列状に連続的に形成してあ
る。夫々のアイランド２及びリード３は、行方向にアイ
ランド２とリード３とが交互に配置され、列方向には隣
接する封止領域間にて即ち封止領域外で連結されてい
る。FIG. 3 is a plan view showing a lead frame used for manufacturing the semiconductor device of the present embodiment, and FIG. 4 is an enlarged plan view and a vertical sectional view showing a portion a in FIG. In the lead frame 6, the islands 2 and the leads 3, which are individual semiconductor devices, are continuously formed in a matrix in each of the sealing body 5 forming regions indicated by broken lines in FIG. Each of the islands 2 and the leads 3 has the islands 2 and the leads 3 alternately arranged in the row direction, and is connected between the adjacent sealing regions in the column direction, that is, outside the sealing region.
【００３５】リードフレーム６としては、銅系または鉄
系の材料を用いるので、多層セラミック基板を用いる場
合に比べて、半導体素子寸法に近似した半導体装置の材
料費を抑制することができる。Since the lead frame 6 is made of a copper-based or iron-based material, it is possible to reduce the material cost of the semiconductor device which is close to the dimensions of the semiconductor element, as compared with the case where a multilayer ceramic substrate is used.
【００３６】先ず、リードフレーム６のアイランド２上
に半導体素子１が適切な接合ロー材によってダイボンデ
ィングされる。この際、リードフレーム下面のアイラン
ド２の凹部に対応させて凹凸を設けたヒートブロックに
よって接触加熱されることによってリードフレーム６は
適切な接合温度条件下に保持される。ダイボンディング
後、ボンディングワイヤ４により半導体素子１の電極パ
ッドとリード３の上面とを電気的に接続するワイヤボン
ディングを行なう。このダイボンディング及びワイヤボ
ンディング作業はリードフレーム６に配置した全てのア
イランド２及びリード３に対して施される。First, the semiconductor element 1 is die-bonded on the island 2 of the lead frame 6 using a suitable bonding material. At this time, the lead frame 6 is maintained under an appropriate bonding temperature condition by being contact-heated by a heat block provided with projections and depressions corresponding to the depressions of the island 2 on the lower surface of the lead frame. After die bonding, wire bonding for electrically connecting the electrode pads of the semiconductor element 1 and the upper surfaces of the leads 3 with the bonding wires 4 is performed. The die bonding and wire bonding operations are performed on all the islands 2 and the leads 3 arranged on the lead frame 6.
【００３７】こうしてダイボンディング及びワイヤボン
ディングを完了したリードフレーム６をトランスファー
モールド装置の下金型にセットし、その後、上金型によ
りリードフレーム６を挟み込み、封止樹脂を注入し、各
列を夫々一つのキャビティ７として、その列に並ぶ複数
の半導体素子１を一体に封止する樹脂封止を行なう。The lead frame 6 on which the die bonding and the wire bonding have been completed is set in a lower mold of a transfer molding apparatus, and thereafter, the lead frame 6 is sandwiched by an upper mold, a sealing resin is injected, and each row is individually set. As one cavity 7, resin sealing for integrally sealing the plurality of semiconductor elements 1 arranged in the row is performed.
【００３８】この樹脂封止では、リードフレーム６下面
の凹部にも樹脂が十分に充填される様に行い、この凹部
に充填された封止樹脂は、個別半導体装置に分割した後
は、半導体装置底面の絶縁層の役割を果たす。各キャビ
ティ７に充填した半導体封止用樹脂を硬化させた後、次
工程前に不要な樹脂部分であるランナ７ａ及びゲート７
ｂを切除する。この状態の平面図を図５に示し、図５中
のａ部を拡大した平面図及び縦断面図を図６に、斜視図
を図７に示す。なお、図５中ではキャビティ７、ランナ
７ａ及びゲート７ｂ以外の樹脂が充填される部分に斜線
を付してある。In this resin encapsulation, the resin is sufficiently filled also in the concave portion on the lower surface of the lead frame 6, and after the sealing resin filled in the concave portion is divided into individual semiconductor devices, Acts as an insulating layer on the bottom. After the semiconductor sealing resin filled in each cavity 7 has been cured, the runner 7a and the gate
Cut off b. FIG. 5 shows a plan view of this state, FIG. 6 shows a plan view and a longitudinal cross-sectional view in which an a portion in FIG. 5 is enlarged, and FIG. 7 shows a perspective view. In FIG. 5, the portions filled with resin other than the cavity 7, the runner 7a and the gate 7b are shaded.
【００３９】本実施の形態では一列に並んだ複数の封止
体５を列毎に一つのキャビティ７として樹脂封止するこ
とによって、封止樹脂の硬化時に生ずる収縮に影響され
て、リードフレーム６が行方向に湾曲或いは反って、全
体が変形するのを防止することができる。この結果、リ
ードフレーム６の大型化が可能となり、取得数を増やす
ことができる。なお、キャビティ７列間にキャビティ７
と平行にリードフレームの略全幅にわたってスリットを
設けることによって、熱応力或いは封止後の樹脂硬化の
過程において生じるレジン収縮等の変形を抑制すること
も可能である。In the present embodiment, a plurality of sealing bodies 5 arranged in a row are resin-sealed as one cavity 7 for each row, so that the shrinkage generated when the sealing resin is cured is influenced by the lead frame 6. Can be prevented from being curved or warped in the row direction and thus entirely deformed. As a result, the size of the lead frame 6 can be increased, and the number of acquisitions can be increased. In addition, the cavity 7
By providing slits over substantially the entire width of the lead frame in parallel with the above, it is also possible to suppress deformation such as resin shrinkage that occurs during the resin curing process after sealing or thermal stress.
【００４０】また、例えば一つの列に形成される半導体
装置の数が多いためにキャビティ７が長くなると列方向
にレジンの反りが生じる場合がある。そうした場合に
は、キャビティ７を列方向に分割する。即ち、複数の半
導体装置を列毎に樹脂封止するキャビティ７を列方向に
複数形成する構成とすることも可能である。Further, for example, since the number of semiconductor devices formed in one row is large, if the cavity 7 becomes long, the resin may be warped in the column direction. In such a case, the cavity 7 is divided in the column direction. That is, a plurality of cavities 7 for resin-sealing a plurality of semiconductor devices for each column may be formed in the column direction.
【００４１】次に、アイランド２及びリード３のキャビ
ティ７から露出する部分が半導体装置の外部電極となる
リードフレーム６下面にハンダ等のメッキを施す。この
メッキに先立って液体ホーニング等の処理によるメッキ
付着面に付着した樹脂等の異物の除去を行う。この浄化
処理によって封止体５とリードフレーム６との間に隙間
が生じることがある。また、リードフレーム６を、予め
パラジウムメッキ等の方法を用いて比較的軟質な材料で
予め覆っておくことも可能であり、このような処理を施
すことによって、この軟質材料が謂わばパッキングとし
て機能し、モールド時に樹脂が外部電極面へ付着するの
を防止することができる。このパラジウムメッキ等の方
法を用いれば、前記異物除去処理を省略することが可能
であり、封止体５とリードフレーム６との間に前記異物
除去処理によって隙間が生じるのを防止することができ
る。Next, plating such as solder is applied to the lower surface of the lead frame 6 where the portions of the island 2 and the leads 3 exposed from the cavities 7 become the external electrodes of the semiconductor device. Prior to this plating, foreign matter such as resin adhered to the plating surface is removed by a treatment such as liquid honing. A gap may be formed between the sealing body 5 and the lead frame 6 due to this purification process. In addition, it is possible to previously cover the lead frame 6 with a relatively soft material using a method such as palladium plating, and by performing such processing, this soft material functions as a so-called packing. However, it is possible to prevent the resin from adhering to the external electrode surface during molding. If a method such as palladium plating is used, it is possible to omit the foreign matter removing process, and it is possible to prevent a gap from being generated between the sealing body 5 and the lead frame 6 due to the foreign matter removing process. .
【００４２】更に、基板実装の際のハンダ付け性を向上
させるため、外部電極面にハンダメッキ等のメッキ処理
を行なう。前記のように予めリードフレームにパラジウ
ム等がメッキされている場合には、パラジウムメッキが
ハンダ付け性に優れているため、外部電極面のハンダ等
のメッキ処理を省略して、工程数を削減することも可能
である。なお最近では、パラジウムメッキのハンダ付け
性を更に高めるため、パラジウムメッキ表面に金をフラ
ッシュ処理する場合もある。Further, in order to improve the solderability at the time of mounting on the substrate, the external electrode surface is subjected to a plating treatment such as solder plating. In the case where palladium or the like is previously plated on the lead frame as described above, palladium plating is excellent in solderability, so that the plating process such as soldering on the external electrode surface is omitted, and the number of steps is reduced. It is also possible. Recently, in order to further enhance the solderability of the palladium plating, gold may be flash-treated on the surface of the palladium plating.
【００４３】次工程にて、封止樹脂表面等に製品名等を
刻印（マーキング）した後に、列毎に一つのキャビティ
７として封止されている複数の半導体装置を個別の半導
体装置に分割する。その手順を以下に説明する。In the next step, after marking the product name or the like on the sealing resin surface or the like, a plurality of semiconductor devices sealed as one cavity 7 for each column are divided into individual semiconductor devices. . The procedure will be described below.
【００４４】先ず、図８の（ａ）に示すように、各キャ
ビティ７の平坦部を上金型８及び下金型９で挟み、切断
金型１０によってプレス切断する。この際、また、切断
部分のリードフレーム６は下面に凹部が設けられて切断
面積が小さくされているため、容易にキャビティ７樹脂
とリードフレーム６の金属とをプレス切断することがで
きる。プレス切断によってキャビティ７列間の不用部分
を除去した状態を図８の（ｂ）及び図９に示す。First, as shown in FIG. 8A, a flat portion of each cavity 7 is sandwiched between an upper die 8 and a lower die 9, and press-cut by a cutting die 10. At this time, the cut portion of the lead frame 6 is provided with a concave portion on the lower surface to reduce the cutting area, so that the resin of the cavity 7 and the metal of the lead frame 6 can be easily press-cut. FIGS. 8B and 9 show a state where unnecessary portions between the seven rows of cavities are removed by press cutting.
【００４５】また、こうした切断によって、切断面に切
断方向に沿って小さな突起（バリと通称されている）が
生じることがある。このような突起が実装面である底面
に向かって形成された場合には、半導体装置と実装基板
との間に間隙が生じ、実装不良となることがある。本実
施の形態では、半導体装置のアイランド２及びリード３
の下面部外方に、夫々凹部を設けてあるのでアイランド
２或いはリード３の端部は、三方を封止体５によって挟
まれ上面を上金型８によって抑えられているために、切
断の際に前記突起が生じにくくなり、突起が生じた場合
にも半導体装置の底面から突出することがない。更に、
本実施の形態では底面側から切断金型１０がプレス切断
するため、このようなバリが生じたとしても、突起が底
面側に生じないため実装不良の原因とはならない。ま
た、アイランド２及びリード３が、前記凹部によって封
止体５に強固に保持されることとなり、外部より加えら
れた力によってアイランド２或いはリード３が剥離・脱
落或いは接合部分への亀裂の発生等が生じにくくなる。In addition, such cutting may cause small projections (commonly called burrs) on the cut surface along the cutting direction. If such protrusions are formed toward the bottom surface, which is a mounting surface, a gap may be formed between the semiconductor device and the mounting substrate, which may result in mounting failure. In the present embodiment, the island 2 and the lead 3 of the semiconductor device
Since the recesses are provided on the outer side of the lower surface of each of the islands, the ends of the islands 2 or the leads 3 are sandwiched on three sides by the sealing body 5 and the upper surface is suppressed by the upper mold 8, so that they are The protrusions are less likely to be formed, and even when the protrusions are formed, they do not protrude from the bottom surface of the semiconductor device. Furthermore,
In the present embodiment, since the cutting die 10 is press-cut from the bottom surface side, even if such burrs are generated, no projection is formed on the bottom surface side, so that it does not cause a mounting failure. Further, the island 2 and the lead 3 are firmly held by the sealing body 5 by the concave portion, and the island 2 or the lead 3 peels off or falls off due to a force applied from the outside, or a crack is generated in a joint portion. Is less likely to occur.
【００４６】なお、切断部分の樹脂がリードフレーム６
と比べて薄い場合、或いは切断部分の金属部分の断面積
が大きい場合等には、リードフレーム６とキャビティ７
との間に剥離の生じる可能性が高くなる。こうした場合
には、このプレス切断に先立って、図１０に平面図を図
１１に部分拡大平面図及び断面図を示すように、切断部
分に溝１１を形成しておいてもよい。溝１１としては、
アイランド２或いはリード３の薄い部分を切断し、その
凹部に充填された封止体５の樹脂が露出する程度が望ま
しい。この溝１１を設けることによって、図１２の
（ａ）に示すように金型８，９，１０を用いたプレス切
断によってキャビティ７に加えられるストレスを更に低
減させることができる。また、封止に用いられる樹脂は
金属と比較して脆性体であるため、溝を設けることによ
って、プレス切断が容易になる。こうした溝は、図１２
の（ｂ）に示すように、ブレード１２を用いたダイシン
グによって容易に形成することができる。The cut portion of the resin is the lead frame 6
When the cross section of the metal portion of the cut portion is large, the lead frame 6 and the cavity 7
And the likelihood of peeling increases. In such a case, prior to this press cutting, a groove 11 may be formed in the cut portion as shown in a plan view in FIG. 10 and a partially enlarged plan view and a sectional view in FIG. As the groove 11,
It is desirable that the thin portion of the island 2 or the lead 3 is cut and the resin of the sealing body 5 filled in the concave portion is exposed. By providing the groove 11, the stress applied to the cavity 7 by press cutting using the dies 8, 9, and 10 can be further reduced as shown in FIG. Further, since the resin used for sealing is a brittle substance as compared with metal, press cutting is facilitated by providing the groove. These grooves are shown in FIG.
(B), it can be easily formed by dicing using the blade 12.
【００４７】次に、粘着性のダイシングテープにリード
フレーム６下面（外部電極面）を貼り付け、更にその周
囲をリング状のテープホルダーに固定する。ダイシング
テープとしては、後の剥離工程で粘着成分がリードフレ
ーム６下面に残り難いもの、例えば紫外線照射型のテー
プ（所謂ＵＶテープ）が望ましい。続いて、ダイシング
位置合わせスリットを基準としてダイシング装置（ウエ
ーハダイシング装置の流用が可能：図示せず）によっ
て、図１３及び図１４に示すように、個別半導体装置に
切削分割する。切削方法としては、半導体ウエーハ切断
時に常用されている所謂フルカットダイシング方法を用
い、ブレード１２を用いてキャビティ７は完全に切断す
るが、ダイシングテープ１２は部分的に切断し一体化し
たままとする。リードフレーム６に切断目標となる位置
合わせ認識マークとしてスリット或いは貫通孔（図面中
には記載せず）を施しておくことによって、樹脂封止、
フレームハンダメッキを施した後、ダイシングにて個別
半導体装置に切断する過程において、切断寸法精度を保
証することができる。Next, the lower surface (external electrode surface) of the lead frame 6 is adhered to an adhesive dicing tape, and the periphery thereof is fixed to a ring-shaped tape holder. As the dicing tape, a tape in which an adhesive component hardly remains on the lower surface of the lead frame 6 in a subsequent peeling step, for example, an ultraviolet irradiation type tape (a so-called UV tape) is desirable. Subsequently, as shown in FIGS. 13 and 14, the semiconductor device is cut and divided into individual semiconductor devices by a dicing apparatus (a wafer dicing apparatus can be diverted: not shown) based on the dicing alignment slit. As a cutting method, a so-called full-cut dicing method commonly used when cutting a semiconductor wafer is used, and the cavity 7 is completely cut using the blade 12, but the dicing tape 12 is partially cut and remains integrated. . By forming slits or through holes (not shown in the drawings) as alignment recognition marks serving as cutting targets on the lead frame 6, resin sealing,
After the frame solder plating, in the process of cutting into individual semiconductor devices by dicing, the cutting dimensional accuracy can be guaranteed.
【００４８】このダイシングでは、キャビティ７の樹脂
のみを切断する。樹脂は金属と比較して脆性体であるた
め、樹脂のみの切断はダイシングを迅速に行なうことが
可能であり、また、切断する樹脂に最適化したブレード
１２を用いることが可能となるため、ブレード１２の目
づまりも生じにくい。更に、ダイシングテープに貼り付
けた状態でフルカット方法により切断するため、切断後
の個別半導体装置が飛散することなく、その位置関係も
ずれることはない為、その後の扱いが容易になる。In this dicing, only the resin in the cavity 7 is cut. Since the resin is a brittle substance as compared with the metal, the dicing of the resin alone can be performed quickly, and the blade 12 optimized for the resin to be cut can be used. Twelve clogging hardly occurs. Furthermore, since the individual semiconductor devices after the cutting are cut by the full-cut method in a state of being attached to the dicing tape, the individual semiconductor devices after the cutting do not scatter and their positional relationship does not shift, thereby facilitating subsequent handling.
【００４９】また、従来のスルーモールド方式により、
半導体素子別にキャビティを形成する場合、封止体サイ
ズが小さくなる程、封止樹脂導入路であるゲートを小さ
く構成しなければならず、レジン注入の観点からその限
界寸法がある。本方式によれば、後に不要部分を切削切
断すれば良いので、ゲートのサイズによって制約される
ことがない。また、多層セラミック基板を用いた場合と
の比較では、セラミックが脆性材料である点或いは基板
焼成過程において若干の変形が生じている点を考慮する
と、従来の金型を用いたトランスファーモールド方法に
より樹脂封止することは困難であるが、本願発明の如く
リードフレームを用いた場合にはこの様な懸念はない。Also, by the conventional through mold method,
When a cavity is formed for each semiconductor element, as the size of the sealing body becomes smaller, the gate serving as a sealing resin introduction path must be made smaller, and there is a critical dimension from the viewpoint of resin injection. According to this method, the unnecessary portion may be cut and cut later, so that there is no restriction on the size of the gate. Also, in comparison with the case where a multilayer ceramic substrate is used, considering that ceramic is a brittle material or that a slight deformation occurs during the substrate baking process, the resin is transferred by the conventional transfer molding method using a mold. Although it is difficult to seal, there is no such concern when a lead frame is used as in the present invention.
【００５０】この後、各半導体装置の電気的特性を測定
する。この測定では、分離された各半導体装置が接着さ
れた状態の前記テープホルダーを、複数枚一組にリング
カセットに入れた状態で選別工程のハンドリング装置の
ローダー部にセットする。セットされたテープホルダー
は、一枚毎にハンドリング装置のローディング部に移送
する。ハンドリング装置は、従来のダイレクトピックア
ップ方式のダイボンダと同様の構成であり、リングホル
ダと協働する個別半導体装置突き上げ機構を具備し、予
め設定された座標位置または認識装置の認識結果から指
定された座標位置データに基づき、突き上げ動作を行い
ダイシングテープより所定の半導体装置を引き剥がす。
なお引き剥がす際には、紫外線照射型のダイシングテー
プを用いた場合は、紫外線照射を適量行い半導体装置底
面とダイシングテープとの接合強度を弱めることによっ
て、粘着成分が半導体装置底面に残存するのを防止する
ことができる。Thereafter, the electrical characteristics of each semiconductor device are measured. In this measurement, the tape holder to which the separated semiconductor devices are bonded is set in a loader section of a handling device in a sorting process in a state where a plurality of the tape holders are put in a ring cassette. The set tape holders are transferred one by one to a loading unit of a handling device. The handling device has the same configuration as a conventional direct pickup type die bonder, includes an individual semiconductor device push-up mechanism that cooperates with a ring holder, and has a predetermined coordinate position or a coordinate specified from a recognition result of the recognition device. A predetermined semiconductor device is peeled off from the dicing tape by performing a push-up operation based on the position data.
When peeling off, if an ultraviolet irradiation type dicing tape is used, an appropriate amount of ultraviolet irradiation is performed to weaken the bonding strength between the semiconductor device bottom surface and the dicing tape so that the adhesive component remains on the semiconductor device bottom surface. Can be prevented.
【００５１】（実施の形態２）図１５は本発明の他の実
施の形態である半導体装置を示す斜視図であり、（ａ）
はその外形を、（ｂ）は封止体を透過して内部を示して
ある。Embodiment 2 FIG. 15 is a perspective view showing a semiconductor device according to another embodiment of the present invention.
Shows the outer shape, and (b) shows the inside through the sealing body.
【００５２】本実施の形態の半導体装置では、単結晶シ
リコン等の半導体基板にＦＥＴ等の所定の素子を形成し
た半導体素子１を、例えば金等のロー材によってアイラ
ンド２に固定し、半導体素子１とリード３とをボンディ
ングワイヤ４によって接続してある。半導体素子１をダ
イボンディングするアイランド２には下面部内方及び外
方に凹部が設けられ、リード３には下面部外方に凹部が
設けられている。In the semiconductor device of this embodiment, a semiconductor element 1 in which a predetermined element such as an FET is formed on a semiconductor substrate of single crystal silicon or the like is fixed to an island 2 by a brazing material such as gold. And the lead 3 are connected by a bonding wire 4. An island 2 for die-bonding the semiconductor element 1 is provided with concave portions inside and outside the lower surface, and a lead 3 is provided with concave portions outside the lower surface.
【００５３】半導体素子１、アイランド２、リード３の
上面及び側面、ボンディングワイヤ４は、例えばエポキ
シ樹脂にフィラを混入させた封止樹脂を用いた封止体１
３によって封止されているが、本実施の形態の封止体１
３では、単一の封止体１３に半導体素子１、アイランド
２及びリード３の組が２組封止されている点が、前述し
た実施の形態とは相異しているが、他の構成は前述した
実施の形態と同様である。The semiconductor element 1, the island 2, the top and side surfaces of the leads 3, and the bonding wires 4 are made of, for example, a sealing body 1 using a sealing resin in which a filler is mixed into an epoxy resin.
3, the sealing body 1 of the present embodiment.
3 is different from the above-described embodiment in that two sets of the semiconductor element 1, the island 2, and the lead 3 are sealed in a single sealing body 13. Is the same as in the above-described embodiment.
【００５４】例えば、封止体１３の短手方向に沿った側
面（以下、短側面という）下部にはわずかに張出した平
坦部１３ａが形成されており、この平坦部１３ａではア
イランド２及びリード３の端部上面及び外端部が露出し
ているが、アイランド２或いはリード３の端部は、封止
体１３の長手方向に沿った側面（以下、長側面という）
には露出しない構成となっている。このため、長側面側
に隣接して形成される複数の半導体装置を、図１６に示
すようにブレード１２による切断位置を変更するだけ
で、金型変更等をすることなしに、一体化することが可
能となる。For example, a slightly protruding flat portion 13a is formed below a side surface (hereinafter, referred to as a short side surface) of the sealing body 13 along the short direction. Of the island 2 or the lead 3 is exposed on the side surface along the longitudinal direction of the sealing body 13 (hereinafter referred to as long side surface).
Is not exposed to the camera. For this reason, a plurality of semiconductor devices formed adjacent to the long side surface can be integrated without changing the mold by merely changing the cutting position by the blade 12 as shown in FIG. Becomes possible.
【００５５】封止される半導体素子としては、同種の素
子を搭載して耐圧或いは許容電流を向上させることが可
能となり、更に異種の素子、例えば発振回路の発振用の
素子と増幅用の素子とを搭載してもよい。そして搭載し
た素子は、ボンディングワイヤ４によって互いにアイラ
ンド２或いはリード３を接続して必要な接続を行ない、
回路としての配線長を短縮することも可能である。ま
た、単一の封止体１２によって封止する、半導体素子
１、アイランド２及びリード３の組を３組以上とする構
成も可能である。As the semiconductor element to be sealed, the same kind of element can be mounted to improve the withstand voltage or the allowable current. Further, different kinds of elements, such as an oscillation element and an amplification element of an oscillation circuit, can be used. May be mounted. The mounted elements make necessary connections by connecting the islands 2 or the leads 3 to each other by bonding wires 4.
It is also possible to shorten the wiring length as a circuit. A configuration in which three or more sets of the semiconductor element 1, the island 2, and the lead 3 are sealed by a single sealing body 12 is also possible.
【００５６】以上、本発明者によってなされた発明を、
前記実施の形態に基づき具体的に説明したが、本発明
は、前記実施の形態に限定されるものではなく、その要
旨を逸脱しない範囲において種々変更可能であることは
勿論である。As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.
【００５７】例えば、以上の説明では、主として本発明
者によってなされた発明をその背景となった利用分野で
あるトランジスタについてレジン封止によるＣＳＰ(Chi
p Size Package)技術を適用した場合について説明した
が、それに限定されるものではなく、本発明は、ダイオ
ード或いはＱＦＮ型半導体装置等の他の形式の半導体装
置にも広く適用が可能である。For example, in the above description, the invention made mainly by the present inventor is mainly applied to the CSP (Chinese resin-encapsulated resin) for the transistor which is the application field in which the invention is based.
Although the case where the (p Size Package) technology is applied has been described, the present invention is not limited thereto, and the present invention can be widely applied to other types of semiconductor devices such as a diode or a QFN type semiconductor device.
【００５８】[0058]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。 （１）本発明によれば、半導体素子寸法に近似した半導
体装置(ＣＳＰ)に関し、個別半導体素子搭載基板として
金属材料を用いたリードフレームの使用が可能となると
いう効果がある。 （２）本発明によれば、微小な半導体装置の封止体を一
括モールドによって樹脂封止することができるという効
果がある。 （３）本発明によれば、上記効果（１）（２）により、
半導体装置を安価に製造することができるという効果が
ある。 （４）本発明によれば、ダイシングによって、切断面に
切断方向に沿って突起が生じるのを防止することができ
るという効果がある。 （５）本発明によれば、上記効果（４）により、実装不
良の発生を防止することができるという効果がある。 （６）本発明によれば、、樹脂のみをブレード切断する
ため目づまりが生じにくく、分離工程の効率を向上させ
ることができるという効果がある。 （７）本発明によれば、金属と樹脂との接合界面に亀裂
が入りにくいので、耐湿性が向上するという効果があ
る。 （８）本発明によれば、複数の半導体素子を単一の封止
体に封止した半導体装置を、金型の変更なしに製造する
ことができるという効果がある。 （９）本発明によれば、半導体装置下面に、絶縁層を樹
脂モールド方法により形成したことにより、実装基板上
に形成された回路配線との電気的短絡を防止することが
できるという効果がある。 （１０）本発明によれば、複数の半導体素子を列毎に一
つのキャビティとして樹脂封止することによって、熱ま
たは樹脂の収縮作用による反りを防止しつつ、仕上がり
寸法精度の良い個別半導体装置を提供することが可能と
なるという効果がある。The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, a semiconductor device (CSP) having dimensions similar to those of a semiconductor element has an effect that a lead frame using a metal material can be used as an individual semiconductor element mounting substrate. (2) According to the present invention, there is an effect that a sealed body of a minute semiconductor device can be resin-sealed by collective molding. (3) According to the present invention, the effects (1) and (2)
There is an effect that a semiconductor device can be manufactured at low cost. (4) According to the present invention, there is an effect that projections can be prevented from being formed on a cut surface along a cutting direction by dicing. (5) According to the present invention, the effect (4) has an effect that occurrence of mounting failure can be prevented. (6) According to the present invention, since only the resin is cut with a blade, clogging hardly occurs and the efficiency of the separation step can be improved. (7) According to the present invention, a crack is less likely to be formed at a bonding interface between a metal and a resin, and thus there is an effect that moisture resistance is improved. (8) According to the present invention, there is an effect that a semiconductor device in which a plurality of semiconductor elements are sealed in a single sealing body can be manufactured without changing a mold. (9) According to the present invention, since the insulating layer is formed on the lower surface of the semiconductor device by the resin molding method, there is an effect that an electrical short circuit with the circuit wiring formed on the mounting substrate can be prevented. . (10) According to the present invention, a plurality of semiconductor elements are resin-sealed as one cavity for each column, thereby preventing warpage due to heat or shrinkage of the resin and achieving an individual semiconductor device having a high finished dimensional accuracy. There is an effect that it can be provided.
【図１】本発明の一実施の形態である半導体装置を封止
体を透視して示す斜視図である。FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention, seeing through a sealing body.
【図２】本発明の一実施の形態である半導体装置を示す
斜視図及びその底面の投影図である。FIG. 2 is a perspective view showing a semiconductor device according to an embodiment of the present invention, and a projection view of the bottom surface thereof.
【図３】本実施の形態に用いられるリードフレームを示
す平面図である。FIG. 3 is a plan view showing a lead frame used in the present embodiment.
【図４】図３中のａ部を拡大して示す平面図及び断面図
である。FIG. 4 is an enlarged plan view and a cross-sectional view of a part a in FIG. 3;
【図５】本発明の一実施の形態である半導体装置を製造
工程毎に示す平面図である。FIG. 5 is a plan view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process.
【図６】図５中のａ部を拡大して示す平面図及び断面図
である。6 is an enlarged plan view and a cross-sectional view of a part a in FIG. 5;
【図７】本発明の一実施の形態である半導体装置を製造
工程毎に示す斜視図である。FIG. 7 is a perspective view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process.
【図８】本発明の一実施の形態である半導体装置を製造
工程毎に示す断面図及び斜視図である。8A and 8B are a cross-sectional view and a perspective view illustrating a semiconductor device according to an embodiment of the present invention for each manufacturing process.
【図９】本発明の一実施の形態である半導体装置を製造
工程毎に示す平面図である。FIG. 9 is a plan view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process.
【図１０】本発明の一実施の形態である半導体装置を製
造工程毎に示す平面図である。FIG. 10 is a plan view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process.
【図１１】図１０中のａ部を拡大して示す平面図及び断
面図である。11A and 11B are a plan view and a cross-sectional view showing an a portion in FIG. 10 in an enlarged manner.
【図１２】本発明の一実施の形態である半導体装置を製
造工程毎に示す断面図及び斜視図である。12A and 12B are a cross-sectional view and a perspective view illustrating a semiconductor device according to an embodiment of the present invention for each manufacturing process.
【図１３】本発明の一実施の形態である半導体装置を製
造工程毎に示す平面図である。FIG. 13 is a plan view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process.
【図１４】本発明の一実施の形態である半導体装置を製
造工程毎に示す斜視図である。FIG. 14 is a perspective view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process.
【図１５】本発明の他の実施の形態である半導体装置を
示す平面図である。FIG. 15 is a plan view showing a semiconductor device according to another embodiment of the present invention.
【図１６】本発明の他の形態である半導体装置の製造方
法を示す斜視図である。FIG. 16 is a perspective view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.
１…半導体素子、２…アイランド、３…リード、４…ボ
ンディングワイヤ、５，１３…封止体、６…リードフレ
ーム、７…キャビティ、７ａ…ランナ、７ｂ…ゲート、
８…上金型、９…下金型、１０…切断金型、１１…溝、
１２…ブレード。DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Island, 3 ... Lead, 4 ... Bonding wire, 5, 13 ... Sealing body, 6 ... Lead frame, 7 ... Cavity, 7a ... Runner, 7b ... Gate,
8 ... upper mold, 9 ... lower mold, 10 ... cutting mold, 11 ... groove,
12 ... Blade.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 25/18 (72)発明者 藤田 直樹 群馬県高崎市西横手町１番地１ 日立東部 セミコンダクタ株式会社内 (72)発明者 三上 昭夫 群馬県高崎市西横手町１番地１ 日立東部 セミコンダクタ株式会社内 Ｆターム(参考） 4M109 AA01 BA01 CA21 DB15 FA04 5F061 AA01 BA01 CA21 CB13 DD12 5F067 AA07 AA09 AB04 BA02 BA08 BB04 BE02 DE02 DE20 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H01L 25/18 (72) Inventor Naoki Fujita 1 Nishiyokote-cho, Takasaki City, Gunma Prefecture 1 Hitachi East Semiconductor Company, Ltd. (72) Inventor Akio Mikami 1-1-1 Nishiyokote-cho, Takasaki-shi, Gunma F-term in Hitachi Eastern Semiconductor Co., Ltd. (Reference) 4M109 AA01 BA01 CA21 DB15 FA04 5F061 AA01 BA01 CA21 CB13 DD12 5F067 AA07 AA09 AB04 BA02 BA08 BB04 BE02 DE02 DE20
Claims (5)
ドとを接続し封止体によって封止した半導体装置におい
て、 前記アイランド或いはリードが封止体底面にて露出して
半導体装置の外部端子となり、このアイランド或いはリ
ードの外端部が、前記封止体の相対する２側面に露出
し、前記２側面と直交する他の２側面には露出していな
いことを特徴とする半導体装置。In a semiconductor device in which a semiconductor element fixed to an island and a lead are connected to each other and sealed by a sealing body, the island or the lead is exposed at a bottom surface of the sealing body to become an external terminal of the semiconductor device. A semiconductor device, wherein outer ends of islands or leads are exposed on two opposite sides of the sealing body and are not exposed on the other two sides orthogonal to the two sides.
下面或いは外端部の側面角部の少なくとも何れかに凹部
が設けられていることを特徴とする請求項１に記載の半
導体装置。2. The semiconductor device according to claim 1, wherein a concave portion is provided on at least one of a lower surface of an outer end portion of the island or the lead or a side corner of the outer end portion.
露出している前記封止体の相対する２側面に平坦部が設
けられていることを特徴とする請求項１又は請求項２に
記載の半導体装置。3. The flat body according to claim 1, wherein flat portions are provided on two opposite side surfaces of the sealing body where the outer ends of the islands or the leads are exposed. Semiconductor device.
露出している封止体の相対する２側面に沿った方向に隣
接する複数組のアイランド及びリードが同一の封止体に
封止され、夫々のアイランドに同種又は異種の半導体素
子が固定されていることを特徴とする請求項１乃至請求
項３の何れか一項に記載の半導体装置。4. A plurality of sets of islands and leads adjacent in a direction along two opposing side surfaces of the sealing body in which the outer ends of the islands or the leads are exposed are sealed by the same sealing body; 4. The semiconductor device according to claim 1, wherein the same type or different types of semiconductor elements are fixed to each of the islands. 5.
ドとを接続し封止体によって封止した半導体装置の製造
方法において、 個々の半導体装置に用いられるアイランド或いはリード
の組を行列状に複数組設け、行方向に隣接するアイラン
ド或いはリードを連続させて一体に形成したリードフレ
ームを用意し、このリードフレームの各アイランドに夫
々半導体素子のダイボンディングを行なう工程と、 前記夫々の半導体素子と前記リードとを電気的に接続す
る工程と、 半導体素子、アイランド及びリードを封止する前記封止
体を、列毎に複数を一体に一つのキャビティとして樹脂
モールドする工程と、 前記封止体の列間の樹脂及びリードフレームをプレス切
断する工程と、 前記封止体の行間のキャビティをブレード切断して個別
の半導体装置に分離する工程とを有することを特徴とす
る半導体装置の製造方法。5. A method of manufacturing a semiconductor device in which a semiconductor element fixed to an island and a lead are connected and sealed by a sealing body, wherein a plurality of sets of islands or leads used in each semiconductor device are provided in a matrix. Preparing a lead frame in which islands or leads adjacent to each other in the row direction are continuously formed and integrally formed, and performing die bonding of a semiconductor element to each of the islands of the lead frame; and Electrically sealing the semiconductor element, the islands and the leads, and resin-molding the plurality of sealing bodies for each column as one cavity integrally; and between the rows of the sealing bodies. Press cutting the resin and the lead frame; and cutting the cavity between the rows of the sealing body with a blade to separate individual semiconductor devices. The method of manufacturing a semiconductor device characterized by a step of separating the.
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|---|---|---|---|
| JP2000111466A JP3660854B2 (en) | 2000-04-13 | 2000-04-13 | Manufacturing method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000111466A JP3660854B2 (en) | 2000-04-13 | 2000-04-13 | Manufacturing method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2001298144A true JP2001298144A (en) | 2001-10-26 |
| JP3660854B2 JP3660854B2 (en) | 2005-06-15 |
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ID=18623784
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000111466A Expired - Fee Related JP3660854B2 (en) | 2000-04-13 | 2000-04-13 | Manufacturing method of semiconductor device |
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| Country | Link |
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| JP (1) | JP3660854B2 (en) |
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|---|---|---|---|---|
| JP2005529493A (en) * | 2002-06-06 | 2005-09-29 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Non-lead quad flat package with semiconductor devices |
| US7172924B2 (en) | 2003-11-07 | 2007-02-06 | Oki Electic Industry Co., Ltd. | Semiconductor device having a semiconductor chip mounted on external terminals and fabrication method thereof |
| US7402502B2 (en) | 2003-12-25 | 2008-07-22 | Oki Electric Industry Co., Ltd. | Method of manufacturing a semiconductor device by using a matrix frame |
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| JP2005529493A (en) * | 2002-06-06 | 2005-09-29 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Non-lead quad flat package with semiconductor devices |
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| US7402502B2 (en) | 2003-12-25 | 2008-07-22 | Oki Electric Industry Co., Ltd. | Method of manufacturing a semiconductor device by using a matrix frame |
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