JP2010267727A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- JP2010267727A JP2010267727A JP2009116755A JP2009116755A JP2010267727A JP 2010267727 A JP2010267727 A JP 2010267727A JP 2009116755 A JP2009116755 A JP 2009116755A JP 2009116755 A JP2009116755 A JP 2009116755A JP 2010267727 A JP2010267727 A JP 2010267727A
- Authority
- JP
- Japan
- Prior art keywords
- bonding wire
- semiconductor device
- gel
- wire
- filler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
- H01L2224/49052—Different loop heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49174—Stacked arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、半導体装置に関し、詳細には、耐振動強度向上技術に関する。 The present invention relates to a semiconductor device, and more particularly to a technique for improving vibration resistance strength.
従来、例えばエンジンやモータ等の出力軸線方向よりもエンジンのシリンダ内に振動が作用する方向や出力軸線回りの振れ回りの振動の方が大きいのに合わせて、電子制御ユニットやパワーユニット等の電子回路をモジュール化したモジュール部品を、振動の影響の少ない出力軸線方向に対してボンディングワイヤを含む平面が垂直となるように配置することで、ボンディングワイヤの耐久性を損なうボンディングワイヤを含む面に垂直な方向への大きな振動が加わるのを防止する技術が提案されている(例えば、特許文献1に記載)。 Conventionally, electronic circuits such as an electronic control unit and a power unit are adapted to the direction in which vibration is applied in the cylinder of the engine and the vibration around the output axis are larger than the direction of the output axis of the engine or motor, for example. By arranging module parts that are modularized so that the plane including the bonding wire is perpendicular to the output axis direction where the influence of vibration is small, it is perpendicular to the surface including the bonding wire that impairs the durability of the bonding wire. A technique for preventing a large vibration in a direction from being applied has been proposed (for example, described in Patent Document 1).
しかし、特許文献1に記載の技術では、外乱によって半導体装置に入力される大きな振動(加振力)に対してモジュールケース内に充填された粘弾性を呈するゲル状物質が共振することによって変位し、そのゲル状物質の変位に連動してボンディングワイヤも変位することから、前記ボンディングワイヤが断線等するといった問題が発生する。
However, in the technique described in
そこで、本発明は、ケース内に充填されたゲル状充填材の揺動によるボンディングワイヤの断線を防止し、耐振動強度を向上させることのできる半導体装置を提供する。 Therefore, the present invention provides a semiconductor device capable of preventing the bonding wire from being broken by the swinging of the gel filler filled in the case and improving the vibration resistance strength.
本発明の半導体装置では、半導体装置に発生する振動方向とゲル状充填材の短手方向を一致させて前記ゲル状充填材をケース内に充填した構造とし、これに加えて、ゲル状充填材の長手方向をボンディングワイヤの配索方向に一致させた構造とする。 In the semiconductor device of the present invention, the vibration direction generated in the semiconductor device and the short direction of the gel filler are made to coincide with each other to fill the case with the gel filler, and in addition to this, the gel filler It is set as the structure which made the longitudinal direction of this correspond with the wiring direction of a bonding wire.
本発明の半導体装置によれば、半導体装置に発生する振動方向とゲル状充填材の短手方向を一致させたことにより、ゲル状充填材の長手方向に対して短手方向は揺動し難い(共振し難い)ことからゲル状充填材の揺動を抑制することができ、ボンディングワイヤに加わる強制変位を低減できる。また、ゲル一次共振モードは、ゲル長手方向の共振となるため、ゲル状充填材の長手方向をボンディングワイヤの配索方向に一致させることにより、ワイヤ剛性及び強度の高いボンディングワイヤの配索方向がゲル状充填材の共振し易い長手方向に一致できる。その結果、ボンディングワイヤの断線を防止することができ、半導体装置の耐振信頼性を向上させることができる。 According to the semiconductor device of the present invention, since the vibration direction generated in the semiconductor device matches the short direction of the gel filler, the short direction hardly swings with respect to the longitudinal direction of the gel filler. Since it is difficult to resonate, the gel filler can be prevented from swinging, and the forced displacement applied to the bonding wire can be reduced. In addition, since the gel primary resonance mode is resonance in the longitudinal direction of the gel, by aligning the longitudinal direction of the gel filler with the bonding direction of the bonding wire, the bonding direction of the bonding wire having high wire rigidity and strength can be achieved. It is possible to match the longitudinal direction of the gel filler which is likely to resonate. As a result, disconnection of the bonding wire can be prevented, and the vibration resistance reliability of the semiconductor device can be improved.
以下、本発明を適用した具体的な実施形態について図面を参照しながら詳細に説明する。 Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.
「実施形態1」
図1は実施形態1の半導体装置の全体斜視図、図2は図1の半導体装置において、ケースと蓋を分離した状態の半導体装置の全体斜視図、図3は図1のA−A線断面図、図4は図1の半導体装置において、ケース内に設けられた半導体素子と導体を接続するボンディングワイヤの配索方向を示す図である。
“
1 is an overall perspective view of the semiconductor device of the first embodiment, FIG. 2 is an overall perspective view of the semiconductor device in a state where a case and a lid are separated in the semiconductor device of FIG. 1, and FIG. 3 is a cross-sectional view taken along line AA in FIG. 4 and 4 are diagrams showing the wiring direction of bonding wires for connecting a semiconductor element provided in a case and a conductor in the semiconductor device of FIG.
実施形態1の半導体装置1は、図1から図3に示すように、回路基板2に搭載された半導体素子3と、回路基板2上に絶縁体4を介して積層された導体5と、半導体素子3と導体5とを電気的に繋ぐボンディングワイヤ6と、回路基板2を内部に収容するように該回路基板2の周囲に取り付けられたケース7と、ケース7内に充填されて少なくとも半導体素子3とボンディングワイヤ6を保護するゲル状充填材8と、回路基板2に貼り合わされた放熱板9と、ケース7に取り付けられてゲル状充填材8を封止する蓋10と、を備えている。
As shown in FIGS. 1 to 3, the
半導体素子3は、例えば電気自動車等において電力変換をするためのデバイスとして使用される。具体的には、バッテリーからの直流電源をモーターへの3相交流に変換して流すインバータにおいて、電流変換を行うパワーモジュール中に設けたスイッチング素子の導通、非導通を制御する機能として半導体素子3が使用される。この半導体素子3は、電子回路部が形成された回路基板2の一面2aとなる部品実装面に実装されている。
The
導体5は、回路基板2の部品実装面である一面2a上に、直接設けられるのではなく絶縁体4を介して設けられている。
The
ボンディングワイヤ6は、半導体素子3に電力を供給する電力供給線として機能する。このボンディングワイヤ6は、半導体素子3と導体5とを電気的に繋ぐように接続されている。具体的には、ボンディングワイヤ6は、一端を半導体素子3に電気的に接続し、他端を導体5に接続させてアーチ状とされている。半導体素子3と導体5間を接続するボンディングワイヤ6は、例えば3本或いはそれ以上の複数本とされている。
The
ケース7は、回路基板2を内部に収容するように該回路基板2の周囲に取り付けられる平面視長方形をなす枠体として形成されている。このケース7は、内部に半導体素子3や導体5若しくはボンディングワイヤ6を実装させた回路基板2とゲル状充填材8とを充填させるキャビティとしても機能する。
The
放熱板9は、半導体素子3が発する熱を放熱するヒートシンクとして機能する。この放熱板9は、前記回路基板2の部品実装面である一面2aとは反対側の他面2bに貼り付けられている。また、放熱板9は、半導体素子3の発熱をケース外へと放熱するため、ケース7の底に取り付けられている。別の見方をすると、放熱板9は、ケース7の底を構成している。
The heat sink 9 functions as a heat sink that dissipates heat generated by the
ゲル状充填材8は、回路基板2上に実装された半導体素子3、導体5及びボンディングワイヤ6を覆うようにしてケース7内に充填されている。かかるゲル状充填材8は、これら半導体素子3、導体5及びボンディングワイヤ6が損傷等しないように外力から保護する役目をする。また、ゲル状充填材8は、ケース7内に隙間無く満たされるように充填される。ゲル状充填材8としては、例えばシリコン系、エポキシ系等の粘弾性を呈する樹脂が使用される。ゲル状充填材として使用できる樹脂としては、例えば、シリコン、ウレタン、エポキシがある。
The
蓋10は、ゲル状充填材8を充填させたケース7の上部に取り付けられている。このケース7の上部が蓋10で閉蓋されると、ゲル状充填材8が封止されることになる。
The
本実施形態の半導体装置では、半導体装置1に発生する(加えられる)振動方向(加振方向)Kと、前記ゲル状充填材8の短手方向Sを一致させて、前記ゲル状充填材8を前記ケース7内に充填させた構造としている。
In the semiconductor device of the present embodiment, the gel-
半導体装置1には、例えば図2に示すように、自動車等に搭載されるエンジンやモーター等の車両駆動装置からの振動やロードノイズがケース7の長手方向ではなく短手方向Kに発生する(加振される)ものとする。そうした場合、ケース7内に充填されたゲル状充填材8は、前記半導体装置1に発生する振動に対してそのゲル状充填材8自身の長手方向Lには共振し易く、ゲル状充填材8自身の短手方向Sには共振し難い特性を有する。
In the
したがって、半導体装置1に発生する(加振される)振動方向Kにゲル状充填材8の短手方向Sを一致させれば、ゲル状充填材8の長手方向Lに対して短手方向Sは共振し難い(揺動し難い)ことから、ゲル状充填材8の揺動を抑制することができる。つまり、本実施形態の半導体装置1によれば、該半導体装置1に発生する振動に共振するゲル状充填材8の共振点が高くなり、ボンディングワイヤ6に加わる強制変位の低減及びボンディングワイヤ内部に発生する応力を低減することができる。したがって、本実施形態の半導体装置1によれば、ボンディングワイヤ6の断線を回避することができ、耐振動強度を大幅に向上させることができる。
Therefore, if the short direction S of the
また、本実施形態の半導体装置では、図2で示すゲル状充填材8の長手方向Lを、図4で示すボンディングワイヤ6の配索方向Wに一致させた構造としている。ゲル状充填材8は、半導体装置1の長手方向又は短手方向に発生する振動方向(加振方向)に拘わらず、ゲル一次共振モードがゲル長手方向Lの共振となる。
Further, the semiconductor device of this embodiment has a structure in which the longitudinal direction L of the
前記ボンディングワイヤ6のワイヤ配索方向Wでは、ワイヤ剛性及びワイヤ強度が、該ワイヤ配索方向Wと直交する方向に比べて高い。そのため、ゲル状充填材8が振動し易い該ゲル状充填材8の長手方向Lとワイヤ剛性及びワイヤ強度が高いボンディングワイヤ6のワイヤ配索方向Wを一致させることで、加振されてゲル状充填材8が揺動してもボンディングワイヤ6に発生する応力を低減することができる。したがって、本実施形態の半導体装置によれば、ボンディングワイヤ6の断線を防止することができ、該ボンディングワイヤ6の耐振信頼性を高めることができる。
In the wire routing direction W of the
「実施形態2」
図5はワイヤ配索高さの低いボンディングワイヤのワイヤ径を太くした実施形態2のボンディングワイヤの斜視図である。
“
FIG. 5 is a perspective view of the bonding wire of the second embodiment in which the wire diameter of the bonding wire having a low wire routing height is increased.
実施形態2の半導体装置では、図5に示すように、ボンディングワイヤ6(6a、6b、6c)の配索高さH(Ha、Hb、Hc)が異なる場合に、配索高さHの高い側のボンディングワイヤ6b、6cのワイヤ径Db、Dcに比べて配索高さHの低い側のボンディングワイヤ6aのワイヤ径Daを太くした構成としている。
In the semiconductor device of the second embodiment, as shown in FIG. 5, the wiring height H is high when the wiring heights H (Ha, Hb, Hc) of the bonding wires 6 (6 a, 6 b, 6 c) are different. The wire diameter Da of the
前記半導体装置1が加振されてゲル状充填材8が揺動した際のボンディングワイヤ6の変形挙動は、ゲル変形に沿った形でのワイヤ強制変位となる。具体的には、ボンディングワイヤ6は、半導体素子3又は導体5との接合部位である根元に捻り応力Fが発生し、その捻れ応力Fでワイヤ配索方向と直交する方向に変位せしめられる。強制変位時は、相対的な変位量が短いワイヤが大きくなる。そのため、相対的な変位量が短いワイヤ、つまり配索高さHの高い側のボンディングワイヤ6b、6cのワイヤ径Db、Dcに比べて配索高さHの低い側のボンディングワイヤ6aのワイヤ径Daを太くする。図5では、最も配索高さHの低いボンディングワイヤ6aのワイヤ径Daを、これよりも配索高さHの高いボンディングワイヤ6b、6cのワイヤ径Db、Dcに対して太くしている。
The deformation behavior of the
このように構成した実施形態2の半導体装置では、ボンディングワイヤ6a、6b、6cの配索高さHa、Hb、Hcが異なる場合に、配索高さHの高い側のボンディングワイヤ6b、6cのワイヤ径Db、Dcに比べて配索高さHの低い側のボンディングワイヤ6aのワイヤ径Daを太くしたことにより、ワイヤ剛性が高まってゲル状充填材8の揺動により生じる捻り力Fに耐え得ることができ、このボンディングワイヤ6aの強制変位量を少なくすることができる。したがって、本実施形態2によれば、ボンディングワイヤ6の断線を防止でき、当該ボンディングワイヤ6の耐振信頼性を高めることが可能となる。
In the semiconductor device of the second embodiment configured as described above, when the bonding heights Ha, Hb, and Hc of the
「実施形態3」
図6はゲル状充填材中央領域に相当する部位に配索されたボンディングワイヤのワイヤ径を太くした実施形態3を示す図、図7は図6のB−B線断面図である。
“
FIG. 6 is a diagram showing a third embodiment in which the wire diameter of the bonding wire arranged in a portion corresponding to the central region of the gel filler is increased, and FIG. 7 is a cross-sectional view taken along the line BB of FIG.
先の実施形態2の半導体装置では、全てのボンディングワイヤ6のワイヤ径を同一径とした実施形態1とは異なり、図6及び図7に示すように、ゲル状充填材8のうち略中央領域A1に相当する部位に配索されたボンディングワイヤ6Aのワイヤ径DAを、それ以外の領域A2の部位に配索されたボンディングワイヤ6Bのワイヤ径DBよりも太くした構成としている。
In the semiconductor device according to the second embodiment, unlike the first embodiment in which the wire diameters of all the
前記ゲル状充填材8は、半導体装置1に発生する振動によって略中央領域A1が最も加振の影響を受けて揺動する。そのため、ゲル状充填材8の略中央領域A1に相当する部位に配索されたボンディングワイヤ6Aは、それ以外の領域A2に相当する部位に配索されたボンディングワイヤ6Bに作用する応力よりも大きな応力を受ける。したがって、この略中央領域A1に相当する部位に配索されたボンディングワイヤ6Aのワイヤ径を、それ以外の領域A2に相当する部位に配索されたボンディングワイヤ6Bのワイヤ径よりも太くすることで、中央領域A1のボンディングワイヤ6Aのワイヤ剛性が高くなることにより、このボンディングワイヤ6Aに作用する応力を低減することができ、当該ボンディングワイヤ6Aの断線を防止することができる。
The gel-
なお、この実施形態3の半導体装置においては、先の実施形態2と同様、ボンディングワイヤ6の配索高さHの高い側のボンディングワイヤのワイヤ径に比べて配索高さHの低い側のボンディングワイヤのワイヤ径を太くしてもよい。 In the semiconductor device according to the third embodiment, as in the second embodiment, the wire on the side where the wiring height H is lower than the wire diameter of the bonding wire on the side where the bonding wire H is high is connected. The wire diameter of the bonding wire may be increased.
「実施形態4」
図8はゲル状充填材のうち略中央領域に相当する部位を除いてボンディングワイヤを配索した実施形態4を示す図である。
“
FIG. 8 is a
実施形態4では、ゲル状充填材8の略中央領域A1が最も揺動するため、この略中央領域A1に相当する部位にボンディングワイヤ6を配索せず、この略中央領域A1を除く領域にボンディングワイヤ6を配索させている。
In the fourth embodiment, the substantially central region A1 of the
このように構成した実施形態4の半導体装置では、ゲル状充填材8が最も揺動する略中央領域A1に相当する部位を除いてボンディングワイヤ6を配索しているので、中央領域A1以外の部位に配索されたボンディングワイヤ6への応力が抑制される。したがって、実施形態4によれば、ボンディングワイヤ6の断線を防止することができ、該ボンディングワイヤ6の耐振信頼性を向上させることができる。
In the semiconductor device of the fourth embodiment configured as described above, the
本発明は、回路基板上に実装された半導体素子と導体を接続するボンディングワイヤ等をゲル状充填材で覆った半導体装置を自動車等に搭載する技術として利用することができる。 INDUSTRIAL APPLICABILITY The present invention can be used as a technique for mounting a semiconductor device in which a bonding wire or the like connecting a semiconductor element mounted on a circuit board and a conductor is covered with a gel filler on an automobile or the like.
1…半導体装置
2…回路基板
3…半導体素子
4…絶縁体
5…導体
6(6a,6b,6c)…ボンディングワイヤ
7…ケース
8…ゲル状充填材
9…放熱板
10…蓋
DESCRIPTION OF
Claims (4)
前記回路基板上に絶縁体を介して積層された導体と、
前記半導体素子と前記導体とを電気的に繋ぐボンディングワイヤと、
前記回路基板を内部に収容するように該回路基板の周囲に取り付けられたケースと、
前記ケース内に充填されて少なくとも前記半導体素子と前記ボンディングワイヤを保護するゲル状充填材と、を備えた半導体装置であって、
前記半導体装置に発生する振動方向と前記ゲル状充填材の短手方向を一致させて前記ゲル状充填材を前記ケース内に充填すると共に、前記ゲル状充填材の長手方向を前記ボンディングワイヤの配索方向に一致させた
ことを特徴とする半導体装置。 A semiconductor element mounted on a circuit board;
A conductor laminated via an insulator on the circuit board;
A bonding wire that electrically connects the semiconductor element and the conductor;
A case attached around the circuit board so as to accommodate the circuit board;
A semiconductor device comprising a gel-like filler filled in the case and protecting at least the semiconductor element and the bonding wire,
The vibration direction generated in the semiconductor device and the short direction of the gel filler are aligned to fill the case with the gel filler, and the longitudinal direction of the gel filler is aligned with the bonding wire. A semiconductor device characterized by matching with the direction of the cable.
前記ボンディングワイヤの配索高さが異なる場合に、配索高さの高い側のボンディングワイヤのワイヤ径に比べて配索高さの低い側のボンディングワイヤのワイヤ径を太くした
ことを特徴とする半導体装置。 The semiconductor device according to claim 1,
When the wiring height of the bonding wire is different, the wire diameter of the bonding wire having a lower wiring height is made larger than the wire diameter of the bonding wire having a higher wiring height. Semiconductor device.
前記ゲル状充填材のうち略中央領域に相当する部位に配索された前記ボンディングワイヤのワイヤ径を、それ以外の領域に相当する部位に配索されたボンディングワイヤのワイヤ径よりも太くした
ことを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2, wherein
The wire diameter of the bonding wire routed in the portion corresponding to the substantially central region of the gel filler is made larger than the wire diameter of the bonding wire routed in the portion corresponding to the other region. A semiconductor device characterized by the above.
前記ゲル状充填材のうち略中央領域に相当する部位を除く領域に前記ボンディングワイヤを配索した
ことを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2, wherein
The bonding wire is routed in a region excluding a portion corresponding to a substantially central region in the gel filler.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009116755A JP5428512B2 (en) | 2009-05-13 | 2009-05-13 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009116755A JP5428512B2 (en) | 2009-05-13 | 2009-05-13 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010267727A true JP2010267727A (en) | 2010-11-25 |
JP5428512B2 JP5428512B2 (en) | 2014-02-26 |
Family
ID=43364471
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009116755A Active JP5428512B2 (en) | 2009-05-13 | 2009-05-13 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5428512B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2014097798A1 (en) * | 2012-12-18 | 2017-01-12 | 富士電機株式会社 | Semiconductor device |
JP2017079307A (en) * | 2015-10-22 | 2017-04-27 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01265544A (en) * | 1988-04-15 | 1989-10-23 | Hitachi Ltd | Electronic device |
JPH07263621A (en) * | 1994-03-18 | 1995-10-13 | Toshiba Corp | Semiconductor device |
JP2001298144A (en) * | 2000-04-13 | 2001-10-26 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
JP2008192971A (en) * | 2007-02-07 | 2008-08-21 | Renesas Technology Corp | Semiconductor device |
-
2009
- 2009-05-13 JP JP2009116755A patent/JP5428512B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01265544A (en) * | 1988-04-15 | 1989-10-23 | Hitachi Ltd | Electronic device |
JPH07263621A (en) * | 1994-03-18 | 1995-10-13 | Toshiba Corp | Semiconductor device |
JP2001298144A (en) * | 2000-04-13 | 2001-10-26 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
JP2008192971A (en) * | 2007-02-07 | 2008-08-21 | Renesas Technology Corp | Semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2014097798A1 (en) * | 2012-12-18 | 2017-01-12 | 富士電機株式会社 | Semiconductor device |
JP2017079307A (en) * | 2015-10-22 | 2017-04-27 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
US10600765B2 (en) | 2015-10-22 | 2020-03-24 | Mitsubishi Electric Corporation | Semiconductor device and method for producing the same |
Also Published As
Publication number | Publication date |
---|---|
JP5428512B2 (en) | 2014-02-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5206822B2 (en) | Semiconductor device | |
US8643234B2 (en) | Electrical rotating machine | |
JP6455364B2 (en) | Semiconductor device, intelligent power module and power converter | |
JP4655020B2 (en) | Smoothing capacitor module and power converter using the same | |
KR101343140B1 (en) | 3D power module package | |
JP6562998B2 (en) | Power converter | |
JP5821949B2 (en) | SEMICONDUCTOR DEVICE, INVERTER DEVICE HAVING THE SAME, AND VEHICLE ROTARY ELECTRIC DEVICE HAVING THE SAME | |
WO2015174158A1 (en) | Power semiconductor module and composite module | |
US10938269B2 (en) | Motor with stress absorbing portions | |
JP2004190547A (en) | Inverter integrated motor-driven compressor and its assembling method | |
JP2003324903A (en) | Inverter integrated motor for vehicle | |
JP2014120657A (en) | Semiconductor device | |
US20140233188A1 (en) | Mounting structure for printed circuit board, and semiconductor device using such structure | |
JP5428512B2 (en) | Semiconductor device | |
JP2012204576A (en) | Semiconductor device | |
JP6094197B2 (en) | Power module | |
JP2013197573A (en) | Semiconductor device | |
JP6395894B1 (en) | Controller-integrated rotating electrical machine | |
JP2008294338A (en) | Power module, and transport machine equipped with the same | |
ES2392206T3 (en) | Configuration with at least one semiconductor component, in particular a semiconductor power component for the control of high intensity current power | |
JP4407712B2 (en) | Actuator control device and electric brake device | |
JP6869309B2 (en) | Power converter and power converter integrated rotary electric machine | |
JP6147359B2 (en) | Electronic component fixing structure | |
JP2010267726A (en) | Semiconductor device | |
WO2016194815A1 (en) | Control device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120328 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20121126 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130402 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130517 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131105 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131118 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 5428512 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |