WO2006011232A1 - リコンフィギュラブル回路およびリコンフィギュラブル回路の制御方法 - Google Patents
リコンフィギュラブル回路およびリコンフィギュラブル回路の制御方法 Download PDFInfo
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- WO2006011232A1 WO2006011232A1 PCT/JP2004/010953 JP2004010953W WO2006011232A1 WO 2006011232 A1 WO2006011232 A1 WO 2006011232A1 JP 2004010953 W JP2004010953 W JP 2004010953W WO 2006011232 A1 WO2006011232 A1 WO 2006011232A1
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- configuration information
- configuration
- processing
- reconfigurable circuit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Definitions
- the present invention relates to a reconfigurable circuit and a control method for the reconfigurable circuit, and more particularly to a reconfigurable circuit and a reconfigurable circuit having a plurality of processing elements whose configurations are reconfigured by configuration information.
- the present invention relates to a control method for a labile circuit.
- a reconfigurable circuit having a reconfigurable arithmetic unit group.
- the reconfigurable circuit configures a computing unit group based on the configuration data and can perform various processes.
- the reconfigurable circuit if one pipeline process cannot be implemented, the reconfigurable circuit is divided into pipeline stages, and the processes at each stage are switched sequentially.
- FIG. 10 is a circuit block diagram of a conventional reconfigurable circuit.
- the reconfigurable circuit has a processing element (PE:
- Processing Element 101a, 101d, and network 102.
- Each of PElOla 101d includes, for example, a plurality of ALUs (Arithmetic Logical Units), multipliers, and adders.
- ALUs Arimetic Logical Units
- multipliers and adders.
- adder of PElOla 101d are configured based on configuration data so that one stage of pipeline processing can be performed.
- the network 102 connects the PElOla 101d based on the configuration data so that the PElOla-101d can perform pipeline processing.
- pipeline processing refers to processing for performing sequential operations on sequentially input data.
- a product-sum operation indicated by a FIR (Finite Impulse Response) filter is a pipeline process that sequentially performs a product-sum operation on sequentially input data.
- An operation is one of the operations that are performed sequentially.
- the product-sum operation is sequentially performed on sequentially input data.
- One of the multiply-accumulate operations becomes one operation.
- Pipeline processing is divided into multiple stages, and one or more operations are performed in one stage.
- FIG. 11 is a diagram showing pipeline processing.
- Pipeline processing 111 shown in the figure performs one pipeline processing in operation OP1 0 P8.
- the arrows shown in the figure indicate the flow of data, and it is assumed that data to be processed in operation ⁇ P1 is sequentially input.
- the above-described product-sum operation is described as follows: Operation 0 P1-OP8 performs 8-stage product-sum operation on the data input to operation OP1, and each of operations OP1-OP8 has one Perform product-sum operation.
- FIG. 12 is a diagram showing a flow of the pipeline processing of FIG. 11 in the reconfigurable circuit of FIG.
- the square shown in the figure represents PElOla-101d in FIG.
- operations OP1 to OP8 assigned to PEs 101a to 101d are shown.
- the data to be processed is sequentially input from operation OP1.
- operation OP1 is assigned to PElOla and data is input.
- PElOlb is assigned operation OP2.
- the data of operation OP1 processed in cycle 1 is input to PElOlb, and the next data is input to operation OP1.
- operations OP3, ⁇ P4 are assigned to cycles 3, 4 and PE1 01c, 101d, and the data of the previous operation (previous cycle) operation ⁇ P2, ⁇ P3 is input.
- data is sequentially input to operation OP1.
- cycles 6-8 operations OP6-OP8 are sequentially assigned to PElOlb-101d, and the data of operations 0P5-OP7 in the previous stage (previous cycle) is input. In cycles 5-8, no new data is input. Operation OP1 ⁇ P4 is not hit by P ElOla 101d, and cannot perform pipeline processing. Although not shown, when Cycle No. 9, PElOla is assigned operation O1 and the next data is input.
- the method of dividing PElOla 101d and sequentially switching and implementing the pipeline processing of each stage is different from the method of implementing pipeline stages that can be implemented in PE 101a 101d at once. Processing time is shortened. In the method of mounting at once, after processing of the installed pipeline stage is completed, the processing result must be temporarily saved in the storage device, and then the next pipeline stage must be mounted on PElOla-101d. It is. On the other hand, in the method of sequentially switching and implementing pipeline processing at each stage, the processing time is not temporarily saved in the storage device, so the processing time is shortened.
- FIG. 13 is a diagram illustrating pipeline processing when a plurality of pipeline stages are simultaneously allocated to processing elements.
- FIG. 14 is a diagram showing a flow of the pipeline processing of FIG. 13 in the reconfigurable circuit of FIG.
- PElOla shows the operation 0P1-OP7 assigned to lOld.
- the data to be processed is sequentially input from operations OP1 and OP2. none indicates that the operation is assigned and the status is valid.
- the first stage of the pipeline processing 112 shown in FIG. 13 is that operations OP1 and OP2 and two operations must be executed.
- operations OP3, ⁇ P4 and two operations must be executed. Therefore, the reconfigurable circuit shown in Fig. 10 needs to be configured so that PElOla, 10 lb and PElOlc, lOld can execute two operations simultaneously, as shown in Fig. 14.
- cycle 1 operations O1 and O2 are assigned to PElOla and 101b, and data is input to each of them.
- PElOlc and lOld are subjected to operation OP3 and OP4 forces.
- the data of operations OP1 and OP2 processed in cycle 1 are input to PElOlc and lOld.
- the following data is input to the operations OP 1 and OP 2.
- operation OP5—O P7 is assigned to PElOla, 101b and PE 101c, lOld in sequence, and the previous data is input.
- Operation OP5-— OP7 needs to be processed one by one as shown in Fig. 13, so only one can be installed in PElOla, 101b and PElOlc, lOld.
- PElOla, 101b and PElOlc, lOld are configured to execute two operations at the same time. Therefore, PElOla, 101b and PE101c, lOld have one processing element in an empty state (none), resulting in low mounting efficiency.
- cycle 6 following operation of cycle 5, operation ⁇ P7 must be implemented in PElOla, 101b. This is because the data input in cycle 1 is processed by operation OP7 in cycle 5 and ends. The data input in cycle 2 is still processed only in operation OP6 in cycle 5. It is not necessary to perform operation OP7 in cycle 6.
- Cycle 3 In cycle 6, no data is input, and the next data can be input in the next cycle 7.
- FIG. 15 is a timing chart showing data input / output timing of the pipeline processing of FIG.
- CLK shown in the figure indicates the timing at which the operation is executed.
- IN indicates the timing of data input to operations 0P1 and 0P2.
- OUT indicates the timing of the data output from operation O P7.
- FCCM Computiong Machines
- the present invention has been made in view of such a point, and improves the mounting efficiency of the pipeline processing to the processing element, and improves the processing performance of the reconfigurable circuit and the reconfigurable circuit.
- An object is to provide a control method.
- a plurality of storage units la and lb in which configuration information of a plurality of PE4a-4d is stored and configuration information in each stage of pipeline processing 5 processed by the plurality of PE4a-4d A storage switching unit 2 that switches and stores the units la and lb, and a configuration information output unit 3 that switches the plurality of storage units la and lb and outputs the configuration information to the plurality of PE4a-4d.
- a featured reconfigurable circuit is provided.
- a plurality of storage units la and lb are provided, and the configuration information of each stage of the pipeline processing 5 is switched and stored. Then, the plurality of storage units la and lb are switched, and the configuration information is output to the plurality of PEs 4a 4d. Therefore, virtually all pipeline processing stages can be assigned to PE4a-4d.
- the reconfigurable circuit of the present invention includes a plurality of storage units, and switches and stores the configuration information of each stage of the nopline processing. Then, a plurality of storage units are switched to output configuration information to a plurality of processing elements. As a result, it is possible to virtually assign all stages of pipeline processing to processing elements, improve the efficiency of mounting pipeline processing on processing elements, and improve processing performance.
- FIG. 1 is a diagram illustrating an outline of a reconfigurable circuit.
- FIG. 2 is a circuit block diagram of a reconfigurable circuit according to the first embodiment.
- FIG. 3 is a circuit block diagram of a configuration switching unit.
- FIG. 4 is a circuit block diagram of the network.
- FIG. 5 is a diagram showing a flow of the pipeline processing of FIG. 13 in the reconfigurable circuit of FIG.
- FIG. 6 is a timing chart showing data input / output timing of the pipeline processing of FIG. 13 in the reconfiguration circuit of FIG.
- FIG. 7 is a diagram for explaining the operation of the configuration load unit in FIG. 3.
- FIG. 8 is a diagram showing pipeline processing for explaining a second embodiment.
- FIG. 9 is a diagram showing a flow of the pipeline processing of FIG. 8 in a reconfigurable circuit having flip-flops.
- FIG. 10 is a circuit block diagram of a conventional reconfigurable circuit.
- FIG. 11 is a diagram showing pipeline processing.
- FIG. 12 is a diagram showing the flow of the pipeline processing of FIG. 11 in the reconfigurable circuit of FIG.
- FIG. 13 is a diagram showing pipeline processing when a plurality of pipeline stages are simultaneously assigned to a processing element.
- FIG. 14 is a diagram showing the flow of the pipeline processing of FIG. 13 in the reconfigurable circuit of FIG.
- FIG. 15 is a timing chart showing the input / output timing of the pipeline processing data in FIG.
- FIG. 1 is a diagram for explaining the outline of the reconfigurable circuit.
- the reconfigurable circuit includes storage units la and lb, a storage switching unit 2, a configuration information output unit 3, and PE4a-4d.
- the figure also shows pipeline processing 5 that is processed by the reconfigurable circuit.
- the storage units la and lb store the configuration information of the PE4a 4d.
- the PE 4a 4d has a circuit configured by the configuration information stored in the storage units la and lb, and performs predetermined processing.
- the storage switching unit 2 stores the configuration information in each stage of the pipeline processing 5 processed by the PEs 4a-4d by switching the storage units la and lb in order from the first stage. Note that operations 1 and 2 are performed in the first stage of pipeline processing 5, and operations OP3 and OP4 are performed in the second stage. 3rd stage 1st 5th stage Operation OP5- OP7 is performed. Then, it is assumed that data is sequentially input in operations 0 P1 and OP2. Also, the configuration information for realizing the processing of operations OP1-OP7 with PE4a-4d is OPC1-OPC7. [0032] The configuration information output unit 3 switches the storage units la and lb, and outputs the configuration information stored in the storage units la and lb to the plurality of PEs 4a-4d.
- the storage switching unit 2 stores the configuration information OPCl and OPC2 of the first stage of the pipeline processing 5 from the storage unit la. Thereafter, the storage units la and lb are alternately switched to store the configuration information OPC3 to OPC7 of each stage.
- the configuration information output unit 3 outputs the configuration information from the storage unit la to the PE 4a-4d, and thereafter outputs the configuration information by alternately switching the storage units la and lb.
- the storage switching unit 2 stores the configuration information OPC1 and OPC2 of the operations OP1 and OP2 in the first stage of the pipeline processing 5 in the storage unit la.
- the configuration information output unit 3 outputs the configuration information OPCl and OPC2 of the storage unit la to the PEs 4a and 4b.
- PE4a and 4b are configured according to the configuration information OPCl and OPC2. As a result, data is input to the operations OP 1 and OP2 and processed.
- the storage switching unit 2 stores the configuration information OPC3, OPC4 of the operations OP3, OP4 in the second stage of the pipeline processing 5 in the storage unit lb.
- the configuration information output unit 3 outputs the configuration information OPC3 and OPC4 of the storage unit lb to the PEs 4a and 4b.
- PE4a and 4b a circuit according to the configuration information OPC3 and OPC4 is configured.
- operations OP3 and OP4 are processed.
- the configuration information OPC3 inputs at least the data of PE4a force S itself (data of operation OP1 processed last time) and the data output from PE4b (data of operation OP2 processed last time). It has a connection relationship.
- PE4b inputs its own data (data of operation ⁇ P2 processed last time) and data output from PE4a (data of operation ⁇ P1 processed last time) is input. It has a connection relationship.
- the storage switching unit 2 stores the configuration information 0PC5 of the operation 0P5 in the third stage of the pipeline processing 5 in the storage unit la.
- the configuration information output unit 3 outputs the configuration information OPCl, OPC2 and OPC5 of the storage unit la to the PE4a 4c.
- PE4a 4c contains configuration information Information A circuit according to OPCl, OPC2, OPC5 is constructed. As a result, the operation OP5 is processed.
- operations PE1 and OP2 are configured in PE4a and 4b, the following data can be input to operations OP1 and OP2.
- the storage switching unit 2 stores the configuration information OPC6 of the operation OP6 in the fourth stage of the pipeline processing 5 in the storage unit lb.
- the configuration information output unit 3 outputs the configuration information OPC3, OPC4, and OPC6 of the storage unit lb to the PE4a 4c.
- PE4a 4c a circuit according to the configuration information OPC3, OPC4, and OPC6 is configured.
- the processing of operation OP6 is performed. Since operations OP3 and ⁇ P4 are configured in PE4a and 4b, the data of operations ⁇ 1 and OP2 processed in the previous stage can be processed in operation OP3, ⁇ P4.
- the storage switching unit 2 stores the configuration information OPC7 of the operation OP7 in the fifth stage of the pipeline processing 5 in the storage unit la.
- the configuration information output unit 3 outputs the configuration information OPCl, OPC2, OPC5, and OPC7 of the storage unit la to the PE4a-4d.
- PE4a-4d is composed of circuits according to the configuration information OPCl, OPC2, OPC5, OPC7.
- the processing of operation OP7 is performed. Since PE4a-4c is configured with operations OP1, OP2, and OP5, the next data can be input to operations OP1 and OP2, and the data of operations ⁇ P3 and OP4 processed in the previous stage is operated. Can be processed with OP 5.
- pipeline processing 5 is performed.
- a plurality of storage units la and lb are provided, and the configuration information of each stage of the pipeline processing 5 is switched and stored. Then, the plurality of storage units la and lb are switched to output the configuration information to a plurality of PE4a-4d.
- all stages of pipeline processing 5 can be virtually damaged by PE4a 4d, improving the efficiency of mounting pipeline processing on processing elements and improving processing performance. Can do.
- FIG. 2 is a circuit block diagram of the reconfigurable circuit according to the first embodiment.
- the reconfigurable circuit includes a configuration switching unit 10, a network 20, and PEs 31-34.
- the configuration switching unit 10 has a plurality of memories.
- the configuration switching unit 10 performs processing described later based on the configuration data, and stores the configuration data by switching a plurality of memories.
- the plurality of memories are switched for each cycle, and the configuration data of the selected memory is executed in PE31.
- Each of the PE31-34 has a plurality of ALUs, multipliers, and adders, for example.
- Each ALU, multiplier, and adder of PE31-34 are configured based on configuration data so that one operation of pipeline processing can be realized.
- the network 20 connects the PEs 31-34 based on the configuration data so that the PE 31 34 performs predetermined pipeline processing.
- the configuration switching unit 10 will be described in detail.
- FIG. 3 is a circuit block diagram of the configuration switching unit.
- the configuration switching unit 10 includes a configuration memory 1
- the configuration memory 11 stores configuration data that determines the configuration of the PE 31-34 and the connection relationship of the network 20.
- the sequencer 12 selects the next configuration data to be output based on the configuration data currently output from the configuration memory 11.
- Control to output to the configuration toggle section 13-16 Control to output to the configuration toggle section 13-16.
- the sequencer 12 switches the output of configuration data on a task basis.
- the configuration toggle section 13 16 is provided corresponding to the PE 31-34.
- the configuration toggle unit 13-16 outputs the configuration data output from the configuration memory 11 to the corresponding PE 31-34 and the network 20 based on a predetermined process.
- the configuration toggle section 13 includes a configuration load section 13a, a low force NOR configuration memory 13ba-13bf, a selector 13c, and a counter 13d. Note that the configuration toggle part 14 1 16 is a configuration toggle.
- the circuit configuration is the same as that of the unit 13, and the description thereof is omitted.
- the configuration load unit 13a performs processing described later based on the configuration data output from the configuration memory 11, and stores the configuration data by switching the local configuration memory 13ba 13bf. ⁇
- the local configuration memory 13ba 13bf stores configuration data.
- the configuration data stored in the local configuration memory 13ba 13bf is output to the PE 31 via the selector 13c.
- the selector 13c selects the configuration data stored in the local configuration memory 13ba 13bf according to the signal output from the counter 13d, and outputs it to the PE 31 and the network 20.
- the counter 13d outputs a signal for controlling the output of the selector 13c to the selector 13c.
- the counter 13d outputs a signal to the selector 13c so as to be output to the data power PE31 of the local configuration memory 13ba-13bf in which the configuration data is stored.
- the counter 13d repeatedly counts the numbers from 1 to 4 and outputs them to the selector 13c.
- the selector 13c outputs the configuration data of the local configuration memory 13 ba-13bd corresponding to the number 1 to 4.
- the local configuration data is output to the configuration data PE31 of the local configuration memory 13ba-13bd in which the local configuration data is stored.
- Fig. 4 is a circuit block diagram of the network.
- the network 20 has selectors 21-28.
- the inputs of selectors 21-28 are connected to four signal lines connected to PE31-34.
- the output of selector 2 1 1 28 is connected to PE31-34 and output.
- the selector 21 28 is connected to the configuration toggle section 13 14 and is input based on the configuration data. Control the output of the generated signal. As a result, the connection relationship of PE31-34 can be determined.
- Each PE 31 34 of the reconfigurable circuit shown in FIG. 2 is configured to execute one operation of the pipeline processing 112.
- FIG. 5 is a diagram illustrating the flow of the pipeline processing of FIG. 13 in the reconfigurable circuit of FIG.
- the large square in the figure represents PE31-34 in Figure 2.
- the operation ⁇ P1-OP7 assigned to PE31-34 is shown. none indicates that the operation is assigned and indicates the status.
- the small squares indicate the connection relationships of PE31-34 in Fig. 2 by the numbers shown therein. 1 1 4 indicates that each is connected to PE 31 34.
- PE31 1 and 2 with OP3 assigned in S2 of cycle 2 indicate that they are connected to PE31 force PE31 (self) and PE32.
- the configuration surfaces SI and S2 in each cycle correspond to the local configuration memory of the configuration toggle section 13-16 shown in FIG.
- the configuration plane S1 corresponds to the local configuration memory 13ba and the local configuration memory corresponding to the local configuration memory 13ba of the configuration toggle unit 14-16.
- the configuration surface S2 corresponds to the local configuration memory 13bb and the local configuration memory corresponding to the local configuration memory 13bb of the configuration toggle unit 14-16.
- the configuration planes SI and S2 that is, the local configuration memory, switch every cycle, and PE31-34 is connected in the connection relationship (numbers in small squares) indicated by the configuration planes Sl and S2. Is done. In cycle 1, configuration plane S1 is executed, and in cycle 2, configuration plane S2 is executed. After that, configuration surfaces SI and S2 alternately Suppose that switches. In addition, the number of faces differs depending on the number of stages of pipeline processing 112 and the number of processing elements, and may be 2 or more. How to determine the number of faces will be described later
- cycle 2 the configuration plane S2 is valid, and operations OP3 and OP4 in the second stage of the pipeline processing 112 shown in FIG. 13 are assigned to PEs 31 and 32.
- PE31 is connected to itself and PE32 according to the configuration data.
- PE32 is connected to PE31 and itself.
- the data of operations OP1 and OP2 processed in cycle 1 are input to operation OP3.
- operation OP4 the data of operation ⁇ P1 and OP2 processed in cycle 1 is input. Therefore, the processing up to the second stage of the pipeline processing 112 shown in FIG. 13 is performed.
- cycle 3 configuration plane S1 is enabled, and operation OP5 is assigned to PE33.
- PE33 is connected to PE31 and PE32 according to the configuration data.
- operation OP5 is input to operation OP5.
- the following data is input to the operations 0P1 and OP2 assigned to the PEs 31 and 32.
- cycle 4 the configuration plane S2 becomes valid, and the operation OP6 is assigned to PE33.
- PE33 is connected to PE33 according to the configuration data.
- the data of operation O P5 processed in cycle 3 is input to operation O P6.
- cycle 5 configuration plane S1 is enabled, and PE34 is Yong OP7 is assigned. At this time, as shown in the small square, PE34 is connected to PE33 according to the configuration data. As a result, the data of operation OP6 processed in cycle 4 is input to operation OP7. In cycle 3, the following data is input to operations ⁇ P1 and OP2 assigned to PE31 and 32.
- configuration surfaces Sl and S2 are provided for PE31-34. Then, the operations of each stage of the pipeline processing 112 are alternately assigned to the configuration surfaces SI and S2 (actually, each stage of the pipeline processing 112 is alternately assigned to the configuration surfaces SI and S2. Operation configuration data is stored). Alternately, the configuration data stored in the configuration planes Sl and S2 is output to the PE 31-34, and the pipeline processing 112 is executed.
- FIG. 6 is a timing chart showing the input / output timing of the data in the pipeline processing of FIG. 13 in the reconfiguration circuit of FIG.
- CLK shown in the figure indicates the timing at which the operation is executed.
- IN indicates the timing of data input to operation 0 P1 and OP2.
- OUT indicates the timing of data output from operation OP7.
- the operation OP7 is processed at CLK5 for the data input at CLK1. Therefore, the data input at CLK1 is output at CLK6.
- the data input at CL K3 is processed for operation OP7 at CLK7. Therefore, the data input at CLK3 is output at CLK8.
- FIG. 7 is a diagram for explaining the operation of the configuration load unit in FIG.
- the configuration loading unit 13a in FIG. 3 first determines the number of configuration surfaces necessary for the pipeline processing to be processed.
- the configuration load unit 13a performs Nop / Npe division based on the configuration data output from the configuration memory 11.
- Nop is the number of pipeline processing operations
- Npe is the number of processing elements. If Nop / Npe force S is divisible by Lower O, the division result is taken as the number of configuration faces, and if it is not divisible, the smallest integer value equal to or greater than the division result is taken as the number of faces in the configuration face.
- the configuration loading unit 13a loads the configuration surface created in advance by the following procedure from the configuration memory 11 stored therein, and sets it in the local configuration memory 13ba.
- the method of creating each configuration surface is as follows.
- the configuration loading unit 13a loads the determined configuration plane from the configuration memory 11, and assigns the pipeline processing operation to the processing element. Since the number of configuration planes differs for each pipeline process, a plurality of local configuration memories 13ba-13bf are provided so as to be compatible with various pipeline processes.
- the circuit configuration of the reconfigurable circuit according to the second embodiment has a storage device that temporarily saves the data processed in the operation, for example, a flip-flop. This is different from the circuit configuration of the reconfigurable circuit according to the first embodiment. Therefore, recon A detailed description of the circuit configuration of the FIG.
- FIG. 8 is a diagram showing pipeline processing for explaining the second embodiment.
- operations 0P1 and OP2 are processed in the first stage.
- Operation OP3 is processed in the second stage, and operations ⁇ P4 and OP5 are processed in the third stage.
- operations ⁇ P6 and ⁇ P7 are processed sequentially.
- the arrows in the figure indicate the flow of data, and it is assumed that the data to be processed are sequentially input to operations ⁇ 1 and ⁇ P2.
- the implementation of this pipeline processing 41 in the reconfigurable circuit of FIG. 2 having a flip-flop that temporarily holds data will be described.
- FIG. 9 is a diagram showing the flow of the pipeline processing of FIG. 8 in the reconfigurable circuit having flip-flops.
- the squares shown in the figure indicate PE3 1 1 34 of the reconfigurable circuit of FIG. 2 equipped with flip-flops. In the square, operations OP1-OP7 assigned to PE3134 are shown.
- SI and S2 shown in the figure indicate configuration surfaces.
- FF42 indicates a flip-flop included in the reconfigurable circuit of FIG. Operations OP1- OP7 of pipeline processing 41 in Fig. 8 are alternately assigned to PE31-34 of configuration plane SI, S2 every cycle.
- operation OP3 is assigned to PE31 in configuration plane S2.
- operation OP6 is assigned to PE32 in configuration plane S2.
- cycle 5 the operation element P1 should be assigned the processing element P1 in the configuration plane S1.
- PE33 and 34 in configuration S2 are still assigned operations. It is not available and there is a vacancy and it is possible to assign operation OP7 to PE33. Therefore, in cycle 5, the data processed in operation OP6 is temporarily stored in FF42.
- cycle 6 operation OP7 is assigned to PE33 of configuration plane S2. At this time, FF42 data is read into PE33.
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Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2006527758A JP4201816B2 (ja) | 2004-07-30 | 2004-07-30 | リコンフィギュラブル回路およびリコンフィギュラブル回路の制御方法 |
CNB2004800429986A CN100545827C (zh) | 2004-07-30 | 2004-07-30 | 可重配置电路及可重配置电路的控制方法 |
EP04748114A EP1780644A4 (en) | 2004-07-30 | 2004-07-30 | CONVERTIBLE CIRCUIT AND CONTROL PROCEDURE OF A CONVERTIBLE CIRCUIT |
PCT/JP2004/010953 WO2006011232A1 (ja) | 2004-07-30 | 2004-07-30 | リコンフィギュラブル回路およびリコンフィギュラブル回路の制御方法 |
US11/546,284 US7849288B2 (en) | 2004-07-30 | 2006-10-12 | Alternately selecting memory units to store and retrieve configuration information in respective areas for a plurality of processing elements to perform pipelined processes |
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PCT/JP2004/010953 WO2006011232A1 (ja) | 2004-07-30 | 2004-07-30 | リコンフィギュラブル回路およびリコンフィギュラブル回路の制御方法 |
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US11/546,284 Continuation US7849288B2 (en) | 2004-07-30 | 2006-10-12 | Alternately selecting memory units to store and retrieve configuration information in respective areas for a plurality of processing elements to perform pipelined processes |
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EP (1) | EP1780644A4 (ja) |
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Cited By (3)
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JP2008181361A (ja) * | 2007-01-25 | 2008-08-07 | Fuji Xerox Co Ltd | データ処理装置、画像処理装置、及びデータ処理プログラム |
JP2011522317A (ja) * | 2008-05-29 | 2011-07-28 | アクシス・セミコンダクター・インコーポレーテッド | リアルタイムな信号処理及び更新のためのマイクロプロセッサ技術 |
JPWO2014132669A1 (ja) * | 2013-03-01 | 2017-02-02 | アトナープ株式会社 | データ処理装置およびその制御方法 |
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US8099583B2 (en) | 2006-08-23 | 2012-01-17 | Axis Semiconductor, Inc. | Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing |
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Also Published As
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CN100545827C (zh) | 2009-09-30 |
JP4201816B2 (ja) | 2008-12-24 |
JPWO2006011232A1 (ja) | 2008-05-01 |
EP1780644A4 (en) | 2007-11-21 |
US20070083733A1 (en) | 2007-04-12 |
CN1954311A (zh) | 2007-04-25 |
US7849288B2 (en) | 2010-12-07 |
EP1780644A1 (en) | 2007-05-02 |
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