WO2005123988A1 - Procede de traitement de surface a couche barriere pour permettre le cuivrage direct sur un metal barriere - Google Patents

Procede de traitement de surface a couche barriere pour permettre le cuivrage direct sur un metal barriere Download PDF

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WO2005123988A1
WO2005123988A1 PCT/US2005/019902 US2005019902W WO2005123988A1 WO 2005123988 A1 WO2005123988 A1 WO 2005123988A1 US 2005019902 W US2005019902 W US 2005019902W WO 2005123988 A1 WO2005123988 A1 WO 2005123988A1
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plating
copper
substrate
group viii
current density
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PCT/US2005/019902
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WO2005123988B1 (fr
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Zhi-Wen Sun
Renren He
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Applied Materials, Inc.
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Priority to EP05758773A priority Critical patent/EP1778896A1/fr
Priority to JP2007527630A priority patent/JP2008502806A/ja
Publication of WO2005123988A1 publication Critical patent/WO2005123988A1/fr
Publication of WO2005123988B1 publication Critical patent/WO2005123988B1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/34—Pretreatment of metallic surfaces to be electroplated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the invention generally relate to a method for barrier layer surface treatment to enable direct copper plating on barrier metal.
  • VLSI very large scale integration
  • ULSI ultra large scale integration
  • the multilevel interconnects that lie at the heart of this technology require the filling of contacts, vias, lines, and other features formed in high aspect ratio apertures. Reliable formation of these features is very important to the success of both VLSI and ULSI as well as to the continued effort to increase circuit density and quality on individual substrates and die.
  • the widths of contacts, vias, lines and other features, as well as the dielectric materials between them may be decreased to less than about 65 nm, whereas the thickness of the dielectric layers remains substantially constant with the result that the aspect ratios for the features, i.e., their height divided by width, increase.
  • Many conventional deposition processes do not consistently fill structures in which the aspect ratio exceeds 6:1 , and particularly when the aspect ratio exceeds 10:1. As such, there is a great amount of ongoing effort being directed at the formation of void-free, nanometer-sized structures having high aspect ratios wherein the ratio of feature height to feature width could be 6:1 or higher.
  • the device current typically remains constant or increases, which results in an increased current density for such features.
  • Elemental aluminum and aluminum alloys have been the traditional metals used to form vias and lines in semiconductor devices because aluminum has a perceived low electrical resistivity, superior adhesion to most dielectric materials, and ease of patterning, and the aluminum in a highly pure form is readily available.
  • aluminum has a higher electrical resistivity than other more conductive metals, such as copper (Cu).
  • Cu copper
  • Aluminum can also suffer from electromigration, leading to the formation of voids in the conductor.
  • Copper and copper alloys have lower resistivities than aluminum, as well as a significantly higher electromigration resistance compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Copper also has good thermal conductivity. Therefore, copper is becoming a choice metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.
  • ECP processes are generally two-stage processes, wherein a seed layer is first formed over the surface of features on the substrate (this process may be performed in a separate system), and then the surface of the features is exposed to an electrolyte solution while an electrical bias is simultaneously applied between the substrate surface and an anode positioned within the electrolyte solution.
  • ALD and CVD techniques are also prone to generate discontinuities in the seed layer. These discontinuities in the seed layer have been shown to cause plating defects in the layers plated over the seed layer.
  • copper tends to oxidize readily in the atmosphere and copper oxide readily dissolves in the plating solution.
  • the copper seed layer is usually made relatively thick (as high as 800 A), which can inhibit the plating process from filling the features. Therefore, it is desirable to have a copper plating process that allows direct electroplating of copper on thin barrier layer(s) without a copper seed layer. [0009] Therefore, there is a need for a copper plating process that can fill features and does not require a copper seed layer.
  • Embodiments of the invention generally provide a method of barrier layer surface treatment to enable direct copper plating without copper seed layer.
  • a method of directly plating copper on a substrate with a group VIII metal layer on the substrate surface comprises pre-treating the substrate surface to remove a group VIII metal surface oxide layer and/or organic surface contaminants on the substrate surface to reduce a critical current density during plating, and plating a continuous and void-free copper layer on the pre-treated substrate surface in an acidic plating bath with a plating current density equaling to or greater than the critical current density.
  • Figure 2 shows the critical current density as a function of sulfuric acid concentration.
  • Figure 3A shows the process flow of pre-treating a substrate surface before copper plating.
  • Figure 3B shows the critical current density as a function of sulfuric acid concentration for as-deposited and annealed Ru substrates.
  • Figure 4 shows the SEM of copper plated on annealed Ru surface in
  • Figure 5 is a top plan view of one embodiment of an electrochemical plating system.
  • Figure 6 illustrates an exemplary embodiment of a plating cell used in the electrochemical plating cell of the invention.
  • Ruthenium (Ru) thin films can be a potential candidate for a seedless diffusion barrier between intermetal dielectric (IMD) and copper interconnect for ⁇ 45 nm technology.
  • Ruthenium is a group VIII metal that has low electrical resistivity (resistivity ⁇ 7 ⁇ -cm) and high thermal stability (high melting point ⁇ 2300°C). It is relatively stable even in the presence of oxygen and water at ambient temperature.
  • the thermal and electrical conductivities of Ru are twice those of Tantalum (Ta). Ruthenium also does not form an alloy with copper below 900°C and shows good adhesion to copper. Therefore, the semiconductor industry has shown an interest in using Ru as a copper barrier layer.
  • the low resistivity of Ru can be an advantage when trying to fill ruthenium coated features with copper without a seed layer.
  • Figures 1A-1C illustrate cross-sectional views of a substrate at different stages of a copper interconnect fabrication sequence incorporating a group VIII metal barrier layer of the present invention.
  • Figure 1A for example, illustrates a cross-sectional view of a substrate 100 having metal contacts 104 and a dielectric layer 102 formed thereon.
  • the substrate 100 may comprise a semiconductor material such as, for example, silicon, germanium, or gallium arsenide.
  • the dielectric layer 102 may comprise an insulating material such as, silicon dioxide, silicon nitride, silicon oxynitride and/or carbon-doped silicon oxides, such as SiO x C y , for example, BLACK DIAMONDTM low-k dielectric, available from Applied Materials, Inc., located in Santa Clara, California.
  • the metal contacts 104 may comprise for example, copper, among others.
  • Apertures 120 may be defined in the dielectric layer 102 to provide openings over the metal contacts 104.
  • the apertures 120 may be defined in the dielectric layer 102 using conventional lithography and etching techniques.
  • the width of apertures 120 could be equal to or less than about 900 A.
  • the thickness of dielectric layer 102 could be in the range between about 1000 A to about 10000 A.
  • a barrier layer 106 may be formed in the apertures 120 defined in the dielectric layer 102.
  • the optional barrier layer 106 may include one or more refractory metal-containing layers used as a copper- barrier material such as, for example, titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, tungsten and tungsten nitride, among others.
  • the optional barrier layer 106 may be formed using a suitable deposition process, such as ALD, chemical vapor deposition (CVD) or physical vapor deposition (PVD).
  • titanium nitride may be deposited using a CVD process or an ALD process wherein titanium tetrachloride and ammonia are reacted.
  • tantalum and/or tantalum nitride is deposited as a barrier layer by an ALD process as described in commonly assigned United States Patent Publication 20030121608, published July 3, 2003, and is herein incorporated by reference.
  • the thickness of the optional barrier layer is between about 5 A to about 150 A and preferably less than 100 A.
  • a thin film of group VIII metal such as ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum (Pt) may be used as an underlayer (or barrier layer) for the copper vias and lines.
  • group VIII metal which is resistant to corrosion and oxidation, may provide a surface upon which a copper layer is subsequently deposited using an electrochemical plating (ECP) process.
  • ECP electrochemical plating
  • the group VIII metal acts as a copper-barrier layer.
  • the group VIII metal can also be deposited on the conventional barrier layer, such as Ta (tantalum) and/or TaN (tantalum nitride), to serve as a glue layer between the conventional barrier layer and copper.
  • the group VIII metal is typically deposited using a chemical vapor deposition (CVD) process, atomic layer deposition (ALD) or a physical vapor deposition (PVD) process.
  • a group VIII barrier metal layer 108 such as ruthenium (Ru) is formed on the substrate, and in this example on the optional barrier layer 106.
  • the thickness for the group VIII metal layer 108 often depends on the device structure to be fabricated.
  • the thickness of the group VIII metal layer 108, such as ruthenium (Ru) is less than about 1 ,000 A, preferably between about 5 A to about 200 A.
  • the group VIII metal layer 108 is a ruthenium layer having a thickness less than about 100 A, for example, about 50 A.
  • the apertures 120 may be filled with copper 110 to complete the copper interconnect.
  • the noble or transitional metal layer such as ruthenium layer, serves as a seed layer to which a copper is directly deposited using an ECP or other copper plating techniques.
  • the electrochemical plating solution for ECP generally includes a copper source, an acid source, a chlorine ion source, and at least one plating solution additive, i.e., levelers, suppressors, accelerators, antifoaming agents, etc.
  • the plating solution may contain between about 30 g/l and about 60 g/l of Cu, between about 10 g/l to about 50 g/l of sulfuric acid, between about 20 and about 100 ppm of Cl ions, between about 5 and about 30 ppm of an additive accelerator, between about 100 and about 1000 ppm of an additive suppressor, and between about 1 and about 6 ml/I of an additive leveler.
  • the plating current may be in the range from about 2 mA/cm 2 to about 10 mA/cm 2 for filling copper into the submicron trench and/or via structures. Examples of copper plating chemistries and processes can be found in commonly assigned U.S.
  • a continuous copper film is formed on Ru when the plating current density and/or concentration of H 2 SO 4 (or acidity) are increased beyond the values used in conventional copper plating.
  • a minimum or critical current density (CCD) has been found where plating current densities equal to or above this value will form a thin continuous copper film on a Ru layer and current densities below this value will not form a thin continuous film on the Ru layer.
  • the magnitude of the CCD is strongly dependent on the acidity of the plating solution.
  • Figure 2 illustrates an example of the critical current density (CCD) versus sulfuric acid (H 2 SO ) concentration.
  • the CCD as shown in Figure 2, is defined as the minimum current density required to form a 1000 A continuous copper film on a Ru surface.
  • Cu adatoms are copper atoms that land on the substrate surface during plating and before they are incorporated into the Cu film. Since the plating current density depends on the electrochemical over-potential for a given bath, the copper deposit structure/morphology is therefore affected by the plating current density.
  • a substrate that has a 5000 A thick continuous copper film can be formed on a Ru (100 A thick and deposited by PVD) film, using a plating solution that contained 60 g/l of H 2 SO and a plating current density of about 10 mA/cm 2 (slightly lower than the CCD of 15 mA/cm 2 ).
  • a plating solution that contained 60 g/l of H 2 SO and a plating current density of about 10 mA/cm 2 (slightly lower than the CCD of 15 mA/cm 2 ).
  • the plating current was increased to 30 mA/cm 2 , the density of the crystallites was found to increase and the sizes of the crystallites was found to decrease near the center of the substrate.
  • no continuous copper film was formed on Ru surface since the plating current was below the CCD.
  • the Ru film was 100 A thick and was deposited by PVD.
  • the concentration of sulfuric acid needs to be increased. When the sulfuric acid concentration is raised to 160 g/l and the plating current is at 5 mA/cm 2 , which is equal to the CCD at the particular acidic concentration, a continuous 1000 A copper film was formed across a 100 A Ru film on a substrate.
  • RuO 2 ruthenium oxide
  • RuO 2 has a metal-like conductivity, and copper also plates and adheres strongly to ruthenium oxide.
  • the high CCDs observed on as-deposited Ru surface could be a result of Ru surface oxidation and/or the existence of organic surface contaminants.
  • the "pure" Ru surface is suspected to be more active for Cu nucleation. Removing the surface oxide layer or organic surface contaminants by a pre-treatment process before copper plating could greatly reduce the plating current and the plating bath acidity required to form a continuous copper layer without copper/Ru interface voids.
  • the pre-treatment process could be exposing the substrate surface to a reducing agent.
  • Figure 3A shows the pre-treatment process flow.
  • the substrate with a group VIII metal, such as Ru, on top is pre-treated by a process, such as annealing in a reducing gas (e.g. hydrogen gas), to clean the surface of metal oxide or organic contaminants.
  • a reducing gas e.g. hydrogen gas
  • a copper film is directly plated on the pre- treated substrate.
  • One possible oxide reduction reaction is shown in equation (1) below. RuO 2 + 2 H 2 > Ru + 2 H 2 O
  • a substrate with 100 A PVD Ru film is pre-treated by annealing just prior to Cu plating.
  • the annealing process is performed in the presence of a hydrogen-containing gas, such as a forming gas, which contains 4% H 2 and 96% N 2 , at a temperature between about room temperature to about 400°C, preferably between about 100°C to about 400°C, a gas flow rate between about 1 seem to about 20 slm, and under about 5 mTorr to about 1500 Torr for about 2 seconds to about 5 hours.
  • the annealing time is preferably within 1 hour for manufacturing efficiency.
  • the purpose of the substrate annealing is either to reduce the RuO 2 surface back to Ru and/or to desorb the organic surface contaminants.
  • the hydrogen-containing gas is mixed with non-reactive gases, such as N 2 or inert gases (e.g. Ar, He, etc.).
  • non-reactive gases such as N 2 or inert gases (e.g. Ar, He, etc.).
  • annealing with a non-reactive gas to Ru such as N 2 or inert gas (e.g., Ar)
  • the annealing process can be performed in a single-wafer rapid thermal annealing chamber, available from Applied Materials in Santa Clara, California, or in a batch furnace.
  • Figure 3B illustrates an example of where the magnitude of the CCD was reduced after the as-deposited Ru substrate was annealed in the forming gas at 270°C for 30 seconds in an anneal chamber described in Figure 5 below.
  • Curve 311 shows the CCD for copper plating on an as-deposited Ru substrate surface.
  • Curve 312 shows the much reduced CCD for copper plating on a forming gas annealed Ru substrate surface.
  • the CCD for a solution containing 10 g/l of H 2 SO lowered the CCD from 40 mA/cm 2 to 8 mA/cm 2 and a plating solution containing 100 g/l of H 2 SO 4 lowered the CCD from 10 mA/cm 2 to 3 mA/cm 2 .
  • Both curves 311 and 312 show that CCD decreases with the increase of acid concentration.
  • the acid used in the plating solution could be other types of acids, such as sulfonic acid (including alkane sulfonic acids). If another type of acid is used, instead of sulfuric acid, the equivalent acid concentration range should be used.
  • the direct copper plating process can be operated at similar current densities as the conventional copper plating process.
  • the Ru substrate surface tends to become more hydrophilic, as is expected for a clean and pure Ru surface.
  • Cu plating onto the forming-gas annealed Ru films must be performed within 4 hours and preferably within 2 hours, following the forming-gas anneal, in order to maintain the large reduction in CCD. If the substrate is exposed to the oxygen or other contaminants for too long, the CCD will gradually go back to the pre-anneal state due to reformation of RuO x or re-deposition of organic surface contaminants from ambient atmosphere.
  • the copper/Ru interface shows good integrity without voids even when PCD/CCD equals to 1 when Cu is deposited on forming-gas annealed Ru surface.
  • PCD/CCD 1 when Cu is deposited on forming-gas annealed Ru surface.
  • a clean Ru surface allows better copper nucleation and deposition and therefore the interface integrity is improved.
  • Another benefit of pre-treating the group VIII metal surface with hydrogen-containing gas anneal is the improved adhesion between copper and the group VIII metal.
  • Figure 4 shows the SEM of excellent gapfill of plated copper on an annealed Ru surface in 0.14 ⁇ m x 0.8 ⁇ m trenches.
  • the as-deposited Ru is an 80 A ALD Ru.
  • the pre-treatment is a forming gas anneal at 300°C for 3 minutes.
  • the copper plating current is 10 mA/cm 2 for the first 100 A and 5 mA/cm 2 for the remaining 1900 A,
  • the annealing process can be performed in an integrated annealing chamber, such as annealing chamber 535 in Figure 5, or in a separate annealing system.
  • the annealing process can be performed in either a single- wafer chamber or a batch furnace.
  • the surface pre-treatment of the group VIII metal prior to direct copper plating can also be accomplished by other methods.
  • One example of another pre-treatment method is a cathodic treatment in a copper-ion-free acid solution.
  • the surface RuO ⁇ film can be cathodically reduced and the weakly-bound organic surface contaminants can be expelled from the surface by the cathodic polarization.
  • One possible reduction reaction is shown in equation (2) below.
  • the cathodic treatment can be performed in an integrated cell similar to the copper plating cell, as described below in association with Figure 6, or in a treatment cell separated from the copper plating system.
  • the cathodic treatment cell requires an anode, a cathode and a copper-ion-free acid bath.
  • the acidic concentration range should be in the range between about 10 g/l to about 100 g/l, and preferably in the range between about 10 g/l to about 50 g/l.
  • a preferred acid is H 2 SO , but other types of acidic solutions, such as organic sulfonic acid solutions (e.g. methylsulfonic acid), can also be used.
  • the acidic bath needs to be free of copper to prevent copper deposition, which would be poorly nucleated copper islands, on Ru during the cathodic treatment.
  • the cathodic treatment can be realized through potential control or current control.
  • a reference electrode is needed to monitor the wafer potential, in addition to the working electrodes, which are the thin as-deposited Ru film on the wafer surface, and an anode.
  • the preferred reference electrode is a thin copper wire placed close to the substrate surface.
  • the potential control can be realized through a potentiostat.
  • the controlled Ru electrode potential, with respect to the copper reference electrode is in the range of about 0 volt to about -0.5 volt.
  • H 2 evolution could occur on the Ru film surface.
  • a cathodic current will be passed between the substrate with as-deposited Ru and an anode.
  • the current density should be in the range of about 0.05 mA/cm 2 to about 1 mA/cm 2 .
  • the treatment time should be in the range of about 2 seconds to about 30 minutes. However, for throughput concern, the treatment is preferably kept below 5 minutes.
  • the experimental results and discussion related to Ru is merely used as examples.
  • the inventive concept can be applied to other group VIII metals, such as rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum (Pt).
  • Copper plating can be performed within a cell on the Electra Cu ECP® system or the SlimCell Copper Plating system, both of which are available from Applied Materials, Inc.
  • FIG. 5 illustrates a top plan view of a SlimCell Copper Plating system 500.
  • ECP system 500 includes a factory interface (Fl) 530, which is also generally termed a substrate loading station.
  • Factory interface 530 includes a plurality of substrate loading stations configured to interface with substrate containing cassettes 534.
  • a robot 532 is positioned in factory interface 530 and is configured to access substrates contained in the cassettes 534. Further, robot 532 also extends into a link tunnel 515 that connects factory interface 530 to processing mainframe or platform 513.
  • robot 532 allows the robot to access substrate cassettes 534 to retrieve substrates therefrom and then deliver the substrates to one of the processing cells 514, 516 positioned on the mainframe 513, or alternatively, to the annealing station 535.
  • robot 532 may be used to retrieve substrates from the processing cells 514, 516 or the annealing chamber 535 after a substrate processing sequence is complete. In this situation robot 532 may deliver the substrate back to one of the cassettes 534 for removal from system 500.
  • the anneal station 535 which will be further discussed herein, generally includes a two position annealing chamber, wherein a cooling plate/position 536 and a heating plate/position 537 are positioned adjacently with a substrate transfer robot 540 positioned proximate thereto, e.g., between the two stations.
  • the robot 540 is generally configured to move substrates between the respective heating plate 537 and cooling plate 536.
  • the anneal chamber 535 is illustrated as being positioned such that it is accessed from the link tunnel 515, embodiments of the invention are not limited to any particular configuration or placement.
  • the anneal station 535 may be positioned in direct communication with the mainframe 513, i.e., accessed by mainframe robot 520.
  • the anneal station 535 may be positioned in direct communication with the link tunnel 515, which allows for access to mainframe 513, and as such, the anneal chamber 535 is illustrated as being in communication with the mainframe 513. Details of a suitable annealing chamber are described in commonly assigned U.S. patent application number 60/463,860, titled “Two Position Anneal Chamber", filed on April 18, 2003. [0047]
  • the annealing process is performed in an integrated annealing chamber, as shown as annealing chamber 535 in Figure 5.
  • the annealing process is performed in a separate annealing system.
  • the annealing process is performed in a single-wafer chamber or a batch furnace.
  • ECP system 500 also includes a processing mainframe 513 having a substrate transfer robot 520 centrally positioned thereon.
  • Robot 520 generally includes one or more arms/blades 522, 524 configured to support and transfer substrates thereon. Additionally, the robot 520 and the accompanying blades 522, 524 are generally configured to extend, rotate, and vertically move so that the robot 520 may insert and remove substrates to and from a plurality of processing locations 502, 504, 506, 508, 510, 512, 514, 516 positioned on the mainframe 513.
  • factory interface robot 532 also includes the ability to rotate, extend, and vertically move its substrate support blade, while also allowing for linear travel along the robot track that extends from the factory interface 530 to the mainframe 513.
  • process locations 502, 504, 506, 508, 510, 512, 514, 516 may be any number of processing cells utilized in an electrochemical plating platform. More particularly, the process locations may be configured as electrochemical plating cells, rinsing cells, bevel clean cells, spin rinse dry cells, substrate surface cleaning cells (which collectively includes cleaning, rinsing, and etching cells), electroless plating cells, metrology inspection stations, and/or other processing cells that may be beneficially used in conjunction with a plating platform.
  • Each of the respective processing cells and robots are generally in communication with a process controller 511 , which may be a microprocessor-based control system configured to receive inputs from both a user and/or various sensors positioned on the system 500 and appropriately control the operation of system 500 in accordance with the inputs.
  • a process controller 511 may be a microprocessor-based control system configured to receive inputs from both a user and/or various sensors positioned on the system 500 and appropriately control the operation of system 500 in accordance with the inputs.
  • FIG. 6 illustrates a partial perspective and sectional view of an exemplary plating cell 600 that may be implemented in processing locations 502, 504, 506, 508, 510, 512, 514, 516 of Figure 5.
  • the electrochemical plating cell 600 generally includes an outer basin 601 and an inner basin 602 positioned within outer basin 601.
  • Inner basin 602 is generally configured to contain a plating solution that is used to plate a metal, e.g., copper, onto a substrate during an electrochemical plating process.
  • the plating solution is generally continuously supplied to inner basin 602 (at about 1 gallon per minute for a 10 liter plating cell, for example), and therefore, the plating solution continually overflows the uppermost point (generally termed a "weir") of inner basin 602 and is collected by outer basin 601 and drained therefrom for chemical management and recirculation.
  • Plating cell 600 is generally positioned at a tilt angle, i.e., the frame portion 603 of plating cell 600 is generally elevated on one side such that the components of plating cell 600 are tilted between about 3° and about 30°, or generally between about 4° and about 10° for optimal results.
  • the frame member 603 of plating cell 600 supports an annular base member on an upper portion thereof.
  • Base member 604 includes an annular or disk shaped recess formed into a central portion thereof, the annular recess being configured to receive a disk shaped anode member 605.
  • Base member 604 further includes a plurality of fluid inlets/drains 609 extending from a lower surface thereof. Each of the fluid inlets/drains 609 are generally configured to individually supply or drain a fluid to or from either the anode compartment or the cathode compartment of plating cell 600.
  • Anode member 605 generally includes a plurality of slots 607 formed therethrough, wherein the slots 607 are generally positioned in parallel orientation with each other across the surface of the anode 605. The parallel orientation allows for dense fluids generated at the anode surface to flow downwardly across the anode surface and into one of the slots 607.
  • Plating cell 600 further includes a membrane support assembly 606.
  • Membrane support assembly 606 is generally secured at an outer periphery thereof to base member 604, and includes an interior region configured to allow fluids to pass therethrough.
  • a membrane 608 is stretched across the support 606 and operates to fluidly separate a catholyte chamber and anolyte chamber portions of the plating cell.
  • the membrane support assembly may include an o-ring type seal positioned near a perimeter of the membrane, wherein the seal is configured to prevent fluids from traveling from one side of the membrane secured on the membrane support 606 to the other side of the membrane.
  • a diffusion plate 610 which is generally a porous ceramic disk member and is configured to generate a substantially laminar flow or even flow of fluid in the direction of the substrate being plated, is positioned in the cell between membrane 608 and the substrate being plated.
  • the exemplary plating cell is further illustrated in commonly assigned United States Patent Application Serial No. 10/268,284, which was filed on October 9, 2002 under the title "Electrochemical Processing Cell", claiming priority to United States Provisional Application Serial No.

Abstract

La présente invention concerne un procédé de traitement de surface à couche barrière pour permettre le cuivrage direct sans couche de germination du cuivre. Un mode de réalisation décrit dans cette invention concerne un procédé permettant de déposer du cuivre sur un substrat présentant une couche de métal du groupe VIII; ce procédé consiste à prétraiter la surface du substrat par élimination d'une couche superficielle d'oxyde métallique du groupe VIII et/ou des contaminants de surface, puis à déposer le cuivre sur la surface de métal du groupe VIII prétraitée. Le prétraitement du substrat peut être réalisé par recuit du substrat dans un environnement avec un environnement gazeux contenant de l'azote et/ou un ou plusieurs gaz non réactifs avec le métal du groupe VIII, au moyen d'un traitement cathodique dans un bain contenant de l'acide, ou par immersion du substrat dans un bain contenant de l'acide.
PCT/US2005/019902 2004-06-10 2005-06-07 Procede de traitement de surface a couche barriere pour permettre le cuivrage direct sur un metal barriere WO2005123988A1 (fr)

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EP05758773A EP1778896A1 (fr) 2004-06-10 2005-06-07 Procede de traitement de surface a couche barriere pour permettre le cuivrage direct sur un metal barriere
JP2007527630A JP2008502806A (ja) 2004-06-10 2005-06-07 バリア金属上への直接の銅メッキを可能にするバリア層表面処理方法

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US57912904P 2004-06-10 2004-06-10
US60/579,129 2004-06-10
US11/007,857 US20050274621A1 (en) 2004-06-10 2004-12-09 Method of barrier layer surface treatment to enable direct copper plating on barrier metal
US11/007,857 2004-12-09

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TWI292925B (en) 2008-01-21
JP2008502806A (ja) 2008-01-31

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