TWI292925B - Method of barrier layer surface treatment to enable direct copper plating on barrier metal - Google Patents

Method of barrier layer surface treatment to enable direct copper plating on barrier metal Download PDF

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TWI292925B
TWI292925B TW094118707A TW94118707A TWI292925B TW I292925 B TWI292925 B TW I292925B TW 094118707 A TW094118707 A TW 094118707A TW 94118707 A TW94118707 A TW 94118707A TW I292925 B TWI292925 B TW I292925B
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copper
substrate
plating
layer
tempering
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TW094118707A
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Chinese (zh)
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TW200603269A (en
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Zhi-Wen Sun
Renren He
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Applied Materials Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/34—Pretreatment of metallic surfaces to be electroplated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Description

1292925 九、發明說明： 【發明所屬之技術領域】 本發明係關於可直接鍍銅於阻隔金屬上之阻隔層表面 處理方法。 5 【先前技術】 在超大型積體電路（VLSI)與極大型積體電路（ULSI)之 φ 下世代半導體元件中，深次微米多層金屬化為關鍵技術之 一。核心技術中之多層内連線需要填充接觸孔（c〇ntacts)、 10 通孔（vias)、線、以及其他具深寬比的特徵孔。持續努力於 個別基材與晶粒的電路密度增加與品質提升之外，可靠的 形成這些特徵孔亦是達成VLSI與ULSI的關鍵點。 隨著電路密度的增加，接觸孔、孔洞、線、其他特徵 孔以及介於其間之介電材料的寬度會縮小至小於65nm，然 15而介電材料之厚度維持不變，使得多數半導體特徵孔的深 寬比（高度除以寬度）實質增加。許多傳統的沈積製程無法一 貫地填充於深寬比超過6:1的半導體結構中，特別是當深寬 比超過10:1。如此，針對形成具有深寬比大於6:1的無空隙 奈米特徵結構仍有許多進步的空間。 20 、此外當特徵孔寬度減少，元件電流一般會維持不變或 增加，而造成此些特徵孔的電流密度增加。在半導體元件 形成孔洞與線一般所使用的金屬為元素鋁與鋁合金，因紹 2有低電阻率、相對於大多介電層具良好的黏著性、以及 谷易圖樣化，且高純度之鋁易於獲取。然而鋁相對於其他 5 1292925 •導電金屬之電阻率過高，如銅。銘又易於電子遷移，導致 — 導電體中產生孔隙。 銅與銅合金具有相較於鋁較低的電阻率，且相較於鋁 較南的電子遷移阻力。在高階整合與高速元件下，此特性 5在供應高電流密度時非常重要。銅亦具有好的熱導性。因 此銅成為填充深次微米中半導體基材上高深寬比内連線特 徵孔的選擇。 傳統上，沈積技術如化學氣相沈積（CVD)與物理氣相 ®沈積（PVD)用於填充内連線之特徵孔。然而隨著内連線尺寸 10變小與深寬比增加，使用傳統金屬化技術（例如CVD與PVD) 之無孔隙的内連線特徵孔填充變的非常困難。因此在積體 電路製造過程中，電鍍技術如電化學電鍍（ECp)成為可實行 用於填充深次微米尺寸高深寬比内連線特徵孔的製程。 大多ECP製程需要兩道步驟，其中種晶層首先形成於 15 基材之特徵孔表面（此步驟可在一分離系統中實行），接 著特徵孔之表面暴露於電解質溶液中，同時一電偏壓施加 馨於基材表面（視為陰極）與一位於電解質中的陽極之間。 一般電鍍之實施包括利用物理氣相沈積（physical vapor deposition，PVD)、化學氣相沈積（chemicai vapor 20 deposition，CVD)或原子層沈積（atomic layer deposition)形 成銅種晶層至一擴散阻隔層（例如鈕或氮化鈕）上。然而 隨著特徵孔尺寸逐漸變小，利用PVD技術階梯覆蓋種晶層 變的非常困難，此時非連續島狀之銅結塊形成於接近特徵 孔底部的側壁上。當使用CVD或ALD沈積製程以取代pvd 6 1292925 >< " 來沈積連續側壁層遍佈高深寬比特徵孔的深處時，較厚的 鋼層會形成於外圍寬敞區域。此較厚的銅層會造成特徵孔 的入口部在側壁完成覆蓋前先被關閉。當沈積之厚度控制 到不使入口關閉時，ALD與CVD技術也會傾向於產生非連 5 續之種晶層。此種非連續的種晶層會造成電鍍於種晶層上 之電鍍層缺陷。此外，銅在大氣下傾向於快速氧化，而氧 化銅會快速的溶解於電鍍液中。為防止銅在特徵孔中完全 溶解’銅種晶層常常會製作的相對厚（高至8〇〇A)，其會 Φ 抑制電鍍製程填充特徵孔。因此一般期望銅電鍍製程允許 10 直接電鍍銅於適當的阻隔層上而沒有銅種晶層。 因此銅電鍍製程中填充特徵孔而不需要銅種晶層是有 其需要性。 【發明内容】 15 本發明之實施例主要提供阻隔層表面處理之方法，以 直接鍍銅而不需銅種晶層。在一實施例中，直接鍍鋼於表 •面具有VIII族金屬之基材上之方法，包括前處理基材表面以 去除VIII族金屬表面氧化層與/或有機表面污染物，以降低 在電鍵日守的E品界電流也、度，以及在一酸性電锻槽中電_二 20 連續且無孔隙銅層於已前處理過之基材表面上，此時之電 流密度大於或等於臨界電流密度。 【實施方式】 7 1292925 • 小於45nm技術下，利用如CVD、ALD、或PVD所沉積 之釕（Ru)薄膜可為介於内部金屬介電（IMD)與銅内連線之 無種晶擴散阻隔之最具潛力的選擇。釕為VIII族金屬，具有 低電阻率（電阻率約7μΩ<πι)與高熱穩定性（高熔點〜2300 5 °C )。釕甚至在具有氧與水的環境溫度下相對地穩定。釕之 熱與電導性為钽（Ta)的兩倍。在900°C下釕不與銅形成合 金，並且與銅具良好的附著性。因此半導體工業對於以釕 作為銅阻隔層產生高度興趣。在無種晶層下，釕的低電阻 # 率在填充銅於釕覆蓋之特徵孔時具有相當的優勢。 1〇 圖1A〜1C說明不同步驟下之銅金屬内連線製造流程的 基材剖視圖，並且以本發明之VIII族金屬作為阻隔層。例如 在圖1A中，形成具有金屬接觸孔104與介電層102的基材 100。此基材100可包括半導體材料，如矽、鍺、或砷化鎵。 介電層102可包括絕緣材料如二氧化矽、氮化矽、氮氧化 15 矽、或碳摻雜二氧化矽（SiOxCy，例如註冊商標為黑鑽石 低介電常數之介電材料，其由美國加州Santa Clara之應用材 φ 料公司所供應）。金屬接觸孔104可包括銅或其他材料。孔 洞120係於介電層102中定義，並提供金屬接觸孔104上之開 口。介電層102所定義之孔洞120可利用傳統之微影蝕刻技 2〇 術達成。孔洞120的寬度可等於或小於900A。介電層102的 厚度可介於1000A至10000A之間。 在一實施例中，阻隔層106可形成於孔洞120中，並由 介電層102所定義。此選擇性的阻隔層106可包含一或多之 而才火含金屬層，用以作為銅之阻隔材料，例如鈦、氮化鈦、 8 1292925 ▲ 氮化石夕鈦（titanium silicon nitride)、钽、氣化钽、氮化石夕组 (tantalum silicon nitride)、鹤、氮化鶴或其他材料。選擇性 阻隔層106可利用適當之沈積製程形成，例如原子層沈積 (ALD)、化學氣才目沈積（CVD)、或物理氣才目沈積（PVD)。例 5 如氮化鈦在CVD製程或ALD製程中，利用四氣化鈦與氨來 形成。在一實施例中，氮化鈕和/或鈕沈積為阻隔層係利用 ALD製程，其製程描述於美國專利公開號2003/0121608,公 開曰2003年7月3曰，其亦一併做為參考。選擇性之阻隔層 • 106—般的厚度介於約5A至150A之間，較佳為小於100A。 1〇 在一實施例中VIII族金屬薄層例如為釕（Ru)、铑（Rh)、 鈀（Pd)、餓（Os)、銥（Ir)、與鉑（Pt)可作為銅孔洞或線的底層 (或阻隔層）。VIII族金屬材料提供抗腐蝕與抗氧化，而使得 利用電化學電鍍製程沉積的銅層隨後形成於其表面上。VIII 族金屬作為銅阻隔層。VIII族金屬亦可沈積在傳統之阻隔層 15 (例如為钽Ta與/或氮化鈕TaN)上，以作為傳統阻隔層與銅 之間的黏著層。VIII族金屬一般使用化學氣相沈積（CVD)、 _ 原子層沈積（ALD)、或物理氣相沈積（PVD)來沈積。 請參考圖IB，VIII族阻隔金屬層108 (例如釕）形成於 基材上，且在此例中位於選擇性阻隔層106上。VIII族金屬 2〇 層108之厚度通常依據欲製造之元件結構而定。一般VIII族 金屬層108 (例如釕）之厚度為小於1000A，較佳為介於5A 至200A之間。在一實施例中，VIII族金屬層1〇8為具有厚度 小於約100A，例如50 A，之釕層。 9 1292925 • 其後請參考圖1C，孔洞120可被銅110填充，以完成銅 • 金屬内連線。在一實施例中，貴金屬或過渡金屬層（例如釕 層）可視為種晶層，而銅利用電化學電鍍或其他銅電鍍製程 直接沈積。ECP銅電鍍的電化學電鍍溶液一般包括銅源、酸 5 源、氣離子源、以及至少一電鍍溶液添加劑，亦即平整劑、 抑制劑、促進劑、抗泡劑等。例如電鍍溶液可包含約30至 60g/L的銅、約10至50g/L的硫酸、約20至lOOppm的氯離子、 約5至30ppm的添加促進劑、約1 〇〇至1 〇〇〇ppm的添加抑制 劑、約1至6ml/L的添加平整劑。電艘電流可在2mA/cm2至 10 10mA/cm2之間，用以填充銅至次微米溝槽與/或通孔（vias) 結構中。銅電鍍化學劑與製程之例子可見於美國專利申請 號10/616,097，名稱為「直接銅電鍍於阻隔金屬上的多步驟 電沈積製程（Multiple-Step Electrodeposition Process for Direct Copper Plating on Barrier Metals)」，申請於2003年7 15 月8日，以及美國專利申請號60/510，190，名稱為「於次微 米特徵中提供沈積銅之初始均勻的電化學沈積的方法與化 •學劑(Methods and Chemistry for Providing Initial Conformal Electrochemical Deposition of Copper in Sub-micro Features)」，申請於2003年10月10日。電化學電鍍（ECP)系 20 統與電鍍室的例子將於圖5〜6中描述。 傳統銅電鍍製程在使用10-50g/l之硫酸與電鍍電流密 度為2-10mA/cm2時，發現並不會形成連續之銅薄膜（S 1000A)沈積於釕層上。形成於釕層上的連續銅膜必須在電 鍍電流密度和/或硫酸濃度增加至傳統銅電鍍之值以上。一 1292925 . 最小或臨界電流密度（CCD)已被發現，當電鍍電流密度等於 或大於此值時’將會形成一連續之銅薄膜於釕層上，當電 鍍電流密度小於此值時，將不會形成一連續之銅薄膜於釕 層上。CCD的大小與電鑛溶液的酸性有極大的相關。 5 圖2說明臨界電流密度（CCD)與硫酸濃度的關係。如圖2 顯示的CCD定義為需要形成丨〇〇〇人連續銅薄膜於釕表面的 隶小電流岔度。在CCD以下的值，並無視覺上光澤之連續 銅膜沈積在基材的中央區域。當CCD之大小與電鍍室之酸 •性具有極大的相關，然而CCD與釕沈積的方法（例如ald、 10 CVD、PVD)並無相關。 一般熟知，電沈積的成核與結晶成長的動力學與在成 核/成長位置上的區域電化學過電位（〇Ver_P〇tential)密切相 關。過電位定義為實際電位與零電流（開路）電位的差值。高 過電位傾向於新的結晶成核，係藉由降低臨界晶核大小與 15 增加晶核密度達成；而低過電位傾向於成長於存在的結晶 上。此外，含硫有機添加劑（例如促進劑）存在於電鑛溶液 _中’可增強銅吸附原子（Cu adatoms)的表面擴散，在消耗成 核下促進結晶成長。銅吸附原子是指在電鍍時或在它包含 在銅層之别者陸於基材表面的銅原子。因為電鍍電流密度 20 由給定之電鍍槽的電化學過電位所決定，鋼沈積的結構與 型態由電鍍電流密度所影響。 在具有1000A (由接近基材邊緣量測）銅層電鍍於1〇〇a 之釕層上、含有10g/l硫酸之電鍍溶液中、與電流為3mA/cm2 下，掃瞄式電子顯微鏡（SEM)接近基材中央之圖示發現大的 η 1292925 . 結晶與較差的膜沈積於基材中央位置。此時ΙΟΟΑ厚的釕層 ♦ 由PVD沈積。依據圖2所顯示的結果，在硫酸濃度為10g/l 下，CCD約為40mA/cm2。3mA/cm2的電流密度遠低於40 mA/cm2 (CCD)，故如預料地產生一非連續層。一般相信在 5 此電鍍條件下，僅少數的結晶夠穩定而足以視為更進一步 結晶成長的成核中心，因此電鑛電流產生的能量基本上用 以成長這些結晶，而幫助銅吸附原子快速表面擴散。因此 SEM顯示出在基材中央區域中大的結晶與銅島狀沈積。在 % 此條件下要形成連續銅層橫越整個基材表面，沈積層就必 10 須非常厚，且此沈積層可能會產生孔隙而造成銅内連線的 不適用。當使用含有60g/l硫酸之電鍍溶液與電鍍電流密度 為10mA/cm2(稍微低於15mA/cm2的CCD)下，在基材上可形 成5000人厚的連續銅層於釕層（100入厚由？¥0沈積）上。然而 會有大的孔隙在銅/釕介面上。 15 當電鍵電流增加至30mA/cm2，結晶密度會增加，結晶 尺寸在基材中央附近會變小。然而非連續銅層仍形成於釕 φ 表面上，因為電鍍電流低於CCD。如前面所述釕層為100人 厚並由PVD沈積。 在增加電鍍電流時仍會有一些缺點。一般在高電鍍電 20 流密度會傾向於較差的填洞能力。一般在電鍍電流密度小 於10mA/cm2，可促進底部至上部的填洞能力。為了降低電 鍍電流密度使其介於利於底部至上部的填洞能力範圍，硫 酸的濃度需要增加。當硫酸濃度增加至160g/l且電鍍電流為 5mA/cm2(其等同於在特定酸性濃度下的CCD)時，一連續 12 12929251292925 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a surface treatment method for a barrier layer which can be directly plated with copper on a barrier metal. 5 [Prior Art] Deep submicron multilayer metallization is one of the key technologies in the next generation semiconductor devices of ultra large integrated circuits (VLSI) and very large integrated circuits (ULSI). Multilayer interconnects in the core technology need to fill contact holes (c〇ntacts), 10 vias, wires, and other feature holes with aspect ratios. In addition to continuous efforts to increase the circuit density and quality of individual substrates and dies, the reliable formation of these feature holes is also a key point in achieving VLSI and ULSI. As the density of the circuit increases, the contact holes, holes, lines, other feature holes, and the width of the dielectric material interposed therebetween are reduced to less than 65 nm, while the thickness of the dielectric material remains unchanged, so that most of the semiconductor feature holes The aspect ratio (height divided by the width) actually increases. Many conventional deposition processes cannot be filled in a semiconductor structure with an aspect ratio greater than 6:1, especially when the aspect ratio exceeds 10:1. Thus, there is still much room for improvement in forming a void-free nanofeature with an aspect ratio greater than 6:1. 20. In addition, as the feature hole width decreases, the component current generally remains constant or increases, causing the current density of these feature holes to increase. The metal used in the formation of holes and wires in semiconductor elements is elemental aluminum and aluminum alloy. Insole 2 has low electrical resistivity, good adhesion to most dielectric layers, and easy-to-grain patterning, and high-purity aluminum. Easy to access. However, aluminum has a higher resistivity than other 5 1292925 • conductive metals, such as copper. Ming is also easy to migrate electrons, resulting in - the formation of pores in the electrical conductor. Copper and copper alloys have lower resistivities than aluminum and have electron mobility resistance souther than aluminum. This feature is very important when supplying high current densities with high-level integration and high-speed components. Copper also has good thermal conductivity. Copper therefore becomes the choice for filling high aspect ratio interconnects on deep semiconductor substrates in deep submicron. Traditionally, deposition techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD) have been used to fill the characteristic holes of interconnects. However, as the interconnect size 10 becomes smaller and the aspect ratio increases, it is very difficult to fill the void-free interconnect feature holes using conventional metallization techniques such as CVD and PVD. Therefore, in the fabrication of integrated circuits, electroplating techniques such as electrochemical plating (ECp) have become a process that can be used to fill deep submicron size high aspect ratio interconnect features. Most ECP processes require two steps, in which the seed layer is first formed on the surface of the characteristic hole of the 15 substrate (this step can be carried out in a separate system), and then the surface of the feature hole is exposed to the electrolyte solution while an electrical bias is applied. A sinus is applied between the surface of the substrate (considered as a cathode) and an anode located in the electrolyte. The general plating implementation includes forming a copper seed layer to a diffusion barrier layer by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition ( For example, button or nitride button). However, as the feature hole size becomes smaller, it is very difficult to cover the seed layer layer by the PVD technique step, in which case a discontinuous island-like copper agglomerate is formed on the side wall near the bottom of the feature hole. When a CVD or ALD deposition process is used instead of pvd 6 1292925 ><"" to deposit a continuous sidewall layer deep in the high aspect ratio feature hole, a thicker steel layer is formed in a peripherally spacious region. This thicker copper layer causes the entrance portion of the feature hole to be closed before the side wall finishes covering. ALD and CVD techniques also tend to produce non-continuous seed layers when the thickness of the deposition is controlled so that the inlet is not closed. Such a discontinuous seed layer can cause plating defects on the seed layer. In addition, copper tends to oxidize rapidly under the atmosphere, and copper oxide dissolves rapidly in the plating solution. To prevent copper from completely dissolving in the feature holes, the copper seed layer is often made relatively thick (up to 8 〇〇A), which Φ suppresses the plating process to fill the feature holes. It is therefore generally desirable that the copper plating process allows 10 direct plating of copper onto a suitable barrier layer without a copper seed layer. Therefore, it is necessary to fill the feature holes in the copper plating process without requiring a copper seed layer. SUMMARY OF THE INVENTION 15 Embodiments of the present invention primarily provide a method of surface treatment of a barrier layer for direct copper plating without the need for a copper seed layer. In one embodiment, a method of directly plating steel onto a substrate having a Group VIII metal surface comprises pretreating a surface of the substrate to remove a surface oxide layer of the Group VIII metal and/or organic surface contaminants to reduce the electrical bond The current and current of the E-consistence of the Essence, and the continuous and non-porous copper layer on the surface of the pretreated substrate in an acid electric forging tank, the current density is greater than or equal to the critical current. density. [Embodiment] 7 1292925 • 钌 (Ru) film deposited by using CVD, ALD, or PVD under less than 45nm technology can be a seedless diffusion barrier between internal metal dielectric (IMD) and copper interconnects. The most potential choice.钌 is a Group VIII metal having a low electrical resistivity (resistivity of about 7 μΩ < πι) and high thermal stability (high melting point ~ 2300 5 ° C). Tantalum is relatively stable even at ambient temperatures with oxygen and water. The heat and conductivity of 钌 are twice that of tantalum (Ta). At 900 ° C, the alloy does not form an alloy with copper and has good adhesion to copper. The semiconductor industry therefore has a high interest in using germanium as a copper barrier. In the absence of a seed layer, the low resistance of the crucible has a considerable advantage in filling the characteristic holes covered by copper in the crucible. 1A to 1C are cross-sectional views showing a substrate of a copper metal interconnection manufacturing process in different steps, and using a Group VIII metal of the present invention as a barrier layer. For example, in Figure 1A, a substrate 100 having metal contact holes 104 and a dielectric layer 102 is formed. This substrate 100 can comprise a semiconductor material such as germanium, germanium, or gallium arsenide. Dielectric layer 102 may comprise an insulating material such as hafnium oxide, tantalum nitride, hafnium oxide, or carbon doped hafnium oxide (SiOxCy, such as a dielectric material having a low dielectric constant of black diamond, registered by the United States) Applied by φ Material Company, Santa Clara, California). Metal contact holes 104 may comprise copper or other materials. Hole 120 is defined in dielectric layer 102 and provides an opening in metal contact hole 104. The holes 120 defined by the dielectric layer 102 can be achieved using conventional lithography techniques. The width of the hole 120 may be equal to or less than 900A. Dielectric layer 102 may have a thickness between 1000A and 10000A. In an embodiment, a barrier layer 106 can be formed in the via 120 and defined by the dielectric layer 102. The selective barrier layer 106 may comprise one or more fire-containing metal layers for use as a barrier material for copper, such as titanium, titanium nitride, 8 1292925 ▲ titanium nitride, tantalum, Gasification enthalpy, tantalum silicon nitride, crane, nitride crane or other materials. The selective barrier layer 106 can be formed using a suitable deposition process, such as atomic layer deposition (ALD), chemical gas deposition (CVD), or physical gas deposition (PVD). Example 5 For example, titanium nitride is formed by using titanium tetrachloride and ammonia in a CVD process or an ALD process. In one embodiment, the nitride button and/or the button are deposited as a barrier layer using an ALD process, the process of which is described in U.S. Patent Publication No. 2003/0121608, published on Jul. 3, 2003, which is incorporated herein by reference. . Selective barrier layer • 106-thick thickness is between about 5A and 150A, preferably less than 100A. In one embodiment, a thin layer of a Group VIII metal such as ruthenium (Ru), rhodium (Rh), palladium (Pd), hungry (Os), iridium (Ir), and platinum (Pt) can be used as copper pores or lines. The bottom layer (or barrier layer). The Group VIII metal material provides corrosion resistance and oxidation resistance, so that a copper layer deposited by an electrochemical plating process is subsequently formed on the surface thereof. Group VIII metals act as copper barriers. The Group VIII metal may also be deposited on a conventional barrier layer 15 (e.g., tantalum Ta and/or nitride button TaN) as an adhesion layer between the conventional barrier layer and copper. Group VIII metals are typically deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Referring to Figure IB, a Group VIII barrier metal layer 108 (e.g., tantalum) is formed on the substrate and, in this example, on the selective barrier layer 106. The thickness of the Group VIII metal 2 layer 108 is generally dependent upon the structure of the component to be fabricated. Typically, the Group VIII metal layer 108 (e.g., tantalum) has a thickness of less than 1000 A, preferably between 5 A and 200 A. In one embodiment, the Group VIII metal layer 1 〇 8 is a ruthenium layer having a thickness of less than about 100 A, such as 50 A. 9 1292925 • Referring now to Figure 1C, the hole 120 can be filled with copper 110 to complete the copper/metal interconnect. In one embodiment, a precious metal or transition metal layer (e.g., a ruthenium layer) can be considered a seed layer, while copper is deposited directly using electrochemical plating or other copper plating processes. Electrochemical plating solutions for ECP copper plating generally include a copper source, an acid source, a gas ion source, and at least one plating solution additive, that is, a leveling agent, an inhibitor, an accelerator, an antifoaming agent, and the like. For example, the plating solution may comprise about 30 to 60 g/L of copper, about 10 to 50 g/L of sulfuric acid, about 20 to 100 ppm of chloride ions, about 5 to 30 ppm of an addition promoter, about 1 to 1 ppm. Adding inhibitor, about 1 to 6 ml/L of added leveling agent. The battery current can range from 2 mA/cm2 to 10 10 mA/cm2 to fill the copper to submicron trench and/or vias structure. Examples of copper electroplating chemicals and processes can be found in U.S. Patent Application Serial No. 10/616,097, entitled "Multiple-Step Electrodeposition Process for Direct Copper Plating on Barrier Metals". Application No. 60/510,190, issued on July 8, 2003, and entitled "Initial Uniform Electrochemical Deposition of Deposited Copper in Submicron Features and Methods" (Methods and Chemistry) For Providing Initial Conformal Electrochemical Deposition of Copper in Sub-micro Features), application on October 10, 2003. Examples of electrochemical plating (ECP) systems and plating chambers will be described in Figures 5-6. The conventional copper electroplating process found that a continuous copper film (S 1000A) was deposited on the ruthenium layer when 10-50 g/l of sulfuric acid was used and the plating current density was 2-10 mA/cm2. The continuous copper film formed on the tantalum layer must increase the plating current density and/or sulfuric acid concentration above the value of conventional copper plating. A 1292925. The minimum or critical current density (CCD) has been found. When the plating current density is equal to or greater than this value, a continuous copper film will be formed on the germanium layer. When the plating current density is less than this value, it will not A continuous copper film is formed on the tantalum layer. The size of the CCD is highly correlated with the acidity of the electromineral solution. 5 Figure 2 illustrates the relationship between critical current density (CCD) and sulfuric acid concentration. The CCD shown in Figure 2 is defined as the small current turbulence required to form a continuous copper film on the surface of the crucible. At values below the CCD, there is no visually glossy continuous copper film deposited in the central region of the substrate. When the size of the CCD is highly correlated with the acidity of the plating chamber, the CCD is not related to the method of germanium deposition (eg, ald, 10 CVD, PVD). It is well known that the kinetics of nucleation and crystal growth of electrodeposition are closely related to the regional electrochemical overpotential (〇Ver_P〇tential) at the nucleation/growth position. The overpotential is defined as the difference between the actual potential and the zero current (open circuit) potential. High overpotential tends to new crystal nucleation, which is achieved by lowering the critical nucleation size and increasing the nucleation density by 15; while the low overpotential tends to grow on the existing crystal. In addition, the presence of a sulfur-containing organic additive (e.g., an accelerator) in the electromineral solution _ can enhance the surface diffusion of Cu adatoms and promote crystal growth under depletion nucleation. The copper absorbing atom refers to a copper atom which is deposited on the surface of the substrate at the time of electroplating or in which it is contained in the copper layer. Since the plating current density 20 is determined by the electrochemical overpotential of a given plating bath, the structure and pattern of steel deposition are affected by the plating current density. Scanning electron microscope (SEM) with a 1000A (measured near the edge of the substrate) copper layer on a layer of 1〇〇a, a plating solution containing 10g/l sulfuric acid, and a current of 3mA/cm2 A close to the center of the substrate shows a large η 1292925 . Crystallization and poor film deposition in the center of the substrate. At this time, the thick layer of 钌 is deposited by PVD. According to the results shown in Fig. 2, the CCD is about 40 mA/cm2 at a sulfuric acid concentration of 10 g/l. The current density of 3 mA/cm2 is much lower than 40 mA/cm2 (CCD), so that a discontinuous layer is unexpectedly produced. . It is generally believed that under the 5 plating conditions, only a small amount of crystals are stable enough to be regarded as a nucleation center for further crystal growth, so the energy generated by the electric current is basically used to grow these crystals, and to help the copper adsorb the atomic fast surface. diffusion. The SEM thus shows large crystal and copper island deposits in the central region of the substrate. Under the condition that a continuous copper layer is formed across the entire surface of the substrate, the deposited layer must be very thick, and the deposited layer may have pores which may cause the copper interconnect to be unsuitable. When using a plating solution containing 60 g/l sulfuric acid and a plating current density of 10 mA/cm2 (slightly lower than 15 mA/cm2), a continuous copper layer of 5,000 thick can be formed on the substrate in the layer (100 thick) Deposited by ?¥0). However, there will be large pores on the copper/germanium interface. 15 When the key current is increased to 30 mA/cm2, the crystal density increases and the crystal size becomes smaller near the center of the substrate. However, the discontinuous copper layer is still formed on the 钌 φ surface because the plating current is lower than the CCD. The tantalum layer was 100 people thick as previously described and was deposited by PVD. There are still some disadvantages when increasing the plating current. Generally, in high plating power, 20 flow densities tend to have poor hole filling ability. Generally, the plating current density is less than 10 mA/cm2, which can promote the hole filling ability from the bottom to the upper portion. In order to reduce the current density of the plating so that it is in the range from the bottom to the upper part, the concentration of sulfuric acid needs to be increased. When the sulfuric acid concentration is increased to 160g/l and the plating current is 5mA/cm2 (which is equivalent to the CCD at a specific acid concentration), one continuous 12 1292925

. ΙΟΟΟΑ的銅層形成於橫越基材上ΙΟΟΑ的釕層。然而，SEM ^ 剖面照顯示有孔隙形成於銅/釕介面上。當電鍍電流升至10 mA/cm2(兩倍之5mA/cm2cCD)且硫酸濃度仍維持在 160gn，一連續的5000A銅層形成於100A的釕層上並且無孔 5 隙形成於銅/釕介面上。 CCD依賴於槽中酸性的原因相關於上述之區域電化學 過電位。較低酸性的電鐘液具有較高的電阻。因此需要高 的CCD來克服低酸性電鍍槽中的高電阻。 鲁 2003年3月23日至27日舉辦於路易斯安那州紐奥良舉 10 行之美國化學學會國際會議中北德州大學之Chyan等人發 表之研究顯示氧化釕（Ru〇2)具有類金屬導電性，且銅亦會 電鍍且強烈附著於氧化釕上。由剛沈積之釕表面所觀測之 高CCD可能是由於釕表面氧化和/或有機表面污染的存在。” 純”的釕表面懷疑為對銅成核更具活性。藉由在銅電鍍前之 15 前處理製程移除表面氧化層或有機表面污染，可大大減少 需要形成連續銅層之電鍍電流與電鍍槽酸性，且不會形成 φ 銅釕介面的孔隙。前處理製程可暴露基材表面至一還原 劑。圖3A顯示前處理製程之流程。在步驟301，具有VIII族 金屬（例如釕）於上的基材由一製程前處理，例如在一還原氣 20 體（例如氫氣）中回火，以清理表面的金屬氧化物或有機污 染。在步驟302中，銅層直接電鍍於被前處理過的基材。一 可能的氧化還原反應如下之方程式（1)所示。A copper layer of tantalum is formed on the tantalum layer across the substrate. However, the SEM ^ cross-section shows that pores are formed on the copper/germanium interface. When the plating current is raised to 10 mA/cm2 (twice 5 mA/cm2 cCD) and the sulfuric acid concentration is maintained at 160 gn, a continuous 5000 A copper layer is formed on the 100 A tantalum layer and a non-porous 5 gap is formed on the copper/germanium interface. . The reason why the CCD depends on the acidity in the bath is related to the electrochemical overpotential in the above region. The lower acidity of the clock fluid has a higher electrical resistance. Therefore, a high CCD is required to overcome the high resistance in the low acid plating bath. Lu, held at the American Chemical Society International Conference, held in New Orleans, Louisiana, from March 23 to 27, 2003. A study published by Chyan et al. at the University of North Texas showed that ruthenium oxide (Ru〇2) has metal-like conductivity. And copper will also be electroplated and strongly attached to the yttrium oxide. The high CCD observed from the surface of the as-deposited crucible may be due to the presence of niobium surface oxidation and/or organic surface contamination. The "pure" surface of the crucible is suspected to be more active for copper nucleation. By removing the surface oxide layer or organic surface contamination during the pre-treatment process prior to copper plating, the plating current required to form a continuous copper layer and the acidity of the plating bath can be greatly reduced, and the pores of the φ copper-germanium interface are not formed. The pretreatment process exposes the surface of the substrate to a reducing agent. Figure 3A shows the flow of the pre-processing process. In step 301, the substrate having the Group VIII metal (e.g., ruthenium) is treated by a pre-process, such as tempering in a reducing gas (e.g., hydrogen) to clean the surface of the metal oxide or organic contamination. In step 302, the copper layer is directly electroplated onto the pretreated substrate. A possible redox reaction is shown in the following equation (1).

Ru〇2+2H2-—->Ru+2H2〇 ⑴ 13 1292925 . 具有lOOA PVD釕層的基材在Cu電鍍前由回火前處 理。此回火製程在存在有含氫氣體下實施，例如為形成含 有4%氫氣與96%氮氣之氣體，溫度介於室溫至約400°C，較 佳為介於約100°C至約400°C，氣體流量介於約lsccm至約20 5 slm，且在約5mTorr至約1500Torr之下約2秒至約5小時。為 了製造效率考量，回火時間較佳為在1小時内。基材回火之 目的係為了減少Ru〇2表面以回到Ru和/或有機表面污染之 去吸附。在一實施例中，含氫氣體與非反應性氣體（例如為 0 N2或其他鈍性氣體如氬氣、氦氣等）混合。為了去吸附有機 10 表面污染，利用回火時通入非反應氣體（如N2或其他鈍性氣 體如氬氣）至釕。回火製程可實施於一單片晶圓之快速熱回 火室，可由加州Santa Clara之應用材料公司提供，或者在一 批次爐管中。 圖3B說明在剛沈積Ru之基材回火時CCD之減少狀 15 況，其中回火在一形成氣體中，溫度為270°C 30秒，於以下 圖5所示之回火室中進行。曲線311顯示電鐘銅層於剛沈積 φ Ru基材表面之CCD。曲線312顯示電鍍銅層於一形成氣體回 火之Ru基材表面之縮減的CCD。例如在含有10g/l之硫酸溶 液下，CCD由40mA/cm2降低至8 mA/cm2，在含有1〇(^八之 2〇 硫酸溶液下，CCD由10mA/cm2降低至3 mA/cm2。兩曲線311 與312均顯示CCD隨酸性濃度之增加而減少。電鍍溶液之酸 可為其他型態之酸，例如磺酸（包含烷烴磺酸）。若取代 硫酸而使用其他的酸，需使用當量酸濃度範圍。 1292925 • 隨著形成氣體之回火，直接銅電鍍製程可與傳統之銅 電鍍製程操作於相似的電流密度下。在形成氣體回火之 後’ Ru基材表面會變得更具親水性，如同於期望之乾淨且 純的Ru表面。cu電鍍於已形成氣體回火過之Ru層，其電鍍 5 時間實施需小於4小時，較佳為小於2小時，用以大量減少 CCD。若基材暴露於氧或其他污染源太久，CCD會逐漸回 到未回火前之狀態，此乃因為由大氣環境中！^〇\再形成或 有機表面污染之再沈積。 Φ 由於含氫氣體回火之大幅減少的CCD非常的重要，因 10 為使用包含範圍在l〇g/l至300g/l之所有實用酸濃度之酸性 硫酸銅槽，縮減的CCD可允許Cu層沈積時，電流密度適於 填充次微米之溝槽與通孔結構。 在一例子中，沈積1000A銅層於回火過之8〇A ALD Ru，並利用包含硫酸濃度為i〇〇g/i之電鍍溶液與電鍍電流密 15 度（PCD)為 3mA/cm2(相同於 CCD，PCD/CCD=1)，SEM照片 顯示可沈積連續的銅層，且無孔隙介於銅/釕介面上。無孔 _ 隙存在於銅/釕介面上表示良好的銅釕介面整合與良好的 銅附著於回火之釕表面。在一第二例子中，沈積1000A銅層 於回火過之8〇A ALD Ru，並利用包含硫酸濃度為10(^八之 20 電鍍溶液與電鍍電流密度（PCD)為4.5 mA/cm2(或PCD/CCD = 1.5)，SEM照片亦顯示可沈積連續的銅層，並且無孔隙介 於銅/釕介面上。相同地，電鑛電流密度為7.5 mA/cm2(或 PCDA：CD=2.5)，亦顯示可沈積連續的銅層，並且無孔隙介 15 1292925 • 於銅/釕介面上。此結果表示氣體回火之前處理降低電鍍電 流密度’並增進Ru/Cu介面之接著與整合。 當銅沈積於形成氣體回火之釕表面，Ru/Cu介面顯示無 孔隙之良好的整合，甚至當PCD/CCD等於“夺。相反的，當 5電鍍在CCD(或PCD/CCD=1)時，介於鋼與未回火釕表面之 介面產生介面孔隙，如前所述。一乾淨的釕表面允許較佳 的銅成核與沈積，因此介面整合會改善。 另一個利用含氫氣體回火來前處理vm族金屬表面的 •優勢為促進銅與VIII族金屬的接著。實驗結果顯示因為良好 10 的銅/釕介面整合（無孔隙），較佳的接著介於鋼與前處理、 乾淨、或是無氧化的Ru表面。介於銅與釕層間的良好介面 整合可使半導體元件的可靠度增加。具有前處理之及以表面 明顯地是形成高品質Cu沈積於釕層之關鍵。 另一方面，因為如上所述之親水性的改善，電鍍銅層 15於形成氣體回火之Ru表面，銅將覆蓋整個基材表面。電^ 銅於基材特徵孔的階梯覆蓋性應會改善，因為回火的釘^ _面較具親水性，且更可將電鍍溶液深入傳送至特徵孔中。 圖4顯示良好填孔力之SEM,其為電鍍銅於回火釕表面之 〇·14μηιχΟ·8μιη溝槽上。其中剛沈積之^^為肋入ALDRu。前 20 處理為一形成氣體回火於3〇〇°C耗時3分鐘。銅電鍍電流為 在前 100A 時為 1〇 mA/cm2，剩下 1900A 為 5mA/cm2。 回火製程可實施於一整合回火室中，例如圖5中的回火 室535，或在一分離回火系統中。回火製程可實施於單片晶 圓室或是一批次爐管。 阳 1292925 =了利用含氫氣體回火，在直接電鑛銅之前的權族 ^表面前處理亦可由其他方法達成。前處理方法之一例 …在無銅離子之酸性溶液中陰極處理。表面之㈣X層可 =陰細原，而弱鍵結有機表面污染物可藉由陰極極化從 。-可能之還原反應如下之方程式⑺所示。陰極 2理實施於一整合室中，其類似於如下所述圖6之銅電鍍 室γ或者為一分離於銅電鍍系統的處理室中。陰極處理需 要陽極、陰極、與無銅離子之酸性槽。酸性濃度範圍應介 響於約l〇g/l至約100g/卜較佳範圍介於約10g/1至約5〇§/1之 10間。較佳之酸為硫酸，但其他型態之酸性溶液例如有機磺 (亦即甲基磺酸）亦可被使用。酸性槽需要無銅，以避免銅 沈積，此在陰極處理時之沈積將會導致較差的成核銅島產 生於Ru表面。Ru〇2+2H2--->Ru+2H2〇 (1) 13 1292925. A substrate having a 100A PVD layer is treated by tempering prior to Cu plating. The tempering process is carried out in the presence of a hydrogen-containing gas, for example, to form a gas containing 4% hydrogen and 96% nitrogen, at a temperature ranging from room temperature to about 400 ° C, preferably from about 100 ° C to about 400. °C, the gas flow rate is from about 1 sccm to about 20 5 slm, and from about 5 mTorr to about 1500 Torr for about 2 seconds to about 5 hours. For manufacturing efficiency considerations, the tempering time is preferably within one hour. The purpose of substrate tempering is to reduce the Ru〇2 surface to return to Ru and/or organic surface contamination for adsorption. In one embodiment, the hydrogen containing gas is mixed with a non-reactive gas (e.g., 0 N2 or other passive gases such as argon, helium, etc.). In order to adsorb the surface contamination of the organic 10, a non-reactive gas (such as N2 or other passive gas such as argon) is introduced into the crucible by tempering. The tempering process can be implemented in a single wafer wafer rapid thermal tempering chamber, available from Applied Materials, Inc., Santa Clara, Calif., or in a batch of tubes. Fig. 3B illustrates the reduction of CCD in the tempering of the substrate just after deposition of Ru, wherein the tempering is carried out in a forming gas at a temperature of 270 ° C for 30 seconds in the tempering chamber shown in Fig. 5 below. Curve 311 shows the copper layer of the electric clock on the CCD just deposited on the surface of the φ Ru substrate. Curve 312 shows the reduced CCD of the electroplated copper layer on the surface of a Ru substrate that forms a gas temper. For example, in a sulfuric acid solution containing 10 g/l, the CCD is reduced from 40 mA/cm2 to 8 mA/cm2, and the CCD is reduced from 10 mA/cm2 to 3 mA/cm2 in a solution containing 1 〇 (2 〇2 〇 sulfuric acid solution. Curves 311 and 312 both show that the CCD decreases with increasing acid concentration. The acid of the plating solution can be other types of acids, such as sulfonic acid (including alkane sulfonic acid). If other acids are used instead of sulfuric acid, the equivalent acid is used. Concentration range 1292925 • With the formation of gas tempering, the direct copper plating process can operate at a similar current density as the conventional copper plating process. After the gas tempering, the Ru substrate surface becomes more hydrophilic. As expected, a clean and pure Ru surface. cu is plated on a Ru layer that has been gas tempered, and its plating time is less than 4 hours, preferably less than 2 hours, to reduce the CCD significantly. If the material is exposed to oxygen or other sources of pollution for too long, the CCD will gradually return to the state before the tempering, because it is re-deposited by the atmosphere or re-formation of the organic surface. Φ Due to the tempering of hydrogen-containing gas The greatly reduced CCD is very Importantly, since 10 is an acidic copper sulfate bath containing all practical acid concentrations ranging from l〇g/l to 300g/l, the reduced CCD allows the Cu layer to be deposited with a current density suitable for filling submicron trenches. Through-hole structure. In one example, a 1000A copper layer is deposited on a tempered 8〇A ALD Ru, and a plating solution containing a sulfuric acid concentration of i〇〇g/i is used with a plating current density of 15 degrees (PCD) of 3 mA. /cm2 (same as CCD, PCD/CCD=1), SEM photograph shows that a continuous copper layer can be deposited with no pores on the copper/germanium interface. No pores exist in the copper/germanium interface to indicate good copper. The tantalum interface is integrated with good copper attached to the surface of the tempered crucible. In a second example, a 1000A copper layer is deposited on the tempered 8〇A ALD Ru and is electroplated using a sulfuric acid concentration of 10 (^8-20) The solution and plating current density (PCD) is 4.5 mA/cm2 (or PCD/CCD = 1.5), and the SEM image also shows that a continuous copper layer can be deposited with no pores on the copper/germanium interface. Similarly, the electric current is The density is 7.5 mA/cm2 (or PCDA: CD=2.5), which also shows the deposition of a continuous copper layer without voids. 5 • On the copper/germanium interface. This result indicates that the treatment reduces the plating current density before the gas is tempered and improves the adhesion and integration of the Ru/Cu interface. When the copper is deposited on the surface of the gas tempering, the Ru/Cu interface is displayed. Good integration without voids, even when PCD/CCD is equal to “win. On the contrary, when 5 is electroplated at CCD (or PCD/CCD=1), the interface between the steel and the untempered surface creates interface pores, such as As mentioned before. A clean tantalum surface allows for better copper nucleation and deposition, so interface integration will improve. Another advantage of using a hydrogen-containing gas to temper to pre-treat the surface of the vm metal is to promote the bonding of copper to the Group VIII metal. The experimental results show that because of the good 10 copper/germanium interface integration (no porosity), it is preferred to follow the surface of the steel with pre-treated, clean, or non-oxidized Ru. Good interface integration between the copper and germanium layers can increase the reliability of the semiconductor component. It is important to have a pre-treatment and a surface that is clearly the formation of high quality Cu deposited on the ruthenium layer. On the other hand, because of the improvement in hydrophilicity as described above, the electroplated copper layer 15 is formed on the Ru surface of the gas tempering, and the copper will cover the entire surface of the substrate. The step coverage of the copper to the characteristic holes of the substrate should be improved because the tempered nails are more hydrophilic and the plating solution can be further transported into the feature holes. Figure 4 shows a SEM of good hole-filling force on a 〇14μηιχΟ8μιη groove of electroplated copper on the surface of the tempered crucible. The newly deposited ^^ is ribbed into ALDRu. The first 20 treatments took a gas tempering at 3 °C for 3 minutes. The copper plating current is 1 〇 mA/cm 2 at the first 100 A and 5 mA/cm 2 at the 1900 A. The tempering process can be carried out in an integrated tempering chamber, such as tempering chamber 535 in Figure 5, or in a separate tempering system. The tempering process can be implemented in a single wafer chamber or a batch of tubes. Yang 1292925 = The use of hydrogen-containing gas for tempering, before the direct electro-mineralization of the copper ^ surface pretreatment can also be achieved by other methods. An example of a pretreatment method ... cathodic treatment in an acidic solution without copper ions. The (4) X layer of the surface can be as follows, while the weakly bonded organic surface contaminants can be polarized by the cathode. - Possible reduction reaction is shown in equation (7) below. The cathode 2 is implemented in an integrated chamber similar to the copper plating chamber γ of Fig. 6 as described below or in a processing chamber separate from the copper plating system. Cathodic treatment requires an anode, a cathode, and an acid bath without copper ions. The acid concentration range should range from about 10 g/l to about 100 g/b preferably in the range of from about 10 g/1 to about 5 〇/1. The preferred acid is sulfuric acid, but other types of acidic solutions such as organic sulfonate (i.e., methanesulfonic acid) can also be used. The acid bath requires no copper to avoid copper deposition, which deposition during cathode processing will result in poor nucleation of copper islands on the Ru surface.

Ru〇2+4H*+4e-……>Ru+2H2〇 (2) 15 陰極處理可由控制電位與電流來達成。在由電位控制 的方式中，除工作電極外參考電極需使用來監控晶圓電 鲁位’上述之工作電極為在晶圓表面之薄沈積Ru層以及陽 極。較佳之參考電為置放於接近基材表面之薄銅線。電位 之控制可透過恒電位儀（potentiostat)達成。相對於銅參考電 20 位，被控制的Ru電極電位之範圍介於〇 v〇lt至約-0.5 volt之 間。除了 RuOx還原為Ru，H2之放出可發生於Ru層表面。在 由電流控制的方式中，陰極電流在沈積Ru之基材與陽極間 通過。電流密度應介於約0.05 mA/cm2至約1 mA/cm2。處理 17 1292925 . 時間應於範圍約2秒至約30分鐘。然而由於生產力之考量， - 處理時間較佳維持於5分鐘以下。 雖然實驗之結果與討論上，僅相關於Ru使用於例子 中。本發明之概念亦可應用於其他VIII族金屬，例如铑 5 (Rh)、鈀（Pd)、锇（Os)、銥（Ir)、與鉑（Pt)。 銅電艘可於Electra Cu ECP®系統或SlimCell銅電鐘系 統之室中實施，兩者均可由加州Santa Clara之應用材料公司 提供。圖5顯示SlimCell銅電鍍系統500之上視圖。ECP系統 φ 500包括工作介面（FI)530，其一般亦稱為基材裝載站。工作 •10 介面530包括複數個基材裝載站，其結構用以與基材卡匣 534聯繫。機械臂532位在工作介面530内，用以接取位於卡 匣534中的基材。此外，機械臂532也延伸至連結通道515 中，以連結工作介面530至製程主要平台513。機械臂532的 位置允許機械臂伸至基材卡匣534中以取出基材，並傳送基 15 材至位在主要平台513的其中一個製程室514、516、或是至 回火站535中。相似地，在基材製程程序完成後，機械臂532 亦用以從製程室514、516、或是從回火站535中取出基材。 在此狀況下，機械臂532可將基材移出系統500外，傳送回 其中一卡匣534。 2〇 回火站535將於下更詳細描述，其一般包括兩個回火 室，其中冷卻盤536與加熱盤537位在鄰近位置，並有一傳 送機械臂540位在其中，例如介於兩盤之間。機械臂540 — 般用以移動介於對應之冷卻盤536與加熱盤537之基材。此 外，雖然如例中所述之回火室535位在連結通道5 15鄰近 18 1292925 :處，本發明之實施例並不限定於任何特定之形式或配置。 在-實施例中’回火站535可與主要平台513直接連通，亦 即可由主要平台機械臂進出。例如圖5所示，回火站可 位在與連結通道515直接連通之位置，此連結通道515鄰近 5於主要平台513’以致回火室535可與主要平台513聯繫。詳 細的適當回火室描述於美國專利申請號為6〇/463,86〇，名稱 為”二位置回火室（Two position Anneal Chamber)”，申請於 2003年4月18日。 籲 在一貝施例’回火製程貫施於一整合回火室中，如圖5 10所示之回火室535。在另一實施例中，回火室實施於一分離 之回火系統中。在另一貫施例中，回火製程實施於單片晶 圓室或於批次爐管中。 如上所述，ECP系統500亦包括一製程主要平台jig， 其具有一基材傳送機械臂520位在中央。機械臂520—般包 15 括一或多個臂/葉片522,524,用以支撐與傳送位在其上之基 材。此外機械臂520與伴隨之葉片522,524—般可延伸、旋轉 _與垂直移動，故機械臂520可移動基材進出位在主要平台 513上的複數個製程位置502、504、506、508、510、512、 514、516。相似地，工作介面機械臂532亦包括延伸、旋轉 20 與垂直移動位在其上之基材的能力，亦可線性地穿越機械 臂轨道由工作介面530延伸至主要平台513。一般製程位置 502、504、506、508、510、512、514、5 16可為任何數目 之製程室，其使用於電化學電鑛平台。尤其製程位置可設 計為電化學電鍍室、洗滌室、斜面清洗室、旋轉洗滌乾燥 1292925 ' 室、基材表面清洗室（其整體包括清洗、洗滌、與蝕刻室）、 無電極電鍍室、度量檢測室、和/或其他任何與電鍍平台結 合具優勢的製程室。每一個別之製程室與機械臂一般與製 程控制器511相聯繫，此控制器可為一微處理控制系統，用 5以由使用者與/或位在系統500上的各種感測器接收輸入， 並適當地根據輸入來操作系統5〇〇。 圖6說明一電鍍室600之部份剖視與透視圖，其可實施 於圖 5之製程位置 5〇2、5〇4、506、508、51〇、512、514、 鲁516上。電化學電鍍室_ 一般包括外盆6〇1與一位在外盆 10 601内之内盆602。内盆602—般承裝電鍍溶液，用以在電化 學電鍍製程中電鍍金屬（例如銅）於基材上。在電鍍製程時， 電鑛溶液-般被連續地供應至内盆6 〇 2 (例如對i 〇升的電鑛 室為約每分鐘丨加侖），因此電鍍溶液連續地溢流於内盆6〇2 之最高點卜般稱為堰）’並由外盆6G1收集並由此排放以做 化學劑管理與再循環。電鍵室6〇〇 一般位於一傾斜角度，亦 即電鑛室_之主要架構6〇3—般為一邊升高，故電鑛室繼 _之零件傾斜介於3。至3G。之間，或—般之理想結果為介於4。 至1〇°之間°電鑛室_之主要架構603支撐位在其上部的環 形基座。因為主要架構6〇3 一邊之升高，故基座6〇4的上表 20面-般由水平傾斜至一角度，此角度相當於主要架構相 對於平之角度。基座6Q4—般包括形成於其中央部份之環 形或盤形接收，環形接收用以接收一盤形陽極元件605。基 座6〇4更包括延伸於其下表面之複數個流體入口 /排放口 _。每個流體入口 /排放口 _一般為獨立地供應或排放流 20 1292925 • 體，使流體進出電鍍室600之陽極隔間或陰極隔間。陽極元 件605—般包括複數個狹縫607通過其中，其中狹縫607—般 為彼此互相平行，並橫越陽極元件605之表面。平行之排列 允許產生於陽極表面之濃稠流體往下流動穿越陽極表面至 5 狹縫607中。電鍍室600更包括膜支撐元件606。膜支撐元件 606—般用其外周緣固定於基座604上，並包括一内部區域 用以使流體通過其中。膜608延伸橫越支撐元件606，並操 作用以流體上分離電鍍室之陰極電解液室與陽極電解液 • 室。膜支撐元件606可包括一位在膜邊緣附近的Ο形密封， 10 其中此密封用以防止流體由固定於支撐元件606的膜之一 側流至另一側。擴散板610—般為一多孔性陶瓷盤元件，且 用以產生層流或流體之流動於被電鍍之基材方向，擴散板 610位在電鍍室中介於膜608與被電鍍之基材之間。一電鍍 室的例子更進一步說明於美國專利申請號1〇/268,284,其申 15 請於2002年10月9日，名稱為”電化學製程室 (Electrochemical Processing cell)”並申明美國專利臨時申 φ 請號60/398,345之優先權，其申請於2002年7月24日，兩者 均一併做為參考。 上述實施例僅係為了方便說明而舉例而已，本發明所 20 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖1A〜1C係整合電路製作流程之剖視圖。 21 1292925 圖2說明臨界電流密度與硫酸濃度之關係圖。 圖3 A說明在銅電鍍前基材表面前處理之流程圖。 圖3B係說明As沉積與回火釕基材之臨界電流密度與硫酸濃 度之關係圖。 圖4係銅電鍍於回火釕基材表面在一 〇.14μιηΧ〇·8μιη溝槽之 SEM 圖。 圖5係本發明之一 較佳實施例之電化學電鍍系統之示意圖 圖6係用於本發明之電化學電鍍系統之電鍍室一較佳實 例之示意圖。 【主要元件符號說明】 100基材 102介電層 104 金屬接觸孔 106阻隔層 108 VIII族金屬層 110 金屬材料 120孔洞 301步驟 302 步驟 311曲線 312曲線 500 ECP系統 502製程位置 504 製程位置 506製程位置 508製程位置 510 製程位置 512製程位置 514製程位置 516 製程位置 511控制器 513主要平台 515 連結通道 520機械臂 522葉片 524 葉片 5 3 0工作介面 Ψ 532機械臂 534 卡匣 535回火站 536冷卻盤 537 加熱盤 540機械臂 600電鍍室 601外盆 602 内盆 22 1292925 605陽極元件 608膜 603主要架構 604基座 606支撐元件 607狹縫 609入口 /排放口 610擴散板 23Ru〇2+4H*+4e-...>Ru+2H2〇 (2) 15 Cathodic treatment can be achieved by controlling the potential and current. In the potential controlled mode, the reference electrode is used in addition to the working electrode to monitor the wafer ohmic position. The above working electrode is a thin deposited Ru layer and an anode on the surface of the wafer. A preferred reference is a thin copper wire placed near the surface of the substrate. The control of the potential can be achieved by a potentiostat. The controlled Ru electrode potential ranges from 〇 v〇lt to about -0.5 volt relative to the copper reference 20 bits. In addition to the reduction of RuOx to Ru, the release of H2 can occur on the surface of the Ru layer. In the current controlled mode, the cathode current passes between the substrate where the Ru is deposited and the anode. The current density should be between about 0.05 mA/cm2 and about 1 mA/cm2. Treatment 17 1292925. The time should range from about 2 seconds to about 30 minutes. However, due to productivity considerations, the processing time is preferably maintained below 5 minutes. Although the results and discussion of the experiment are only relevant to Ru used in the examples. The concepts of the present invention are also applicable to other Group VIII metals such as ruthenium 5 (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum (Pt). Copper vessels can be implemented in the Electra Cu ECP® system or in the SlimCell copper bell system, both from Applied Materials, Inc., Santa Clara, California. Figure 5 shows a top view of the SlimCell copper electroplating system 500. The ECP system φ 500 includes a working interface (FI) 530, which is also commonly referred to as a substrate loading station. Work • The 10 interface 530 includes a plurality of substrate loading stations that are configured to interface with the substrate cassette 534. The robot arm 532 is positioned within the working interface 530 for accessing the substrate located in the cassette 534. In addition, the robot arm 532 also extends into the connecting passage 515 to connect the working interface 530 to the process main platform 513. The position of the robotic arm 532 allows the robotic arm to extend into the substrate cassette 534 to remove the substrate and transport the substrate 15 into one of the process chambers 514, 516 of the primary platform 513 or to the tempering station 535. Similarly, after the substrate processing procedure is completed, the robotic arm 532 is also used to remove the substrate from the process chambers 514, 516, or from the tempering station 535. In this situation, the robotic arm 532 can move the substrate out of the system 500 and back to one of the cassettes 534. The second tempering station 535 will be described in more detail below, which generally includes two tempering chambers, wherein the cooling plate 536 is positioned adjacent to the heating plate 537 and has a transfer robot 540 therein, such as between two disks. between. The robot arm 540 is generally used to move the substrate between the corresponding cooling plate 536 and the heating plate 537. In addition, although the tempering chamber 535 is as described in the example adjacent to the connecting passage 5 15 adjacent to 18 1292925 :, embodiments of the present invention are not limited to any particular form or configuration. In the embodiment, the tempering station 535 can be in direct communication with the main platform 513, or can be accessed by the main platform robot. For example, as shown in Fig. 5, the tempering station can be in direct communication with the connecting passage 515 which is adjacent to the main platform 513' such that the tempering chamber 535 can be in communication with the main platform 513. A detailed appropriate tempering chamber is described in U.S. Patent Application Serial No. 6/463,86, entitled "Two Position Anneal Chamber", filed on April 18, 2003. The tempering process is applied to an integrated tempering chamber, such as the tempering chamber 535 shown in FIG. In another embodiment, the tempering chamber is implemented in a separate tempering system. In another embodiment, the tempering process is carried out in a single wafer chamber or in a batch furnace tube. As noted above, the ECP system 500 also includes a process master platform jig having a substrate transfer robot 520 located centrally. The robotic arm 520 generally includes one or more arms/blades 522, 524 for supporting and transporting the substrate thereon. In addition, the robot arm 520 and the accompanying blades 522, 524 can be extended, rotated, and moved vertically, so that the robot arm 520 can move the substrate into and out of the plurality of process positions 502, 504, 506, 508, 510 on the main platform 513. 512, 514, 516. Similarly, the working interface robot 532 also includes the ability to extend, rotate 20, and vertically move the substrate thereon, or to extend linearly across the robot arm track from the working interface 530 to the main platform 513. The general process locations 502, 504, 506, 508, 510, 512, 514, 5 16 can be any number of process chambers for use in an electrochemical power plant platform. In particular, the process position can be designed as an electrochemical plating chamber, a washing chamber, a bevel cleaning chamber, a rotary washing and drying 1292925 ' chamber, a substrate surface cleaning chamber (which includes cleaning, washing, and etching chambers as a whole), an electroless plating chamber, and a measurement test. A chamber, and/or any other process chamber that combines advantages with an electroplating platform. Each individual process chamber and robotic arm is typically associated with a process controller 511, which may be a microprocessor control system that receives input by various users and/or various sensors located on system 500. , and according to the input, the operating system 5〇〇. Figure 6 illustrates a partial cross-sectional and perspective view of a plating chamber 600 that can be implemented at process locations 5, 2, 5, 4, 506, 508, 51, 512, 514, and 516 of Figure 5. The electrochemical plating chamber _ generally includes an outer pot 6〇1 and an inner pot 602 in the outer pot 10 601. The inner basin 602 generally houses a plating solution for plating a metal (e.g., copper) onto the substrate during the electrochemical plating process. During the electroplating process, the electromineral solution is generally continuously supplied to the inner basin 6 〇 2 (for example, about 5 gallons per minute for the i-elevated electric mine), so that the plating solution continuously overflows into the inner basin 6〇 The highest point of 2 is commonly referred to as 堰)' and is collected by the outer basin 6G1 and thus discharged for chemical management and recycling. The key compartment 6〇〇 is generally located at an oblique angle, that is, the main structure of the electric mine compartment _3 〇3 is generally raised on one side, so the parts of the electric mining chamber are inclined at 3. To 3G. The ideal result between, or generally, is between 4. Between 1 ° ° ° main compartment 603 of the main structure 603 supports the annular base located in the upper part. Since the main structure of the 6〇3 side is raised, the upper surface 20 of the base 6〇4 is generally tilted horizontally to an angle corresponding to the angle of the main structure relative to the flat. The susceptor 6Q4 generally includes an annular or disk-shaped receiving portion formed at a central portion thereof for receiving a disk-shaped anode member 605. The base 6〇4 further includes a plurality of fluid inlet/discharge ports _ extending from the lower surface thereof. Each fluid inlet/discharge port _ is generally supplied or vented separately 20 1292925 • to allow fluid to enter and exit the anode or cathode compartment of the plating chamber 600. The anode member 605 generally includes a plurality of slits 607 therethrough, wherein the slits 607 are generally parallel to each other and traverse the surface of the anode member 605. The parallel arrangement allows the thick fluid generated on the anode surface to flow down through the anode surface into the 5 slits 607. The plating chamber 600 further includes a membrane support member 606. Membrane support member 606 is generally secured to base 604 by its outer periphery and includes an interior region for fluid to pass therethrough. Membrane 608 extends across support member 606 and functions to fluidly separate the catholyte chamber of the plating chamber from the anolyte chamber. Membrane support member 606 can include a one-shot seal adjacent the edge of the membrane, 10 wherein the seal prevents fluid from flowing from one side of the membrane secured to support member 606 to the other. The diffuser plate 610 is generally a porous ceramic disk member and is used to generate a laminar flow or a fluid flow in the direction of the substrate to be plated. The diffusion plate 610 is located in the plating chamber between the film 608 and the substrate to be plated. between. An example of a plating chamber is further described in U.S. Patent Application Serial No. 1/268,284, filed on October 9, 2002, entitled "Electrochemical Processing Cell" and affirmed the U.S. Patent Provisional Application φ Please refer to the priority of 60/398,345, and the application is on July 24, 2002, both of which are incorporated by reference. The above-described embodiments are merely examples for convenience of description, and the scope of the claims of the present invention is determined by the scope of the claims, and is not limited to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are cross-sectional views showing a process of manufacturing an integrated circuit. 21 1292925 Figure 2 illustrates the relationship between critical current density and sulfuric acid concentration. Figure 3A illustrates a flow chart of substrate surface pretreatment prior to copper plating. Figure 3B is a graph showing the relationship between the critical current density of As deposited and the tempered tantalum substrate and the concentration of sulfuric acid. Figure 4 is an SEM image of a copper plated on a tempered crucible substrate surface in a 14.14μιη·8μιη groove. Figure 5 is a schematic illustration of an electrochemical plating system in accordance with a preferred embodiment of the present invention. Figure 6 is a schematic illustration of a preferred embodiment of a plating chamber for use in the electrochemical plating system of the present invention. [Main Component Symbol Description] 100 Substrate 102 Dielectric Layer 104 Metal Contact Hole 106 Barrier Layer 108 Group VIII Metal Layer 110 Metal Material 120 Hole 301 Step 302 Step 311 Curve 312 Curve 500 ECP System 502 Process Location 504 Process Location 506 Process Location 508 Process Location 510 Process Location 512 Process Location 514 Process Location 516 Process Location 511 Controller 513 Main Platform 515 Connection Channel 520 Robot Arm 522 Blade 524 Blade 5 3 0 Working Interface Ψ 532 Robot Arm 534 Card 535 tempering Station 536 Cooling Plate 537 heating plate 540 robot arm 600 plating chamber 601 outer basin 602 inner basin 22 1292925 605 anode element 608 film 603 main structure 604 base 606 support element 607 slit 609 inlet / discharge port 610 diffuser plate 23

Claims (1)

1292925 十、申請專利範圍·· 1· γ種直接鍍銅於基材上的方法，其中該基材具有一 VIII族金屬於其表面上，包括： 前處理該基材表面，以移除位在該基材上之VIII族金屬 5表面氧化層和/或有機表面污染物，使電鍍時的臨界電流密 度減小；以及 在一酸性槽中，電鍍一連續且無孔隙之銅層於該前處 籲理過之基材表面’其中使用之一電錢電流密度等於或大於 該臨界電流密度。 10 2·如申叫專利範圍第1項所述之方法，其中該VIII族金 屬選自於由釕（Ru)、铑（Rh)、鈀（Pd)、鐵（〇s)、銥（ΐΓ)、與鉑 (Pt)所構成之群組。 3.如申請專利範圍第1項所述之方法，其中該vm族金 屬之厚度小於1〇〇〇A。 15 (如中睛專利圍第1項所述之方法，其中在該前處 理之後的該銅電鍍實施時間小於4小時。 _ . 5.如中請專利範圍第i項所述之方法，其中該臨界電 流密度隨著該酸性槽之酸性增加而減少。 6.如申請專利範圍第i項所述之方法，其中該酸性槽 20之酸性來自於硫酸，該硫酸濃度介於1〇的至3〇_之間。 7·如申請專利範圍第1項所述之方法，其中該臨界電 流密度小於10mA/cm2。 24 1292925 15 20 8·如申請專利範圍第1項所 — 国矛貝所述之方法，其中前處理該 基材係猎由回火該基材於一含 s氧乳體與/或一對於VIII族金 屬不反應之氣體環境下達成。 9·如申請專利範圍第8項所述之方法 量介於lsccm至20slm之間。 10 ·如申請專利範圍第8項所述之方法 生在温度介於l〇〇°C至4〇〇°c之間。 11·如申請專利範圍第8項所述之方法 生在壓力介於5mTorr至1500T〇rr之間。 12·如申請專利範圍第8項所述之方法 間介於2秒至5小時之間。 13·如申請專利範圍第1項所述之方法 前處理小於1小時。 14·如申請專利範圍第1項所述之方法 實施於一整合之單片晶圓回火室。 15 ·如申請專利範圍第1項所述之方法 基材係藉由在一含酸槽中之陰極處理達成 16·如申請專利範圍第15項所述之的方法，其中該含酸 槽具有之酸濃度介於10g/l至100g/l之間。 ^.如申請專利範圍第丨5項所述之的方法，其中該陰極 處理實施在一電位介於〇伏(她)至_〇5伏之間或在一電流 迷、度介於0.05mA/cm2至1 mA/cm2之間。 18.如申請專利範圍第15項所述之的方法，其中該含酸 槽具有硫酸。 其中該氣體流 其中該回火發 其中該回火發 其中該回火期 其中該基材之 其中該前處理 其中前處理該 25 1292925 _ 19.如申請專利範圍第16項所述之的方法，其中該酸濃 度介於10g/l至50g/l之間。 20.如申請專利範圍第1項所述之方法，其中該電鍍銅 於該前處理之VIII族金屬表面之起始電鍍電流至少等於該 5 臨界電流密度。1292925 X. Patent Application Scope 1. The method for directly plating copper on a substrate, wherein the substrate has a Group VIII metal on the surface thereof, comprising: pretreating the surface of the substrate to remove the The surface oxide layer and/or organic surface contaminants of the Group VIII metal 5 on the substrate reduce the critical current density during electroplating; and in a acidic bath, a continuous and void-free copper layer is plated at the front The surface of the substrate that has been arbitrarily used is one in which the current density of the electricity is equal to or greater than the critical current density. The method of claim 1, wherein the Group VIII metal is selected from the group consisting of ruthenium (Ru), rhodium (Rh), palladium (Pd), iron (〇s), and ruthenium (ΐΓ). And a group of platinum (Pt). 3. The method of claim 1, wherein the vm group metal has a thickness of less than 1 〇〇〇A. The method of claim 1, wherein the copper plating implementation time after the pre-treatment is less than 4 hours. _. 5. The method of claim i, wherein The critical current density decreases as the acidity of the acid bath increases. 6. The method of claim i, wherein the acid bath 20 is acid derived from sulfuric acid, the sulfuric acid concentration being between 1 and 3 7. The method of claim 1, wherein the critical current density is less than 10 mA/cm2. 24 1292925 15 20 8. The method of claim 1 of the patent scope Wherein the pretreatment of the substrate is achieved by tempering the substrate in a gaseous environment containing s oxy-emulsion and/or a non-reactive VIII metal. 9. As described in claim 8 The method amount is between 1sccm and 20slm. 10 · The method described in item 8 of the patent application is produced at a temperature between 1 ° C and 4 ° C. 11 · If the patent application is 8 The method described in the section is between 5mTorr and 1500T〇rr. The method described in item 8 of the range of interest is between 2 seconds and 5 hours. 13. The method according to the method of claim 1 is pre-treated for less than 1 hour. 14 as described in claim 1 The method is implemented in an integrated single wafer tempering chamber. 15 · The method of claim 1 is performed by a cathode treatment in an acid tank. The method of claim 15, wherein the acid-containing tank has an acid concentration of between 10 g/l and 100 g/l. The method of claim 5, wherein the cathode treatment is carried out. At a potential between 〇 ( (her) to _ 〇 5 volts or in a current fan, the degree is between 0.05 mA / cm 2 to 1 mA / cm 2 18. As described in claim 15 The method, wherein the acid containing tank has sulfuric acid. wherein the gas stream wherein the tempering occurs, wherein the tempering occurs during the tempering period wherein the substrate is pretreated in the substrate wherein the pretreatment is 25 1292925 _ 19. The method of claim 16 wherein the acid concentration is between 10 g/l and 50 g/l. The method of claim 1 Item patent range, wherein the electroless copper plating current at the start of a Group VIII metal surface prior to the treatment at least equal to the critical current density 5. 2626
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