JP2008502806A - Barrier layer surface treatment method enabling direct copper plating on barrier metal - Google Patents

Abstract

Embodiments of barrier layer surface treatment methods that allow direct copper plating without the use of a copper seed layer are described. In one embodiment, a method of plating copper on a substrate with a Group VIII metal layer thereon pre-treats the substrate surface by removing a Group VIII metal surface oxide layer and / or surface contaminants, Plating copper on the treated Group VIII metal surface. Pretreating the substrate includes annealing the substrate in a hydrogen-containing gas environment and / or an environment with a gas that does not react with Group VIII, by cathodic treatment in an acid-containing vessel, or in a substrate containing an acid-containing vessel. It is feasible by soaking.

Description

Field of the invention

  Embodiments of the present invention generally relate to a method for barrier layer surface treatment that allows direct copper plating on the barrier metal.

Background art description

  Sub-quarter micron multi-layer metal technology is one of the next generation advanced technologies for ultra-large scale integrated circuit (VLSI) and ultra super large scale integrated (ULSI) semiconductor devices. Multilayer interconnects at the heart of this technology require the filling of contacts, vias, lines, and other features that are formed in high aspect ratio openings. The reliable formation of these configurations is crucial for the success of VLSI and ULSI, as well as for continued efforts to increase circuit density and the quality of individual substrates and semiconductor chips.

  As circuit density increases, the width of contacts, vias, lines, and other features, as well as the insulating material between them, decreases to about 65 nm or less, however, the thickness of the insulating layer is substantially constant. As a result, the aspect ratio to the shape, ie the height divided by the width, increases. Many conventional deposition technology processes do not consistently fill structures with aspect ratios greater than 6: 1, especially when aspect ratios exceed 10: 1. As such, there are a number of ongoing attempts towards the formation of void-free, nanometer-sized structures with a high aspect ratio of feature height to feature width of 6: 1 or higher.

  In addition, when the feature width decreases, the device current generally remains constant or increases, so that the current density increases for such features. Aluminum is an elemental aluminum because it has recognized low electrical resistance, excellent adhesion to most insulating materials, and ease of patterning, and high purity aluminum is readily available. And aluminum alloys have been the customary metals used to form vias and lines in semiconductor devices. However, aluminum has a higher electrical resistance than other more conductive metals, such as copper (Cu). In addition, aluminum can undergo electrophoresis (electromigration), leading to the formation of voids in the conductor.

  Copper and copper alloys have a lower resistance than aluminum, as well as a sufficiently high electrophoretic resistance compared to aluminum. These features are important to withstand high levels of integration and high current densities experienced at increased device speeds. Copper also has excellent thermal conductivity. Thus, copper becomes a selective metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.

  Traditionally, chemical vapor deposition (CVD) and physical vapor deposition (PVD) techniques have been used to fill these interconnect features. However, as interconnect sizes decrease and aspect ratios increase, void-free interconnect features filled by conventional metal wiring techniques become increasingly difficult using CVD and / or PVD. As a result, plating techniques, such as electrochemical plating (ECP), have emerged as a viable process for filling sub-quarter micron sized high aspect ratio interconnect features within integrated circuit manufacturing processes.

  Most ECP processes are generally two-step processes, where a seed layer is first formed on the surface of the feature on the substrate (this process can be performed in a separate system), and then the surface of the feature is exposed to the electrolyte solution. While an electrical bias is simultaneously applied between the substrate surface and the anode located in the electrolyte solution.

  Conventional plating methods deposit a copper seed layer on a diffusion barrier layer (eg, tantalum or tantalum nitride) by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Including that. However, as feature sizes become smaller, it becomes difficult to have a proper seed stage coating using PVD technology, and discontinuous islands of copper mass are often obtained within the feature sidewalls near the feature bottom. A thick copper layer is formed over the region when using a CVD or ALD deposition process instead of PVD to deposit a continuous sidewall layer through the depth of the high aspect ratio feature. A thick copper layer on the area can cause the feature mouth to close before the feature sidewalls are completely covered. ALD and CVD techniques tend to create discontinuities in the seed layer as well, when the deposition thickness on the region is reduced to prevent the mouth from closing. These discontinuities in the seed layer have been shown to cause plating defects in the layer plated on the seed layer. In addition, copper tends to oxidize easily in the atmosphere and copper oxide dissolves easily in the plating solution. In order to prevent complete dissolution of the copper in the feature, the copper seed layer is often relatively thick (as high as 800 Å) and may prevent the plating process from filling the feature. Therefore, it is desirable to have a copper plating process that allows direct electrolytic plating of copper onto a thin barrier layer without the use of a copper seed layer.

  Therefore, there is a need for a copper plating process that can be filled with features and does not require a copper seed layer.

Summary of the present invention

  Embodiments of the present invention generally provide a method for barrier layer surface treatment that allows direct copper plating without the use of a copper seed layer. In one embodiment, a method of directly plating copper on a substrate with a Group VIII metal layer on the substrate includes a Group VIII metal surface oxidation on the substrate surface to reduce critical current density during plating. Pre-treat substrate surface to remove layer and / or organic surface contaminants, continuous and void-free on substrate surface pre-treated in acid plating bath at plating current density equal to or greater than critical current density Plating a copper layer.

Detailed description

  Ruthenium (Ru) thin films deposited by CVD, ALD, or PVD are potential candidates for a seedless diffusion barrier between interlayer insulation (IMD) and copper interconnects for ≦ 45 nm technology. Ruthenium is a Group VIII metal having low electrical resistance (resistivity ˜7 μΩcm) and high thermal stability (high melting point˜2300 ° C.). It is relatively stable in the presence of oxygen and water at room temperature. The thermal and electrical conductivity of Ru is twice that of tantalum (Ta). Further, ruthenium does not form an alloy with copper at 900 ° C. or less, and exhibits excellent adhesion to copper. Accordingly, the semiconductor industry has shown interest in using Ru as a copper barrier layer. The low resistance of Ru can be an advantage when attempting to fill ruthenium-coated features with copper without using a seed layer.

1A-1C show cross-sectional views of a substrate at different stages of a copper interconnect manufacturing sequence incorporating a Group VIII metal barrier layer of the present invention. FIG. 1A shows a cross-sectional view of a substrate 100 having, for example, a metal contact 104 and an insulating layer 102 formed thereon. The substrate 100 may include a semiconductor material such as, for example, silicon, germanium, or gallium arsenide. Insulating layer 102 is silicon oxide, silicon nitride, silicon oxynitride and / or SiO _x C _y , such as Black Diamond® low dielectric interlayer insulating film available from Applied Materials, Inc., located in Santa Clara, California. Or a silicon oxide insulating material doped with carbon. The metal contact 104 can include copper, for example, among others. The opening 120 may be defined in the insulating layer 102 to provide an opening on the metal contact 104. The opening 120 can be defined in the insulating layer 102 using conventional lithography and etching techniques. The width of the opening 120 can be equal to or less than about 900 cm. The thickness of the insulating layer 102 can range between about 1000 and about 10,000 inches.

  In one embodiment, the barrier layer 106 may be formed in the opening 120 defined in the insulating layer 102. Optional barrier layer 106 may be one or more melts used as a copper barrier material, such as, among others, titanium, titanium nitride, titanium nitride, tantalum, tantalum nitride, tantalum silicon nitride, tungsten, and tungsten nitride. It may contain a difficult metal-containing layer. Optional barrier layer 106 may be formed using a suitable deposition process, such as ALD, chemical vapor deposition (CVD) or physical vapor deposition (PVD). For example, titanium nitride can be deposited using a CVD process or an ALD process in which titanium tetrachloride and ammonia react. In one embodiment, the tantalum and / or tantalum nitride is described in U.S. Patent Publication No. 2003-0121608, published on Jul. 3, 2003, incorporated herein by reference and commonly assigned. Is deposited as a barrier layer. The optional barrier layer thickness is between about 5 and about 150 mm, preferably less than 100 mm.

  In one embodiment, a thin film of a Group VIII metal, such as ruthenium (Ru), rhodium (Rh), palladium (Pd), osium (Os), iridium (Ir), and platinum (Pt), includes copper vias and lines. Can be used as an underlayer (or barrier layer) for Such a Group VIII metal that is resistant to corrosion and oxidation can provide a surface on which a copper layer is subsequently deposited using an electrochemical plating (ECP) process. The Group VIII metal acts as a copper barrier layer. In addition, Group VIII metals can serve as a glue layer (glue layer) between a conventional barrier layer and copper, such as Ta (tantalum) and / or TaN (tantalum nitride). It can be deposited on the barrier layer. Group VIII metals are typically deposited using chemical vapor deposition (CVD) processes, atomic layer deposition (ALD) or physical vapor deposition (PVD) processes.

  Referring to FIG. 1B, a Group VIII barrier metal layer 108, such as ruthenium (Ru), is formed on the substrate, in this embodiment on the optional barrier layer 106. The thickness of the Group VIII barrier metal layer 108 depends largely on the device structure being fabricated. Generally, the thickness of the Group VIII barrier metal layer 108, such as ruthenium (Ru), is less than about 1000 mm, preferably between about 5 mm and about 200 mm. In one embodiment, the Group VIII barrier metal layer 108 is a ruthenium layer having a thickness of less than about 100 inches, for example, about 50 inches.

Thereafter, referring to FIG. 1C, the opening 120 may be filled with copper 110 to complete the copper interconnect. In one embodiment, a noble or transition metal layer, such as a ruthenium layer, serves as a seed layer where copper is directly deposited using ECP or other copper plating techniques. Electrochemical plating solutions for ECP generally include a copper source, an acid source, a chloride ion source, and one plating solution additive: stabilizers, inhibitors, accelerators, antifoaming agents, and the like. For example, the plating solution may comprise about 30 g / l to about 60 g / l Cu, about 10 g / l to about 50 g / l sulfuric acid, about 20 to about 100 ppm Cl ions, about 5 to about 30 ppm addition promoter, about 100 to about 1000 ppm addition inhibitor and about 1 to about 6 ml / l addition stabilizer may be included. Plating current, in order to fill copper into submicron trenches and / or vias within the structure can range from about 2 mA / cm ² ~ about 10 mA / cm ^2. An example of a copper plating chemistry and process was filed on Jul. 8, 2003 and commonly assigned U.S. patent application entitled “Multistage Electrodeposition Process for Direct Copper Plating on Barrier Metals”. U.S. Patent Application No. 60, filed 10 / 1016,097, and October 10, 2003, entitled "Methods and Chemistry for Providing Initial Conformal Electrochemical Deposition of Copper in Submicron Forms". / 510197. An example of an electrochemical plating (ECP) system and a representative plating cell are described in FIGS. 5 and 6 below.

It has been found that the conventional copper plating process using 10-50 g / l H ₂ SO ₄ and a plating current density of 2-10 mA / cm ² does not result in continuous copper thin film (≦ 1000 kg) deposition on Ru. A continuous copper film is formed on Ru when the plating current density and / or the concentration (or acidity) of H ₂ SO ₄ increases beyond the values used in conventional copper plating. A minimum or critical current density (CCD) is known, where a plating current density equal to or greater than this value forms a continuous copper film on the Ru layer, and a current density below this value is present on the Ru layer. Do not form a continuous thin film. The size of the CCD strongly depends on the acidity of the plating solution.

FIG. 2 shows an example of critical current density (CCD) versus sulfuric acid H ₂ SO ₄ concentration. The CCD shown in FIG. 2 is defined as the minimum current density required to form a 1000 連 続 continuous copper film on Ru. Below the CCD, a continuous copper film that is visually glossy is not deposited in the central region of the substrate. The size of the CCD strongly depends on the acidity level of the plating bath, while the CCD does not depend on the Ru deposition method (either ALD, CVD or PVD).

It is well known that nucleation kinetics and crystal growth for electrolytic deposition are closely related to local electrochemical overvoltage at the nucleation / growth site. Overvoltage is defined as the difference between the actual voltage and the zero current (open circuit) voltage. A high overvoltage reduces the critical nucleus size and increases the density of the nuclei to assist in the formation of new crystal nuclei, while the low electrochemical overvoltage assists the growth of existing crystals. Furthermore, the presence of sulfur-containing organic additives (eg, promoters) in the plating solution is believed to enhance the surface diffusion of Cu adatoms and thus promote crystal growth at the expense of nucleation. Cu adsorbed molecules are copper atoms that deposit on the substrate surface during plating as well as before they are incorporated into the Cu thin film. Since the plating current density depends on the electrochemical overvoltage for a known bath, the copper deposition structure / morphology is affected by the plating current density. Photographed near the center of the substrate of a 1000 Å copper thin film (measured near the end of the substrate) plated on a 100 Ｒ Ru thin film in a 10 g / l sulfuric acid containing plating solution at a plating current of 3 mA / cm ² Scanned electron microscope (SEM) images revealed large crystals and poor quality thin film deposits near the center of the substrate. A 100 厚 thick Ru film was deposited by PVD. According to the results shown in FIG. 2, the CCD is about 40 mA / cm ² when the sulfuric acid concentration is 10 g / l. The current density of 3 mA / cm ² was even lower than 40 mA / cm ² (CCD), so a discontinuous layer was formed as expected. Under this plating condition, only a few crystals are stable enough to serve as nucleation centers for further crystal growth, so the energy from the plating current is the fast copper adatom surface It is thought that it helps diffusion and is mainly used for the growth of these crystals. Therefore, SEM shows large crystals and Cu island deposition in the center of the substrate. In order to form a continuous copper film across the substrate under this condition, the deposited layer must be very thick and the deposited layer probably contains voids, which are not compatible with Cu interconnect applications. A substrate having a continuous copper thin film with a thickness of 5000 mm has a plating current density of about 10 mA / cm ² (slightly lower than a 15 mA / cm ² CCD) and a plating solution containing 60 g / l H ₂ SO _4. Used and found to be able to be formed on Ru (100 （thick and deposited by PVD) thin films. However, there were large voids at the copper / Ru interface.

It was found that when the plating current was increased to 30 mA / cm ² , the crystal density increased and the crystal size decreased at the center of the substrate. However, a continuous copper thin film was not formed on the Ru surface because the plating current was below the CCD. As before, the Ru thin film was 100 mm thick and was deposited by PVD.

In addition, there is a drawback that the plating current increases. Generally, high plating current density tends to result in poor quality gap filling. In general, plating current densities of less than about 10 mA / cm ² have been found to promote bottom-up gap filling. In order to reduce the plating current density to a range compatible with bottom-up gap filling, it is necessary to increase the sulfuric acid concentration. When the sulfuric acid concentration rose to 160 g / l and the plating current was 5 mA / cm ² equal to the CCD at a specific acidic concentration, a 1000 連 続 continuous copper thin film was formed over the 100 Å Ru thin film. However, the cross-sectional SEM image shows that the void was formed at the copper / Ru interface. When the plating current is increased to 10 mA (twice that of a 5 mA / cm 2 CCD) and the sulfuric acid concentration is maintained at 160 g / l, a continuous copper thin film of 5000 liters has no void at the copper / Ru interface and 100 liters of Ru. Formed on the layer.

  One reason for the CCD dependence of bath acidity is related to the local electrochemical overvoltage discussed above. A low acidity plating solution has a high resistance. Therefore, a high CCD is required to overcome the high resistance in a low acidity plating bath.

A recent study presented by Chian et al. From the University of North Texas at a national meeting of the American Chemical Society in New Orleans, Louisiana showed that ruthenium oxide (RuO ₂ ) has a metal-like conductivity and copper It is plated on ruthenium oxide on it and shows strong adhesion. The high CCD observed on the actual deposited (as-deposited) Ru surface may be the result of Ru surface oxidation and / or the presence of organic surface contaminants. It is speculated that the “pure” Ru surface is more active for Cu nucleation. Removing the surface oxide layer or organic surface contaminants by a pre-treatment process prior to copper plating reduces the plating current and the acidity of the plating bath required to form a continuous copper layer without copper / Ru interface voids. Reduce greatly. The pretreatment process may expose the substrate surface to a reducing agent. FIG. 3 shows the flow of the pretreatment process. In step 301, a substrate with a Group VIII metal, such as Ru, is subjected to a process, such as an annealing process in a reducing gas (eg, hydrogen gas) to clean the surface of metal oxide or organic contaminants. Is preprocessed. In step 302, the copper film is directly plated on the pretreated substrate. One possible redox reaction is shown as chemical formula (1) below.

A substrate with a 100 Å PVDRu thin film is pretreated by an annealing process slightly before Cu plating. The annealing process is between about room temperature and about 400 ° C., preferably between about 100 ° C. and about 400 ° C. in the presence of a hydrogen-containing gas, such as a forming gas, containing 4% H ₂ and 96% N _2. At a gas flow rate between about 1 sccm and about 20 slm at a temperature of about 5 mTorr to about 1500 Torr for about 2 seconds to about 5 hours. The annealing time is preferably within 1 hour for manufacturing efficiency. The purpose of the substrate annealing process is to reduce the RuO ₂ surface to Ru and / or remove organic surface contaminants. In one embodiment, the hydrogen-containing gas is mixed with a gas that does not react, such as N ₂ or an inert gas (eg, Ar, He, etc.). For the purpose of removing organic surface contaminants, an annealing treatment with a gas that does not react with Ru, such as N ₂ or an inert gas (eg, Ar) can be used. The annealing process can be performed in a single wafer rapid thermal annealing chamber available from Applied Materials, Santa Clara, California, or in a batch furnace.

FIG. 3B shows the size of the CCD after the actually deposited (as-deposited) Ru substrate was annealed with forming gas at 270 ° C. for 30 seconds in the annealing chamber described in FIG. 5 below. An example in which is reduced. Curve 311 shows the CCD for copper plating on the actual (as-deposited) Ru substrate surface. Curve 312 shows a further reduced CCD for copper plating on a Ru substrate surface annealed with forming gas. For example, the CCD for a solution containing 10 g / l H ₂ SO ₄ drops from 40 mA / cm ² to a CCD of 8 mA / cm ² , and the plating solution containing 100 g / l H ₂ SO ₄ starts from 10 mA / cm ^2. Reduced to 3 mA / cm ² CCD. Both curves 311 and 312 show that the CCD decreases with increasing acid concentration. The acid used in the plating solution can be other types of acids, such as sulfonic acids (including alkane sulfonic acids). If other types of acids are used instead of sulfuric acid, an equivalent acid concentration range must be used.

Using a forming gas annealing process, a direct copper plating process can be operated at a similar current density as a conventional copper plating process. After the forming gas anneal, the Ru substrate surface tends to become more hydrophobic, as expected for a clean, pure Ru surface. Cu plating on the Ru thin film annealed with forming gas should be performed within 4 hours, preferably within 2 hours, following the forming gas annealing process to maintain a large reduction in CCD. If the substrate is exposed to oxygen or other contaminants for too long, the CCD will gradually return to its pre-anneal state due to RuO _x re-formation or organic surface contaminant re-deposition from the atmosphere.

Current density compatible with gap filling into sub-micron trench / via structures using an acidic CuSO ₄ bath with CCD reduction including all feasible acid concentrations ranging from about 10 g / l to about 300 g / l Therefore, the large reduction of CCD caused by the hydrogen-containing gas annealing process is extremely important because it allows the Cu thin film to be deposited.

In one example, on an annealed 80 ＡＬ ALDRu using a plating solution containing a sulfuric acid concentration of 100 g / l and a plating current density (PCD) of 3 mA / cm ² (equal to CCD, PCD / CCD = 1). SEM images taken of the 1000 銅 copper film deposited on the substrate showed that a continuous copper film was deposited without voids between the copper / Ru interface. The absence of voids between the copper / Ru interface indicates excellent copper (Cu) and Ru interface consistency and excellent Cu adhesion on the annealed Ru surface. Further, as a second embodiment, an annealing process of 80 mm ALDRu using a plating solution containing a sulfuric acid concentration of 100 g / l and a plating current density of 4.5 mA / cm ² (or PCD / CCD = 1.5) was performed. A photographed SEM image of the 1000 薄膜 copper film deposited above showed that a continuous copper film was deposited without voids between the copper / Ru. Similarly, a plating current density of 7.5 mA / cm ² (or PCD / CCD = 2.5) realized a continuous copper film without voids between copper / Ru. These results indicate that the gas annealing pretreatment reduces plating current density and improves Ru / Cu interface adhesion and consistency.

  The copper / Ru interface exhibits excellent void-free consistency even when PCD / CCD is equal to 1 when Cu is deposited on a Ru surface annealed with forming gas. In contrast, when plated with a CCD (or PCD / CCD = 1), the interface between the copper and the unannealed Ru surface generates interface voids as described above. A clean Ru surface shows better copper nucleation and deposition, thus improving interfacial consistency.

  Another benefit of pretreating a Group VIII metal surface with a hydrogen-containing gas annealing treatment is improved adhesion between copper and the Group VIII metal. Experimental results showed that the adhesion was better between Cu and pretreated soil free oxygen free Ru surface as much as possible due to excellent copper / Ru interface consistency (no voids). . The excellent interfacial consistency between the Cu and Ru layers can be an important aspect in forming a reliable semiconductor device. Clearly, having a pre-treated Ru surface is critical to achieving high quality Cu deposition on the Ru thin film.

Another aspect of Cu plating on Ru surfaces annealed with forming gas is a complete substrate surface coating with a Cu film to be plated due to the improved hydrophobicity described above. The step coverage of copper plating on the substrate feature should be improved because the annealed Ru surface is more hydrophobic and allows the plating solution to be drawn deeper into the feature. FIG. 4 shows an excellent gap-fill SEM of copper plated on an annealed Ru surface in a 0.14 μm × 0.8 μm trench. The actual deposited (as deposited) Ru is 80ｕ ALDRu. The pretreatment is a forming gas annealing treatment at 300 ° C. for 3 minutes. The copper plating current is 10 mA / cm ² for the first 100 Å and 5 mA / cm ² for the remaining 1900 Å.

  The annealing process can be performed in an integrated annealing chamber, such as annealing chamber 535 of FIG. 5, or in a separate annealing system. The annealing process can be performed in either one of a single wafer chamber or a batch furnace.

In addition to annealing with a hydrogen-containing gas, surface pretreatment of the Group VIII metal prior to direct copper plating can be performed by other methods. One example of another pretreatment method is cathodic treatment in a copper ion free acid solution. The surface RuO _x thin film can be reduced as an electrolytic cathode, and weakly bound organic surface contaminants can be discharged from the surface by cathodic polarization. One possible reduction reaction is represented by the following chemical formula (2). Cathodic processing can be performed in an integrated cell similar to a copper plating cell, as described below in connection with FIG. 6, or in a processing cell that is separate from the copper plating system. The cathode treatment cell requires an anode, a cathode and a copper ion free acid bath. The acidic concentration range should be in the range between about 10 g / l and about 100 g / l, preferably in the range between about 10 g / l and about 50 g / l. The preferred acid is H ₂ SO ₄ , but other types of acidic solutions can be used as well, such as organic sulfonic acid solutions (eg, methyl sulfonic acid). In order to prevent copper deposition, an inferior nucleated copper island on Ru during cathodic treatment, it is necessary that the acid bath be free from copper.

Cathodic treatment can be realized through voltage control or current control. With voltage control means, in addition to the working electrode and anode, which are thin, actually deposited (as-deposited) Ru films on the wafer surface, a reference electrode is required to monitor the voltage of the water . A preferred reference electrode is a thin copper wire located near the substrate surface. The voltage control can be realized through a voltage control device (potentiostat). The controlled Ru electrode voltage for the copper reference electrode is in the range of about 0 volts to about -0.5 volts. In addition to the reduction of RuO _x to Ru, H ₂ generation can occur on the Ru thin film surface. Using current control means, the cathode current is passed between the substrate with the actual deposited (as deposited) Ru and the anode. Current density should be in the range of about 0.05 mA / cm ² ~ about 1 mA / cm ^2. The processing time should be in the range of about 2 seconds to 30 minutes. However, due to throughput concerns, processing is preferably less than 5 minutes.

  Experimental results and discussions related to Ru are only used as examples. The inventive concept is applicable to other Group VIII metals such as rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum (Pt).

  Copper plating can be performed in a cell on an Electra CuECP ™ system or a slim cell copper plating system, both available from Applied Materials, Inc., Santa Clara, California. FIG. 5 shows a top view of the slim cell copper plating system 500. The ECP system 500 includes a factory interface (FI) 530 generally referred to as a substrate stacking unit. The factory interface 530 includes a plurality of substrate stacking units arranged so as to be in contact with the substrate-containing cassette 534. The robot 532 is located within the factory interface 530 and is arranged to access the substrates contained in the cassette 534. In addition, the robot 532 extends into a link tunnel 515 that connects the factory interface 530 with the processing mainframe or platform 513. The position of the robot 532 allows the robot to access the substrate cassette 534 to take out the substrate and transport the substrate to one of the processing cells 514, 516 located on the main frame 513, or to the annealing unit 535. To do. Similarly, the robot 532 can be used to remove a substrate from the processing cells 514, 516 or the annealing chamber 535 after the substrate processing sequence is complete. In this situation, the robot 532 may transfer the substrate to one of the cassettes 534 for removal from the system 500.

  The annealing section 535 further described herein generally includes two position annealing chambers, with a cooling plate / position 536 and a heating plate / position 537 adjacent to them, eg, between the two sections. It is disposed adjacent to the substrate transfer robot 540 to be disposed. The robot 540 is generally arranged to move the substrate between each heating plate 537 and cooling plate 536. Further, although the annealing chamber 535 is shown as being located for access from the link tunnel 515, embodiments of the invention are not limited to any particular form or location. In one embodiment, the annealing treatment unit 535 is disposed in direct communication with the main frame 513, that is, can be accessed by the main frame robot 520. For example, as shown in FIG. 5, the annealing unit 535 can be disposed in direct communication with the link tunnel 515 that allows access to the main frame 513, and the annealing chamber 535 is connected to the main frame 513. Shown as communicating. Details of a suitable annealing chamber are described in commonly assigned US patent application Ser. No. 60 / 463,860, filed Apr. 18, 2003 and entitled “Two-position annealing chamber”.

  In one embodiment, the annealing process is performed in an integrated annealing chamber, as shown as annealing chamber 535 in FIG. In other embodiments, the annealing process is performed in a separate annealing system. In other embodiments, the annealing process is performed in a single wafer chamber or batch furnace.

  In addition, as described above, the ECP system 500 includes the processing main frame 513 having the substrate transfer robot 520 disposed at the center on the ECP system 500. The robot 520 generally includes one or more arms / blades 522, 524 arranged to support and transport a substrate thereon. In addition, the robot 520 and associated blades 522, 524 generally provide the robot 520 to and from a plurality of processing units 502, 504, 506, 508, 510, 512, 514, 516 located on the main frame 513. It is arranged to extend, rotate and move vertically so that the substrate can be inserted and removed. Similarly, the factory interface robot 532 can rotate, extend and vertically move the substrate support blade, while allowing linear movement along the robot track extending from the factory interface 530 to the main frame 513. In general, the processing units 502, 504, 506, 508, 510, 512, 514, 516 can be any number of processing cells used in an electrochemical plating platform. In particular, the processing unit includes an electrochemical plating cell, a rinse cell, a bevel cleaning cell, a spin rinse drying cell, a substrate surface cleaning cell (including cleaning, rinsing, and etching cells), an electroless plating cell, a shape inspection unit, and / or Alternatively, it may be arranged as another processing cell that can be beneficially used in conjunction with a plating platform. Each processing cell and each robot typically receives inputs from both users and / or various sensors located in the system 500, and is a microprocessor-based control arranged to appropriately control the operation of the system 500 according to the inputs. It communicates with a processing controller 511 which can be a system.

  FIG. 6 shows a partial perspective and cross-sectional view of an exemplary plating cell 600 that may be implemented within the processing portions 502, 504, 506, 508, 510, 512, 514, 516 of FIG. Electrochemical plating cell 600 generally includes an outer container 601 and an inner container 602 located within outer container 601. Inner vessel 602 is typically positioned to contain a plating solution used to plate a metal, eg, copper, on a substrate during an electrochemical plating process. During the plating process, the plating solution is generally continuously fed into the inner vessel 602 (eg, about 1 gallon per minute for a 10 liter plating cell), so that the plating solution is continuously fed to the inner vessel 602. The upper point (generally referred to as “weir”) flows out and is collected in an outer vessel 601 and discharged therefrom for chemical processing and recirculation. The plating cell 600 is generally located at an angle of inclination, i.e., the frame portion 603 of the plating cell 600 generally has a component of the plating cell 600 between about 3 ° and about 30 °, or generally about 4 ° to about 4 ° for optimal results. Raised on one side to tilt between about 10 °. The frame member 603 of the plating cell 600 supports the annular base member on the upper portion thereof. As the frame member 603 is raised on one side, the upper surface of the base member 604 is generally inclined from the horizontal at an angle corresponding to the angle of the frame member 603 relative to the horizontal position. Base member 604 includes an annular or disk-shaped recess formed in a central portion thereof, and the annular recess is arranged to receive a disk-shaped anode member 605. Base member 604 further includes a plurality of fluid inlet / drains 609 extending from its lower surface. Each of the fluid inlet / drains 609 is generally arranged to supply and discharge fluid individually to or from either the anode or cathode portion of the plating cell 600. The anode member 605 generally includes a plurality of long grooves 607 formed therethrough, where the long grooves 607 are generally positioned parallel to each other across the surface of the anode 605. The parallel orientation allows the dense fluid generated at the anode surface to flow down the anode surface and into one of the long grooves 607. The plating cell 600 further includes a membrane support assembly 606. Membrane support assembly 606 is generally secured to base member 604 at its outer periphery and includes an interior region disposed to allow fluid to pass therethrough. Membrane 608 extends across support 606 and acts to fluidly separate the cathode and anode chambers of the plating cell. The membrane support assembly can include an O-ring type seal located near the periphery of the membrane, where the fluid passes from one side of the membrane secured on the membrane support 606 to the other side of the membrane. Arranged to prevent it from doing. A diffuser plate 610, typically a porous ceramic disk member, arranged to generate a substantially laminar flow or fluid flow in the direction of the substrate to be plated, is between the membrane 608 and the substrate to be plated. Located in the cell. A representative plating cell is named “Electrochemical Processing Cell” on October 9, 2002, claiming priority from US Provisional Application No. 60 / 398,345, filed July 24, 2002. It is further shown in filed and commonly assigned US patent application Ser. No. 10 / 268,284, both of which are hereby incorporated by reference in their entirety.

  While several preferred embodiments incorporating the subject matter of the present invention have been shown and described in detail, those skilled in the art can readily devise many different embodiments that further incorporate these subject matter.

The disclosure of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
~ It is typical sectional drawing of an integrated circuit manufacturing sequence. It is a figure which shows the critical current density as a function of sulfuric acid concentration. It is a figure which shows the process flow which pre-processes the board | substrate surface before copper plating. FIG. 4 is a diagram showing critical current density for an actually deposited and annealed Ru substrate as a function of sulfuric acid concentration. FIG. 6 shows an SEM of copper plated on an annealed Ru surface of 0.14 μm × 0.8 μm trench. 1 is a top view of one embodiment of an electrochemical plating system. FIG. It is a figure which shows typical embodiment of the plating cell used for the electrochemical plating cell of this invention.

  For ease of understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the drawings. The drawings are not dimensioned.

Claims (20)

A method of directly plating copper on a substrate comprising a Group VIII metal layer on the substrate surface,
Removing the Group VIII metal surface oxide layer and / or organic surface contaminants on the substrate surface;
Pretreat the substrate to reduce the critical current density during plating,
Plating a continuous and void-free copper layer on a substrate surface pretreated in an acid plating bath at a plating current density equal to or greater than a critical current density.   The method of claim 1, wherein the Group VIII metal is selected from the group of ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) and platinum (Pt).   The method of claim 1, wherein the thickness of the Group VIII metal is less than about 1000 mm.   The method of claim 1, wherein the copper plating is performed within 4 hours after the pretreatment.   The method of claim 1, wherein the critical current density decreases with increasing acidity of the plating bath.   The method of claim 1, wherein the acidity in the acid plating bath is generated from sulfuric acid at a concentration between about 10 g / l and about 300 g / l. The method of claim 1, wherein the critical current density is less than 10 mA / cm ² .   The method of claim 1, wherein the pretreatment of the substrate is performed by annealing the substrate in an environment with a hydrogen-containing gas and / or a gas that does not react with the Group VIII metal.   The method of claim 8, wherein the gas flow rate is between about 1 sccm and about 20 sim.   The method of claim 8, wherein annealing occurs at a temperature between about 100C and 400C.   The method of claim 8, wherein the annealing occurs at a pressure between about 5 mTorr and about 1500 Torr.   The method of claim 8, wherein the annealing has a time of about 2 seconds to about 5 hours.   The method of claim 1, wherein the substrate is pretreated for less than about 1 hour.   The method of claim 1, wherein the pretreatment is performed in an integrated single wafer anneal chamber.   The method according to claim 1, wherein the pretreatment of the substrate is performed by a cathode treatment in an acid-containing tank.   16. The method of claim 15, wherein the acid containing tank has an acid concentration of about 10 g / l to about 100 g / l. Cathodic treatment is from about 0 volts to about -0.5 volts the voltage range of, or about 0.05 mA / cm ² to about 16. The method of claim 15, wherein the executed at a current density in the range of 1 mA / cm ^2.   The method according to claim 15, wherein the acid-containing tank contains sulfuric acid.   17. The method of claim 16, wherein the acid concentration ranges from 10 g / l to about 50 g / l.   The method of claim 1 wherein the initial plating current for plating copper on the pretreated Group VIII metal surface is at least equal to the critical current density.

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