US20060219566A1 - Method for fabricating metal layer - Google Patents

Method for fabricating metal layer Download PDF

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Publication number
US20060219566A1
US20060219566A1 US11/092,594 US9259405A US2006219566A1 US 20060219566 A1 US20060219566 A1 US 20060219566A1 US 9259405 A US9259405 A US 9259405A US 2006219566 A1 US2006219566 A1 US 2006219566A1
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Prior art keywords
substrate
layer
wafer
deposition
metal
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US11/092,594
Inventor
Hsi-Kuei Cheng
Hsien-Ping Feng
Ming-Yuan Cheng
Jung-Chih Tsao
Shih-Chi Lin
Ray Chuang
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US11/092,594 priority Critical patent/US20060219566A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHUANG, RAY, CHENG, HSI-KUEI, CHENG, MING-YUAN, FENG, HSIEN-PING, LIN, SHIH-CHI, TSAO, JUNG-CHIH
Priority to TW094142339A priority patent/TWI281211B/en
Publication of US20060219566A1 publication Critical patent/US20060219566A1/en
Abandoned legal-status Critical Current

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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00Processes for servicing or operating cells for electrolytic coating
    • C25D21/10Agitating of electrolytes; Moving of racks
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/04Electroplating with moving electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Definitions

  • the present invention relates to a method and apparatus for fabricating a metal layer on a substrate, and more particularly, to a method for fabricating a metal layer on a substrate using electrochemical deposition (ECD).
  • ECD electrochemical deposition
  • Conductive interconnections on integrated circuits typically take the form of trenches and vias in the background art.
  • the trenches and vias are typically formed by a damascene or dual damascene process.
  • Copper is currently used in ultra large scale integration (ULSI) metallization as a replacement for aluminum due to its lower resistivity and better electromigration resistance.
  • Electrochemical copper deposition (ECD) has been adopted as the standard damascene or dual damascene process because of larger grain size (good electromigration) and higher deposition rates. More particularly, electroplating is well suited for the formation of small embedded damascene feature metallization due to its ability to readily control growth of the electroplated film for bottom-up filling, and the superior electrical conductivity characteristics of the electroplated film.
  • FIGS. 1A-1D illustrate a typical metallization technique for forming interconnect features in a multi-layered substrate of the background art.
  • the method includes physical vapor deposition of a barrier layer over the feature surfaces, physical vapor deposition of a conductive metal seed layer, preferably copper, over the barrier layer, and electroplating of a conductive metal, preferably copper, over the seed layer to fill the interconnect structure/features.
  • the deposited layers and the dielectric layers are then planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
  • CMP chemical mechanical polishing
  • a semiconductor substrate 10 is provided.
  • a copper metal interconnect 20 is shown patterned within an insulating layer 25 , i.e., silicon oxide.
  • a dielectric layer 30 is deposited and patterned with a via portion 32 and a trench portion 34 .
  • the dual damascene structure is thus formed including a via portion 32 and a trench portion 34 .
  • FIGS. 1A-1D other types of interconnect features are also typically metallized using this technique.
  • a barrier layer 42 preferably including tantalum (Ta) or tantalum nitride (TaN), is deposited over the surface of the dielectric 30 , including the surfaces of the via portion 32 and the trench portion 34 .
  • the barrier layer limits the diffusion of copper into the semiconductor substrate and the dielectric layer, thereby dramatically increasing reliability of the copper interconnect features.
  • a copper seed layer 44 is deposited over the barrier layer 34 using physical vapor deposition (PVD). The copper seed layer 44 provides good adhesion for a subsequently electroplated copper layer.
  • a copper layer 50 is electroplated over the copper seed layer 44 to metallize the dual damascene structure.
  • the electroplating metallization process presently practiced may yield voids 52 and 54 , some of which can even reach the barrier/seed layer, possibly leading to defective or prematurely exhausted devices.
  • the top portion of the processed substrate i.e., the exposed electroplated copper layer 50 (shown in FIG. 1C ) is then planarized, preferably by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • portions of the copper layer 50 , copper seed layer 44 , barrier layer 42 , and a top surface of the dielectric layer 30 are removed from the top surface of the substrate, leaving a fully planar surface with conductive interconnect features, such as the dual damascene structure.
  • One challenge facing damascene and dual damascene processing is the formation of defects, such as pits, voids and swirling defects.
  • defects such as pits, voids and swirling defects.
  • a number of obstacles impair defect-free electrochemical deposition of copper onto substrates having submicron, high aspect features. Therefore, it is important that the electroplating surface is uniform and reliable to ensure defect-free deposition.
  • the present invention overcomes the shortcomings associated with the background art and achieves other advantages not realized by the background art.
  • An object of the present invention is to provide a defect-free metal layer utilizing electrochemical deposition (ECD).
  • ECD electrochemical deposition
  • Another object of the present invention is to provide a method of inhibiting entrapment of air bubbles on an electroplating surface during electroplating.
  • a method for electrochemical deposition comprising: providing a substrate; and electrochemically depositing metal onto the substrate in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition of metal onto the substrate.
  • a method for electrochemical deposition comprising providing a substrate; depositing a TaN barrier layer and a copper seed layer on one or more surfaces of the substrate; and electrochemically depositing copper onto the substrate in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition.
  • a method for fabricating integrated circuit devices on a semiconductor substrate with damascene structures using electrochemical deposition comprising providing a semiconductor substrate having an insulating layer on the substrate; providing a level of copper metal interconnecting wiring patterned within the insulating layer; providing a dielectric layer having a trench opening and a via opening to the copper metal interconnecting wiring; depositing a barrier layer and a copper seed layer over the dielectric layer covering and lining the trench and via openings; and electrochemically depositing a copper to fill the trench and via openings in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition.
  • a defect-free, metal layer electrochemically deposited on a semiconductor wafer comprising a semiconductor wafer; and an electrochemically deposited metal layer on the semiconductor wafer, wherein a density of defects of the metal layer is less than 1 per mm 2 .
  • the tilt angle ⁇ of the substrate assembly is approximately 0.5 to 3 degrees.
  • the rotating speed of the substrate holder assembly is above 150 rpm.
  • the invention improves on conventional methods in that the electroplating surfaces of the structure with a barrier layer and a seed layer are tilted during the electroplating process.
  • tilting the substrate holder assembly during electroplating may slightly reduce the uniformity of the metal layer, however, pits and broken lines are eliminated by about 1-2 orders.
  • FIGS. 1A-1D are partial side views of a semiconductor substrate showing a typical metallization method in the background art for forming interconnect features
  • FIG. 2 is an upper plan view of the ECP system according to the present invention.
  • FIG. 3 is a schematic view of an electroplating apparatus according to the present invention.
  • FIGS. 4A-4D are cross sectional views of dual damascene interconnect lines during various stages of the fabrication process.
  • FIG. 2 is an upper plan view of the ECD system according to the present invention.
  • FIG. 3 is a schematic view of an electroplating apparatus according to the present invention.
  • FIGS. 4A-4D are cross sectional views of dual damascene interconnect lines during various stages of the fabrication process.
  • FIG. 2 is an upper plan view of the ECD system 300 .
  • the ECD system 300 generally includes a loadlock station 310 , a rapid thermal annealing (RTA) chamber 360 , spin-rinse-dry (SRD) and edge bevel removal (EBR) chambers 340 , a dual blade robot 380 , and one or more electrochemical plating process cells 320 .
  • An electrolyte solution system (not shown) is positioned adjacent the ECD system 300 and is individually connected to the process cells 320 to circulate electrolyte solution for the electroplating process.
  • the ECD system 300 also includes a controller having a programmable microprocessor.
  • FIG. 3 is a diagrammatical view of an electrochemical plating process apparatus 400 , with a wafer 402 mounted therein in accordance with one embodiment of the present invention.
  • Apparatus 400 includes a substrate holder assembly 403 mounted on a rotatable spindle 405 that allows rotation thereof.
  • a simplified electrochemical plating apparatus one of skill in the art will appreciate that other electrochemical plating apparatuses are equally suitable to achieve the desired processing results.
  • wafer 402 is mounted in the substrate holder assembly 403 , which is then placed in a plating bath 422 containing a plating solution.
  • the plating solution is continually applied by a pump 440 .
  • the plating solution flows upwards to the center of wafer (anode) 401 and then radially outward and across wafer 402 , as indicated by arrows 414 .
  • the plating solution then overflows from plating bath 422 to an overflow reservoir 420 as indicated by arrows 410 and 411 .
  • the plating solution is then filtered (not shown) and returned to pump 440 as indicated by arrow 412 , completing recirculation.
  • a DC power supply 450 has a negative output lead electrically connected to wafer 402 through one or more slip rings, brushes, and contacts (not shown).
  • the positive output lead of power supply 450 is electrically connected to an anode (wafer) 401 located in plating bath 422 .
  • power supply 450 biases wafer 402 to provide a negative potential relative to anode (wafer) 401 causing electrical current to flow from the anode (wafer) 401 to wafer 402 .
  • electrical current flows in the same direction as the net positive ion flux and opposite to the net electron flux. This causes an electrochemical reaction (e.g.
  • Cu 2+ +2e ⁇ Cu
  • the electrically conductive layer e.g. copper
  • the typical electroplating solution contains electrolyte, such as CuSO 4 , suppressor, and other additives.
  • the suppressor is a long chain polymer comprising polyether polymers, polyethylene glycol (PEG), or polyoxyethylene-polyoxypropylene copolymer (EO-PO).
  • the suppressor can slow the electroplating by forming a monolayer at the interface. The monolayer may induce and entrap air bubbles. However, some bubbles will be induced when the substrate holder assembly 403 enters the plating bath 422 , and cannot be removed by laminar bath flow. It is difficult to eliminate all micro-bubbles by increasing rotation speed or flow speed.
  • electrolyte solution cannot physically contact those portions of the seed layer on the substrate underlying formed air bubbles or bridges, and metal film cannot thus be deposited on the cover areas.
  • These bubbles can also limit the filling of the features on the substrate, leading to the creation of voids, or spaces, within features formed in the deposited metal film, and/or leading to unreliable, unpredictable, and unusable devices.
  • the present invention limits the number of air bubbles or bridges contacting the seed layer during processing by providing a uniform electric current density across the seed layer on the substrate during plating by tilting the substrate assembly during ECD or ECP.
  • the pumping through rate is increased by the tilting, and eliminates the formation of defects during ECD.
  • the tilting angle ⁇ of the substrate assembly is approximately 0.5 to 3°.
  • the rotating speed of the substrate holder assembly is approximately 150-600 rpm.
  • Tilting the substrate holder assembly during electroplating may, however, slightly reduce uniformity of the metal layer.
  • the uniformity of the metal layer is approximately between 1-4%.
  • the tilt angle of the substrate holder assembly is preferably less than 3°, but more preferably, 2° or less.
  • the number of defects in the metal layer is lower than about 50, and more specifically, the density of defects of the metal layer is lower than about 1 per mm 2 .
  • FIGS. 4A-4D are cross sectional views of dual damascene interconnect lines during various stages of the fabrication process.
  • FIGS. 4A-4D show a metallization technique forming interconnect features in a multi-layered substrate.
  • the method comprises physical vapor deposition of a barrier layer over the feature surfaces, and a conductive metal seed layer, preferably copper, over the barrier layer, followed by electroplating a conductive metal, preferably copper, over the seed layer to fill the interconnect structure/feature.
  • the deposited layers and the dielectric layers are planarized, e.g., by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
  • CMP chemical mechanical polishing
  • a semiconductor substrate 100 is provided.
  • a copper metal interconnect 120 is shown patterned within an insulating layer 125 , i.e., silicon oxide.
  • a dielectric layer 130 is deposited and patterned with a via portion 132 and a trench portion 134 .
  • the dual damascene structure is thus formed comprising a via portion 132 and a trench portion 134 .
  • a barrier layer 142 preferably comprising tantalum (Ta) or tantalum nitride (TaN), is deposited over the surface of the dielectric 130 , including the surfaces of the via portion 132 and the trench portion 134 .
  • the barrier layer 142 is typically deposited using physical vapor deposition (PVD) by sputtering or reactive PVD.
  • PVD physical vapor deposition
  • the barrier layer 142 limits the diffusion of copper into the semiconductor substrate and the dielectric layer, thereby dramatically increasing reliability.
  • the barrier layer is preferably deposited by low temperature ( ⁇ 350° C.) PVD and then annealed at between about 350° C.
  • a barrier layer has a film thickness between about 250 ⁇ and 500 ⁇ for an interconnect structure/feature having sub-micron opening width. It is preferred that the barrier layer has a thickness between about 500 ⁇ and about 3000 ⁇ .
  • a copper seed layer 144 is deposited over the barrier layer 34 using PVD. The copper seed layer 144 provides good adhesion for subsequently electroplated copper. It is preferred that the seed layer have a thickness between about 500 ⁇ and 300 ⁇ .
  • a copper layer 150 is electroplated over the copper seed layer 144 to metallize the dual damascene structure.
  • the substrate holder assembly is tilted during ECP process to reduce formation of bubbles, by increasing the pumping through rate during ECD.
  • the tilting angle ⁇ of the substrate assembly is approximately 0.5 to 3°.
  • the rotating speed of the substrate holder assembly is about 150-600 rpm. Tilting the substrate holder assembly during electroplating may, however, slightly reduce uniformity of the metal layer. Nevertheless, pits and broken lines are eliminated by about 1-2 orders.
  • the tilt angle of the substrate holder assembly is preferably less than 30, but more preferably, 2° or less.
  • the top portion of the processed substrate i.e., the exposed electroplated copper layer 150 (shown in FIG. 4C ) is then planarized, preferably by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • portions of the copper layer 150 , copper seed layer 144 , barrier layer 142 , and a top surface of the dielectric layer 130 are removed from the top surface of the substrate, leaving a fully planar surface with conductive interconnect features, such as a dual damascene structure.

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Abstract

A method for filling a structure using electrochemical deposition includes a barrier layer and a seed layer being deposited on one or more surfaces of the structure. Metal is electrochemically deposited to fill the structure in an electrochemical plating cell, wherein the electroplating surface of the substrate is tilted and rotated during electrochemical deposition.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a method and apparatus for fabricating a metal layer on a substrate, and more particularly, to a method for fabricating a metal layer on a substrate using electrochemical deposition (ECD).
  • 2. Description of the Related Art
  • Conductive interconnections on integrated circuits typically take the form of trenches and vias in the background art. In modern deep submicron integrated circuits, the trenches and vias are typically formed by a damascene or dual damascene process. Copper is currently used in ultra large scale integration (ULSI) metallization as a replacement for aluminum due to its lower resistivity and better electromigration resistance. Electrochemical copper deposition (ECD) has been adopted as the standard damascene or dual damascene process because of larger grain size (good electromigration) and higher deposition rates. More particularly, electroplating is well suited for the formation of small embedded damascene feature metallization due to its ability to readily control growth of the electroplated film for bottom-up filling, and the superior electrical conductivity characteristics of the electroplated film.
  • FIGS. 1A-1D illustrate a typical metallization technique for forming interconnect features in a multi-layered substrate of the background art. Generally, the method includes physical vapor deposition of a barrier layer over the feature surfaces, physical vapor deposition of a conductive metal seed layer, preferably copper, over the barrier layer, and electroplating of a conductive metal, preferably copper, over the seed layer to fill the interconnect structure/features. The deposited layers and the dielectric layers are then planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
  • In FIG. 1A, a semiconductor substrate 10 is provided. A copper metal interconnect 20 is shown patterned within an insulating layer 25, i.e., silicon oxide. In addition, a dielectric layer 30 is deposited and patterned with a via portion 32 and a trench portion 34. The dual damascene structure is thus formed including a via portion 32 and a trench portion 34. Although a dual damascene structure is illustrated in FIGS. 1A-1D, other types of interconnect features are also typically metallized using this technique.
  • In FIG. 1B, a barrier layer 42, preferably including tantalum (Ta) or tantalum nitride (TaN), is deposited over the surface of the dielectric 30, including the surfaces of the via portion 32 and the trench portion 34. The barrier layer limits the diffusion of copper into the semiconductor substrate and the dielectric layer, thereby dramatically increasing reliability of the copper interconnect features. A copper seed layer 44 is deposited over the barrier layer 34 using physical vapor deposition (PVD). The copper seed layer 44 provides good adhesion for a subsequently electroplated copper layer.
  • In FIG. 1C, a copper layer 50 is electroplated over the copper seed layer 44 to metallize the dual damascene structure. However, the electroplating metallization process presently practiced may yield voids 52 and 54, some of which can even reach the barrier/seed layer, possibly leading to defective or prematurely exhausted devices.
  • In FIG. 1D, the top portion of the processed substrate, i.e., the exposed electroplated copper layer 50 (shown in FIG. 1C), is then planarized, preferably by chemical mechanical polishing (CMP). During planarization, portions of the copper layer 50, copper seed layer 44, barrier layer 42, and a top surface of the dielectric layer 30 are removed from the top surface of the substrate, leaving a fully planar surface with conductive interconnect features, such as the dual damascene structure.
  • However, the present inventors have determined that there are problems relating to the quality of the deposited metal film. One challenge facing damascene and dual damascene processing is the formation of defects, such as pits, voids and swirling defects. A number of obstacles impair defect-free electrochemical deposition of copper onto substrates having submicron, high aspect features. Therefore, it is important that the electroplating surface is uniform and reliable to ensure defect-free deposition.
  • One of the difficulties inherent in immersion of the wafer in a plating solution is air bubbles occurring on the wafer surface. The air bubbles may disrupt the flow of electrolytes and electrical current to the wafer plating surface impacting the uniformity and the function of the deposited layer. A conventional method of reducing air bubble function immerses the wafer vertically into the plating solution. However, mounting the wafer vertically for immersion into the plating solution adds complexity and hinders automation of the electroplating process. Accordingly, it is desirable to have an apparatus for electroplating a wafer that avoids air bubble occurrence.
  • U.S. Pat. No. 6,582,578 to Dordi et. al., the entirety of which is hereby incorporated by reference, describes an electrochemical plating (ECP) system that limits the formation of air bubbles between the substrate and/or the substrate holder assembly during immersion of the substrate into the electrolyte solution. A substrate is immersed in the electrochemical plating system by tilting the substrate as it enters the solution to the trapping or formation of air bubbles between the substrate and the substrate holder assembly. However, in the aforementioned method, it is difficult to eliminate all micro-bubbles during ECD.
  • SUMMARY OF THE INVENTION
  • The present invention overcomes the shortcomings associated with the background art and achieves other advantages not realized by the background art.
  • An object of the present invention is to provide a defect-free metal layer utilizing electrochemical deposition (ECD).
  • Another object of the present invention is to provide a method of inhibiting entrapment of air bubbles on an electroplating surface during electroplating.
  • One or more of these and other objects are accomplished by a method for electrochemical deposition comprising: providing a substrate; and electrochemically depositing metal onto the substrate in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition of metal onto the substrate.
  • One or more of these and other objects are accomplished by a method for electrochemical deposition comprising providing a substrate; depositing a TaN barrier layer and a copper seed layer on one or more surfaces of the substrate; and electrochemically depositing copper onto the substrate in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition.
  • One or more of these and other objects are accomplished by a method for fabricating integrated circuit devices on a semiconductor substrate with damascene structures using electrochemical deposition comprising providing a semiconductor substrate having an insulating layer on the substrate; providing a level of copper metal interconnecting wiring patterned within the insulating layer; providing a dielectric layer having a trench opening and a via opening to the copper metal interconnecting wiring; depositing a barrier layer and a copper seed layer over the dielectric layer covering and lining the trench and via openings; and electrochemically depositing a copper to fill the trench and via openings in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition.
  • One or more of these and other objects are accomplished by a defect-free, metal layer electrochemically deposited on a semiconductor wafer comprising a semiconductor wafer; and an electrochemically deposited metal layer on the semiconductor wafer, wherein a density of defects of the metal layer is less than 1 per mm2.
  • The tilt angle θ of the substrate assembly is approximately 0.5 to 3 degrees. The rotating speed of the substrate holder assembly is above 150 rpm.
  • The invention improves on conventional methods in that the electroplating surfaces of the structure with a barrier layer and a seed layer are tilted during the electroplating process. In the method of forming a defect-free metal layer filling a structure utilizing electrochemical deposition (ECD), tilting the substrate holder assembly during electroplating may slightly reduce the uniformity of the metal layer, however, pits and broken lines are eliminated by about 1-2 orders.
  • Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will become more fully understood from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
  • FIGS. 1A-1D are partial side views of a semiconductor substrate showing a typical metallization method in the background art for forming interconnect features;
  • FIG. 2 is an upper plan view of the ECP system according to the present invention;
  • FIG. 3 is a schematic view of an electroplating apparatus according to the present invention; and
  • FIGS. 4A-4D are cross sectional views of dual damascene interconnect lines during various stages of the fabrication process.
  • DETAILED DESCRIPTION OF THE INVENTION
  • The present invention will hereinafter be described with reference to the accompanying drawings. FIG. 2 is an upper plan view of the ECD system according to the present invention. FIG. 3 is a schematic view of an electroplating apparatus according to the present invention. FIGS. 4A-4D are cross sectional views of dual damascene interconnect lines during various stages of the fabrication process.
  • The present invention, which provides a method of fabricating a metal layer using electrochemical deposition (ECD), is described in greater detail by referring to the drawings that accompany the present invention. It is noted that in the accompanying drawings, like and/or corresponding elements are referred to by like reference numerals.
  • FIG. 2 is an upper plan view of the ECD system 300. Referring to FIG. 2, the ECD system 300 generally includes a loadlock station 310, a rapid thermal annealing (RTA) chamber 360, spin-rinse-dry (SRD) and edge bevel removal (EBR) chambers 340, a dual blade robot 380, and one or more electrochemical plating process cells 320. An electrolyte solution system (not shown) is positioned adjacent the ECD system 300 and is individually connected to the process cells 320 to circulate electrolyte solution for the electroplating process. The ECD system 300 also includes a controller having a programmable microprocessor.
  • FIG. 3 is a diagrammatical view of an electrochemical plating process apparatus 400, with a wafer 402 mounted therein in accordance with one embodiment of the present invention. Apparatus 400 includes a substrate holder assembly 403 mounted on a rotatable spindle 405 that allows rotation thereof. Although the invention is described using a simplified electrochemical plating apparatus, one of skill in the art will appreciate that other electrochemical plating apparatuses are equally suitable to achieve the desired processing results.
  • During the electrochemical plating cycle, wafer 402 is mounted in the substrate holder assembly 403, which is then placed in a plating bath 422 containing a plating solution. As indicated by arrow 413, the plating solution is continually applied by a pump 440. Generally, the plating solution flows upwards to the center of wafer (anode) 401 and then radially outward and across wafer 402, as indicated by arrows 414. The plating solution then overflows from plating bath 422 to an overflow reservoir 420 as indicated by arrows 410 and 411. The plating solution is then filtered (not shown) and returned to pump 440 as indicated by arrow 412, completing recirculation.
  • A DC power supply 450 has a negative output lead electrically connected to wafer 402 through one or more slip rings, brushes, and contacts (not shown). The positive output lead of power supply 450 is electrically connected to an anode (wafer) 401 located in plating bath 422. During use, power supply 450 biases wafer 402 to provide a negative potential relative to anode (wafer) 401 causing electrical current to flow from the anode (wafer) 401 to wafer 402. In the following description, electrical current flows in the same direction as the net positive ion flux and opposite to the net electron flux. This causes an electrochemical reaction (e.g. Cu2++2e=Cu) on wafer 402 which results in deposition of the electrically conductive layer (e.g. copper) on wafer 401. The ion concentration of the plating solution is replenished during the plating cycle, e.g., by dissolution of a metallic anode (e.g. Cu=Cu2++2e).
  • The typical electroplating solution contains electrolyte, such as CuSO4, suppressor, and other additives. The suppressor is a long chain polymer comprising polyether polymers, polyethylene glycol (PEG), or polyoxyethylene-polyoxypropylene copolymer (EO-PO). The suppressor can slow the electroplating by forming a monolayer at the interface. The monolayer may induce and entrap air bubbles. However, some bubbles will be induced when the substrate holder assembly 403 enters the plating bath 422, and cannot be removed by laminar bath flow. It is difficult to eliminate all micro-bubbles by increasing rotation speed or flow speed.
  • Air bubbles or bridges trapped in the electrolyte solution contact the surface of the substrate during plating. However, electrolyte solution cannot physically contact those portions of the seed layer on the substrate underlying formed air bubbles or bridges, and metal film cannot thus be deposited on the cover areas. These bubbles can also limit the filling of the features on the substrate, leading to the creation of voids, or spaces, within features formed in the deposited metal film, and/or leading to unreliable, unpredictable, and unusable devices.
  • The present invention limits the number of air bubbles or bridges contacting the seed layer during processing by providing a uniform electric current density across the seed layer on the substrate during plating by tilting the substrate assembly during ECD or ECP. The pumping through rate is increased by the tilting, and eliminates the formation of defects during ECD. In a preferred embodiment of the present invention, the tilting angle θ of the substrate assembly is approximately 0.5 to 3°. The rotating speed of the substrate holder assembly is approximately 150-600 rpm. By increasing the tilt angle θ, any gas bubbles entrapped on electroplating surface are quickly dislodged. Tilting the substrate holder assembly during electroplating may, however, slightly reduce uniformity of the metal layer. The uniformity of the metal layer is approximately between 1-4%. Nevertheless, pits and broken lines are eliminated by about 1-2 orders. The tilt angle of the substrate holder assembly is preferably less than 3°, but more preferably, 2° or less. The number of defects in the metal layer is lower than about 50, and more specifically, the density of defects of the metal layer is lower than about 1 per mm2.
  • FIGS. 4A-4D are cross sectional views of dual damascene interconnect lines during various stages of the fabrication process. FIGS. 4A-4D show a metallization technique forming interconnect features in a multi-layered substrate. Generally, the method comprises physical vapor deposition of a barrier layer over the feature surfaces, and a conductive metal seed layer, preferably copper, over the barrier layer, followed by electroplating a conductive metal, preferably copper, over the seed layer to fill the interconnect structure/feature. Finally, the deposited layers and the dielectric layers are planarized, e.g., by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
  • Referring to FIG. 4A, a semiconductor substrate 100 is provided. A copper metal interconnect 120 is shown patterned within an insulating layer 125, i.e., silicon oxide. In addition, a dielectric layer 130 is deposited and patterned with a via portion 132 and a trench portion 134. The dual damascene structure is thus formed comprising a via portion 132 and a trench portion 134.
  • Referring to FIG. 4B, a barrier layer 142, preferably comprising tantalum (Ta) or tantalum nitride (TaN), is deposited over the surface of the dielectric 130, including the surfaces of the via portion 132 and the trench portion 134. The barrier layer 142 is typically deposited using physical vapor deposition (PVD) by sputtering or reactive PVD. The barrier layer 142 limits the diffusion of copper into the semiconductor substrate and the dielectric layer, thereby dramatically increasing reliability. For a high conductance barrier layer comprising tantalum, the barrier layer is preferably deposited by low temperature (<350° C.) PVD and then annealed at between about 350° C. and 600° C., or deposited by PVD at between about 350° C. and 600° C. Preferably, a barrier layer has a film thickness between about 250 Å and 500 Å for an interconnect structure/feature having sub-micron opening width. It is preferred that the barrier layer has a thickness between about 500 Å and about 3000 Å. A copper seed layer 144 is deposited over the barrier layer 34 using PVD. The copper seed layer 144 provides good adhesion for subsequently electroplated copper. It is preferred that the seed layer have a thickness between about 500 Å and 300 Å.
  • Referring to FIG. 4C, a copper layer 150 is electroplated over the copper seed layer 144 to metallize the dual damascene structure. The substrate holder assembly is tilted during ECP process to reduce formation of bubbles, by increasing the pumping through rate during ECD. In a preferred embodiment of the present invention, the tilting angle θ of the substrate assembly is approximately 0.5 to 3°. The rotating speed of the substrate holder assembly is about 150-600 rpm. Tilting the substrate holder assembly during electroplating may, however, slightly reduce uniformity of the metal layer. Nevertheless, pits and broken lines are eliminated by about 1-2 orders. The tilt angle of the substrate holder assembly is preferably less than 30, but more preferably, 2° or less.
  • Referring to FIG. 4D, the top portion of the processed substrate, i.e., the exposed electroplated copper layer 150 (shown in FIG. 4C), is then planarized, preferably by chemical mechanical polishing (CMP). During planarization, portions of the copper layer 150, copper seed layer 144, barrier layer 142, and a top surface of the dielectric layer 130 are removed from the top surface of the substrate, leaving a fully planar surface with conductive interconnect features, such as a dual damascene structure.
  • The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims (19)

1. A method for electrochemical deposition comprising:
providing a substrate; and
electrochemically depositing metal onto the substrate in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition of metal onto the substrate.
2. The method according to claim 1, further comprising depositing a barrier layer and a seed layer on the substrate.
3. The method according to claim 2, wherein deposition of the barrier layer is accomplished by sputtering Ta, TaN, TiN or a ternary compound.
4. The method according to claim 2, wherein deposition of the seed layer is accomplished by electrochemical deposition (ECD) of Cu or chemical vapor deposition (CVD) of Cu.
5. The method according to claim 1, wherein the metal is Cu.
6. The method according to claim 1, wherein a tilt angle of the electroplating surface is between 0.5 to 3 degrees.
7. The method according to claim 1, wherein a rotating speed of the electroplating surface is 150-600 rpm.
8. A method for fabricating integrated circuit devices on a semiconductor substrate with damascene structures using electrochemical deposition comprising:
providing a semiconductor substrate having an insulating layer on the substrate;
providing a level of copper metal interconnecting wiring patterned within the insulating layer;
providing a dielectric layer having a trench opening and a via opening to the copper metal interconnecting wiring;
depositing a barrier layer and a copper seed layer over the dielectric layer covering and lining the trench and via openings; and
electrochemically depositing a copper to fill the trench and via openings in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition.
9. The method according to claim 8, wherein deposition of the barrier layer is accomplished by sputtering Ta, TaN, TiN or a ternary compound.
10. The method according to claim 8, wherein deposition of the copper seed layer is accomplished by electrochemical deposition of Cu or chemical vapor deposition of Cu.
11. The method according to claim 8, wherein a tilt angle of the electroplating surface is between 0 to 3 degrees.
12. The method according to claim 8, wherein a rotating speed of the electroplating surface is 150-600 rpm.
13. A defect-free, metal layer electrochemically deposited on a semiconductor wafer comprising:
a semiconductor wafer; and
an electrochemically deposited metal layer on the semiconductor wafer, wherein a density of defects of the metal layer is less than 1 per mm2.
14. The wafer according to claim 13, wherein the semiconductor substrate is a monocrystalline silicon wafer.
15. The wafer according to claim 13, wherein the semiconductor substrate comprises a barrier and a seed layer on the semiconductor substrate.
16. The wafer according to claim 13, wherein the metal layer deposited onto the substrate is Cu.
17. The wafer according to claim 13, wherein the wafer is manufactured by providing a substrate; and electrochemically depositing metal onto the substrate in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition of metal onto the substrate.
18. The wafer according to claim 13, wherein a number of defects of the metal layer is less than 50.
19. The wafer according to claim 13, wherein the uniformity of the metal layer is approximately between 1-4%.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11655554B2 (en) * 2019-10-09 2023-05-23 Dongguan Hualuo Electronics Co., Ltd. Method for preparing electrode of inductive component

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI383071B (en) * 2008-10-30 2013-01-21 All Ring Tech Co Ltd Electroplating apparatus for chips
TWI410531B (en) * 2010-05-07 2013-10-01 Taiwan Semiconductor Mfg Vertical plating equipment and plating method thereof
CN112853441B (en) * 2021-01-08 2022-04-08 上海戴丰科技有限公司 Wafer horizontal electroplating device and cathode electroplating solution jet flow method

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2446476A (en) * 1944-12-09 1948-08-03 William C Huebner Apparatus for coating cylindrical surfaces
US2491925A (en) * 1944-09-16 1949-12-20 Lazaro Anton Apparatus for electroplating
US6258220B1 (en) * 1998-11-30 2001-07-10 Applied Materials, Inc. Electro-chemical deposition system
US6391166B1 (en) * 1998-02-12 2002-05-21 Acm Research, Inc. Plating apparatus and method
US6399479B1 (en) * 1999-08-30 2002-06-04 Applied Materials, Inc. Processes to improve electroplating fill
US6402923B1 (en) * 2000-03-27 2002-06-11 Novellus Systems Inc Method and apparatus for uniform electroplating of integrated circuits using a variable field shaping element
US6551487B1 (en) * 2001-05-31 2003-04-22 Novellus Systems, Inc. Methods and apparatus for controlled-angle wafer immersion
US6582578B1 (en) * 1999-04-08 2003-06-24 Applied Materials, Inc. Method and associated apparatus for tilting a substrate upon entry for metal deposition
US6610189B2 (en) * 2001-01-03 2003-08-26 Applied Materials, Inc. Method and associated apparatus to mechanically enhance the deposition of a metal film within a feature
US20050164499A1 (en) * 2002-09-27 2005-07-28 Tokyo Electron Limited Electroless plating method and apparatus
US20050196523A1 (en) * 2002-10-07 2005-09-08 Tokyo Electron Limited Electroless plating method and apparatus, and computer storage medium storing program for controlling same
US20060037858A1 (en) * 2002-09-19 2006-02-23 Tokyo Electron Limited Electroless plating apparatus and electroless plating method
US20070153062A1 (en) * 2005-12-30 2007-07-05 Shie Jin S Monolithic fabrication method and structure of array nozzles on thermal inkjet print head

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2491925A (en) * 1944-09-16 1949-12-20 Lazaro Anton Apparatus for electroplating
US2446476A (en) * 1944-12-09 1948-08-03 William C Huebner Apparatus for coating cylindrical surfaces
US6391166B1 (en) * 1998-02-12 2002-05-21 Acm Research, Inc. Plating apparatus and method
US6258220B1 (en) * 1998-11-30 2001-07-10 Applied Materials, Inc. Electro-chemical deposition system
US6582578B1 (en) * 1999-04-08 2003-06-24 Applied Materials, Inc. Method and associated apparatus for tilting a substrate upon entry for metal deposition
US6399479B1 (en) * 1999-08-30 2002-06-04 Applied Materials, Inc. Processes to improve electroplating fill
US6402923B1 (en) * 2000-03-27 2002-06-11 Novellus Systems Inc Method and apparatus for uniform electroplating of integrated circuits using a variable field shaping element
US6610189B2 (en) * 2001-01-03 2003-08-26 Applied Materials, Inc. Method and associated apparatus to mechanically enhance the deposition of a metal film within a feature
US6551487B1 (en) * 2001-05-31 2003-04-22 Novellus Systems, Inc. Methods and apparatus for controlled-angle wafer immersion
US7097410B1 (en) * 2001-05-31 2006-08-29 Novellus Systems, Inc. Methods and apparatus for controlled-angle wafer positioning
US20060037858A1 (en) * 2002-09-19 2006-02-23 Tokyo Electron Limited Electroless plating apparatus and electroless plating method
US20050164499A1 (en) * 2002-09-27 2005-07-28 Tokyo Electron Limited Electroless plating method and apparatus
US20050196523A1 (en) * 2002-10-07 2005-09-08 Tokyo Electron Limited Electroless plating method and apparatus, and computer storage medium storing program for controlling same
US20070153062A1 (en) * 2005-12-30 2007-07-05 Shie Jin S Monolithic fabrication method and structure of array nozzles on thermal inkjet print head

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11655554B2 (en) * 2019-10-09 2023-05-23 Dongguan Hualuo Electronics Co., Ltd. Method for preparing electrode of inductive component

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