TWI281211B - Methods for electrochemical deposition (ECD) and for fabrication integrated circuit devices on a semiconductor substrate with damascene structures and defect-free ECD metal layer on the semiconductor wafer - Google Patents

Abstract

A method for filling a structure using electrochemical deposition includes a barrier layer and a seed layer being deposited on one or more surfaces of the structure. Metal is electrochemically deposited to fill the structure in an electrochemical plating cell, wherein the electroplating surface of the substrate is tilled and rotated during electrochemical deposition.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for forming an integrated circuit component, and more particularly to a method and apparatus for chemically plating a metal plating layer on a semiconductor substrate. [Prior Art] The interconnections in the conventional integrated circuit are presented in the form of a trench and a via hole. Especially in deep sub-micron integrated circuit technology, interconnect trenches and vias are formed using damascene or duai damascene processes. Gradually, copper wires have replaced the Ming wire as the mainstream of today's ultra-large integrated circuit (ULSI) metallization process (metamzati〇n). With the evolution of integrated circuit process technology, electroplated deposition (ECD) metal copper has become a standard step in the inlay or dual damascene process because of its larger particles (ie, better electrons) Migration impedance), lower resistivity and higher deposition rate. In particular, the 'electricity ship's mixed work is combined with a small-sized metallization, which is due to its superior coating growth rate control capability and superior conductive properties of the coating. / 1A-1D shows a conventional metallization process by means of an electroless plating process to form an interconnect structure on a substrate having a multilayer structure. In general, the above metallization process method includes physical vapor deposition (4) sical vap〇r curry addition, forming a layer of transition, and forming a seed layer on the bottom of the soil by physical vapor deposition on the barrier layer. Upper, and electroplated conductive: genus: on the seed layer. The plating structure and the layer, the core structure (e.g., dielectric layer) are then planarized, e.g., by chemical mechanical polishing (clearing), to define a conductive interconnect structure. 2〇: Read the iA diagram ‘providing—the base lG—® case of the paste inner layer 20 ft / formed in the oxidative dream. The dielectric layer 30 can be formed by depositing a dielectric layer 30 on the insulating layer which is a late-dielectric layer or a dielectric material having a low dielectric constant. The visual consistency needs to be adjusted. The number and thickness of the layer 3丨. Next, the dielectric > % is patterned to form a via portion π which " electrical layer 30 and a trench portion 34, thereby comprising a via 32 and a trench 0503-A30164TWF/Jamn Gwo, 1281211 • * • The inlaid opening structure of 34, that is, the structure as shown in Fig. ia. [See IB ® / Child Product Block Layer 42 on the dielectric layer %, including compliant coating γγ^Γ: 2 * groove % on the surface. The material f of the barrier layer 42 includes a button (Ta) or a nitride group, and a seed layer 44 of, for example, copper is formed on the barrier layer 42 by physical vapor deposition. Copper crystal 2 # can provide a subsequent electrical_metal layer is better. It is called the 1C figure of the tea to form an electroplated copper layer 5 on the copper seed layer 44 and filled in the double damascene opening 2, thus completing the metallization process of the double-joined interconnect structure. _, in the actual chemical clock metal ^ wealth, often repair layer structure and interface at the fine (four) d) defects 52 and 54. Through the _ knives, it is known that the defect is even deep into the interface of the barrier layer 42 and the seed layer 44, thereby compensating for the reliability of the component, which leads to the overall failure of the component.曰 ^ 嶋 嶋 m diagram, now learning mechanical grinding _) flattening dew (four) copper layer 5 〇 surface until the surface of the dielectric layer 30 is exposed. Part of the electric clock copper metal (4), the seed layer 44 and the barrier layer 42 are removed from the upper surface of the dielectric layer 3〇 during the planarization process to form an interconnected conductive structure having a flat surface, such as in a dual damascene Connection structure. However, the above conventional method of forming an interconnect structure on a multi-layered wire base produces a lot of _, such as lack of generation and poor interfacial adhesion, when the metal layer is deposited.一妒(4), in the chemical deposits of the metal layer, often produced defects such as micropores and spiral defects, making it difficult to pass through the sub-micro-high-height wide and in-line, _ mouth structure to fill the metal film without defects / / In the manufacturing process of components, it is extremely important to ensure the formation of a recessed metal film. In view of this, the difficulty in the conventional process is that when the plated material enters the electric ore solution, it is avoided to generate Wei bubble. When the microbubble traps are in the table, the current is uneven, and the defects are formed in the coating interface, and even the unevenness of the overall film thickness is caused. Conventionally, a method of reducing the generation of microbubbles is to enter a plating solution into an electric money solution at an oblique angle. US ^ 6,582,578 EDordi et al. disclose a chemical plating device that enters at an oblique angle when the surface of the money member enters the lightning fluid. Avoiding the interface between the surface of the plated member and the battery and the substrate. 〇503-A30164TWF /Jamn Gwo 6 1281211. Figure 2 is a plan view of a chemical electroplating deposition (ECD) device system 300 in accordance with an embodiment of the present invention. In Fig. 2, the electroplating deposition apparatus system lion includes - carrying / unloading (badk ^) clothing 310 thermal annealing chamber to (rapid thermal annealing diambei ^ 360, - rotating _ / month washing dry (spin rinse- Dry 'SRD) and edge bevel removal (EBR) chamber 3/40, -mechanical arm 380 and one or more electroless plating tanks 32. A chemical clock supply = system (not shown Provided in a system adjacent to the electroless plating apparatus and connected to each of the electroless plating tanks 32 to provide a circulating electroplating liquid system. The chemical clock deposition apparatus system also includes a control device including a programmable microprocessor. Individual control outputs and respective devices that are numbered A to the electroplating deposition apparatus system 3. Fig. 3 shows a chemical electric clock reaction device according to an embodiment of the present invention, having a plated member 402' such as a dream wafer, The chemical electric clock reaction device includes a substrate fixing device 4〇4 fixed on the rotating shaft 4〇5 to provide the substrate fixing device side rotating moving soil. Although the present invention simplifies the chemical clock reaction Device example The embodiments of the present invention are not intended to limit the practice of the present invention, and other chemical electroplating reaction devices have the desired results achieved by the present invention, and are included in the scope of the present invention. The substrate pedestal and the substrate fixing device are completely immersed in the plating bath 422 including the plating solution. The circulation of the entire plating solution is shown in 414, and a continuous uterine ring clock liquid is provided by a secret. In other words, the plating solution flows upward to the plating member (anode) 402 and then expands outwardly through the plating member 4, as indicated by symbol 414. The circulation direction of the plating solution flows from the plating tank 422 to the plating solution storage tank 42〇, For example, 芩aa. 410 and 411. The plating solution flows out of the storage tank 42 and flows through a tearing cry 仃唬w λ to flow back to the pump 440' and completes the entire cycle step, as indicated by the arrow symbol 412. Shown. A DC power supply 45〇 provides a negative wheel, a dream, a slip ring, a brush and a contact (not shown), electrically connected to the ginseng or the positive and positive The battery is electrically connected to the anode 401 in the plating bath 422. After the electric iron: 2. Take X Ning, the power supply 〇503-A30l64TWF/Jamn Gwo 1281211 bias [the iron piece 402 produces a negative potential drop relative to the anode 401, causing a charge flow ^ self-exhaustion 4G2 (hetero (four) gratitude magnetic direction 舆 ^ The same is opposite to the direction of electron flow). The above-mentioned charge flow leads to an electrochemical reaction (ie, u仏-〇〇 on the surface of the money piece, thus depositing a metal layer such as copper on the bell. The ion concentration in the electric clock is determined by the entire electric energy, such as metal Yangqi In general, the composition of the electro-mineral liquid includes copper (CuS〇4), inhibitors or other additives. Agents such as high-strength polymers of hydrazine chains, including poly-shirts Non-alcohol (4) ^ (tetra) II Iyeihylene glyc〇 1, pEG), polyoxyethylene-polyoxypropyl copolymer 〇y〇xyethylene-p〇lyoxypropylene copolymer) 0 formation - monolayer (m〇n〇 Layer) to inhibit the deposition rate of chemical ore reaction. This single molecule H initiates and traps bubbles formed on the surface. Moreover, when the base pedestal enters the electricity, it can avoid the generation of air bubbles on the surface of the substrate, even if it is not removed by the laminator. Therefore, it is still impossible to remove the fine bubble (10) seven by changing the rotation speed or laminar flow velocity of the base pedestal. In the electric ship, the trapping in the base wire _ bubble will make the electric ship unable to directly touch the crystal surface of the fish base surface, causing the Wei shot production to be trapped or even the hole bridge. Into the shadow of the metal clock. The formation of the above-mentioned missing limb bridge will also limit the filling rate of the opening portion or the groove portion, so that the hole defect and the hole bridge in the metal plating or the interconnecting line can affect the reliability of the component and the instability of the component. In accordance with the present invention, in the case of metal/chemical surface deposition, a stable and uniform current density is provided between the cathode faces and the substrate base is tilted by a specific angle and rotated. During the tilting and rotating substrate reference, the bubbles trapped on the surface of the substrate can be removed by the flow of the plating solution. As the tilt angle of the base base increases, the efficiency of bubble removal increases. However, the inclination of the base base will be uniform in thickness. The present invention 0503-A30164TWF/Jamn Gwo 9 1281211 materializes her _ copper seed layer 144 on the barrier layer 142. The function of the copper seed layer i44 is to provide a subsequent surface crystallization reduction. In general, the thickness range of the copper day a day layer is preferably between 500_3000A. To the eve of the moon / see the 4C figure, a chemical electric clock copper metal layer 15 is formed on the seed layer 144, and the inner layer of the filling layer is formed. The electroplating step can be carried out by the manner and variation of various money-savings implemented by the present invention. In Yuhua (4), the tilting of the base pedestal--the angle of the base is rotated and the bubble removal rate can be increased, thereby effectively reducing the formation of voids. The inclination angle of the soil foundation pedestal | The father is mostly Q.5_3 degrees. The range of rotation rates of the substrate base is preferably between (9) and (iv). The present invention sacrifices part of the white layer uniformity 'the tilt of the base pedestal' to completely remove the air bubbles under the margin of the margin. Under the above conditions, the flatness of the metal is older than 1%_4%. What's more, the number of defects in the air holes or interconnects on the gold riding layer can be reduced by 1-2 orders of magnitude. The connector μ* reads the 4D mesh, planarizes by chemical mechanical polishing (CMp) and removes excess gold lying on the multilayer interconnect structure and exposes the underlying electrical layer (9) to define the conductive line of the honest line. In the chemical mechanical polishing step, the excess portion of the metal layer 15Q, the copper seed layer (4), and the brown layer 142 are sequentially removed to reveal a surface of the dielectric layer of 15 ,, and the surface is flat and double-embedded. Fabrication of wire conductive structures. ^ [Features and Effects of the Case] The functions and effects of the present invention include that the chemical base is made of a chemical, and the base base is tilted by a special angle and rotated to increase the removal rate of the bubble, and to effectively reduce the defect of the hole. form. The invention sacrifices a certain degree of mirror layer uniformity under the permission of the process margin, and the base base is inclined, and the bottom base is stitched. Under the ship, the sum of the gold and gold layers is mostly between the financial assets. . What's more, the number of broken defects in the holes or interconnects on the metal is (four) orders of magnitude. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and anyone skilled in the art can make a change and reliance on the spirit and scope of the present invention, 0503-A30164TWF/Jamn. Gwo 11 1281211 The scope of the invention is therefore defined by the scope of the appended claims.

12 0503-A30164TWF/Janm Gwo 1281211 [Simple description of the diagram] The 1A-1D diagram is on the base of the display structure; Ding Chuan, the first metallization process to form the interconnect structure in the multi-layered second diagram The intention of the embodiment of the present invention; the plane of the electron microscope deposition (ECD) device system shows a chemical chain reaction device according to the example of the present invention; and the brother 4A-4D system shows the metallization dream. Cross-section of each step of the 耘 耘 内 【 【 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体~ barrier layer; 50 ~ electroplated copper metal layer; D ~ spiral defect.

20~metal interconnect; 30~ dielectric layer; 34~ trench portion; 44~ seed layer; 52 and 54~ hole defect; part of the case (2nd to 4D) 300~ chemical electroplating deposition system; 320 ~ chemical plating reaction tank; 360 ~ rapid thermal annealing chamber; 400 ~ chemical plating reaction device; 310 ~ load / unload device; 340 ~ square turn - cleaning - think dry and corner removal chamber · 3 80 ~ mechanical Arm; 401~anode; 402~money piece; 4G3~base base; 4〇4~base fixture; 405~rotation axis; arrow symbol 410 to 414~ key circulation direction; 0503-A30164TWF/Jamn Gwo 13 1281211 422 ~ plating bath; Θ ~ base base tilt angle, 120 ~ metal interconnect; 130 ~ dielectric layer; 134 ~ trench portion; 144 ~ seed layer; 420 ~ storage slot; 450 ~ DC power supply for, 100~ semiconductor substrate; 125~ insulating layer; 132~ via hole portion; 142~ barrier layer; 150 and 150'~ electroplated copper metal layer. 14 0503-A30164TWF/Jamn Gwo

Claims (1)

Amendment date: 95.12.18 i^/j uvV; ί \ 128123⁄43⁄4142339 Patent application scope revision 10. Application scope: 1. An electroless plating deposition method comprising: providing a substrate; and performing chemistry in a chemical plating bath Electroplating depositing a metal layer on the substrate, wherein the substrate has an electroplating surface, the electroplating surface is not parallel to the surface of the electroless plating bath, and is inclined at an angle and rotated; wherein the plating surface of the substrate The range of tilt angles is generally between 0.5 and 3 degrees. 2. The electroless plating deposition method of claim 1, further comprising depositing a barrier layer and a seed layer on the substrate. 3. The electroless plating deposition method according to claim 2, wherein the barrier layer deposited comprises a sputtering button (Ta), a nitride button (TaN), titanium nitride (TiN) or the above three Combination of meta-compounds. 4. The electroless plating deposition method of claim 2, wherein the seed layer deposited comprises electrolessly plated copper or chemical vapor deposited copper. 5. The electroless plating deposition method of claim 1, wherein the metal layer comprises copper. 6. The electroless plating deposition method of claim 1, wherein the plating surface of the substrate has a rotation rate ranging from 150 to 600 rpm. 7. A method of forming an integrated circuit component by chemical electroplating, comprising: providing a semiconductor substrate having an insulating layer thereon; providing a metal interconnect line in the insulating layer; forming a dielectric layer thereon On the insulating layer, the dielectric layer includes a trench opening and a via opening opposite to the metal interconnect line; and chemically depositing a metal layer on the substrate, wherein the substrate has a plating surface, In electroless plating, the plated surface is not parallel to the surface of the electroless plating bath, and is inclined at an angle and rotated; 0503-A30164TWF2 (20061020) 15 1281211 • wherein the plating surface of the substrate has an inclination angle ranging from 0.5 to 3 degree. The method for forming an integrated circuit component by chemical electroplating deposition according to the above-mentioned patent application, wherein the barrier layer includes a group (4), a nitride group (10), and a titanium nitride ( TlN) or a combination of the above ternary compounds. • > 9. A method of forming an integrated circuit component by chemical electroplating as described in claim 7, wherein the seed layer deposited comprises electrolessly plated copper or chemical vapor deposited copper. The method of forming a build-up circuit component by chemical electroplating as described in claim 7 of the patent scope wherein the rotational speed of the key face of the substrate ranges from 150 to 600 rpm. A non-defective electroplated metal layer on a semiconductor wafer, comprising: a semiconductor wafer; and a chemically plated metal layer on the semiconductor wafer, wherein the chemical ore metal layer is patented as claimed The method described in the seventh item is formed by a chemical electric shipbuilding method, and in the chemical electricity (four), the surface of the semiconductor wafer is not parallel to the surface of the chemical electric ore tank, and is inclined at an angle and rotated; wherein, the chemical electricity The defect density on the metal layer of the clock is substantially less than %/square millimeter-two. For example, the defect-free susceptor plating on the semiconductor wafer described in item U is applied to the genus layer, wherein the semiconductor wafer includes a single Wafer wafers. ... 八八如专: The defect-free chemistries on the semiconductor wafer described in the scope U, wherein the semiconductor wafer comprises a barrier layer 晶 - a seed layer on the surface of the basin. Island M. No defect on the semiconductor wafer as described in the scope of claim 5: an electro-mineral metal layer, the chemical money metal layer deposited on the semiconductor wafer, including 0503-A30164TWF2 (20061020) 16 1281211 15.» 15. The non-defective electroplated metal layer on the semiconductor wafer of claim 11, wherein the flatness on the electroless metal layer is substantially between 1% and 4%. 0503-A30164TWF2 (20061020) 17