Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
  • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
  • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of DC power input into DC power output
  • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
  • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of DC power input into DC power output
  • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
  • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
  • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/06—Modifications for ensuring a fully conducting state
  • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches

Definitions

• the present invention relates to a bootstrap type DC-DC converter having a level shift circuit, a high input power supply voltage and a low control power supply voltage, and performing switching of an output transistor at a drive voltage higher than the input power supply voltage. And a switching regulator having the same. Background art
• FIG. 3 shows a configuration example of a conventional switching regulator.
• the switching regulator in FIG. 3 is a switching regulator having a bootstrap DCZDC converter, and includes a PWM signal generation circuit 1, a level shift circuit 2, a bootstrap switching circuit 3, a smoothing circuit 4, It comprises delay circuits 5a and 5b. Note that the input power supply voltage V is larger than the control power supply voltage V.
• the voltage V is + 25V, and the control voltage V is + 5V.
• the PWM signal generation circuit 1 generates a PWM signal according to the output voltage Vo, and supplies the PWM signal to the delay circuits 5a and 5b.
• the delay circuit 5a supplies a PWM signal P1 obtained by delaying the PWM signal output from the PWM signal generation circuit 1 to the level shift circuit 2 '.
• the delay circuit 5b supplies the bootstrap switching circuit 3 with a control noise signal P2 obtained by delaying the PWM signal output from the PWM signal generation circuit 1.
• the power supply voltage of the PWM signal generation circuit 1 and the delay circuits 5a and 5b is the control power supply voltage V. Also,
• the rise timing of the control pulse signal P2 is earlier than the PWM signal P1 by a predetermined time.
• a signal whose fall timing is delayed by a predetermined time A signal whose fall timing is delayed by a predetermined time.
• the level shift circuit 2 'converts the PWM signal P1 into a high-voltage control pulse signal PH and supplies it to the bootstrap switching circuit 3.
• the driver circuit Drl turns on and off the NMOS transistor Trl in response to the high control pulse signal PH, and the control pulse signal P2 is inverted by the inverter circuit 3a.
• Circuit Dr2 turns on and off the NMOS transistor Tr2.
• a capacitor is connected via the Schottky diode SD1 from the terminal 7 to which the control power supply voltage V is applied.
• the charging current flows into the capacitor C1, and the voltage across the capacitor C1 becomes approximately + 5V. Thereafter, after a period in which both the NMOS transistor Trl and the NMOS transistor Tr2 are turned off, when the NMOS transistor Trl is turned on and the NMOS transistor Tr2 is turned off, a connection point between the capacitor C1 and the NMOS transistor Trl is turned off.
• the voltage SW becomes + 25V, and the voltage BOOT at the connection point between the capacitor C1 and the Schottky diode SD1 becomes about + 30V. Then, after a period in which both the NMOS transistor Trl and the NMOS transistor Tr2 are turned off, the NMOS transistor Trl is turned off again and the NMOS transistor Tr2 is turned on.
• a voltage between a connection point between the capacitor C1 and the Schottky diode SD1 and a connection point between the NMOS transistor Trl and the NMOS transistor Tr2 is supplied as a power supply voltage to a circuit subsequent to the level shift circuit 2 '.
• the smoothing circuit 4 is a smoothing filter including the inductor L1 and the capacitor C2, and smoothes the voltage at the connection point between the NMOS transistor Trl and the NMOS transistor Tr2 and outputs the result as the output voltage Vo.
• the operation modes of the switching regulator include a mode in which the output current is directed from the switching regulator to the load (forward mode) and a mode in which the output current is directed from the load to the switching regulator (reverse mode). )
• the voltage Vn matches the voltage BOOT because the NMOS transistor Q0 is off.
• the voltage Vn matches the voltage SW because the NMOS transistor Q0 is on.
• Patent Document 1 Japanese Patent Application Laid-Open No. 2002-315311
• Patent Document 2 Japanese Patent Application Laid-Open No. 2003-235251
• the parasitic capacitance PC between the gate and the source of each transistor in the inverter including the PMOS transistor Q1 and the NMOS transistor Q2 having the connection point n as an input terminal causes the switching regulator of FIG. As shown in the figure, the waveform was distorted at the rise and fall of the voltage Vn.
• the output of the inverter including the PMOS transistor Q1 and the NMOS transistor Q2 may be erroneously inverted in the sections T1 and T2 in which the waveform of the voltage Vn is blunt, which may cause a malfunction. . That is, since the difference between the voltage BOOT and the voltage Vn increases in the section T1, the output of the inverter including the PMOS transistor Q1 and the NMOS transistor Q2 becomes high level, and the difference between the voltage SW and the voltage Vn increases in the section T2. Therefore, there is a possibility that the output power of the inverter including the PMOS transistor Q1 and the NMOS transistor Q2 becomes SLow level.
• the breakdown voltage between the gate and the source of the PMOS transistor Q1 may be defective, which also causes a decrease in reliability.
• Such a problem is caused by an increase in the size of the PMOS transistor Q1 and the NMOS transistor Q2 in response to an increase in the current of the switching regulator, an increase in the parasitic capacitance PC and an increase in the current consumption.
• the time constant due to the parasitic capacitance PC and the resistor R1 increases due to the increase in the resistance value of the resistor R1 in order to reduce it, or when the ON period of the PWM signal P1 is short, it becomes remarkable.
• an object of the present invention is to provide a level shift circuit capable of suppressing malfunction and a switching regulator including the same.
• a level shift circuit receives a first pulse signal, and has a High level higher than the first pulse signal in response to the first pulse signal.
• a level shift circuit for generating a second noise signal comprising: a high-voltage power supply voltage supply line, a low-voltage power supply voltage supply line, the high-voltage power supply voltage supply line, and the low-voltage power supply.
• Inverter that operates with the voltage between the voltage supply line and the power supply voltage A circuit, a first diode having an anode connected to an input terminal of the inverter circuit, and a power diode connected to the high voltage side power supply voltage supply line; and a power source connected to an input terminal of the inverter circuit.
• a second diode having an anode connected to the low voltage side power supply voltage supply line.
• the high-voltage-side power supply voltage supply line Even if the potential rises or falls, the difference between the potential of the high-voltage power supply voltage supply line and the potential of the input terminal does not exceed the forward voltage of the first diode by the first diode. , The waveform of the potential at the input terminal is not blunted.
• the potential of the input terminal is substantially equal to the potential of the low-voltage power supply voltage supply line in response to the first pulse signal, the difference between the potential of the high-voltage power supply voltage supply line and the potential of the input terminal is reduced.
• the waveform of the potential at the input terminal is not distorted. Therefore, it is possible to suppress a malfunction that occurs when the waveform of the potential of the input terminal is distorted and the output of the inverter circuit is erroneously inverted.
• the body diode of the MOS transistor has a small element area and a small parasitic capacitance, if the body diode of the MOS transistor is used for each of the first diode and the second diode, the input terminal voltage of the inverter circuit described above The effect of suppressing the rounding of the waveform becomes larger. Therefore, it is desirable to use a body diode of a MOS transistor for each of the first diode and the second diode.
• the level shift circuit can be applied to a switching regulator having a bootstrap DC-DC converter.
• FIG. 1 is a diagram showing a configuration example of a switching regulator according to the present invention.
• FIG. 2 is a time chart illustrating voltage waveforms of respective parts of a level shift circuit included in the switching regulator of FIG.
• FIG. 3 is a diagram showing a configuration example of a conventional switching regulator.
• FIG. 4 is a time chart showing voltage waveforms of respective parts of a level shift circuit included in the switching regulator of FIG.
• FIG. 1 shows a configuration example of a switching regulator according to the present invention.
• the switching regulator of FIG. 1 is a switching regulator having a bootstrap type DCZDC converter, and includes a PWM signal generation circuit 1, a level shift circuit 2, a bootstrap switching circuit 3, and a smoothing circuit 4. , And a simultaneous ON prevention circuit 6.
• the circuits other than the level shift circuit 2 and the simultaneous ON prevention circuit 6 have the same circuit configuration as the switching regulator of FIG. The description is omitted, and the level shift circuit 2 and the simultaneous ON prevention circuit 6, which are characteristic portions of the present invention, will be described below.
• the simultaneous ON prevention circuit 6 includes an inverter circuit 6a, an AND gate 6b, and an OR gate 6c.
• the inverter circuit 6a receives the output LG of the driver circuit Dr2. That is, the input terminal of the inverter circuit 6a is connected to the connection node between the output terminal of the driver circuit Dr2 and the gate of the NMOS transistor Tr2.
• the output terminal of the inverter circuit 6a is connected to the second input terminal of the AND gate 6b.
• the first input terminal of the AND gate 6b and the first input terminal of the OR gate 6c receive the PWM signal P1 output from the PWM signal generation circuit 1. That is, the first input terminal of the AND gate 6b and the first input terminal of the OR gate 6c The input terminal is connected to the output terminal of the PWM signal generation circuit 1.
• the OR gate 6c inputs the output HG of the driver circuit Drl to the second input terminal. That is, the second input terminal of the OR gate 6c is connected to a connection node between the output terminal of the driver circuit Drl and the gate of the NMOS transistor Trl.
• the output terminal of the AND gate 6b is connected to the gate of the NMOS transistor Q0 in the level shift circuit 2, and the output terminal of the OR gate 6c is connected to the input terminal of the inverter circuit 3a in the bootstrap switching circuit 3.
• the simultaneous ON prevention circuit 6 having the above configuration outputs the PWM signal P1 to the gate of the NMOS transistor Q0 in the level shift circuit 2, and the rising timing is earlier than the PWM signal P1 by a predetermined time.
• the control pulse signal P2 which is a signal delayed by a predetermined time, is output to the input terminal of the inverter circuit 3a in the bootstrap switching circuit 3.
• the level shift circuit 2 includes an NMOS transistor Q0, a resistor R1, a current mirror circuit including NPN transistors Q3 and Q4, a resistor R2 functioning as a current source for supplying a current to the current mirror circuit, and a PMOS. It comprises an inverter circuit composed of a transistor Q1 and an NMOS transistor Q2, inverter circuits 2a and 2b, and NMOS transistors Q5 and Q6. Each inverter circuit is connected to a power supply line to which the voltage BOOT is supplied and to a power supply line to which the voltage SW is supplied, and uses the voltage between the power supply lines as a power supply voltage.
• the drain of the NMOS transistor Q0 is connected via a resistor R1 to a power supply line to which the voltage BOOT is supplied. Further, the source of the NMOS transistor Q0 is connected to the output side of a current mirror circuit composed of NPN transistors Q3 and Q4. Then, a connection point n between the resistor R1 and the NMOS transistor Q0 becomes an input terminal of the inverter circuit including the PMOS transistor Q1 and the NMOS transistor Q2. The output of the inverter circuit including the PMOS transistor Q1 and the NMOS transistor Q2 is inverted by the inverter circuit 2a, and the output of the inverter circuit 2a is inverted by the inverter circuit 2b to become the pulse control signal PH.
• an NMOS transistor Q5 whose gate and source are short-circuited is provided between the connection point n and the power supply line to which the voltage BOOT is supplied, and the power supply line to which the connection point n and the voltage SW are supplied.
• FIG. 2 shows a time chart of the voltage waveform of each part of the level shift circuit 2.
• Vn in FIG. 2 is a voltage at a connection point n between the NMOS transistor QO to which the PWM signal P1 is supplied to the gate and the resistor R1
• Vs in FIG. 2 is a forward voltage of the Schottky diode SD1.
• V in Fig. 2 is the forward voltage of the body diode of NMOS transistor Q2.
• V in FIG. 2 is the forward voltage of the body diode of NMOS transistor Q6.
• the forward mode will be described.
• the voltage Vn becomes equal to the voltage BOOT.
• the difference between the voltage SW and the voltage Vn is fixed to the forward voltage V of the body diode of the NMOS transistor Q6 by the body diode of the NMOS transistor Q6. Therefore, the waveform of the voltage Vn does not change.
• PW the difference between the voltage SW and the voltage Vn
• the voltage Vn rises to a high level value of the voltage BOOT (a value in a section where both the PWM signal P1 and the control pulse signal P2 are at a high level), and then the voltage BOOT becomes low.
• the value is the same as the level value (the value in the section where both the PWM signal P1 and the control pulse signal P2 are at the low level).
• the reverse mode will be described.
• the difference between the voltage BOOT and the voltage Vn due to the body diode of the NMOS transistor Q5 does not exceed the forward voltage of the body diode of the NMOS transistor Q5, so the voltage Vn rises with the rise of the voltage BOOT.
• the waveform of the voltage Vn is not blunted, and the breakdown voltage between the gate and the source of the PMOS transistor Q1 does not become defective, thereby improving the reliability.
• section T2 the section in which voltage Vn is higher than voltage SW conventionally
• the difference between voltage SW and voltage Vn is reduced by the body diode of NMOS transistor Q6 due to the body diode of NMOS transistor Q6. Since the voltage is fixed at the forward voltage V,
• Shape does not change. Therefore, there is no possibility that the output of the inverter including the PMOS transistor Q1 and the NMOS transistor Q2 is erroneously inverted and causes a malfunction. Also, withstand voltage failure may occur between the gate and source of the PMOS transistor Q1 in the section T1. And the reliability is improved.
• a connection point n is connected to the anode and the voltage BOOT is supplied.
• a diode element connected to the power supply line S is provided, and the connection point is used instead of the NMOS transistor Q6.
• the power diode element that can suppress the waveform distortion of the voltage Vn is a body diode of an NMOS transistor Since the parasitic capacitance increases due to the large element area as compared with, the effect of suppressing the waveform distortion of the voltage Vn is reduced.
• the level shift circuit of the present invention can be applied to a switching regulator and the like.
• the switching regulator can be used as a power supply for all electric devices.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Dc-Dc Converters (AREA)
• Power Conversion In General (AREA)
• Logic Circuits (AREA)

Priority Applications (3)

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Cited By (2)

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Citations (6)

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• 2005
  • 2005-05-19 JP JP2006514436A patent/JP4514753B2/ja not_active Expired - Fee Related
  • 2005-05-19 WO PCT/JP2005/009122 patent/WO2005122373A1/ja not_active Ceased
  • 2005-05-19 US US11/628,401 patent/US20080018311A1/en not_active Abandoned
  • 2005-05-19 KR KR1020067025956A patent/KR100834219B1/ko not_active Expired - Fee Related
  • 2005-05-19 EP EP05741539A patent/EP1768240A4/en not_active Withdrawn
  • 2005-05-19 CN CNA2005800185702A patent/CN1965464A/zh active Pending
  • 2005-05-24 TW TW094116807A patent/TW200614637A/zh not_active IP Right Cessation

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