WO2005114625A1 - 画像信号処理装置 - Google Patents
画像信号処理装置 Download PDFInfo
- Publication number
- WO2005114625A1 WO2005114625A1 PCT/JP2005/009833 JP2005009833W WO2005114625A1 WO 2005114625 A1 WO2005114625 A1 WO 2005114625A1 JP 2005009833 W JP2005009833 W JP 2005009833W WO 2005114625 A1 WO2005114625 A1 WO 2005114625A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- rom
- signal processing
- field
- lsi
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
Definitions
- the present invention relates to an image signal processing device such as a plasma display.
- a large number of discharge cells are formed between a front plate and a rear plate which are arranged opposite to each other.
- the front plate has a plurality of display electrodes formed of a pair of scan electrodes and sustain electrodes formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes.
- the back plate is composed of a plurality of parallel data electrodes on a rear glass substrate, a dielectric layer covering them, and a plurality of partitions formed thereon in parallel with the data electrodes. Phosphor layers are formed on the surface of the layer and the side surfaces of the partition walls.
- the front plate and the back plate are opposed to each other so that the display electrode and the data electrode are three-dimensionally intersecting with each other, and are sealed.
- a discharge gas is sealed in an internal discharge space.
- a discharge cell is formed at a portion where the display electrode and the overnight electrode face each other.
- ultraviolet light is generated by gas discharge in each discharge cell, and the ultraviolet light excites and emits phosphors of R, G, and B colors to perform color display.
- a subfield method that is, a method in which one field period is divided into a plurality of subfields and gradation display is performed by a combination of subfields to emit light is generally used.
- a new driving method that minimizes the emission that is not related to the gradation expression, suppresses the increase in black luminance, and improves the contrast ratio is disclosed in Japanese Patent Application Laid-Open No. 2000-22442. No. 4 discloses this.
- an image signal processing device used for driving control of this type of plasma display includes a semiconductor integrated circuit device (LSI) for processing a video signal and an external device outside the LSI.
- LSI semiconductor integrated circuit device
- a flash ROM as an external memory that holds data for controlling the operation of the LSI is used, and data communication is performed between a ROM access control circuit in the LSI and the flash ROM. That is, the ROM access control circuit inside the LSI creates a ROM address and a ROM enable signal, transfers those signals to the flash ROM, and receives the signal, and the flash ROM
- the ROM data is transferred to the R ⁇ ⁇ ⁇ ⁇ M access control circuit, which is the operation control data stored in advance.
- the present invention relates to a semiconductor integrated circuit device comprising: a video signal processing unit for outputting video output data to a display device; and a control unit for holding data for controlling the operation of the video signal processing unit.
- An external memory that is provided outside the device and holds control data to be sent to the control unit, and has an external memory that can control reading of data by the control unit, is transferred between the external memory and the control unit.
- the data includes data that must be updated every field and data that does not need to be updated every field, and is configured to transfer data during the vertical blanking period of video output data. Data that does not need to be updated is divided into a plurality of parts, and the data is divided into a plurality of fields and transferred.
- the present invention is characterized in that the video signal processing unit is provided with a memory for holding data that needs to be updated every field and a memory for holding data that does not need to be updated every field. According to the present invention, even if the control data for driving the display device increases, the data can be transferred between the external memory and the control unit during the vertical blanking period.
- FIG. 1 is a perspective view showing a main part of a panel of a plasma display according to an embodiment of the present invention.
- FIG. 2 is an electrode arrangement diagram of the plasma display panel.
- FIG. 3 is an overall configuration diagram of the plasma display.
- FIG. 4 is a block diagram showing an image signal processing device according to one embodiment of the present invention.
- FIG. 5 is an explanatory diagram for explaining data transfer in the same device.
- FIG. 6 is an explanatory diagram for explaining an example of a case where data is transferred in two in the same device.
- FIG. 7 is an explanatory diagram for explaining an example of a case where data is transferred after being divided into four parts in the same device.
- FIG. 1 is a perspective view showing a main part of a panel used for a plasma display according to one embodiment of the present invention.
- the panel 1 is configured such that a front substrate 2 and a rear substrate 3 made of glass are opposed to each other, and a discharge space is formed therebetween.
- a plurality of scan electrodes 4 and sustain electrodes 5 constituting display electrodes are formed on the front substrate 2 in pairs in parallel with each other.
- a dielectric layer 6 is formed so as to cover scan electrode 4 and sustain electrode 5, and a protective layer 7 is formed on dielectric layer 6.
- a plurality of data electrodes 9 covered with an insulator layer 8 are provided on the rear substrate 3, and a partition wall 1 is provided on the insulator layer 8 between the data electrodes 9 in parallel with the data electrodes 9. 0 is set. Further, the phosphor layer 11 is provided on the surface of the insulator layer 8 and the side surface of the partition wall 10. Then, scan electrode 4 and sustain electrode 5 The front substrate 2 and the rear substrate 3 are opposed to each other in a direction in which the discharge gas flows, and a discharge space formed therebetween is filled with a discharge gas, for example, a mixed gas of neon and xenon.
- a discharge gas for example, a mixed gas of neon and xenon.
- FIG. 2 is an electrode array diagram of the panel.
- n scan electrodes S CN1 to S CN n scan electrode 4 in FIG. 1
- n sustain electrodes SUS 1 to SUS n sustain electrode 5 in FIG. 1
- m data electrodes Dl to Dm data electrode 9 in Fig. 1
- M ⁇ n discharge cells are formed in the discharge space.
- FIG. 3 is an overall configuration diagram of the plasma display.
- This plasma display has a panel data electrode drive circuit 12, a scan electrode drive circuit 13, a sustain electrode drive circuit 14, a timing generation circuit 15, an AD (analog / digital) converter 18, a format converter 19, and a subfield converter 20. And a power supply circuit (not shown). '
- the image signal sig is input to the AD converter 18.
- the horizontal synchronization signal H and the vertical synchronization signal V are supplied to a timing generation circuit 15, an AD converter 18, a format converter 19, and a subfield converter 20.
- the AD converter 18 converts the image signal sig into image data of a digital signal, and supplies the image data to the format converter 19.
- the format conversion unit 19 converts the image data into an image data according to the number of pixels of the panel 1 and supplies the image data to the subfield conversion unit 20.
- the subfield conversion unit 20 divides the image data of each pixel into a plurality of bits corresponding to a plurality of subfields, and outputs the image data of each subfield to the data electrode driving circuit 12.
- the data electrode drive circuit 12 converts image data for each subfield into signals corresponding to the data electrodes Dl to Dm and drives each data electrode.
- the timing generating circuit 15 generates a timing signal based on the horizontal synchronizing signal H and the vertical synchronizing signal V, and supplies the timing signal to the scan electrode driving circuit 13 and the sustain electrode driving circuit 14, respectively.
- the scanning electrode driving circuit 13 scans the scanning electrode S based on the timing signal.
- the driving waveform is supplied to CNl to SCNn, and the sustain electrode driving circuit 14 supplies the driving waveform to the sustain electrodes S US:! To S USn based on the timing signal.
- FIG. 4 is a block diagram showing details of a driving circuit portion of the plasma display according to the embodiment of the present invention.
- the driving circuit portion of the plasma display includes a video signal processing LSI 21 which is a semiconductor integrated circuit device which outputs video output data to a data electrode driving circuit 12 of a panel which is a display device.
- LSI 21 is a semiconductor integrated circuit device which outputs video output data to a data electrode driving circuit 12 of a panel which is a display device.
- the ROM 21 is connected to a ROM access control circuit 22 as a control unit inside the LSI 21 and a flash ROM 23 as an external memory for exchanging control data.
- the LSI 21 includes an image quality correction circuit 24 that receives image input data sent from the format conversion unit 19 and performs signal processing for image quality correction, based on output data of the image quality correction circuit 24.
- a video signal processing unit including a subfield conversion circuit 25 for generating a signal for each subfield and a video signal output circuit 26 for generating video output data based on a signal sent from the subfield conversion circuit 25 is provided. Have been.
- Reference numeral 25 is configured to control the operation based on the ROM data stored in the flash ROM read by the ROM access control circuit 22.
- Each of the image quality correction circuit 24 and the subfield conversion circuit 25 of the video signal processing unit has a SRAM 24 a and a SRAM 25 a which are memories for holding ROM data sent for controlling the operation of each circuit. Is provided. That is, the flash ROM 23 external to the LSI 21 stores data required by the image quality correction circuit 24 and the subfield conversion circuit 25, and is taken into the LSI 21 for each field during the vertical blanking period. It is.
- the ROM access control circuit 22 creates a ROM address and a ROM enable signal, transfers those signals to the flash ROM 23, and receives the signal, and the flash ROM 23 sends the signal to the ROM access control circuit 22.
- the ROM data signal is transmitted to
- the transferred ROM data is held in the SRAMs 24 a and 25 a of the image quality correction circuit 24 and the sub-field conversion circuit 25, respectively.
- the operations of the image quality correction circuit 24 and the subfield conversion circuit 25 are controlled based on the data.
- the LSI 21 further includes an input terminal 27a for inputting data to the LSI 21, an output terminal 27b for outputting data, and an input / output terminal 27c for inputting / outputting data.
- the video output data output from the video signal output circuit 26 is sent to the data electrode drive circuit 12 of the display device through the output terminal 27b and the input / output terminal 27c.
- the ROM access control circuit 22 and the flash ROM 23 outside the LSI 21 are connected to each other through an input / output terminal 27c, and some of the input / output terminals 27c are connected to the data electrode drive circuit 12 of the display device.
- Flash ROM 23 Flash ROM 23.
- a line for transferring a ROM address and a ROM enable signal from the ROM access control circuit 22 of the LSI 21 to the flash ROM 23 is provided with an asynchronous signal transmitted from the input terminal 27a of the LSI 21.
- Buffers 28 and 29 controlled by the reset signal are inserted and arranged.
- the buffers 28 and 29 are configured to release the ROM address and the R ⁇ M enable signal during the period in which the asynchronous reset signal is enabled. In this state, the data content of the flash ROM 23 can be updated by another ROM data writing device 30 during that period.
- the video output data output from the video signal output circuit 26 is transmitted from the output terminal 27 b to the data electrode drive circuit 12 of the display device and from the ROM access control circuit 22.
- the display device through a line that is shared with the ROM data signal through the input / output terminal The data is sent to the data electrode drive circuit 12.
- the input / output terminal 27 c of the LSI 21 is used as a terminal for outputting the video output data from the video signal output circuit 26 and It is configured to be used as a terminal for transferring ROM address and R ⁇ M data between the M access control circuit 22 and the flash ROM 23, and the data is multiplexed and transmitted on the time axis. Is configured.
- FIGS. An example in which the ROM address terminal and the ROM data terminal of the LSI 21 are shared with the output terminal of the video output data of the LSI 21 and each data is multiplexed on the time axis and transmitted is shown in FIGS. This will be described using FIG.
- FIG. 5A shows a vertical synchronization signal
- FIG. 5B shows transfer data between the LSI 21 and the display device and the flash ROM 23
- FIG. 5C shows a data pattern of an example of ROM data in the transfer data.
- video output data output from the video signal output circuit 26 inside the LSI 21 is transferred to the data electrode drive circuit 12 outside the LSI 21.
- a ROM address and a ROM enable signal are transferred from the ROM access control circuit 22 inside the LSI 21 to the flash ROM 23 outside the LSI 21.
- the flash ROM 23 In response to the ROM address and the ROM enable signal, the flash ROM 23 sends the data to the LSI 21 as data d 1—A, dl that must be updated every field as shown in FIG. 5C. — ⁇ ⁇ 'and a ROM data consisting of data d 2 that does not need to be updated every field is transferred.
- FIGS. 6 and 7 show diagrams for explaining the concept of dividing data d2 that does not need to be updated every field into a plurality of pieces and transferring the data d2 to a plurality of fields.
- Fig. 6 is a diagram for explaining the concept of dividing the same data d2 in each field into two fields and transferring the data to two fields.
- Fig. 6A Instead of transferring data consisting of the same data d2 as the variable data dl-A, dl- ⁇ ⁇ ⁇ for each field as shown in Fig. 6B, the same data as shown in Figs. 6C and D is used.
- Data d 2 is divided into two to obtain data d 2-a, 012-13, and variable data d 1-when data A is transferred to SRAM 24 a, data d 2-a is divided into S
- the variable data d1-1B is transferred to the SRAM 24a in the next field after being transferred to the RAM 25a
- the remaining divided data d2-b are transferred to the SRAM 25a.
- the data d2—a transferred to SRAM 25a when transferring variable data d1—A in the first field is not updated when transferring variable data d1—B in the next field. It is held in the SRAM 25a as it is. In the next field, only the data d2_b is transferred and held in the SRAM 25a.
- FIG. 7 is a diagram showing an example in which the same data d2 is divided into four parts for each field and transferred, and FIG. 7A shows ROM data, and FIGS. 7B to 7E show data transferred for each field.
- the data transfer operation is the same as the above-described two-partition operation in FIG.
- the R ⁇ M data can be transferred to the LSI 21 even in a shorter vertical blanking period. .
- the semiconductor integrated circuit device is provided with a terminal commonly connected to the display device and the flash memory, and outputs video output data to the display device through the terminal. It is configured to transfer data, so that even if the video data for driving the display device increases, the number of LSI terminals increases and the chip area can be prevented from increasing.
- an image signal processing device suitable for improving the image quality of a digital display device such as a plasma display and inputting signals in various formats.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of Gas Discharge Display Tubes (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/563,509 US20060165278A1 (en) | 2004-05-24 | 2005-05-24 | Image signal processing device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-152805 | 2004-05-24 | ||
JP2004152805A JP4200321B2 (ja) | 2004-05-24 | 2004-05-24 | 画像信号処理装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005114625A1 true WO2005114625A1 (ja) | 2005-12-01 |
Family
ID=35428585
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/009833 WO2005114625A1 (ja) | 2004-05-24 | 2005-05-24 | 画像信号処理装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20060165278A1 (ja) |
JP (1) | JP4200321B2 (ja) |
KR (3) | KR100868128B1 (ja) |
CN (1) | CN100476913C (ja) |
WO (1) | WO2005114625A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005331559A (ja) * | 2004-05-18 | 2005-12-02 | Matsushita Electric Ind Co Ltd | 画像信号処理装置 |
JP2009239899A (ja) * | 2008-03-04 | 2009-10-15 | Seiko Epson Corp | 画像処理回路及びそれを含む電子機器 |
WO2012001886A1 (ja) * | 2010-06-28 | 2012-01-05 | パナソニック株式会社 | プラズマディスプレイパネル用集積回路、アクセス制御方法及びプラズマディスプレイシステム |
US11978372B1 (en) * | 2023-05-16 | 2024-05-07 | Qualcomm Incorporated | Synchronized dual eye variable refresh rate update for VR display |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH104516A (ja) * | 1996-06-18 | 1998-01-06 | Canon Inc | 情報処理システムおよび情報処理方法 |
JP2001092436A (ja) * | 1999-09-24 | 2001-04-06 | Olympus Optical Co Ltd | 画像処理装置 |
JP2003216131A (ja) * | 2001-11-19 | 2003-07-30 | Matsushita Electric Ind Co Ltd | 表示制御装置、画像表示装置および制御データ転送方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03219291A (ja) * | 1989-11-09 | 1991-09-26 | Matsushita Electric Ind Co Ltd | 大画面画像表示法 |
WO1998044479A1 (fr) * | 1997-03-31 | 1998-10-08 | Matsushita Electric Industrial Co., Ltd. | Procede de visualisation du premier plan d'images et dispositif connexe |
KR100364705B1 (ko) * | 2000-05-18 | 2002-12-16 | 엘지전자 주식회사 | 동기유도 전동기의 회전자 |
KR100438918B1 (ko) * | 2001-12-08 | 2004-07-03 | 엘지전자 주식회사 | 플라즈마 디스플레이 패널의 구동방법 및 장치 |
-
2004
- 2004-05-24 JP JP2004152805A patent/JP4200321B2/ja not_active Expired - Fee Related
-
2005
- 2005-05-24 KR KR1020077020306A patent/KR100868128B1/ko not_active IP Right Cessation
- 2005-05-24 KR KR1020087005803A patent/KR20080028515A/ko not_active Application Discontinuation
- 2005-05-24 CN CNB2005800005377A patent/CN100476913C/zh not_active Expired - Fee Related
- 2005-05-24 WO PCT/JP2005/009833 patent/WO2005114625A1/ja active Application Filing
- 2005-05-24 US US10/563,509 patent/US20060165278A1/en not_active Abandoned
- 2005-05-24 KR KR1020067001097A patent/KR20060032639A/ko active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH104516A (ja) * | 1996-06-18 | 1998-01-06 | Canon Inc | 情報処理システムおよび情報処理方法 |
JP2001092436A (ja) * | 1999-09-24 | 2001-04-06 | Olympus Optical Co Ltd | 画像処理装置 |
JP2003216131A (ja) * | 2001-11-19 | 2003-07-30 | Matsushita Electric Ind Co Ltd | 表示制御装置、画像表示装置および制御データ転送方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20070096061A (ko) | 2007-10-01 |
US20060165278A1 (en) | 2006-07-27 |
JP4200321B2 (ja) | 2008-12-24 |
KR20060032639A (ko) | 2006-04-17 |
KR100868128B1 (ko) | 2008-11-10 |
CN100476913C (zh) | 2009-04-08 |
KR20080028515A (ko) | 2008-03-31 |
JP2005338123A (ja) | 2005-12-08 |
CN1806271A (zh) | 2006-07-19 |
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