Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/10—Intensity circuits
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/14—Picture signal circuitry for video frequency region
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2360/00—Aspects of the architecture of display systems
  • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/04—Synchronising
  • H04N5/08—Separation of synchronising signals from picture signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/14—Picture signal circuitry for video frequency region
  • H04N5/20—Circuitry for controlling amplitude response

Definitions

• the present invention relates to a luminance signal processing device and a luminance signal processing method for performing sampling processing of a video luminance signal.
• FIG. 24 is a block diagram of a conventional luminance signal sampling processing device.
• the thinning reference value setting section 401 of the sampling processing device in the conventional luminance signal processing device is configured as follows. First, the counter 501 is reset every time the vertical differential signal S211 is input. The load hold means 503 loads the output of the counter 01 by the horizontal differential signal S210. The load hold means 503 supplies the loaded output value of the counter 501 to the counter 501 as an input to the counter 501. The counter 501 counts the number of lines by counting the output value of the load holding means 503.
• n bits corresponding to the number of bits corresponding to the repetition pattern of the luminance signal to be thinned out from the number of lines output from the load hold means 503 are extracted from the lower bits and supplied to the counter 502.
• the lower bits described here are taken out of the output power of the load hold means 503. Therefore, every time the number of lines to be processed changes, n bits are taken out. It changes like 1, 2, 3, 0, 1, 2, 3, ....
• the counter 502 counts according to the reference clock, using the lower n bits extracted from the load hold means 503 as an initial value. Since the initial value supplied to the counter 502 differs for each line processed by the lower n bits of the load hold means 503, the value for starting counting differs for each line. Then, the output of the counter 502 becomes the thinning reference value S411.
• Fig. 25 shows a conventional sampling example (an example of generation of the thinning reference value S411).
• one square corresponds to one pixel on the display screen, and the vertical direction corresponds to a line.
• the thinning reference value S411 is such that the value of the first line is "00", the value of the second line is "01" in binary, the value of the third line is “10”, and the value of the fourth line is “00".
• 11 ", the value of the fifth line is" 00 ", and the position where the count is started differs for each line.
• Patent Document 1 WO01 / 039489 (Pages 11-14, Figures 5-7)
• the present invention solves the above-mentioned conventional problem. Even when a luminance signal of a fixed pattern or a repetitive pattern in an oblique direction is input, the luminance signal sampling processing without increasing the circuit scale is performed. In addition, it is an object of the present invention to provide a luminance signal processing device capable of performing accurate and uniform sampling in the vertical, horizontal, and oblique directions on a screen by adjusting sampling pixel positions in line units and field units. With the goal.
• the present invention adjusts sampling pixel positions on a scanning line on a line-by-line or field-by-line basis, so that the vertical, horizontal, and oblique directions on a screen are random and even.
• the sampling position can be specified.
• the luminance signal processing device of the present invention is configured to include the following plurality of components. That is,
• a luminance signal output circuit for selectively outputting a sampled luminance signal when the sample window circuit is valid.
• the luminance signal processing device of the present invention may be composed of the following plural components. That is,
• a differential operation circuit that outputs
• a first counter circuit that counts the number of pixels in one horizontal period by resetting with the horizontal differential signal
• a first AND circuit that performs an AND operation on the horizontal differential signal and the output signal of the first counter circuit
• a first delay circuit for delaying the output signal of the first AND circuit in clock units, and a horizontal thinning adjustment for thinning while adjusting the number of pixels to be thinned in one horizontal period from the output signal of the first delay circuit.
• a first sampling effective period in a horizontal period in which a point at which the output result of the horizontal thinning adjustment circuit and the horizontal period end signal are reset is set as a set;
• a second AND circuit that detects a coincidence between the first sampling valid period and the output result of the horizontal thinning adjustment circuit
• a second signal for delaying the output signal of the second AND circuit by N pixels (N is a natural number of 1 or more) 2 delay circuits
• a first sampling pixel position switching signal generation circuit that generates a sampling pixel position switching signal that repeats inversion every horizontal cycle from the horizontal differential signal
• the total number of pixels in one horizontal period is counted by the first counter circuit, the first AND circuit, and the first delay circuit. Then, the number of sampling pixels in one horizontal period is reduced by the next horizontal thinning adjustment circuit. For example, in the case of thinning out every (N X 2) pixels, a thinning signal is generated in which each (N X 2) pixel is a valid bit and the others are invalid bits.
• the set / reset circuit determines the sampling valid period from the horizontal period start signal, the horizontal period end signal, and the output result of the horizontal thinning adjustment circuit.
• the output of the second AND circuit which detects a point where the sampling valid period matches the thinning signal, determines a horizontal sampling window period for performing sampling for each (N X 2) pixel.
• the second delay circuit further delays the sample window period for each (N X 2) pixel by N pixels. As a result, a sample window ⁇ period of two selection candidates having different positions in the horizontal direction is obtained. The sample window periods of these two selection candidates are input to the first selection circuit.
• the sampling pixel position switching signal generation circuit repeats the inversion of 0, 1, 0, 1,... In units of one horizontal cycle (one line) based on the horizontal differential signal. Generate a replacement signal.
• the first selection circuit is controlled based on the sampling pixel position switching signal. As a result, in the first selection circuit, the first sample window ⁇ period is selected in a certain horizontal period, and the second sample window period is selected in the subsequent horizontal period. An alternating sample window signal is obtained.
• N 4
• the sampling pixel position on the scanning line can be adjusted in units of one line by adjusting the pixel interval of the thinning in the horizontal thinning adjustment circuit, and the sampling position in the horizontal direction on the screen can be freely and freely. It can be specified equally. Therefore, it is possible to accurately sample a luminance signal even for a fixed pattern or a pattern of a repetitive pattern. In sampling the luminance signal, it is not necessary to sample all pixels. Further, it is possible to cope with a plurality of types of broadcasting systems having different effective pixel numbers.
• the following components may be further added. It also:
• a second counter circuit for counting the total number of lines in one vertical period
• a third AND circuit that performs a logical AND operation on the vertical differential signal and an output signal of the second counter circuit
• a load-hold circuit for load-holding the output signal of the third AND circuit with the horizontal differential signal
• a third comparison circuit that compares a signal obtained by bit-shifting the output signal of the vertical direction thinning adjustment circuit with a vertical period start signal
• a fourth comparison circuit that compares a signal obtained by bit-shifting the output signal of the vertical thinning adjustment circuit with the vertical period end signal
• a second set / reset circuit that generates a second sampling valid period signal based on a comparison result obtained by the third comparison circuit and a comparison result obtained by the fourth comparison circuit; and a second sampling valid period signal.
• a fourth AND circuit for performing an AND operation on the output signal of the vertical thinning adjustment circuit and
• a sampling pixel position switching signal generation circuit for generating a sampling pixel position switching signal
• a fifth AND circuit that performs a logical AND operation on the output signal of the first selection circuit and the output signal of the fourth AND circuit to generate a sample window signal is added.
• the sampling pixel position on the scanning line can be adjusted in units of one line, and the line interval of thinning in the vertical thinning adjustment circuit can be adjusted.
• the sampling pixel position on the scanning line can be adjusted by a predetermined number of lines. This makes it possible to arbitrarily and uniformly specify sampling positions in the vertical, horizontal, and oblique directions on the screen. Therefore, it is possible to accurately sample a luminance signal even for a fixed pattern or a repetitive pattern. In sampling the luminance signal, it is not necessary to sample all pixels. Furthermore, it can support a plurality of types of broadcasting systems having different numbers of effective pixels and effective lines.
• the following plurality of components may be further added. It also:
• An inverting circuit that inverts the sampling pixel position switching signal to generate an inverted sampling pixel position switching signal
• a field switching signal generation circuit that generates a field switching signal that repeats inversion at a vertical cycle from the vertical differential signal color
• a second selection circuit that selects one of the sampling pixel position switching signal and the inverted sampling pixel position switching signal based on the field switching signal.
• the first selection circuit is controlled by a sampling pixel position switching signal from the second selection circuit instead of the sampling pixel position switching signal by the sampling pixel position switching signal generation circuit.
• the field switching signal generation circuit is connected to a delay circuit to which the vertical differential signal is supplied as a clock, and counts the output of the delay circuit. It can be configured with an adder circuit that goes up.
• the adjustment of the sampling pixel position on the scanning line in units of a predetermined number of lines can be switched in units of fields.
• one output signal is output from the plurality of horizontal thinning adjustment circuits based on the sampling pixel position switching signal.
• a selection circuit for selecting and outputting the selected signal to the second AND circuit may be provided.
• the sampling pixel position switching signal generation circuit may generate the sampling pixel position switching signal from the output signal of the fourth AND circuit, instead of generating the sampling pixel position switching signal from the vertical minute signal, every one vertical period. Then, a field switching signal for controlling the first selection circuit may be generated.
• the sampling position can be arbitrarily specified in the horizontal direction on the screen. Further, by shifting the sampling pixel position for each field, the arbitrariness can be further improved.
• a field switching signal generation circuit that generates a field switching signal that repeats inversion in a vertical cycle from the vertical differential signal
• a selection circuit that selects one output signal of the plurality of vertical thinning adjustment circuits based on a field switching signal and outputs the selected output signal to the fourth AND circuit. According to this configuration, it is possible to arbitrarily specify the sampling position along the vertical direction on the screen. Further, by making the number of sampling lines variable for each field, the arbitrariness can be further improved.
• the luminance signal processing device of the present invention may include the following plural components. That is,
• the sampling pixel position switching signal generation circuit generates the sampling pixel position switching signal based on the output signal of the vertical thinning adjustment circuit instead of the output signal of the fourth AND circuit,
• a sampling line position switching signal generation circuit that generates a sampling line position switching signal in which a sampling line position is changed using an output signal of the horizontal direction thinning adjustment circuit as a reset signal;
• An inverting circuit for inverting the sampling line position switching signal for inverting the sampling line position switching signal
• a field switching signal generation circuit that generates a field switching signal that switches the sampling line position by using the vertical differentiation signal as a reset signal
• a third selection circuit that selects one of the sampling line switching signal and the output of the inverting circuit based on the field switching signal
• a line memory that delays an output signal of the vertical direction thinning adjustment circuit and switches a sampling pixel position for each line in the vertical direction;
• a fourth selection circuit that selects one of an output signal of the vertical thinning adjustment circuit and an output signal of the line memory circuit based on an output signal of the third selection circuit. It is.
• the field switching signal generation circuit generates a field switching signal for switching the second selection circuit in units of a plurality of fields by using the vertical differential signal as a reset signal. Then, based on this field switching signal, the sampling line position may be switched for each of a plurality of fields.
• the sampling position can be arbitrarily and uniformly designated along the vertical, horizontal, and oblique directions on the screen. Further, by shifting the sampling pixel position in the horizontal direction for each of a plurality of fields, the arbitrariness and uniformity can be further improved.
• the horizontal differential signal synchronized with the horizontal synchronous signal and the vertical differential signal synchronized with the vertical synchronous signal are obtained by detecting the rising edge or the falling edge of the horizontal synchronous signal and the vertical synchronous signal of the input video signal and performing differential operation.
• the sample window signal set at an arbitrary position in the vertical direction and the vertical direction on the screen is converted into the horizontal differential signal and the vertical differential signal.
• Each circuit constituting the present invention described above can also be constituted by software that is not only a combination of an electronic component and a wiring pattern.
• the sampling position on the scanning line in N line units and ⁇ field units ( ⁇ and ⁇ are natural numbers of 1 or more) Since the sampling position can be arbitrarily and uniformly specified along the vertical and diagonal directions on the screen, it is possible to accurately sample the luminance signal even for a fixed pattern or a repetitive pattern. It becomes.
• FIG. 1 is a block diagram showing an overall configuration of a luminance signal processing device according to the present invention.
• FIG. 2 is a diagram showing how a horizontal sample window signal of the present invention is generated.
• FIG. 3 is a diagram showing how a vertical sample window signal of the present invention is generated.
• FIG. 4 is a block diagram showing a configuration of a sample window circuit according to Embodiment 1 of the present invention.
• FIG. 5A is a block diagram showing a configuration of a sampling pixel position switching signal generation circuit according to Embodiment 1 of the present invention.
• FIG. 5B is a timing diagram of the sampling pixel position switching signal generation circuit according to Embodiment 1 of the present invention.
• FIG. 6A is a first diagram showing a state of a sample window signal according to Embodiment 1 of the present invention.
• FIG. 6B is a second diagram showing a state of the sample window signal according to the first embodiment of the present invention.
• FIG. 7 is a block diagram showing a configuration of a sample window circuit according to Embodiment 2 of the present invention.
• FIG. 8A is a first diagram showing a state of a sample window signal according to Embodiment 2 of the present invention.
• FIG. 8B is a second diagram showing a state of a sample window signal according to Embodiment 2 of the present invention.
• FIG. 9 is a block diagram showing a configuration of a sample window circuit according to Embodiment 3 of the present invention.
• FIG. 10A is a block diagram showing a configuration of a field switching signal generation circuit according to Embodiment 3 of the present invention.
• FIG. 10B is a timing chart of the field switching signal generation circuit according to Embodiment 3 of the present invention. It is.
• FIG. 11A is a first diagram illustrating a state of a sample window signal according to Embodiment 3 of the present invention.
• FIG. 11B is a second diagram showing a state of a sample window signal according to Embodiment 3 of the present invention.
• FIG. 11C is a third diagram showing a state of the sample window signal in the third embodiment of the present invention.
• FIG. 11D is a fourth diagram showing a state of the sample window signal in the third embodiment of the present invention.
• FIG. 12 is a block diagram showing a configuration of a sample window circuit according to a fourth embodiment of the present invention.
• FIG. 13A is a first diagram illustrating a state of a sample window signal according to Embodiment 4 of the present invention.
• FIG. 13B is a second diagram showing a state of a sample window signal according to Embodiment 4 of the present invention.
• FIG. 14 is a block diagram showing a configuration of a sample window circuit according to a fifth embodiment of the present invention.
• FIG. 15A is a first diagram showing a state of a sample window signal according to Embodiment 5 of the present invention.
• FIG. 15B is a second diagram showing a state of the sample window signal according to the fifth embodiment of the present invention.
• FIG. 15C is a third diagram showing a state of the sample window signal in the fifth embodiment of the present invention.
• FIG. 15D is a fourth diagram showing a state of the sample window signal in the fifth embodiment of the present invention.
• FIG. 16 is a block diagram showing a configuration of a sample window circuit according to a sixth embodiment of the present invention.
• FIG. 17A is a first diagram showing a state of a sample window signal according to the sixth embodiment of the present invention.
• FIG. 17B is a second diagram illustrating a state of the sample window signal in the sixth embodiment of the present invention.
• FIG. 17C is a third diagram showing the appearance of the sample window signal in the sixth embodiment of the present invention.
• [17D] A fourth diagram showing the appearance of the sample window signal in the sixth embodiment of the present invention.
• FIG. 18 is a block diagram showing a configuration of a sample window circuit according to a seventh embodiment of the present invention.
• FIG. 19 is a timing chart illustrating the operation of the seventh embodiment of the present invention.
• FIG. 20A is a first diagram illustrating a state of a sample window signal according to the seventh embodiment of the present invention.
• FIG. 20B is a second diagram illustrating the appearance of the sample window signal in the seventh embodiment of the present invention.
• FIG. 20C is a third diagram illustrating the appearance of the sample window signal in the seventh embodiment of the present invention.
• FIG. 20D is a fourth diagram illustrating the appearance of the sample window signal in the seventh embodiment of the present invention.
• FIG. 21 is a block diagram showing a configuration of a sample window circuit according to an eighth embodiment of the present invention.
• FIG. 22B is a block diagram illustrating a configuration of a field switching signal generation circuit in units of a plurality of fields according to Embodiment 8 of the present invention.
• FIG. 22B is a timing chart of the field switching signal generation circuit in the eighth embodiment of the present invention.
• FIG. 23A is a first diagram illustrating a state of a sample window signal according to the eighth embodiment of the present invention.
• FIG. 23B is a second diagram illustrating a state of the sample window signal in the eighth embodiment of the present invention.
• FIG. 23C is a third diagram showing a state of the sample window signal in the eighth embodiment of the present invention.
• FIG. 23D is a fourth diagram showing the appearance of the sample window signal in the eighth embodiment of the present invention.
• FIG. 24 is a block diagram showing a configuration of a conventional luminance signal processing device.
• FIG. 25 is a diagram showing a state of a sample window signal in a conventional luminance signal processing device.
• FIG. 1 is a block diagram of a luminance signal processing device according to the present invention.
• the horizontal operation signal S 1 and the vertical operation signal S 2 from which the video signal power is extracted are input to the differential operation circuit 1.
• the differential operation circuit 1 outputs a horizontal differential signal S3 and a vertical differential signal S4 by detecting the edges of the horizontal synchronizing signal S1 and the vertical synchronizing signal S2 and then performing differentiation. Edge detection may be either a rising edge or a falling edge. To detect the rising edge of the horizontal synchronizing signal S1, delay the horizontal synchronizing signal S1 (for example, one clock delay) and take the logical product of the inverted version of the delayed signal and the horizontal synchronizing signal S1. Good.
• the vertical differential signal S4 can also be obtained by the above-described configuration for generating the horizontal differential signal S3.
• the sample window circuit 2 includes a horizontal differential signal S3, a vertical differential signal S4, a horizontal period start signal S5 as a start point when the luminance signal is sampled in the horizontal direction, and a horizontal period end signal S6 as an end point. Then, a vertical period start signal S7 as a start point when the luminance signal is sampled in the vertical direction and a vertical period end signal S8 as an end point are input. Sample ⁇ The window circuit 2 generates and outputs a sample window signal S9 from these signals S3-S8.
• FIG. 2 illustrates how a horizontal sample window period is generated.
• the value of the horizontal period start signal S5 is "10" and the value of the horizontal period end signal S6 is "250", and the number of pixels in one horizontal period is counted by the horizontal differential signal S3.
• the point where the counted number of pixels in the horizontal period matches the value of the horizontal period start signal S5 is the start point of the horizontal sample window period.
• the point where the count number of pixels in one horizontal period matches the value of the horizontal period end signal S6 is the end point of the horizontal sample window period.
• FIG. 3 shows how a sample window period in the vertical direction is generated.
• the value of the vertical period start signal S7 is "10" and the value of the vertical period end signal S8 is "250"
• the number of lines in one vertical period is counted by the vertical differential signal S4.
• the point where the count of the number of lines in the vertical period matches the value of the vertical period start signal S7 is the start point of the sample window period in the vertical direction.
• the point where the count of the number of lines in one vertical period matches the value of the vertical period end signal S8 is the end point of the sample window period in the vertical direction.
• the sample window signal S 9 is finally output from the sample window circuit 2. Also, by inputting the sample window signal S9 and the video luminance signal S10 to the AND circuit 3, a luminance signal S11 after the sample window processing is obtained.
• FIG. 4 is a block diagram showing a configuration of the sample window circuit 2 according to the first embodiment.
• reference numeral 4 denotes a first counter circuit for adding pixel data of a luminance signal in one horizontal period.
• Reference numeral 5 denotes a first AND circuit to which the horizontal differential signal S3 and the count signal S12 of the first counter circuit 4 are input.
• 6 is a first delay circuit.
• Reference numeral 7 denotes a horizontal thinning adjustment circuit for thinning the pixel data of the luminance signal in one horizontal period.
• the horizontal thinning adjustment circuit 7 can adjust the pixel interval of the thinning.
• 8 is between horizontal This is a first comparison circuit that compares the output of the pull adjustment circuit 7 (bit-shifted bit shift signal S16) with the horizontal period start signal S5.
• Reference numeral 9 denotes a second comparison circuit that compares the bit shift signal S16 with the horizontal period end signal S6.
• Reference numeral 10 denotes a first set / reset circuit that sets the output of the first comparison circuit 8 and the output of the second comparison circuit 9 to a sampling valid period.
• Reference numeral 11 denotes a second logical AND process between the horizontal sampling effective period signal S19 output from the first set / reset circuit 10 and the horizontal thinning signal S15 output from the horizontal thinning adjustment circuit 7. Is an AND circuit.
• 12 is a second delay circuit.
• Reference numeral 13 denotes a sampling pixel position switching signal generation circuit that generates a sampling pixel position switching signal S22.
• the sampling pixel position switching signal generation circuit 13 generates a sampling pixel position switching signal S22 based on the horizontal differential signal S3.
• the sampling pixel position switching signal S22 is a signal that repeats the inversion of 0, 1, 0, 1,... 14 is a first selection circuit.
• FIG. 5 is a block diagram showing a specific configuration of the sampling pixel position switching signal generation circuit 13.
• reference numeral 24 denotes a counter circuit.
• Reference numeral 25 denotes a delay circuit to which the horizontal differential signal S3 is input as a clock.
• the horizontal differential signal S3 is input to the first AND circuit 5 as a reset signal, the count of the total number of pixels of the luminance signal in one horizontal cycle is reset.
• the output signal S13 of the first AND circuit 5 is input to the first delay circuit 6, where it is delayed in clock units, and its output is input to the first counter circuit 4, where it is counted up. To go.
• the total pixel count signal S14 is generated by the operations of the first counter circuit 4, the first AND circuit 5, and the first delay circuit 6.
• the pixel count signal S14 indicates a value obtained by counting the total number of pixels in one horizontal cycle.
• the generated total pixel count signal S14 is input to the horizontal thinning adjustment circuit 7.
• the horizontal thinning adjustment circuit 7 generates and outputs a horizontal thinning signal S15 based on the total pixel count signal S14.
• the horizontal thinning signal S15 is a signal for thinning the total pixel data of the luminance signal in one horizontal period, for example, every eight pixels. No. For example, when thinning out every eight pixels, the horizontal thinning signal S15 is 1 for every 8 pixels, and 0 for the others.
• S 16 is a bit shift signal that is bit-shifted by the number of thinning bits, and is output from the horizontal thinning adjustment circuit 7. In the horizontal direction thinning adjustment circuit 7, the pixel interval of thinning can be adjusted.
• the total pixel count signal S14 output from the first delay circuit 6 is the sum of all the pixel numbers within one horizontal period, and the higher the definition of the broadcast format becomes, the higher the total number of pixels in one horizontal period becomes.
• the number of pixels, that is, the count value of the total pixel number count signal S14 increases. Therefore, the number of bits of the first counter circuit 4, the first AND circuit 5, and the first delay circuit 6 must be increased as the total number of pixels in one horizontal period increases.
• the horizontal thinning adjustment circuit 7 can reduce the number of bits of the bit shift signal S16 according to the number of thinned bits. For example, when thinning out every eight pixels, the bit shift signal S16 is shifted by three bits. Therefore, as the number of thinning increases, the number of bits of the bit shift signal S16 can be reduced. Therefore, as the number of thinnings increases, the number of bits of the first comparing circuit 8 and the second comparing circuit 9 can be reduced.
• the bit shift signal S 16 that has been bit-shifted by the horizontal thinning adjustment circuit 7 and the horizontal period start signal S 5 are input to the first comparison circuit 8.
• the first comparison circuit 8 generates and outputs a match detection signal S17 by detecting a match between the bit shift signal S16 and the horizontal period start signal S5.
• the bit shift signal S 16 and the horizontal period end signal S 6 output from the horizontal thinning adjustment circuit 7 are input to the second comparison circuit 9.
• the second comparing circuit 9 generates and outputs a match detection signal S18 by detecting a match between the bit shift signal S16 and the horizontal period end signal S6.
• the match detection signal S17 and the match detection signal S18 are input to the first set / reset circuit 10.
• the first set / reset circuit 10 generates and outputs a horizontal sampling valid period signal S19 in one horizontal cycle from the coincidence detection signals S17 and S18.
• the horizontal thinning signal S15 and the horizontal sampling valid period signal S19 are input to the third AND circuit 11.
• the third AND circuit 11 connects the horizontal decimated signal S15 to the horizontal sampled signal S15. From the pulling valid period signal S19, a horizontal thinning sampling signal S20 during the valid period of one horizontal cycle is generated and output to the first selecting circuit 14 and the second delay circuit 12.
• the second delay circuit 12 delays the horizontal decimated sampling signal S20 by N pixels (N is a natural number equal to or greater than 1) to produce a delayed horizontal decimated sampling signal S21, and outputs the result to the first selection circuit 14. Output.
• the horizontal differential signal S3 is input to the sampling pixel position switching signal generation circuit 13.
• the sampling pixel position switching signal generation circuit 13 generates a sampling pixel position switching signal S22 from the horizontal differential signal S3 and outputs the generated signal to the first selection circuit 14.
• the sampling pixel position switching signal S22 is a signal that repeats inversion of 0, 1, 0, 1,... In units of one horizontal cycle.
• the first selection circuit 14 controls the selection operation based on the sampling pixel position switching signal S22 supplied from the sampling pixel position switching signal generation circuit 13, thereby performing horizontal sampling in units of one horizontal cycle.
• a sample window signal S9 for shifting the pixel position is generated and output.
• FIG. 6A shows a state of sample window signal S 9 for each horizontal cycle in the first embodiment.
• the signal located at the top indicates the top line on the screen.
• the first line repeats the inversion of 0, 1, 0, 1, ... for the start point
• the second line repeats the inversion of 1, 0, 1, 0, ... from the start point
• the third line is the same as the first line
• the inversion of the starting point force 0, 1, 0, 1, ... is repeated
• the fourth line repeats the inversion of 1, 0, 1, 0, ... from the starting point in the same way as the second line.
• FIG. 6B shows a sampling position (square symbol) on the screen by the sample window signal S9 of FIG. 6A. Sampling is performed in 8-pixel units in the horizontal direction and in 1-line units in the vertical direction. The sampling pixel position is shifted by 4 pixels in the horizontal direction in units of 1 line.
• the horizontal thinning adjustment circuit 7 can adjust the pixel interval of thinning.
• the sampling position can be arbitrarily and uniformly designated in the vertical direction on the screen.
• FIG. 7 is a block diagram showing a configuration of the sample window circuit 2 shown in FIG. 1 according to the second embodiment. 7 differs from FIG. 4 in the first embodiment in that The point is that a circuit configuration is further added.
• the added configuration is as follows.
• Reference numeral 15 denotes a second counter circuit that counts the total number of lines in one vertical period.
• Reference numeral 16 denotes a third AND circuit that performs a logical product operation between the vertical differential signal S4 and the count signal S24.
• Reference numeral 17 denotes a load-hold circuit for load-holding the output signal S25 of the third AND circuit 16 with the horizontal differential signal S3.
• Reference numeral 18 denotes a vertical thinning adjustment circuit that thins out the lines to be sampled from all the lines in one vertical period. The vertical thinning adjustment circuit 18 can adjust the line interval of the thinning.
• Reference numeral 19 denotes a third comparison circuit that compares the bit-shifted signal S28 with the vertical period start signal S7.
• Reference numeral 20 denotes a fourth comparison circuit that compares the bit shift signal S28 with the vertical period end signal S8.
• the bit-shifted signal S28 is supplied from the vertical thinning adjustment circuit 18.
• Reference numeral 21 denotes a second set / reset circuit that sets the output of the third comparison circuit 19 and the output of the fourth comparison circuit 20 during the sampling valid period.
• Reference numeral 22 denotes a fourth AND circuit that performs a logical AND operation between the vertical sampling valid period signal S31 output from the second set / reset circuit 21 and the vertical thinning signal S27 that also outputs the vertical thinning adjustment circuit 18. Is an AND circuit.
• Reference numeral 26 denotes a sampling pixel position switching signal generation circuit that generates a sampling pixel position switching signal S33.
• the sampling pixel position switching signal S33 repeats inversion of 0, 1, 0, 1,... In units of thinning lines.
• the sampling pixel position switching signal generation circuit 26 generates a sampling pixel position switching signal S33 based on the output signal S32 of the fourth AND circuit 22.
• Reference numeral 23 denotes a fifth AND circuit that performs a logical product operation between the output signal S23 of the first selection circuit 14 and the output signal S32 of the fourth AND circuit 22.
• the output signal of the fifth AND circuit 23 is the sample window signal S9.
• the other configuration is the same as that of the first embodiment, and a description of the configuration and operation will be omitted.
• the vertical thinning adjustment circuit 18 generates and outputs a vertical thinning signal S27 based on the total line count signal S26.
• the vertical thinning signal S27 is a signal for thinning the total number of lines in one vertical period, for example, every four lines.
• S28 is a bit shift signal obtained by performing a bit shift by the number of bits of the bow I, and is output from the vertical bow I adjustment circuit 18.
• the thinning line interval is adjustable.
• the bit shift signal S 28 subjected to the bit shift processing in the vertical direction thinning adjustment circuit 18 and the vertical period start point signal S 7 are input to the third comparison circuit 19.
• the third comparison circuit 19 generates and outputs a match detection signal S29 by detecting a match between the bit shift signal S28 and the vertical period start signal S7.
• the bit shift signal S 28 output from the vertical direction thinning adjustment circuit 18 and the vertical period end signal S 8 are input to the fourth comparison circuit 20.
• the fourth comparison circuit 20 generates and outputs a match detection signal S30 by detecting a match between the bit shift signal S28 and the vertical period end signal S8.
• the match detection signal S29 and the match detection signal S30 are input to the second set / reset circuit 21.
• the second set / reset circuit 21 generates and outputs a sampling effective period signal S31 in the vertical direction in one vertical period from the coincidence detection signals S29 and S30.
• the vertical thinning signal S27 and the vertical sampling valid period signal S31 are input to the fourth AND circuit 22.
• the fourth AND circuit 22 generates a vertical sampling signal S32 for one vertical period from the vertical sampling signal S27 and the vertical sampling valid period signal S31 to generate a sampling pixel position switching signal.
• the sampling pixel position switching signal generation circuit 26 generates a sampling pixel position switching signal S33 that repeats inversion of 0, 1, 0, 1,...
• the first selection circuit 14 In units of a thinning vertical cycle based on the vertical thinning sampling signal S32. And outputs it to the first selection circuit 14.
• the first selection circuit 14 generates and outputs a horizontal decimated sampling signal S23 that shifts the sampling pixel position in the horizontal direction by one horizontal cycle.
• the selection operation of the first selection circuit 14 is controlled by the sampling pixel position switching signal S33 supplied from the sampling pixel position switching signal generation circuit 26.
• the output of the first selection circuit 14 (horizontal decimated sampling signal S23) and the output of the fourth AND circuit 22 (vertical decimated sampling signal S32) are input to the fifth AND circuit 23.
• the fifth AND circuit 23 generates a sample window signal S9 for shifting the sampling pixel position in the horizontal direction by a thinned vertical cycle unit based on the supplied horizontal thinned sampling signal S23 and vertical thinned sampling signal S32.
• FIG. 8A shows a state of sample window signal S 9 for each horizontal cycle in the second embodiment.
• the fourth line also repeats the inversion of 0, 1, 0, 1, ... for the starting point
• the eighth line repeats the inversion of 1, 0, 1, 0, ... from the starting point
• the twelfth line is the same as the fourth line
• the inversion of the starting point force 0, 1, 0, 1, ... is repeated
• the 16th line repeats the inversion of 1, 0, 1, 0, ... from the starting point like the 8th line.
• FIG. 8B shows a sampling position on the screen by the sample window signal S9 of FIG. 8A.
• Sampling is performed in units of 8 pixels in the horizontal direction and in units of 4 lines in the vertical direction.
• the sampling pixel position is shifted by 4 pixels in the horizontal direction. That is, the sampling pixel positions are shifted in the horizontal direction in units of four lines.
• the pixel interval of the thinning is adjusted by the horizontal thinning adjustment circuit 7.
• the thinning line interval is adjusted by the vertical thinning adjustment circuit 18.
• the sampling position can be arbitrarily and uniformly designated in the vertical, horizontal, and oblique directions on the screen.
• FIG. 9 is a block diagram showing a configuration of the sample window circuit 2 according to the third embodiment shown in FIG. 9 differs from the configuration of Embodiment 2 (FIG. 7) in that some circuit configurations are further added.
• the configuration after the addition is as follows.
• Reference numeral 27 denotes an inversion circuit that inverts the sampling pixel position switching signal S33 output from the sampling pixel position switching signal generation circuit 26 to generate an inverted sampling pixel position switching signal S35.
• 29 is a field switching signal generation circuit for generating a field switching signal S35.
• the field switching signal generation circuit 29 generates a field switching signal S35 based on the vertical differential signal S4.
• the field switching signal S35 repeats inversion of 0, 1, 0, 1,... In units of one vertical cycle by the vertical differential signal S4.
• 28 is a second selection circuit.
• the second selection circuit 28 selects the sampling pixel position switching signal S33 and the inverted sampling pixel position switching signal S34 based on the field switching signal S35 supplied from the field switching signal generation circuit 29, and Output to selection circuit 14.
• the other configuration is the same as that of FIG. 7 in the second embodiment, and thus the description of the configuration and operation is omitted.
• the sampling pixel position switching signal S33 output from the sampling pixel position switching signal generation circuit 26 and the inverted sampling pixel position switching signal S34 output from the inversion circuit 27 are input to the second selection circuit 28.
• the vertical differential signal S4 is input to the field switching signal generation circuit 29.
• the field switching signal generation circuit 29 generates a field switching signal S35 that repeats inversion of 0, 1, 0, 1,... In units of one vertical cycle based on the vertical differentiation signal S4, and outputs the field switching signal S35 to the second selection circuit 28. Output.
• the second selection circuit 28 selects one of the sampling pixel position switching signal S33 and the inverted sampling pixel position switching signal S34 based on the supplied field switching signal S35.
• the second selection circuit 28 outputs the selected signal (S33 or S34) to the first selection circuit 14 as a final sampling pixel position switching signal S36.
• FIG. 10A shows a specific configuration of the field switching signal generation circuit 29.
• 30 is a counter circuit.
• Reference numeral 31 denotes a delay circuit to which the vertical differential signal S4 is input as a clock.
• the field switching signal S35 repeats the inversion of 0, 1, 0, 1,... In the vertical cycle.
• FIG. 11A to FIG. 11D show states of sample window signal S9 in the present embodiment. You.
• FIG. 11A shows the state of sample window signal S 9 every one horizontal cycle in thinning out one field before.
• Line 4 repeats the inversion of 1, 0, 1, 0,... from the starting point
• Line 8 repeats the inversion of the starting force 0, 1, 0, 1,...
• Line 12 is the same as Line 4.
• the inversion of 1, 0, 1, 0, ... is repeated from the starting point
• the 16th line repeats the inversion of the starting point force 0, 1, 0, 1, ... in the same way as the 8th line.
• FIG. 11B shows the sampling position on the screen by the sample window signal S9 of FIG. 11A.
• Sampling is performed in units of 8 pixels in the horizontal direction and in units of 4 lines in the vertical direction.
• the sampling pixel position is shifted by 4 pixels in the horizontal direction. That is, the sampling pixel positions are shifted in the horizontal direction in units of four lines.
• sampling is performed on the 8th, 16th, and 24th pixels.
• sampling is performed on the 12th, 20th, and 28th pixels.
• sampling is performed at the 8th, 16th, and 24th pixels.
• sampling is performed at the 12th, 20th, and 28th pixels, as with the 8th line.
• sampling is performed at the 12th, 20th, and 28th pixels, as with the 8th line.
• FIG. 11C shows the state of sample window signal S9 every one horizontal cycle of thinning out after one field of FIG. 11A.
• the fourth line repeats the inversion of 0, 1, 0, 1,... for the starting point
• the eighth line repeats 1, 0, 1, 0,... from the starting point
• the twelfth line is the same as the fourth line
• the starting point repeats the inversion of 0, 1, 0, 1,...
• the 16th line repeats the inversion of 1, 0, 1, 0,.
• FIG. 11D shows a sampling position on the screen by the sample window signal S9 of FIG. 11C. It is shifted by 4 pixels in the horizontal direction from the sampling pixel position shown in FIG. 11B. That is, the fourth line is sampled at the 12th, 20th, and 28th pixels, the 8th line is sampled at the 8th, 16th, and 24th pixels, and the 12th line is sampled in the same manner as the 4th line Sampling is performed at the 12th, 20th, and 28th pixels. At the 16th line, sampling is performed at the 8th, 16th, and 24th pixels, as with the 8th line. .
• sampling positions can be arbitrarily and uniformly designated in the vertical, horizontal, and oblique directions on the screen. Therefore, it is possible to shift the sampling pixel position for each field, and it is possible to set the sampling position arbitrarily and evenly. The performance is further improved.
• FIG. 12 is a block diagram showing a configuration of the fourth embodiment of the sample window circuit 2 shown in FIG. FIG. 12 differs from FIG. 7 in the second embodiment in that some circuit configurations are further added.
• the added configuration is as follows.
• Reference numeral 32 denotes a first horizontal thinning adjustment circuit that thins out pixel data of a luminance signal in one horizontal period by a first thinning method (for example, thinning every eight pixels). The first horizontal thinning adjustment circuit 32 can adjust the pixel interval of the thinning.
• Reference numeral 33 denotes a second horizontal thinning adjustment circuit that thins out the luminance signal pixel data in one horizontal period by a second thinning method (for example, thinning out every four pixels). The second horizontal thinning adjustment circuit 33 can adjust the pixel interval of the thinning.
• Numeral 34 is a selection circuit for selecting one of the horizontal thinning signal S38 of the first horizontal thinning adjustment circuit 32 and the horizontal thinning signal S39 of the second horizontal thinning adjustment circuit 33.
• the selection circuit 34 is controlled by the sampling pixel position switching signal S33 of the sampling pixel position switching signal generation circuit 26.
• the second delay circuit 12 and the selection circuit 14 in the second embodiment do not exist.
• the output of the second AND circuit 11 is directly input to the fifth AND circuit 23.
• the other configuration is the same as that of the second embodiment (FIG. 7), and the description of the configuration and operation will be omitted.
• the total pixel count signal S14 in one horizontal cycle output from the first delay circuit 6 is input to the first horizontal thinning adjustment circuit 32 and the second horizontal thinning adjustment circuit 33.
• the first horizontal thinning adjustment circuit 32 generates and outputs the horizontal thinning signal S38 by thinning out the total pixel data of the luminance signal in one horizontal period by the first thinning method (for example, thinning every eight pixels). I do.
• the second horizontal thinning adjustment circuit 33 generates a horizontal thinning signal S39 by thinning out the total pixel data of the luminance signal in one horizontal period by a second thinning method (for example, thinning every four pixels). Output.
• the selection circuit 34 selects and outputs one of the horizontal thinning signal S38 and the horizontal thinning signal S39 based on the sampling pixel position switching signal S33.
• FIG. 13A shows a state of sample window signal S 9 for each horizontal cycle in the fourth embodiment.
• the starting point also repeats the inversion of 0, 1, 0, 1,..., and in the eighth line, the starting point also repeats the inversion of 1, 0, 1, 0,....
• the sampling of the fourth line is every eight pixels, whereas the sampling of the eighth line is every four pixels, and the number of samplings is doubled, and the number of sampling points in the horizontal direction is increased.
• the twelfth line repeats the inversion of the starting point force 0, 1, 0, 1,... as in the fourth line, and the 16th line has 1, 0, 1, 0,... from the starting point as in the eighth line. Repeat inversion.
• the sampling of the 12th line is every 8 pixels, while the sampling of the 16th line is every 4 pixels. The number of samplings is doubled, and the number of sampling points in the horizontal direction is increased.
• the sampling position can be arbitrarily specified in the vertical, horizontal, and diagonal directions on the screen, and the sampling position can be set by changing the number of sampling pixels. Arbitrariness and uniformity are further improved.
• FIG. 14 is a block diagram showing a configuration of the fifth embodiment of the sample window circuit 2 shown in FIG. 14 differs from the configuration of the second embodiment (FIG. 7) in that some circuit configurations are further added.
• the added configuration is as follows.
• Reference numeral 35 denotes a field switching signal generation circuit that generates a field switching signal S41 and outputs the field switching signal S41 to the first selection circuit 14.
• the field switching signal generation circuit 35 generates a field switching signal S41 based on the vertical differential signal S4.
• the field switching signal S41 is a signal for switching the sampling pixel position in the horizontal direction every one vertical period.
• the output of the fourth AND circuit 22 is input to the fifth AND circuit 23 but is not input to the field switching signal generation circuit 35.
• Other configurations are the same as those in FIG. 7 in the case of the second embodiment, and a description of the configurations and operations will be omitted.
• the switching operation of the first selection circuit 14 is controlled by using the field switching signal S41 that enables the switching of the sampling pixel position in the horizontal direction in units of one vertical period. Te ru.
• FIG. 15A to FIG. 15D show states of sample window signal S9 in the present embodiment.
• FIG. 15A shows the state of sample window signal S 9 every one horizontal cycle in thinning out one field before.
• the sample window signal S9 repeats the inversion of the starting point forces 0, 1, 0, 1,... On the fourth, eighth, twelfth, and sixteenth lines, respectively.
• FIG. 15B shows a sampling position on the screen by the sample window signal S9 of FIG. 15A.
• the fourth, eighth, twelfth, and sixteenth lines are sampled at the eighth, sixteenth, and twenty-fourth pixels, respectively. .
• FIG. 15C shows the state of sample window signal S9 every one horizontal cycle of thinning-out after one field of FIG. 15A.
• V is shifted by 4 pixels in the horizontal direction from FIG. 15A. That is, sampling is performed at the twelfth, twentieth, and twenty-eighth pixels on the fourth, eighth, twelfth, and sixteenth lines, respectively. .
• the sampling position can be arbitrarily specified in the horizontal direction on the screen, and the sampling pixel position is shifted for each field, so that the sampling position setting is optional and uniform. Is further improved.
• FIG. 16 is a block diagram showing a configuration of the sixth embodiment of the sample window circuit 2 shown in FIG. FIG. 16 differs from the configuration of the second embodiment (FIG. 7) in that some circuit configurations are further added.
• the added configuration is as follows.
• Reference numeral 36 denotes a field switching signal generation circuit that generates a field switching signal S44 and outputs it to the selection circuit 39.
• the field switching signal generation circuit 36 generates a field switching signal S44 based on the vertical differential signal S4.
• the field switching signal S44 is a signal for switching the sampling line position in the vertical direction in units of one vertical period.
• Reference numeral 37 denotes a first vertical thinning adjustment circuit for thinning sampling lines in one vertical period by the first thinning method (for example, thinning every four lines).
• Reference numeral 38 denotes a second vertical thinning adjustment circuit for thinning the sampling lines in one vertical period by the second thinning method (for example, thinning every two lines).
• a selection circuit 39 selects one of the vertical thinning signal S42 of the first vertical thinning adjustment circuit 37 and the vertical thinning signal S43 of the second vertical thinning adjustment circuit 38.
• the selection circuit 39 outputs the selected signal to the fourth AND circuit 22 as a vertical thinning signal S45. Selection
• Selection The selection operation of the selection circuit 39 is controlled based on the field switching signal S44.
• the other configuration is the same as that of the second embodiment (FIG. 7), and the description of the configuration and operation will be omitted.
• the output signal of the load hold circuit 17 is input to first and second vertical thinning adjustment circuits 37 and 38.
• the first and second vertical thinning adjustment circuits 37 and 38 generate and select the vertical thinning signals S42 and S43 by thinning the output signal of the load-hold circuit 17 by the thinning method. Output to circuit 39.
• the selection circuit 39 determines whether one of the vertical thinning signal S42 and the vertical thinning signal S43 is one vertical. By performing selection processing (switching processing) for each period (one field), the sampling line position in the vertical direction is switched every one vertical period (one field).
• FIG. 17A to FIG. 17D show states of sample window signal S9 in the present embodiment.
• FIG. 17A shows the state of sample window signal S 9 every one horizontal cycle in thinning out one field before.
• fourth, eighth, twelfth, and sixteenth lines 0, 1, 0, 1,...
• FIG. 17B shows a sampling position on the screen by the sample window signal S9 of FIG. 17A.
• the fourth, eighth, twelfth, and sixteenth lines are sampled at the eighth, sixteenth, and twenty-fourth pixels, respectively.
• FIG. 17C shows the state of sample window signal S 9 every one horizontal cycle of thinning-out after one field of FIG. 17A.
• the line selection is doubled in the vertical direction. That is, sampling at the 8th, 16th, and 24th pixels at the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th lines, respectively Is performed. .
• the sampling position can be arbitrarily specified in the vertical direction on the screen. Therefore, the number of sampling lines can be changed for each field, and the arbitrariness and uniformity of setting the sampling position are further improved.
• the first and second two are used as vertical thinning adjustment circuits. Although used, three or more may be used.
• FIG. 18 is a block diagram showing a configuration of the seventh embodiment of the sample window circuit 2 shown in FIG. FIG. 18 differs from the configuration of the third embodiment (FIG. 9) in that some circuit configurations are further added.
• the added configuration is as follows.
• Reference numeral 40 denotes a sampling pixel position switching signal generation circuit that generates a sampling pixel position switching signal S47 and outputs it to the first selection circuit 14.
• the vertical pixel thinning signal S27 from the vertical pixel thinning adjustment circuit 18 is input to the sampling pixel position switching signal generation circuit 40.
• the sampling pixel position switching signal generation circuit 40 generates a sampling pixel position switching signal S47 that repeats inversion of 0, 1, 0, 1,... In thinning horizontal cycle units based on the vertical thinning signal S27.
• Reference numeral 41 denotes a sampling line position switching signal generation circuit that generates a sampling line position switching signal S49.
• the output signal (horizontal thinning signal S15) of the horizontal thinning adjustment circuit 7 is input to the sampling line position switching signal generating circuit 41.
• the sampling line position switching signal generation circuit 41 generates a sampling line position switching signal S49 based on the horizontal thinning signal S15.
• the sampling line position switching signal S49 is a signal for switching the sampling pixel position in a unit of a bowed pixel during one horizontal cycle.
• Reference numeral 42 denotes an inverting circuit that inverts the sampling line position switching signal S49 output from the sampling line position switching signal generation circuit 41.
• 43 is a field switching signal generation circuit for generating a field switching signal S51.
• the field switching signal generation circuit 43 generates a field switching signal S51 based on the vertical differential signal S4.
• the field switching signal S51 is a signal that repeats inversion of 0, 1, 0, 1,... In units of one vertical cycle.
• Reference numeral 44 denotes a third selection circuit for selecting one of the sampling line position switching signal S49 and the inverted sampling line position switching signal S50 based on the field switching signal S51.
• a line memory 45 delays the vertical thinning signal S27 from the vertical thinning adjustment circuit 18 by one horizontal period.
• the sixth selection circuit 46 is a signal between the vertical thinning signal S27 from the vertical thinning adjustment circuit 18 and the vertical thinning signal S27a of the delay from the line memory 45. This is a fourth selection circuit for selecting one of them. The selection operation of the fourth selection circuit 46 is controlled based on the output signal S52 of the third selection circuit 44.
• the other configuration is the same as that of the third embodiment (FIG. 9), and the description of the configuration and operation is omitted.
• the sampling pixel position switching signal generation circuit 40 switches the sampling pixel position for each predetermined thinning line.
• the predetermined thinning line unit is set for each number of lines for which thinning processing has been performed in the vertical direction.
• the third selection circuit 44 outputs the signal S52 to the fourth selection circuit 46 by switching between the sampling line position switching signal S49 and the inverted sampling line position switching signal S50.
• the fourth selection circuit 46 is controlled based on the signal S52.
• the fourth selection circuit 46 alternately selects the vertical decimated signal S27 and the vertical decimated signal S27a delayed in the vertical direction, and outputs the selected signal to the fourth AND circuit 22. As a result, the fourth AND circuit 22 switches the sampling pixel position in the vertical direction on a vertical cycle basis.
• FIG. 19 shows a timing chart according to the seventh embodiment.
• S47 is a sampling pixel position switching signal for each thinning line.
• S47 (* The signal here is not S47! /, Please check. * Is a horizontal direction sampling pixel position switching signal.
• S51 is a field switching signal generated every vertical period.
• S52 is an output signal of the third selection circuit 44.
• FIG. 20A to FIG. 20D show states of sample window signal S9 in the present embodiment.
• FIG. 20A shows the state of sample window signal S9 for each thinning-out one horizontal period before one field.
• FIG. 20B shows a sampling position on the screen by the sample window signal S9 of FIG. 20A.
• sampling is performed at the 8th, 16th, and 24th pixels.
• sampling is performed at the 12th, 20th, and 28th pixels.
• the pixel is sampled at the 16th, 16th, and 24th pixels, and the 16th line is sampled at the 12th, 20th, and 28th pixels in the same manner as the 8th line. .
• FIG. 20C shows the state of sample window signal S9 in each thinning-out horizontal cycle after one field of FIG. 20A.
• the 4th and 8th lines were interchanged. Lines 12 and 16 have been swapped. That is, the fourth line is sampled at the 12th, 20th, and 28th pixels, the 8th line is sampled at the 8th, 16th, and 24th pixels, and the 12th line is sampled at the 4th line. Similarly, sampling is performed on the 12th, 20th, and 28th pixels, and on the 16th line, sampling is performed on the 8th, 16th, and 24th pixels in the same manner as on the 8th line. .
• the sampling position can be arbitrarily and evenly designated in the vertical, horizontal, and oblique directions on the screen, and the sampling pixel position is shifted in the vertical direction for each field. This further improves the arbitrariness and uniformity of the sampling position setting.
• FIG. 21 is a block diagram showing a configuration of the eighth embodiment of the sample window circuit 2 shown in FIG. FIG. 21 differs from the configuration of the third embodiment (FIG. 9) in that some circuit configurations are further added.
• the added configuration is as follows.
• Reference numeral 47 denotes a field switching signal generation circuit that generates a field switching signal S53.
• the vertical switching signal S4 is input to the field switching signal generation circuit 47.
• the field switching signal generation circuit 47 generates a field switching signal S53 based on the vertical differential signal S4.
• the field switching signal S53 is a signal that repeats inversion of 0, 1, 0, 1,... In N vertical cycle units (N is a natural number of 1 or more).
• the field switching signal generation circuit 47 can switch the sampling pixel position in the horizontal direction in units of a plurality of fields or units of a plurality of lines.
• the field switching signal generation circuit 47 outputs the field switching signal S53 to the second selection circuit 28.
• the other configuration is the same as the configuration of the third embodiment (FIG. 9), and the description of the configuration and operation will be omitted.
• FIG. 22 shows a field switching signal generation circuit 47.
• a field switching signal generation circuit (counter circuit) 47 that counts up every two fields is shown.
• N is a natural number of 1 or more
• counting is performed in units of N fields. Therefore, in the field switching signal S53 of this example, the vertical differential signal S4 is counted up by one every two fields.
• FIG. 23A to FIG. 23D show states of sample window signal S9 in the present embodiment.
• FIG. 23A shows the state of sample window signal S9 every two horizontal periods before thinning out for each horizontal cycle.
• FIG. 23B shows a sampling position on the screen by the sample window signal S9 of FIG. 23A.
• the fourth line is sampled at the 8th, 16th, and 24th pixels, the 8th line is sampled at the 12th, 20th, and 28th pixels, and the 12th line is sampled in the same way as the 4th line Sampling is performed at the 8th, 16th, and 24th pixels.
• sampling is performed at the 12th, 20th, and 28th pixels, similarly to the 8th line.
• FIG. 23C shows the state of sample window signal S9 for each horizontal cycle of thinning-out after two fields of FIG. 23A.
• the eighth pixel and the twelfth pixel are exchanged, the 16th pixel and the 20th pixel are exchanged, and the 24th pixel and the 28th pixel are exchanged. That is, the fourth line is sampled at the 12th, 20th, and 28th pixels, the 8th line is sampled at the 8th, 16th, and 24th pixels, and the 12th line is sampled at the 4th line.
• sampling is performed on the 12th, 20th, and 28th pixels, and on the 16th line, sampling is performed on the 8th, 16th, and 24th pixels in the same manner as the 8th line.
• the sampling position can be arbitrarily and evenly specified in the vertical, horizontal, and oblique directions on the screen, and the sampling pixel position can be horizontally set for each of a plurality of fields. By shifting, the arbitrariness and uniformity of the sampling position setting are further improved.
• the luminance signal processing device of the present invention enables accurate sampling of a video luminance signal without increasing the circuit scale, and is useful as an image quality improvement device or the like for a video signal. It is.

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