WO2005093506A1 - Structure de pixels et son procede de fabrication - Google Patents

Structure de pixels et son procede de fabrication Download PDF

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Publication number
WO2005093506A1
WO2005093506A1 PCT/CN2004/000273 CN2004000273W WO2005093506A1 WO 2005093506 A1 WO2005093506 A1 WO 2005093506A1 CN 2004000273 W CN2004000273 W CN 2004000273W WO 2005093506 A1 WO2005093506 A1 WO 2005093506A1
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WO
WIPO (PCT)
Prior art keywords
layer
pixel structure
gate
conductive layer
disposed
Prior art date
Application number
PCT/CN2004/000273
Other languages
English (en)
Chinese (zh)
Inventor
Zhihong Jiang
Nishino Daisuke
Original Assignee
Quanta Display Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quanta Display Inc. filed Critical Quanta Display Inc.
Priority to PCT/CN2004/000273 priority Critical patent/WO2005093506A1/fr
Publication of WO2005093506A1 publication Critical patent/WO2005093506A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the invention relates to a pixel structure of a thin film transistor array (Thin Film Transistor Array) substrate and a manufacturing method thereof, and in particular to a pixel structure and a manufacturing method thereof capable of preventing leakage of a pixel storage capacitor.
  • Background technique Thin Film Transistor Array
  • the thin film transistor liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer.
  • the thin film transistor array substrate is composed of a plurality of thin film transistors arranged in an array and a pixel electrode (corresponding to each thin film transistor). Pixel Electrode).
  • the thin film transistor includes a gate, a channel layer, a drain and a source, which are used as switching elements of a liquid crystal display unit. Please refer to FIG. 1, which is a schematic top view of one pixel structure of a conventional thin film transistor array substrate.
  • the pixel structure is disposed on a substrate (not shown), and includes a scan line 102, a data line 104, a thin film transistor 130, a pixel storage capacitor 116, and a pixel electrode 112.
  • the thin film transistor 130 includes a gate 106, a channel layer 108, and a source / drain 110a / 110b, and the gate 106 is electrically connected to the scan line 102, the source 110a is electrically connected to the data line 104, and the drain 110b
  • the contact electrode 114 is electrically connected to the pixel electrode 112.
  • the pixel storage capacitor 116 includes a lower electrode 118, an upper electrode 120, and a capacitive dielectric layer located between the lower electrode 118 and the upper electrode 120.
  • the upper electrode 120 is electrically connected to the pixel electrode 112 through a contact window 122. among them,
  • the lower electrode 118 is a common line, which belongs to the first metal layer (M1) like the scan line 102 and the gate 106.
  • the upper electrode 120 and the data line 104 and the source / drain 110a / 110b also belong to the second metal layer (M2).
  • a gate insulating layer (not shown) is disposed between the first metal layer and the second metal layer, and a protective layer (not shown) is disposed between the second metal layer and the pixel electrode 112.
  • terminal portions are designed at the two edges of the substrate to be electrically connected to the driving circuit.
  • the terminal portions are part of the first metal layer (M1), and Both the data line 104 and the scan line 102 extend to the edge of the substrate and are electrically connected to the terminal portion.
  • M1 first metal layer
  • Both the data line 104 and the scan line 102 extend to the edge of the substrate and are electrically connected to the terminal portion.
  • both the gate insulating layer and the protective layer above the terminal portion must be etched away.
  • the protective layer only needs to be etched away, especially for the contact window 122 on the pixel storage capacitor 116, only the protective layer can be etched there, and it must be kept there.
  • one method is to form an additional amorphous silicon layer under the contact window, which is simultaneously defined when the channel layer of the thin film transistor is defined.
  • an amorphous silicon layer is used as a barrier layer to prevent the gate insulating layer under the contact window from being etched through.
  • this method must adjust the etching selection ratio between the amorphous silicon and the gate insulating layer, so it is not easy to complete.
  • Another existing method is to first form an opening in the lower electrode under the contact window, which means that the lower electrode corresponding to the bottom of the contact window is first hollowed out. In this way, even if the gate insulation layer under the contact window is Erosion does not cause leakage between the upper electrode and the lower electrode.
  • this method still has its disadvantages, which is that it precedes After the opening is dug out in the lower electrode, the contact window opening and the opening in the lower electrode are subsequently aligned, and there is still a problem that alignment is not easy.
  • an object of the present invention is to provide a pixel structure and a method for manufacturing the same, so as to solve the etching steps of the gate insulating layer and the protective layer in the thin film transistor manufacturing in the prior art. 2.
  • the invention provides a pixel structure, which includes a scan line, a common line, a gate insulating layer, a data line, a switching element (such as a thin film transistor), a conductive layer, a protective layer, and a flat layer.
  • a contact window and a pixel electrode The scan lines are arranged on a substrate, the common lines are also arranged on the substrate, and the common lines are arranged in parallel with the scan lines.
  • the common lines serve as the lower electrodes of the pixel storage capacitor.
  • the gate insulating layer is disposed on the substrate and covers the scan lines and the common lines.
  • the data line is disposed on the gate insulating layer.
  • the switching element is disposed on the substrate, and the switching element is electrically connected to the scanning line and the data line.
  • a conductive layer is disposed on the gate insulating layer, and the conductive layer has a coupling portion and a connection portion, wherein the coupling portion is located above the common line and serves as an upper electrode of the pixel storage capacitor, and the connection portion connects the coupling portion Connected to the switching element.
  • the connecting portion of the conductive layer is a multi-channel structure design, which includes a first portion for connecting with the switching element, a second portion for connecting with the coupling portion, and the first portion and the second portion. The third part between the parts, the third part is the design of the multi-channel structure.
  • the protective layer covers the data line, the switching element, and the conductive layer, and the flat layer is disposed on the protective layer.
  • the contact window is disposed in the flat layer and the protective layer on the connection portion.
  • the contact window is disposed in the flat layer and the protective layer on one channel in the multi-channel structure of the connection portion.
  • the pixel electrode is disposed on the surface of the flat layer, and the pixel electrode is connected through The window contacts the window and is electrically connected to the connection portion of the conductive layer. Since the switching element is connected to the conductive layer, and the pixel electrode is electrically connected to the connection portion of the conductive layer, the pixel electrode, the entire conductive layer (including the coupling portion), and the switching element are electrically connected to each other.
  • the present invention further provides a method for manufacturing a pixel structure.
  • This method first forms a gate on a substrate, a scan line electrically connected to the gate, and a common line parallel to the scan line.
  • the common line is subsequently used as a pixel.
  • the lower electrode of the storage capacitor Next, a gate insulating layer is formed on the substrate to cover the gate, the scan lines, and the common lines. After that, a channel layer is formed on the gate insulating layer above the gate. Subsequently, a data line and a conductive layer are formed on the gate insulating layer, and a source / drain is formed on the channel layer, wherein the gate, the channel layer, and the source / drain constitute a thin film transistor, and the data line Electrically connected to the source.
  • the formed conductive layer has a coupling portion and a connection portion, wherein the coupling portion is formed above the common line and serves as an upper electrode of the pixel storage capacitor, and the connection portion of the conductive layer connects the coupling portion and the thin film transistor.
  • the drains are connected.
  • the connection portion of the conductive layer is a multi-channel structure design, which includes a first portion for connecting with the drain, a second portion for connecting with the coupling portion, and a first portion and a second portion.
  • the third part between the parts, the third part is the design of the multi-channel structure, and the contact window opening formed subsequently will expose one of the channels of the third part.
  • a protective layer is formed over the substrate to cover the data lines, the conductive layer, and the thin film transistor, and a flat layer is formed on the protective layer.
  • a contact window opening is formed in the flat layer and the protective layer to expose the connection portion of the conductive layer.
  • the formed contact window opening exposes one of the channels of the connection portion.
  • a pixel electrode is formed on the surface of the flat layer, wherein the pixel electrode is electrically connected to the connection portion of the conductive layer through the contact window opening. Since the drain electrode is connected to the conductive layer, and the pixel electrode is electrically connected to the conductive layer, the pixel electrode, the conductive layer, and the drain electrode are electrically connected to each other.
  • the pixel electrode and the drain thereof, and the pixel storage capacitor are electrically connected through the same contact window, so the pixel structure of the present invention is a design different from the existing pixel structure.
  • FIG. 1 is a schematic plan view of a pixel structure in a conventional thin film transistor array substrate
  • FIG. 2 is a schematic plan view of a pixel structure in a thin film transistor array substrate according to a preferred embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view taken along line II ′ of FIG. 2; and FIG. 4 is a top view of the conductive layer in FIG. 2. detailed description
  • FIG. 2 is a top view of a pixel structure in a thin film transistor array substrate according to a preferred embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view taken along 1- ⁇ in FIG. 2.
  • the manufacturing method of the pixel structure of the present invention first provides a substrate 200, where the substrate 200 is, for example, a glass substrate or a plastic substrate. Thereafter, a gate 206, a scan line 202 electrically connected to the gate 206, and a common line 218 parallel to the scan line 202 are formed on the substrate 200.
  • the common line 218 is subsequently used as a lower electrode of the pixel storage capacitor 216 .
  • the gate 206, the scan line 202 and the common The line 218 belongs to the first metal layer (M1).
  • the first metal layer further includes a plurality of terminal portions (not shown) formed at two edges of the substrate 200, and the scan lines 202 formed above and the data lines formed subsequently extend to the substrate 200 All edges are electrically connected to the terminals.
  • a gate insulating layer 205 is formed on the substrate 200 to cover the first metal layer (including the gate 206, the scan line 202, and the common line 218).
  • the material of the gate insulating layer 205 is, for example, silicon nitride or silicon oxide.
  • a channel layer 208 is formed on the gate insulating layer 205 above the gate 206.
  • the material of the channel layer 208 is, for example, amorphous silicon, and an ohmic contact layer (not shown) is formed on the surface of the channel layer 208 to improve the channel layer 208 and a source electrode formed subsequently. / Drain electrical contact.
  • a data line 204 and a conductive layer 250 are formed on the gate insulating layer 205 (as shown in FIG. 4), and a source / drain 210a / 210b, a data line 204, and a conductive layer are formed on the channel layer 208 at the same time.
  • 250 and the source / drain electrodes 210a / 210b belong to the second metal layer (M2).
  • the source 210a is electrically connected to the data line 204, and the gate 206, the channel layer 208, and the source / drain 210a / 210b constitute a thin film transistor.
  • the conductive layer 250 formed above has a coupling portion 220 and a connection portion 240.
  • the coupling portion 220 is formed above the common line 218 and serves as an upper electrode of the pixel storage capacitor 216.
  • the connection portion 240 connects the coupling portion 220 and the drain.
  • the poles 210b are connected.
  • the connecting portion 240 of the conductive layer 250 may be further defined as a multi-channel structure.
  • the connecting portion 240 includes a first portion 226 a connected to the drain 210 b and a coupling portion 220.
  • the third part 224 is a multi-channel structure, and three channels 224a, 224b, and 224c are shown in the figure. The description is given by way of example, but is not intended to limit the present invention.
  • a multi-channel structure The purpose of making such a multi-channel structure is to limit the opening of the contact window in the following, it will be limited above one of the channels, for example, it will be limited above the middle channel 224b.
  • the other channels 224a and 224c are responsible for conducting the carrier. If one of the channels (such as channel 224a) cannot be conducted due to manufacturing factors or other factors, the remaining channels (such as 224c) can continue. Take on the task of conducting the carrier without making the entire pixel structure inoperable for the reasons mentioned above. It is particularly worth mentioning that a light-shielding layer 222 may be formed under the third portion 224 of the connection portion 240. The light-shielding layer 222 is part of the first metal layer.
  • the light-shielding layer 222 previously defined the gate 206.
  • the scan lines 202 and the common lines 218 are defined simultaneously.
  • the purpose of forming the light shielding layer 222 here is to block the light scattering phenomenon that will be caused by the contact window formed above it.
  • a protective layer 211 is formed over the substrate 200 to cover the second metal layer.
  • the material is, for example, silicon nitride or silicon oxide.
  • a flat layer 213 is formed on the protective layer 211, and the material of the flat layer 213 is, for example, an organic photosensitive material.
  • the flat layer 213 and the protective layer 211 are patterned to form a contact window opening 228 in the flat layer 213 and the protective layer 211 to expose a part of the connection portion 240 of the conductive layer 250.
  • the contact window opening 228 exposes one of the channels 224 b of the connecting portion 240.
  • the second metal layer uses a titanium / aluminum double metal layer as its material, during the etching process that defines the contact window opening 228, it may be appropriate to remove the upper aluminum layer of the channel 224b at the same time, leaving the lower layer.
  • the thickness of the channel 224b in FIG. 3 is obviously smaller than that of the channels 224a and 224c.
  • the contact window opening 228 of the present invention is not Limited to the pixel storage capacitor 216, so even if the etching step that defines the contact window opening 228 will etch through the gate insulation layer 205, it will not cause the pixel storage capacitor 216 between the upper and lower electrodes 218, 220 Leakage. Moreover, if this etching step will etch through the gate insulating layer 205, but because the light shielding layer 222 is disposed under the contact window opening 228, it is a film layer that is not electrically connected to other conductive material layers, so it is still not Will have an adverse effect on the entire component.
  • a pixel electrode 212 is formed on the surface of the flat layer 213, and the pixel electrode 212 is electrically connected to the connection portion 240 (ie, the channel 224b) of the conductive layer 250 through the contact window opening 228. Since the coupling portion 220 of the conductive layer 250 and the drain 210b of the thin film transistor 230 are connected together through a connection portion 240, and the pixel electrode 212 is electrically connected to the connection portion 240, the pixel electrode 212, the conductive layer 250 (including The coupling portion 220 and the connection portion 240) and the drain 210 b of the thin film transistor 230 are electrically connected to each other.
  • the pixel structure of the present invention includes a scan line 202, a common line 218, a gate insulating layer 205, a data line 204, a switching element 230 (such as a thin film transistor), a conductive layer 250, a protective layer 211, a The flat layer 213, a contact window 228, and a pixel electrode 212.
  • the scan line 202 is disposed on a substrate 200
  • the common line 218 is also disposed on the substrate 200, which serves as a lower electrode of the pixel storage capacitor 216, and the common line 218 is disposed in parallel with the scan line 202.
  • the gate insulating layer 205 is disposed on the substrate 200 and covers the scan lines 202 and the common lines 218.
  • the data line 204 is disposed on the gate insulating layer 205.
  • the switching element 230 is, for example, a thin film transistor, which is disposed on the substrate 200.
  • the thin film transistor 230 has a gate 206, a channel layer 208, and a source. / Drain 210a / 210b, where the gate 206 is electrically connected to the scan line 202, the channel layer 208 is disposed on the gate insulating layer 205 above the gate 206, and the source / drain 210a / 210b is disposed on the channel layer 208
  • the source 210a is electrically connected to the data line 204.
  • a conductive layer 250 is disposed on the gate insulating layer 205.
  • the conductive layer 250 has a coupling portion 220 and a connection portion 240.
  • the coupling portion 220 is located above the common line 218 and serves as an upper electrode of the pixel storage capacitor 216.
  • the connection portion 240 connects the coupling portion 220 and the drain 210 b of the thin film transistor 230.
  • the connecting portion 240 of the conductive layer 250 is, for example, a multi-channel structure.
  • the connecting portion 240 includes a first portion 226 a connected to the drain 210 b, a second portion 226 b connected to the coupling portion 220, and The third portion 224 is located between the first portion 226a and the second portion 226b.
  • the third portion 224 is a multi-channel structure design.
  • a light-shielding layer 222 is further disposed under the third portion 224 of the connection portion 240.
  • This light-shielding layer 222 like the gate electrode 206, the scan line 202, and the common line 218, also belongs to the first metal layer, and the light-shielding layer 222 It is used to block the light scattering phenomenon caused by the contact window formed above it.
  • the protective layer 211 covers the data line 204, the thin film transistor 230, and the conductive layer 250.
  • the flat layer 213 is disposed on the protective layer 211.
  • the contact window 228 is disposed in the flat layer 213 and the protective layer 211 above the connection portion 240, and the connection window 240 of the contact window 228 and the conductive layer 250 is electrically connected.
  • the contact window 228 is disposed in the flat layer 213 and the protective layer 211 above the channel 224b of the connection portion 240, and is electrically connected to the channel 224b of the connection portion 240.
  • the pixel electrode 212 is disposed on the surface of the flat layer 213.
  • the pixel electrode 212 is electrically connected to the connection portion 240 of the conductive layer 250 through the contact window 228. More specifically, the pixel electrode 212 is connected to the connection portion 240 through the contact window 228.
  • Channel 224b Electrical connection. Through the electrical contact between the channel 224b and the pixel electrode 212, the pixel electrode 212 and the entire conductive layer 250 are electrically connected to each other.
  • the drain 210b is connected to the conductive layer 250 again, the pixel electrode 212, the conductive layer 250, and the drain 210b are electrically connected to each other. Therefore, the pixel structure of the present invention is electrically connected between the pixel electrode and the drain and the upper electrode of the pixel storage capacitor through the same contact window. Therefore, the pixel structure of the present invention is different from the existing one. Design of pixel structure.
  • the contact window of the pixel structure of the present invention is not disposed above the pixel storage capacitor, even if the etching step of the protective layer and the gate insulating layer will etch through the gate insulating layer, the pixel storage capacitor will not be damaged. Leakage occurs between the upper and lower electrodes.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne une structure pixelisée du substrat d'un ensemble TFT et son procédé de fabrication. Ladite structure pixelisée comprend: une ligne de balayage placée sur le substrat, une ligne publique placée sur le substrat, une couche isolante placée sur le substrat, une ligne de données placée sur la couche isolante, un élément de commutation placé sur le substrat, une couche conductrice placée sur la couche isolante, une couche protectrice recouvrant ladite ligne de données, l'élément de commutation et la couche conductrice, un orifice de contact placé dans la couche protectrice et une électrode de pixels placée sur ladite couche protectrice.
PCT/CN2004/000273 2004-03-29 2004-03-29 Structure de pixels et son procede de fabrication WO2005093506A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2004/000273 WO2005093506A1 (fr) 2004-03-29 2004-03-29 Structure de pixels et son procede de fabrication

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Application Number Priority Date Filing Date Title
PCT/CN2004/000273 WO2005093506A1 (fr) 2004-03-29 2004-03-29 Structure de pixels et son procede de fabrication

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WO2005093506A1 true WO2005093506A1 (fr) 2005-10-06

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102508385A (zh) * 2011-11-17 2012-06-20 华映视讯（吴江）有限公司 像素结构、阵列基板及其制作方法
US10705439B2 (en) 2004-08-19 2020-07-07 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10161094A (ja) * 1996-11-29 1998-06-19 Toshiba Corp 表示装置用アレイ基板
JPH11326950A (ja) * 1998-05-18 1999-11-26 Sharp Corp アクティブマトリクス基板の製造方法
US6034747A (en) * 1995-09-27 2000-03-07 Sharp Kabushiki Kaisha Active matrix substrate and display device incorporating the same
JP2001331125A (ja) * 2000-03-17 2001-11-30 Seiko Epson Corp 電気光学装置
CN1389756A (zh) * 2001-06-04 2003-01-08 达碁科技股份有限公司 薄膜晶体管液晶显示器的制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034747A (en) * 1995-09-27 2000-03-07 Sharp Kabushiki Kaisha Active matrix substrate and display device incorporating the same
JPH10161094A (ja) * 1996-11-29 1998-06-19 Toshiba Corp 表示装置用アレイ基板
JPH11326950A (ja) * 1998-05-18 1999-11-26 Sharp Corp アクティブマトリクス基板の製造方法
JP2001331125A (ja) * 2000-03-17 2001-11-30 Seiko Epson Corp 電気光学装置
CN1389756A (zh) * 2001-06-04 2003-01-08 达碁科技股份有限公司 薄膜晶体管液晶显示器的制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10705439B2 (en) 2004-08-19 2020-07-07 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
CN102508385A (zh) * 2011-11-17 2012-06-20 华映视讯（吴江）有限公司 像素结构、阵列基板及其制作方法

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