Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
  • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
  • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
  • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
  • H10P30/212—Through-implantation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
  • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
  • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides

Definitions

• the present invention relates generally to semiconductor technology, and more specifically to suiciding in semiconductor devices to form abrupt junctions by a suicide growth dopant snowplow effect.
• MOS Metal Oxide Semiconductor
• the transistor contains a gate electrode (usually polysilicon) over a gate dielectric, over a silicon substrate.
• the silicon substrate on both sides of the polysilicon gate is doped by ion implantation of boron or phosphorus or other impurity atoms into the surface of the silicon substrate, thereby becoming conductive. These doped regions of the silicon substrate are referred to as “shallow source/drain junctions", which are separated by a channel region beneath the polysilicon gate.
• a silicon oxide or silicon nitride spacer referred to as a "sidewall spacer" on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain junctions, which are called “deep source/drain junctions".
• the shallow and deep source/drain junctions are collectively referred to as "S/D junctions".
• a silicon oxide dielectric layer is deposited to cover the gate, the spacer, and the silicon substrate.
• openings are etched in the silicon oxide dielectric layer to the polysilicon gate and the S/D junctions. The openings are filled with metal to form electrical contacts.
• the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
• transistors have decreased in size, it has been found that the electrical resistance between the metal contacts and the silicon substrate or the polysilicon has increased to the level where it negatively impacts the performance of the transistors.
• a transition material is formed between the metal contacts and the silicon substrate or the polysilicon.
• the best transition materials have been found to be cobalt suicide (CoSi 2 ) and nickel suicide (NiSi 2 ).
• the suicides are formed by first applying a thin layer of the cobalt (Co) or nickel (Ni) on the silicon substrate above the S/D junctions and the polysilicon gates.
• the semiconductor wafer is subjected to one or more annealing steps at temperatures below 800°C and this causes the cobalt or nickel to selectively react with the silicon and the polysilicon to form the metal suicide.
• the process is generally referred to as "suiciding".
• Transistors used in integrated circuits are accordingly made ever smaller as the complexity and packing density of those circuits continue to increase.
• Those transistors use p-n junctions, which are formed in semiconductor substrates by controlled introduction of one or more of the dopant species in selected areas. Modern, scaled down, high performance devices require these junctions to be shallow and abrupt.
• Such junctions, as they are formed by the ion implantation have ion distribution patterns or profiles in the substrate that are determined by the ion implantation parameters and the substrate properties.
• Such ion distributions have a finite (i.e., limited) sharpness or abruptness at their edges. The abruptness is then dulled as the dopant undergoes thermal annealing to make it electrically active in the substrate.
• Such limited abruptness of the dopant profile and in particular the limited abruptness of the active portion of the dopant profile, poses limitations on the scalability of such devices to very small sizes.
• Various methods have been proposed to sharpen the activated dopant profile at the source and drain junctions. These include solid-phase epitaxial regrowth of a preamorphized part of the doped area, as well as shallow and rapid melting of that area by lasers. In both cases, achieved active dopant profiles at the junction can become sharper than the profiles as originally implanted.
• solutions to such problems have been long sought but prior developments have not taught or suggested solutions and, thus, solutions to these problems have long eluded those skilled in the art.
• the present invention provides devices having abrupt junctions, and a method for the formation thereof.
• a gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric.
• a sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric.
• a thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer.
• Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer.
• Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers.
• a dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.
• FIG. 1 is a view of a transistor in an intermediate stage of fabrication in accordance with the present invention
• FIG. 2 is the structure of FIG. 1 after deposition and etching to form a sidewall spacer
• FIG. 3 is the structure of FIG. 2 following formation of a thickening layer on the surface of the semiconductor substrate
• FIG. 4 is the structure of FIG. 3 during formation of raised source/drain dopant implanted regions in the thickening layer and the adjacent top of the semiconductor substrate
• FIG. 5 is the structure of FIG. 4 during formation of metallic layers on the gate and the raised source/drain dopant implanted regions
• FIG. 6 is the structure of FIG. 5 during the formation of silicide layers
• FIG. 5 is the structure of silicide layers
• FIG. 7 is a graphical representation of the profile of the dopant concentration as originally implanted;
• FIG. 8 is a graphical representation of the profile of the dopant concentration following formation of the silicide layers and the source/drain regions;
• FIG. 9 is the structure of FIG. 6 after deposition of a dielectric layer over the silicide and the sidewall spacer;
• FIG. 10 is the structure of FIG. 9 after formation of metal contacts; and
• FIG. 11 is a simplified flow chart of the method of forming a device in accordance with the present invention.
• silicide is grown into the silicon in S/D junction implanted regions. As the silicide grows into the silicon, the silicide rejects the dopant in the silicon and pushes the dopant along in front of the silicide. The rejection of the dopant is due to the limited solid solubility of dopants in suicides, and to the related segregation thereof at the silicide-silicon interface.
• the transistor is formed with S/D regions that are first thickened by selective epitaxial growth ("SEG" or "epi”). S/D regions are then formed in the thickened S/D regions by implanting them with a desired initial concentration of dopant; e.g., arsenic (As) or boron (B).
• silicide e.g., cobalt silicide (CoSi 2 ) or nickel silicide (NiSi ) on top of the epi layer.
• silicide e.g., cobalt silicide (CoSi 2 ) or nickel silicide (NiSi )
• CoSi 2 cobalt silicide
• NiSi nickel silicide
• FIG. 1 therein is shown a semiconductor device, and in particular a transistor 100 in an intermediate stage of fabrication in accordance with the present invention.
• a gate dielectric layer such as silicon oxide
• a conductive gate layer such as polysilicon
• FIG. 2 therein is shown the structure of FIG. 1 after deposition and etching of a sidewall spacer layer, typically of silicon nitride, to form a sidewall spacer 200.
• the sidewall spacer 200 prevents the epi (see next paragraph) from shorting the S/D regions 606 and 608 (see FIG. 6) and the gate 106.
• the sidewall spacer 200 is quite thin, to allow the S/D regions 606 and 608 to be very close to the edge of the gate 106 (as illustrated in FIG. 6).
• FIG. 3 therein is shown the structure of FIG. 2 following formation by SEG of a thickening layer 300 on the surface of the semiconductor substrate 102 adjacent the sidewall spacer 200 and the gate 106.
• the thickening layer 300 raises the level or height of the surface of the semiconductor substrate adjacent the sidewall spacer 200 and the gate 106, providing for the formation of raised structures thereadjacent.
• FIG. 4 therein is shown the structure of FIG. 3 during a dopant ion implantation 400 to form such a raised structure.
• the dopant ion implantation 400 forms raised S D dopant implanted regions 402 and 404 in the thickening layer 300 (FIG. 3) and the adjacent top of the semiconductor substrate 102.
• the gate 106 and the sidewall spacer 200 act as masks for the formation of the raised S D dopant implanted regions 402 and 404.
• the dopant ion implantation 400 is then followed by a high- temperature anneal (e.g., above 700°C) to activate the implanted impurity atoms in the raised S/D dopant implanted regions 402 and 404.
• Dopants that may be used for the raised S/D dopant implanted regions 402 and 404 include: arsenic (As), phosphorus (P), and antimony (Sb) for NMOS devices, and boron (B) and indium (In) for PMOS devices.
• As arsenic
• P phosphorus
• Sb antimony
• B boron
• In indium
• FIG. 5 therein is shown a deposition process 500 that forms a metallic layer 502 on the gate 106 and on the raised S/D dopant implanted regions 402 and 404, respectively.
• the metallic layer 502 may be formed of cobalt (Co), nickel (Ni), titanium (Ti), hafnium (Hf), or platinum (Pt).
• silicide layers 600, 602, and 604 are formed by thermal silicidation of the metallic layer 502 (FIG. 5) into the silicon material of the gate 106 and the raised S/D dopant implanted regions 402 (FIG. 5) and 404 (FIG. 5), respectively. After the thermal silicidation anneal, any residual metal remaining from the metallic layer 502 is etched away in conventional manner. As the silicide grows downwardly into the raised S/D dopant implanted regions 402 and 404, it injects excess dopant from the prior dopant ion implantation 400 (FIG.
• the S/D regions 606 and 608 have the virtue not only of being highly enriched with dopant from the silicide layers, but also of being very shallow.
• the vertical axis (labeled “cone”) represents the dopant concentration, while the horizontal axis (labeled “d”) represents the depth below the surface of the raised S/D dopant implanted regions 402 and 404.
• FIG. 8 therein is shown a graphical representation, similar to FIG. 7, of the profile
• the silicidation described in connection with FIG. 6 is performed at a low enough temperature that the dopant segregation or plowing effect into the S/D regions 606 and 608 dominates any dopant diffusion within the silicon of the S/D regions 606 and 608 themselves. This preserves and sharpens the dopant profile in the S/D regions 606 and 608. In fact, by keeping the silicidation temperature sufficiently low, dopant diffusion within the S/D regions and the adjacent silicon substrate can be kept essentially nonexistent.
• the epi deposition of the thickening layer 300 (FIG. 3) allows the silicide layers 602 (FIG.
• the epi deposition should preferably be as thick as possible to produce a correspondingly thick silicide.
• the epi deposition cannot be too thick or it may create excessive capacitance with the gate 106. It is believed that an advantage of the present invention is that, as the silicide grows, it may inject more than just excess dopant into the silicon in front of it. It may also inject vacancies into the silicon in front of it that improve the chances of dopant ending up in substitutional sites of the silicon lattice, and thus becoming activated.
• FIG. 9 therein is shown the structure of FIG. 6 after deposition of a dielectric layer 900 over the silicide layers 600, 602, and 604, and the sidewall spacer 200.
• the dielectric layer 900 is deposited in known fashion and may consist, for example, of an appropriate known material having a dielectric constant suitable for the application at hand.
• FIG. 10 therein is shown the structure of FIG. 9 after formation of metal contacts 1000, 1002, and 1004.
• the metal contacts 1000, 1002, and 1004 are respectively electrically connected to the silicide layers 600, 602, and 604, and respectively to the gate 106 and the S/D regions 606 and 608.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Electrodes Of Semiconductors (AREA)

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• 2003
  • 2003-12-03 US US10/727,999 patent/US7081655B2/en not_active Expired - Lifetime
• 2004
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