CN1886838B - 藉利用硅化物生长掺杂物雪耙效应于装置中形成陡接面 - Google Patents

藉利用硅化物生长掺杂物雪耙效应于装置中形成陡接面 Download PDF

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Publication number
CN1886838B
CN1886838B CN200480035297XA CN200480035297A CN1886838B CN 1886838 B CN1886838 B CN 1886838B CN 200480035297X A CN200480035297X A CN 200480035297XA CN 200480035297 A CN200480035297 A CN 200480035297A CN 1886838 B CN1886838 B CN 1886838B
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layer
source
silicide layer
semiconductor substrate
silicide
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Expired - Fee Related
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CN200480035297XA
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Chinese (zh)
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CN1886838A (zh
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W·P·马斯扎拉
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Innovation Core Making Co ltd
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H10P30/212—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
CN200480035297XA 2003-12-03 2004-10-26 藉利用硅化物生长掺杂物雪耙效应于装置中形成陡接面 Expired - Fee Related CN1886838B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/727,999 US7081655B2 (en) 2003-12-03 2003-12-03 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect
US10/727,999 2003-12-03
PCT/US2004/035408 WO2005062387A1 (en) 2003-12-03 2004-10-26 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect

Publications (2)

Publication Number Publication Date
CN1886838A CN1886838A (zh) 2006-12-27
CN1886838B true CN1886838B (zh) 2011-03-16

Family

ID=34633603

Family Applications (1)

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CN200480035297XA Expired - Fee Related CN1886838B (zh) 2003-12-03 2004-10-26 藉利用硅化物生长掺杂物雪耙效应于装置中形成陡接面

Country Status (8)

Country Link
US (2) US7081655B2 (https=)
JP (1) JP2007513516A (https=)
KR (1) KR101093125B1 (https=)
CN (1) CN1886838B (https=)
DE (1) DE112004002401B4 (https=)
GB (1) GB2425404B (https=)
TW (1) TWI370518B (https=)
WO (1) WO2005062387A1 (https=)

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Publication number Priority date Publication date Assignee Title
US20060228850A1 (en) * 2005-04-06 2006-10-12 Pang-Yen Tsai Pattern loading effect reduction for selective epitaxial growth
US7659172B2 (en) * 2005-11-18 2010-02-09 International Business Machines Corporation Structure and method for reducing miller capacitance in field effect transistors
WO2007072305A2 (en) * 2005-12-19 2007-06-28 Nxp B.V. Source and drain formation in silicon on insulator device
US7745847B2 (en) 2007-08-09 2010-06-29 United Microelectronics Corp. Metal oxide semiconductor transistor
US8273631B2 (en) * 2009-12-14 2012-09-25 United Microelectronics Corp. Method of fabricating n-channel metal-oxide semiconductor transistor
US8513765B2 (en) 2010-07-19 2013-08-20 International Business Machines Corporation Formation method and structure for a well-controlled metallic source/drain semiconductor device
US8846492B2 (en) * 2011-07-22 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a stressor and method of forming the same
KR20160058499A (ko) * 2014-11-17 2016-05-25 삼성전자주식회사 반도체 소자, 및 그 반도체 소자의 제조방법과 제조장치
US10510869B2 (en) 2016-05-06 2019-12-17 Silicet, LLC Devices and methods for a power transistor having a Schottky or Schottky-like contact
US9947787B2 (en) 2016-05-06 2018-04-17 Silicet, LLC Devices and methods for a power transistor having a schottky or schottky-like contact
US11228174B1 (en) 2019-05-30 2022-01-18 Silicet, LLC Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US10892362B1 (en) 2019-11-06 2021-01-12 Silicet, LLC Devices for LDMOS and other MOS transistors with hybrid contact
EP4200911A4 (en) 2020-12-04 2025-01-08 Amplexia, LLC SELF-ALIGNED BODY LDMOS AND HYBRID SOURCE
CN120390443B (zh) * 2025-06-30 2025-09-09 合肥晶合集成电路股份有限公司 一种半导体器件及其制作方法

Citations (2)

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US4769686A (en) * 1983-04-01 1988-09-06 Hitachi, Ltd. Semiconductor device
US4885617A (en) * 1986-11-18 1989-12-05 Siemens Aktiengesellschaft Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit

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US4293587A (en) 1978-11-09 1981-10-06 Zilog, Inc. Low resistance backside preparation for semiconductor integrated circuit chips
US4274892A (en) 1978-12-14 1981-06-23 Trw Inc. Dopant diffusion method of making semiconductor products
DE2926874A1 (de) 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
US4362597A (en) 1981-01-19 1982-12-07 Bell Telephone Laboratories, Incorporated Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
US4692348A (en) 1984-06-21 1987-09-08 International Business Machines Corporation Low temperature shallow doping technique
JPH04291929A (ja) * 1991-03-20 1992-10-16 Toshiba Corp 半導体装置の製造方法
US5352631A (en) * 1992-12-16 1994-10-04 Motorola, Inc. Method for forming a transistor having silicided regions
US5780341A (en) * 1996-12-06 1998-07-14 Halo Lsi Design & Device Technology, Inc. Low voltage EEPROM/NVRAM transistors and making method
US6136636A (en) 1998-03-25 2000-10-24 Texas Instruments - Acer Incorporated Method of manufacturing deep sub-micron CMOS transistors
US6326251B1 (en) 1999-01-12 2001-12-04 Advanced Micro Devices Method of making salicidation of source and drain regions with metal gate MOSFET
US6087235A (en) * 1999-10-14 2000-07-11 Advanced Micro Devices, Inc. Method for effective fabrication of a field effect transistor with elevated drain and source contact structures
US6451693B1 (en) * 2000-10-05 2002-09-17 Advanced Micro Device, Inc. Double silicide formation in polysicon gate without silicide in source/drain extensions
US6812527B2 (en) * 2002-09-05 2004-11-02 International Business Machines Corporation Method to control device threshold of SOI MOSFET's

Patent Citations (2)

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US4769686A (en) * 1983-04-01 1988-09-06 Hitachi, Ltd. Semiconductor device
US4885617A (en) * 1986-11-18 1989-12-05 Siemens Aktiengesellschaft Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit

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Jie J. Sun等.Elevated n+/p Junctions by Implant into CoSi2 Formed onSelective Epitaxy for Deep Submicron MOSFET＇s.IEEE TRANSACTIONS ON ELECTRON DEVICES45 9.1998,45(9),1946-1951.
Jie J. Sun等.Elevated n+/p Junctions by Implant into CoSi2 Formed onSelective Epitaxy for Deep Submicron MOSFET＇s.IEEE TRANSACTIONS ON ELECTRON DEVICES45 9.1998,45(9),1946-1951. *
M. Wittmer等.Redistribution of As during Pd2Si formation:Ion channelingmeasurements.J. Appl. Phys53 10.1982,53(10),6781-6786.
M. Wittmer等.Redistribution of As during Pd2Si formation:Ion channelingmeasurements.J. Appl. Phys53 10.1982,53(10),6781-6786. *

Also Published As

Publication number Publication date
US20050121731A1 (en) 2005-06-09
KR20060115892A (ko) 2006-11-10
US7081655B2 (en) 2006-07-25
KR101093125B1 (ko) 2011-12-13
DE112004002401T5 (de) 2006-11-30
GB2425404B (en) 2007-05-16
TWI370518B (en) 2012-08-11
US7306998B2 (en) 2007-12-11
WO2005062387A1 (en) 2005-07-07
GB0612074D0 (en) 2006-07-26
US20060211245A1 (en) 2006-09-21
GB2425404A (en) 2006-10-25
DE112004002401B4 (de) 2009-02-26
CN1886838A (zh) 2006-12-27
JP2007513516A (ja) 2007-05-24
TW200524082A (en) 2005-07-16

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Effective date of registration: 20181116

Address after: New Hampshire

Patentee after: Innovation Core Making Co.,Ltd.

Address before: California, USA

Patentee before: ADVANCED MICRO DEVICES, Inc.

CF01 Termination of patent right due to non-payment of annual fee
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Granted publication date: 20110316