Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/62—Fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
  • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
  • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0135—Manufacturing their gate conductors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0147—Manufacturing their gate sidewall spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

• the present invention relates generally to the field of semiconductor fabrication and, more particularly, to semiconductor fabrication processes employing double gate or "fin" FET transistors.
• a conventional metal-oxide-semiconductor (MOS) transistor has a structure in which a gate electrode is displaced above the transistor channel region by an intermediate gate dielectric film.
• the region below the channel may include the bulk substrate or an epitaxial film.
• the transistor is operated by applying a bias to the gate electrode.
• the bulk material is likely grounded or biased to a constant voltage.
• the conventional transistor may be described as having a single-sided gate since the gate exists on only one side of (i.e., above) the channel. It is generally recognized that single-sided gate transistors inherently exhibit operational characteristics, including leakage current, drive current, and sub-threshold slope, that are less than ideal. These parameters are particularly critical in low power applications such as wireless technology.
• Multiple-gate transistor structures in which gate dielectrics and gate electrodes are formed on two (or more) sides of the transistor channel, have been proposed to address this problem.
• One example of a multiple gate transistor is the "fin" FET, so named because the transistor channel is a fin or wall of silicon positioned above the underlying substrate.
• a gate dielectric is formed on the faces of the fin and a gate electrode is formed by depositing and patterning polysilicon or another suitable material.
• the exposed portions of the fin i.e., the portions not covered by the gate electrode serve as the source/drain regions in the finished transistor structure. Reducing resistivity in the source/drain regions is important in the design of high performance transistors including multiple gate transistors.
• This goal is typically achieved, at least in part, by using a silicide process in which a material that is reactive with silicon, such as titanium, is deposited over a transistor and heated in an oven. During this heat step, a silicide is formed wherever the deposited material contacts exposed silicon.
• the exposed silicon includes the exposed source/drain regions and an upper surface of the silicon-based gate electrode. Additional reduction of resistivity in the source/drain regions may be achieved, at least in part, by growing silicon or silicon germanium selectively on the exposed silicon faces.
• a dielectric spacer is formed adjacent the gate sidewalls prior to silicide deposition. The silicide material does not react with the underlying dielectric.
• the unreacted silicide material is then removed following the silicide heat treatment.
• conventional processing as described above has an undesirable consequence.
• the dielectric spacer formed following gate etch forms, not only on the gate electrode sidewalls, but also the vertically oriented primary fin faces in the source/drain regions (i.e., the regions of the fin not covered by the gate electrode).
• the only part of the source/drain regions that is exposed and capable of being suicided is along the very small, top surface of the fins. It would be desirable to implement a process employing a selective epitaxial process or silicide process or both in which the primary fin faces are exposed for silicide and/or selective epitaxial processing while still preventing gate-to-source/drain short circuits.
• a semiconductor fabrication process including forming a silicon fin overlying a substrate.
• a gate dielectric is formed on primary faces of the fin.
• a gate electrode is formed over at least two faces of the fin.
• the gate material may include a combination of one or more materials including polysilicon, polysilicon germanium, titanium nitride, and tantalum silicon nitride.
• Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces.
• the forming of the gate electrode in one embodiment includes depositing a conductive gate material over the fin and substrate, depositing a capping layer over the conductive gate material, patterning photoresist over the capping layer and etching through the capping layer and the conductive gate material with the patterned photoresist in place wherein the etching produces a conductive gate material width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the conductive gate material where the confined spacers can be formed.
• FIGs 1-12 illustrate a first embodiment of a method of forming spacers confined to the sidewalls of the gate electrode with a series of partial cross sectional views representing selected steps in a sequence of processing steps
• FIGs 13-19 illustrate a second embodiment of a method of forming spacers confined to the sidewalls of the gate electrode with a series of partial cross sectional views representing selected steps in a sequence of processing steps
• FIGs 20-28 illustrate a third embodiment of a method of forming spacers confined to the sidewalls of the gate electrode with a series of partial cross sectional views representing selected steps in a sequence of processing steps.
• FIGs 1 through 12 illustrate a semiconductor fabrication processing sequence according to one embodiment of the present invention.
• a fin is first formed on an underlying substrate.
• the fin will function as the channel region and the source/drain regions of the resulting transistor.
• the fin is formed by depositing a dielectric layer 106, such as a silicon nitride layer, over a substrate 101 that includes a silicon substrate portion 104 and a dielectric portion 102.
• the top dielectric layer 106 is optional.
• a silicon-on-insulator (SOI) wafer provides a shallow, monocrystalline silicon portion 104 and a silicon-oxide portion 102 over an underlying silicon bulk portion (not depicted).
• the depicted substrate 101 may be formed by depositing an oxide (or other dielectric) layer 102 and a silicon layer 104 over an existing silicon substrate.
• the silicon fin 114 is then formed by patterning a photoresist layer overlying dielectric layer 106 of FIG 1, exposing and developing the photoresist layer, and etching through the exposed portions of layers 104 and 106 to leave the fin 114 and a capping dielectric portion 116.
• W represents the electrical width of the resulting transistor in the well known ratio W/L that is a primary determinant of the transistor's source/drain current.
• the factor of 1/2 accounts for the double sided characteristic of the transistor. Because the multiple gate transistor has (at least) two active faces, each face of the fin contributes to the width of the transistor.
• a gate dielectric layer 120 is formed on the primary faces of fin 114, a first layer 122 is deposited over fin 114 and substrate layer 102, and a capping layer 124 is deposited overlying the first layer.
• First layer 122 will ultimately serve as the gate electrode for the multiple gate transistor.
• the first layer 122 is a polysilicon layer while the capping layer 124 is a material with respect to which first layer 124 can be selectively etched.
• capping layer 124 may be a dielectric such as an oxide (e.g., SiO 2 ) or a nitride (e.g., silicon nitride).
• capping layer 124 is a conductive material such as titanium nitride or the like.
• first layer 122 is a conductive material such as silicon germanium while capping layer 124 is polysilicon.
• the formation of gate dielectric layer 120 is accomplished in one embodiment by thermal oxidation of the underlying fin 114.
• gate dielectric layer 120 includes a deposited non-conductive, high-K, metal oxide (e.g., hafnium oxide) or metal silicate (e.g., hafnium silicate).
• a gate electrode 131 is formed by first forming a patterned photoresist layer (not depicted) overlying capping layer 124 of FIGs 4 and 5 using conventional photolithograhy techniques. Following the photolithography step, capping layer 124 and first layer 122 are etched to produce gate structure 131 as shown.
• the etching sequence according to one embodiment of the invention includes a first etch portion during which capping layer 124 is patterned to form a capping layer portion 134 and a second etch portion during which the underlying first layer 122 is etched further.
• the etching of first layer 122 is preferably carried out using a species that is selective to capping layer portion 134 under conditions that produce a relatively isotropic etch of first layer 122 such that first layer 122 is undercut relative to capping layer portion 134.
• the first layer portion 142 resulting from this etch process has a lateral dimension that is less than the lateral dimension of the capping layer portion 134 over it (FIG 6).
• the voids produced directly under the overhanging portions of capping layer 134 enable the formation of confined spacers that will prevent shorting from the transistor gate to its source/drain regions during silicide formation.
• the etch sequence may include a first portion in which a chlorine-based etchant under strong vacuum and bias produces a highly anisotropic etch of the capping layer followed by a second portion in which a fluorine based etchant under lesser bias produces a selective and undercutting etch of first layer 122.
• a dielectric spacer 144 is formed in the voids under the overhanging portions of capping layer portion 134.
• a silicon nitride deposition is followed by an anisotropic etch.
• the deposition fills the voids on the sidewalls of the first layer portion 142 while the etch process removes the nitride everywhere except where the nitride is protected from above by capping layer 134. In this manner, dielectric spacers 144 are confined to the sidewalls of first layer portion 142. As seen in the FIG 9, the portions of silicon fin 114 not covered by gate structure 131 are exposed following the formation of spacers 144. Exposing of a large portion of silicon fin 114 allows for silicon to be selectively grown on this exposed faces and improves the benefit achieved by a subsequent silicide and epitaxial process.
• a selective epitaxial growth is performed to form additional conductive regions or source/drain epitaxial structures 150 shown in the cross section view of FIG 11 (from' above).
• the thick source/drain epitaxial structures 150 reduce the source/drain resistivity and facilitate the subsequent formation of contacts or vias to the source drain regions.
• a silicide sequence is performed to silicide exposed portion of fins 114.
• an appropriate metal such as tantalum or titanium is non-selectively deposited over the wafer and subjected to a heat step. Wherever the metal contacts silicon, a silicide is formed during the heat step.
• confined spacers 144 prevents the silicide from forming on sidewalls of first layer portion 142 and thereby prevents the formation of an electrical path (short) between the gate electrode and the source/drain regions.
• the epitaxial structures 150 cover substantially all of the previously exposed portions of silicon fin 114.
• FIGs 13 through 19 a second embodiment of a process suitable for producing spacer structures confined closely to the sidewalls of the transistor gate structure in a multiple gate semiconductor process is depicted.
• a fin is formed in the same way as described previously with respect to FIGs 1 through 3.
• a gate dielectric 120 is formed as shown on the primary faces of silicon fin 114 in FIG 14.
• a polysilicon deposition is performed followed by an anisotropic etch (also referred to as a spacer etch) to produce polysilicon spacers 202 everywhere on the primary faces of silicon fin 114 (with the gate dielectric 120 positioned intermediate between them.
• a capping material 210 is deposited over polysilicon spacer material 202.
• capping material 210 is a material, preferably a metal, capable of being etched selectively with respect to the silicon in silicon spacers 202.
• capping layer 210 is a refractory metal such as titanium nitride or tantalum silicon nitride.
• the capping material 210 is polysilicon and the spacer 202 is formed using silicon germanium.
• conventional lithography is used to form a gate mask photoresist pattern.
• a gate etch and trim process is performed to produce a formation a gate structure 221 as shown in FIGs 17 and 18.
• Gate structure 221 includes the remaining portions 220 of capping layer 210 and the remaining portions 212 of polysilicon spacers 202. The remaining spacer portions 212 are undercut with respect to capping layer portion 220 as shown in FIG 17.
• dielectric spacers 230 are formed where the voids 211 were present by depositing a dielectric such as silicon nitride and performing an anisotropic etch. Like the dielectric spacers 144 of FIG 10, dielectric spacers 230 are confined to the sidewalls of remaining (polysilicon) spacer portions 212, which serve as the gate electrode. The remaining portions of silicon fins 114 are exposed for subsequent silicide and selective epitaxial processing as described above with respect to FIGs 10 through 12. A third embodiment of a confined spacer processing sequence according to the present invention is depicted in FIGs 20 through 28.
• the fin formation sequence produces a silicon fin 314 that is thinner than the capping dielectric material (e.g., silicon nitride) 316 above.
• the silicon fin 314 is trimmed using a relatively isotropic dry etch to produce the under cut effect that leaves capping dielectric material 316 overhanging fin 314 and creating spaces or voids underneath and adjacent the primary faces of fins 314.
• a gate dielectric 320 is then formed (e.g., by thermal oxidation) on the primary faces of silicon film 314.
• FIG 22 shows the structure from above.
• a polysilicon (or other suitable gate electrode material) deposition is followed by a mask and etch sequence to produce the gate electrode structure 331, which includes a conductive gate electrode 330 and the remaining portions 326 of dielectric 316.
• the polysilicon etch of gate electrode 330 followed by the etch of layer 316 results in the remaining portions 326 of dielectric 316 having a "shouldered" appearance as shown in FIG 23. This can be achieved by a dry etch of the layer 316 that leaves a tapered profile or by trimming the polysilicon after the layer 316 has been etched.
• the remaining dielectric 326 includes a corner portion 327 at each the four corners defined by the gate electrode 330 and silicon fin 314.
• the four corner portions 327 cover underlying voids that are used to form confined spacers.
• dielectric spacers 340 are formed under the overlying corner portions 327 of dielectric 326.
• the spacers 340 are formed by depositing a dielectric such as silicon dioxide or silicon nitride and anisotropically etching the deposited dielectric layers. The spacers 340 are thus confined to the area under corner sections 327 of dielectric 326, adjacent the sidewalls of gate electrode 331.
• the remaining portions of silicon fin 314 may then be subjected to selective epitaxy and suicided .
• spacers are confined to the immediate vicinity of the gate electrode by forming structures that define voids adjacent the gate electrode sidewalls where the voids are covered from above.
• the spacers are then confined by depositing a dielectric and etching it anisotropically everywhere except where covered from above by the void-defining layer, whether it be a metal or a dielectric such as silicon nitride.
• the remaining and exposed portions of the silicon fins is suitable for silicide and selective epitaxial. The increase in the exposed areas of the silicon fins following spacer formation is beneficial in achieving low resistance, high performance transistors.

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• Thin Film Transistor (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Electrodes Of Semiconductors (AREA)

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• 2003
  • 2003-10-28 US US10/695,163 patent/US6951783B2/en not_active Expired - Lifetime
• 2004
  • 2004-10-20 CN CNA2004800317887A patent/CN1875456A/zh active Pending
  • 2004-10-20 JP JP2006538154A patent/JP2007510308A/ja active Pending
  • 2004-10-20 WO PCT/US2004/035349 patent/WO2005045892A2/en not_active Ceased
  • 2004-10-20 EP EP04796345A patent/EP1683186A4/en not_active Withdrawn
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