WO2005041420A1 - Appareil de decodage ou de codage, tampon intermediaire insere entre le decodeur ou l'encodeur de signes arithmetiques et dispositif de binarisation ou de debinarisation - Google Patents

Appareil de decodage ou de codage, tampon intermediaire insere entre le decodeur ou l'encodeur de signes arithmetiques et dispositif de binarisation ou de debinarisation Download PDF

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Publication number
WO2005041420A1
WO2005041420A1 PCT/JP2004/015981 JP2004015981W WO2005041420A1 WO 2005041420 A1 WO2005041420 A1 WO 2005041420A1 JP 2004015981 W JP2004015981 W JP 2004015981W WO 2005041420 A1 WO2005041420 A1 WO 2005041420A1
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Prior art keywords
binary
symbol
code
arithmetic
buffer
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PCT/JP2004/015981
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English (en)
Japanese (ja)
Inventor
Yuzo Senda
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Nec Corporation
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Priority to US10/577,146 priority Critical patent/US7301485B2/en
Priority to JP2005515029A priority patent/JP4677901B2/ja
Priority to EP20040817308 priority patent/EP1684435A4/fr
Publication of WO2005041420A1 publication Critical patent/WO2005041420A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
    • H03M7/4006—Conversion to or from arithmetic code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Definitions

  • Decoding device or coding device in which an intermediate buffer is inserted between a decoder or coding device for arithmetic code and an inverse binary conversion device or binary conversion device
  • the present invention relates to arithmetic code decoding and code decoding.
  • the present invention relates to decoding of an arithmetic code of a binary symbol sequence obtained by binarizing a multi-valued symbol and implementation of the encoding.
  • Binary arithmetic coding is one of the compression coding techniques.
  • binary coding a single multi-valued symbol is binarized to generate a binary symbol sequence, and the binary symbol sequence is arithmetically coded to obtain a final binary arithmetic code.
  • Arithmetic codes have higher processing costs than Huffman codes and so on, and have only been used in applications that do not require real-time processing such as file compression and still image compression.
  • Huffman codes High-speed processing of LSIs
  • they have also been adopted for video coding.
  • One of them is the Main Profile of H.264, a new international video codec standard established by the International Telecommunication Union ⁇ elecommunication Standardization Sector (ITU-T).
  • CABAC Context-based Adaptive Binary Arithmetic Coding
  • a multivalued symbol to be encoded is binarized in a sequence of binary symbols (Bin).
  • Transform (Binarization) and perform binary arithmetic coding on each Bin according to the probability estimation value for the Context defined for each Bin.
  • Binary conversion is the ability to convert a multi-value into a bit pattern according to a format defined by a mathematical expression. This can be considered as a simple variable length coding (VLC).
  • VLC variable length coding
  • the context selection uses the power of the original multivalued symbol, the parameters of the peripheral blocks, and the power of the binary symbol sequence.
  • decoding a probability estimate is obtained from the context of the binary symbol currently being decoded, and the arithmetic code is decoded. When the binary symbol is restored, the probability estimate is updated and the context of the next binary symbol to be decoded is selected.
  • FIG. 1 shows the overall configuration of an H.264 decoder.
  • the H.264 decoder includes a CPB buffer 41 that receives and holds a stream, and an instantaneous decoder 42 that decodes each frame at each frame interval.
  • the instantaneous decoder 42 includes a CA BAC decoder 43 and a block decoder 44.
  • the block decoder 44 performs inverse quantization, inverse discrete integer conversion, motion compensation prediction, in-loop filter processing, and the like, and has a processing cost proportional to the number of pixels.
  • the processing cost of the CABAC decoder 43 is proportional to the number of bins.
  • FIG. 2 shows details of the CABAC decoder.
  • the CABAC decoder 51 includes a binary arithmetic code decoder 54, an inverse binary transform 55, a memory 52 for storing a probability estimation value for each context, and a controller 53 for controlling these.
  • the processing unit is bin decoding, and the controller 53 updates the probability estimate every time the bin is decoded, and transitions the internal state according to the grammar of the H.264 standard. This Since these processes cannot be performed on multiple bins at once, the number of bins determines the processing cost.
  • Max MBPS is the maximum number of macroblocks per second
  • Delta Time is the frame time interval
  • Chroma For mat Factor is the ratio of the number of samples when the chrominance signal is added to the luminance signal
  • MinC R is the minimum compression ratio.
  • the maximum bit rate is 377Mbps. Since the compression ratio of Bin to Bit is specified to be 1.33 or less, it is 503MbinZsec when converted to the maximum Bin rate. Since the maximum bit rate is calculated by the average of the frame period, the maximum bin rate here is the value obtained by dividing the number of bins to be processed by the average of the frame period by the frame period. If the performance of the decoder does not achieve this maximum Bin rate, the decoding process will not be completed by the time the frame should be displayed, causing frame loss and! /
  • FIG. 3 shows the configuration of the H.264 encoder.
  • the block encoder 63 performs motion compensation prediction, discrete integer transform, quantization, inverse quantization, inverse discrete integer transform, and in-loop filter processing at the input pixel rate. Thereafter, the block information is converted into a Bin string by the binary conversion 64. The Bin sequence is converted into a code bit sequence by the arithmetic encoder 65 and sent to the output buffer 66. The accumulated amount of the output buffer 66 is fed back to the block encoder 63 and used for controlling the amount of code inside the block encoder 63. It is.
  • one element of block information for example, a conversion coefficient is converted into a plurality of bins.
  • the generation speed of the Bin sequence instantaneously exceeds 10 times the pixel rate.
  • the controller 62, the memory 61, and the arithmetic coder 65 that handle the bin sequence thereafter need to operate at that speed.
  • the maximum Bin rate of the H.264 encoder is 503 MbinZsec as in the case of the H.264 decoder.
  • An object of the present invention is to provide a decoder that decodes a binary coded arithmetic code in real time at a lower maximum Bin rate and a coder that performs encoding as compared with the related art. It is in.
  • a decoder of the present invention decodes a binary arithmetic code according to an input of a binary arithmetic code, and obtains an arithmetic code decoding unit that obtains a binary symbol.
  • the arithmetic code decoding means and the inverse binarization conversion means operate separately, and usually proceed at different speeds.
  • an encoder provides a binary conversion unit that converts a multilevel symbol into a binary symbol in accordance with the input of the multilevel symbol, It is characterized by having a buffer for storing, and an arithmetic coding means for extracting binary symbols according to its own output and generating binary arithmetic codes when extracting binary symbols from the buffer.
  • the arithmetic coding unit and the binarization conversion unit operate separately, and usually proceed at different speeds.
  • the processing performance that the arithmetic coding means should achieve is the output code It can be specified by the maximum value of the rate.
  • the processing performance to be achieved can be defined by the maximum value of the input multi-level symbol rate.
  • the maximum value of the binary symbol processing rate to be achieved by the decoder and the encoder of the binary arithmetic code can be significantly reduced.
  • the processing performance to be achieved by the arithmetic code decoding means of the present invention can be defined by the maximum value of the input code rate.
  • the processing performance to be achieved by the arithmetic code coding means of the present invention is to be the maximum value of the output code rate. Can be specified.
  • the stream is stored in the CPB buffer, but is not required in the present invention. Instead, it requires slightly more memory than a CPB buffer.
  • the compression ratio of arithmetic codes is limited to 1.33 or less, so the memory means only needs to be 1.33 times the size of the CPB buffer.
  • the encoder of the present invention has a buffer of binary or multilevel symbols! /, So it is delayed by the buffer delay, but the bit number estimating means obtains the actual number of code bits generated. So that a delay-free estimate can be provided as an alternative. Also, when code amount control such as a video encoder is required, the control becomes unstable when the number of generated bits is delayed, but in the present invention, since the estimated value can be used, the effect of buffer delay can be suppressed. .
  • FIG. 1 is a block diagram of an international standard ITU-T H.264 decoder.
  • FIG. 2 is a block diagram showing the inside of an H.264 CABAC decoder.
  • FIG. 3 is a block diagram of an H.264 encoder.
  • FIG. 4 is a block diagram of a video decoder using the decoder for binary coding arithmetic codes of the present invention.
  • FIG. 5 is a block diagram of a video encoder using the encoder of the binary arithmetic code of the present invention.
  • FIG. 6 is a block diagram of a decoder or encoder for a binary arithmetic code of the present invention.
  • FIG. 7 is a flowchart showing a decoding process of a binary arithmetic code according to the present invention.
  • FIG. 8 is a flowchart of a decoding subroutine of the present invention.
  • FIG. 9 is a flowchart showing the encoding process of the binary arithmetic code of the present invention.
  • FIG. 10 is a flowchart of an encoding subroutine of the present invention.
  • An arithmetic code decoder includes an arithmetic code decoder that obtains a binary symbol by decoding in accordance with an input of a binary arithmetic code, an intermediate buffer that stores binary symbols, A binary symbol sequence is extracted from the buffer, converted into a multi-valued symbol and output, and in accordance with the output of the multi-valued symbol, an inverse binary conversion unit is provided for extracting a binary symbol sequence from an intermediate buffer.
  • the arithmetic code encoder includes a binary conversion unit that converts a multilevel symbol into a binary symbol in accordance with the input of the multilevel symbol, and a buffer that stores the binary symbol. And, when extracting a binary symbol from the buffer, an arithmetic code converting means for extracting a binary symbol according to its own output and generating a binary arithmetic code.
  • the arithmetic code decoder includes an arithmetic code decoding means for decoding an arithmetic code according to an input of the arithmetic code to obtain a multi-level symbol, a buffer for storing the multi-level symbol, and a buffer.
  • the output device When extracting a multi-valued symbol, the output device has an inverse conversion means for extracting the multi-valued symbol according to its own output, converting the symbol into an output symbol, and outputting the output symbol.
  • the arithmetic code encoder includes a conversion means for converting an input symbol into a multi-level symbol in accordance with an input of an input symbol, a buffer for storing the multi-level symbol, and a non- When extracting a symbol, an arithmetic coding means for extracting an M-ary symbol according to its own output and generating an arithmetic code is provided.
  • FIG. 4 is a block diagram of a video decoder using the binary code arithmetic decoder according to the present invention.
  • the arithmetic code decoder 10 decodes the arithmetic code of the input stream to obtain a binary symbol (Bin), and supplies the binary symbol (Bin) to the controller 11 and the inverse binary conversion unit 12. Stored in The probability estimate of the context required for decoding is supplied from the controller 11.
  • the controller 11 converts the binary symbol to be currently decoded to the context.
  • the probabilistic estimation value is obtained from the memory 13 and the probability estimation value is supplied to the arithmetic code decoder 10.
  • block information stored in the memory 13 is used.
  • the controller 11 obtains a binary symbol from the arithmetic code decoder 10
  • the controller 11 updates the probability estimation value stored in the memory 13, and also converts the configuration information of the binary symbol sequence into an inverse binary converter 12. To supply.
  • the configuration information includes the parameter name indicated by the multi-valued symbol, the format information of the binary symbol string, and the timing for performing the inverse conversion.
  • the inverse binary transformation 12 converts a binary symbol sequence into a multivalued symbol as necessary based on the binary symbol obtained from the arithmetic code decoder 10 and the configuration information supplied from the controller 11. The conversion is performed, and the resulting block information is stored in the memory 13.
  • the block information to be stored in the memory 13 includes the quantized transform coefficient, quantization parameter, effective block pattern, prediction mode, and motion vector. For reference.
  • the intermediate notifier 14 stores the binary symbols obtained by the arithmetic code decoder 10, and supplies the binary symbols to the controller 15 and the inverse binary transformation 16 at the subsequent stage. Further, when supplying a binary symbol to the controller 15, the binary symbol is supplied based on an instruction from the controller 15.
  • the controller 15 obtains a binary symbol sequence from the intermediate buffer 14 according to the grammar of the stream, and supplies the configuration information to the inverse binarization converter 16.
  • the inverse binary conversion 16 obtains a binary symbol sequence from the intermediate buffer 14, converts the binary symbol sequence into a multi-level symbol from the configuration information supplied from the controller 15, and as a result, The obtained block information is supplied to the block decoder 17.
  • the block decoder 17 obtains a decoded image by performing inverse quantization, inverse integer transform, motion compensation prediction, and in-loop filter processing based on the block information supplied from the inverse binary transformation. , And outputs the obtained decoded image.
  • the process proceeds in accordance with a byte string or the like.
  • the controller 15 which is a block subsequent to the intermediate buffer 14, the inverse binary transformation 16, and the block decoder 17
  • the process proceeds according to the output of the image.
  • the arithmetic code decoder 10 and the inverse binary converter 16 operate independently, and usually perform processing at different speeds.
  • the intermediate buffer 14 absorbs the difference in the processing speed between before and after.
  • FIG. 5 is a block diagram of a video encoder using the encoder of the present invention.
  • the block encoder 20 refers to the estimated number of generated bits provided from the bit number estimator 27, and performs motion vector search, motion compensation prediction, discrete integer conversion, quantization, inverse Performs quantization, inverse discrete integer transform, and in-loop filter processing to generate block information.
  • the block information is information necessary for the stream configuration, and includes quantized transform coefficients, quantization parameters, effective block patterns, prediction modes, motion vectors, and the like.
  • the obtained block information is converted into a binary symbol sequence by a binary conversion 21, and the result is stored in the intermediate buffer 22.
  • the intermediate notifier 22 stores the binary symbol sequence converted by the binary conversion 21, and sends the binary symbol to the arithmetic coder 25 based on the instruction from the arithmetic coder 25. Supply. Further, the intermediate buffer 22 supplies the accumulated amount to the bit number estimator 27.
  • the inverse binary conversion 23 restores block information from the binary symbol sequence obtained from the intermediate buffer 22 and the configuration information supplied from the controller 24, and stores the block information in the memory 26.
  • the controller 24 refers to the block information to be restored.
  • the controller 24 selects a context from the binary symbols to be currently encoded according to the grammar of the stream, obtains the probability estimate from the memory 26, and sends the probability estimate to the arithmetic coder 25. Supply.
  • a context block information stored in the memory 26 is used if necessary.
  • the probability estimation value stored in the memory 26 is updated, and the configuration information of the binary symbol sequence is supplied to the inverse binarization converter 23.
  • Arithmetic encoder 25 performs binary arithmetic encoding from the binary symbols obtained from intermediate buffer 22 and the probability estimation values obtained from controller 24, and outputs the resulting stream. Further, the number of binary symbols read by the arithmetic coding and the number of bits of the generated code are supplied to the bit number estimator 27. [0049] The bit number estimator 27 estimates the relationship between the number of binary symbols and the number of code bits from the number of binary symbols and the number of code bits supplied from the arithmetic encoder 25, and is supplied from the intermediate buffer 22. The amount of accumulation is converted into the number of bits to determine the number of generated bits, which is supplied to the block encoder 20.
  • the binary conversion 21 and the arithmetic encoder 25 operate separately, and usually perform processing at different speeds.
  • Intermediate buffer 22 absorbs the difference in processing speed between before and after.
  • FIG. 6 is a block diagram showing another embodiment of the present invention.
  • the processing unit 31 decodes the arithmetic code, and the processing unit 32 performs the inverse binarization conversion.
  • the memory 33 is accessible from the processing unit 31 and the processing unit 32, and includes a code string that is an input to the processing unit 31, a binary symbol string that is an output of the processing unit 31 and an input to the processing unit 32, and a It holds multivalued symbols to be output, expected probability values required for processing, and block information.
  • FIG. 6 shows the processing unit 31 and the processing unit 32 in order to show a logical configuration
  • the operating system provides a multi-process function
  • the memory 33 does not need to be physically a single memory, and may be accessed only from the processing unit 31.
  • the variables may be directly connected to the processing unit 31 instead of the bus connection.
  • the syntax of the encoding scheme includes an encoding mode, a motion vector, a coded flag, and a coefficient, and it is assumed that these are binary arithmetically encoded.
  • the presence or absence of motion vector information can be known from the coding mode, and the coded flag can be known whether or not there is a coefficient.
  • step A100 initialization is performed in step A100.
  • the probability per context Set the estimate to the initial value.
  • step A110 the coding mode of the block is decoded.
  • step All 1 the process branches depending on whether there is motion vector information. If there is motion vector information, the process proceeds to step A120. If there is no motion vector information, the process proceeds to step A130.
  • step A120 the motion vector horizontal value is decoded.
  • step A121 the motion solid vertical value is decoded.
  • step A130 the coded flag is decoded.
  • step A131 branch is made depending on whether or not there is a coefficient. If there is a coefficient, go to step A140. If there is no coefficient, go to step A150.
  • step A140 the coefficients are decoded.
  • step A141 branching is performed depending on whether the coefficient is completed. In the case of termination, the flow proceeds to step A150, and in the case where the coefficient is continued, the flow proceeds to step A140.
  • Step A150 branches depending on whether or not the code string ends. If not, go to step All 0
  • step A10 the symbol string buffer is emptied.
  • Step Al 1 selects a context that conforms to the current syntax. If necessary, use information on peripheral blocks.
  • step A12 a probability estimate of the current context is obtained.
  • step A13 the arithmetic code is decoded. Waits for code input, and if input, compares the current value of the codeword with the probability estimate and obtains a binary symbol from the magnitude relationship. If the operation is symmetrical with respect to the binary symbols 0 and 1, the probability estimate can be expressed (symmetrically expressed) by the MPS value and the MPS probability estimate.
  • MPS is a symbol with a high estimated probability of occurrence, and the estimated value of MPS takes a value from 0.5 to 1.
  • step A14 the obtained binary symbols are stored in the symbol string buffer and output to the memory.
  • step A15 the probability estimation value is updated according to the value of the binary symbol. If the probability estimate is a symmetric representation, the MPS is inverted if the MPS probability estimate is less than 0.5.
  • step A16 the binary symbol sequence in the symbol sequence buffer is completed to form a complete binary symbol sequence! /! Branch whether or not. If a complete binary symbol sequence is constructed, the process proceeds to step A17; otherwise, the process returns to step Al1 to continue decoding the arithmetic code.
  • step A17 inverse binary conversion is performed as necessary.
  • the required conditions include elements related to syntax and elements that may be referred to in context selection.
  • the entire processing flow operates according to the flow of FIG. However, the decryption subroutine called is different from the processing unit 31.
  • the decoding subroutine used in the processing unit 32 is inverse binary conversion, and decodes a multilevel symbol from a binary symbol sequence. Since the processing unit 32 does not relate to the arithmetic code, it is not necessary to set the probability estimation value to the initial value in step A100.
  • the processing unit 31 performs a binary conversion
  • the processing unit 32 performs an arithmetic coding.
  • the memory 33 is accessible from the processing unit 31 and the processing unit 32, and is a multi-valued symbol input to the processing unit 31, a binary symbol string output from the processing unit 31 and input to the processing unit 32, and a processing unit. It holds 32 output code strings, probability expected values and block information required for processing.
  • step A200 initialization is performed.
  • step A210 the encoding mode of the block is encoded.
  • step A211 the process branches depending on whether there is motion vector information. If there is, go to step A220; otherwise, go to step A230.
  • step A220 the motion vector horizontal value is encoded.
  • step A221 the vertical value of the motion vector is encoded.
  • step A230 the coded flag is encoded.
  • step A231 the process branches depending on whether or not there is a coefficient. If there is a coefficient, go to step A240. If there is no coefficient, go to step A250.
  • step A240 the coefficients are coded.
  • step A241 the process branches depending on whether or not the coefficient ends. In the case of termination, the process proceeds to step A250.
  • Step A250 branches depending on whether or not the encoding is completed. If not, the process proceeds to step A210.
  • the encoding process performed in these steps is a binarization conversion, in which a multi-level symbol is converted into a binary symbol sequence, and an output subroutine for outputting is called to call! / ⁇ .
  • the In the output subroutine the number of output binary symbols is counted and external reference is possible.
  • step A200 an encoding subroutine called initialization of step A200 is different from the processing unit 31.
  • the encoding subroutine used in the processing unit 32 the multi-level symbol is decoded from the binary symbol sequence by the inverse binary conversion, and the arithmetic encoding of the binary symbol sequence is performed.
  • the probability expected value is set to an initial value in the initialization of step A200.
  • step A20 inverse binary conversion is performed to output multi-valued symbols and store the corresponding binary symbol sequence in a symbol sequence buffer.
  • step A21 a probability estimate of the current context is obtained.
  • step A23 one binary symbol is extracted from the head of the symbol string buffer, subjected to arithmetic coding, and output.
  • the number of arithmetic codes and the number of generated bits are counted, and external reference is possible.
  • step A24 the probability estimation value is updated according to the value of the binary symbol. If the probability estimate is a symmetric representation, the MPS is inverted if the MPS probability estimate is less than 0.5.
  • step A25 the operation branches depending on whether the symbol string buffer is empty. If the symbol string buffer is empty, the process ends; otherwise, the process returns to step A21 to continue the arithmetic coding.
  • the processing section 31 outputs the binary symbol power output.
  • the processing section 32 knows the number of arithmetic coding and the number of generated bits.
  • the number of binary symbols stored in the memory can be obtained by reducing the number of output binary symbols and the number of arithmetic coding.
  • the relationship between the number of binary symbols and the number of code bits can be obtained from the number of arithmetic code conversions and the number of generated bits.
  • These values can also calculate the estimated number of generated bits.
  • the estimated number of generated bits may be calculated in an output subroutine of the processing unit 31 so that it can be referred to from outside, or the original value may be calculated outside.
  • the computer system is equipped with a CPU, and a buffer and a memory are connected to the CPU.
  • the memory stores programs for executing the decoding process and the encoding process according to the present invention. By executing this program on the CPU, the decoding process and the encoding process in the present invention are executed.
  • the power described above is not limited to application to binary arithmetic codes.
  • the decoder and encoder of the quaternary arithmetic code of the present invention can be configured simply by replacing the binary in the figures and explanations with a quaternary code. Further, even in a case where binary and ternary arithmetic codes are mixed, a configuration may be adopted in which the processing of binary arithmetic codes and the processing of ternary arithmetic codes are switched according to the context.
  • the present invention is not limited to these applications. If the block decoder 17 is replaced with an audio frame decoder and the block encoder 20 is replaced with an audio frame encoder, the present invention can be easily applied to an audio decoder and an audio encoder. In other media and data encoders and decoders, as long as the encoders and decoders use the binary coding algorithm, the encoder and decoder of the binary coding code of the present invention can be used as in the case of video and audio. A decoder can be applied.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Image Processing (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)

Abstract

L'invention concerne un décodeur de signaux arithmétiques binaires, le décodage et la débinarisation du signe arithmétique étant séparés et un grand tampon intermédiaire étant inséré entre eux. Le décodage du signe arithmétique est exécuté, lorsque un flux est introduit. De cette manière, le signe arithmétique nécessite seulement un décodage au taux de bits d'entrée maximum du décodeur. La séquence de symboles binarisés obtenue est stockée temporairement dans le tampon intermédiaire. Puis, la débinarisation de la séquence de symboles binarisés en symboles à plusieurs niveaux est effectuée d'après le traitement d'un décodeur de blocs dans l'étape suivante.
PCT/JP2004/015981 2003-10-29 2004-10-28 Appareil de decodage ou de codage, tampon intermediaire insere entre le decodeur ou l'encodeur de signes arithmetiques et dispositif de binarisation ou de debinarisation WO2005041420A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/577,146 US7301485B2 (en) 2003-10-29 2004-10-28 Decoding device or encoding device having intermediate buffer interposed between an arithmetic code decoder or encoder and a reverse binarization device or binarization device
JP2005515029A JP4677901B2 (ja) 2003-10-29 2004-10-28 算術符号の復号器または符号化器と逆２値化変換器または２値化変換器との間に中間バッファが挿入された復号装置または符号化装置
EP20040817308 EP1684435A4 (fr) 2003-10-29 2004-10-28 Appareil de decodage ou de codage, tampon intermediaire insere entre le decodeur ou l'encodeur de signes arithmetiques et dispositif de binarisation ou de debinarisation

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JP2003369176 2003-10-29

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JP2007116436A (ja) * 2005-10-20 2007-05-10 Matsushita Electric Ind Co Ltd 符号化装置及び復号化装置
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EP1684435A1 (fr) 2006-07-26
US20070040708A1 (en) 2007-02-22
JPWO2005041420A1 (ja) 2007-10-04
EP1684435A4 (fr) 2007-01-10
TWI311870B (fr) 2009-07-01
KR100801364B1 (ko) 2008-02-05
JP4677901B2 (ja) 2011-04-27
US7301485B2 (en) 2007-11-27
TW200518481A (en) 2005-06-01
CN1875545A (zh) 2006-12-06
KR20060064008A (ko) 2006-06-12

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