WO2005031869A1 - 半導体装置,半導体装置の製造方法,半導体製造装置及びコンピュータ記録媒体 - Google Patents
半導体装置,半導体装置の製造方法,半導体製造装置及びコンピュータ記録媒体 Download PDFInfo
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- WO2005031869A1 WO2005031869A1 PCT/JP2004/013823 JP2004013823W WO2005031869A1 WO 2005031869 A1 WO2005031869 A1 WO 2005031869A1 JP 2004013823 W JP2004013823 W JP 2004013823W WO 2005031869 A1 WO2005031869 A1 WO 2005031869A1
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- lower electrode
- capacitor
- semiconductor device
- insulating film
- plasma
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000003990 capacitor Substances 0.000 claims abstract description 61
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000012545 processing Methods 0.000 claims description 54
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 33
- 239000007789 gas Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 26
- 238000005121 nitriding Methods 0.000 claims description 25
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 24
- 150000004767 nitrides Chemical class 0.000 claims description 16
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 6
- 238000009832 plasma treatment Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 21
- 238000007254 oxidation reaction Methods 0.000 abstract description 21
- 230000000694 effects Effects 0.000 abstract description 12
- 238000010438 heat treatment Methods 0.000 abstract description 12
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 69
- 239000010410 layer Substances 0.000 description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 20
- 229910052710 silicon Inorganic materials 0.000 description 20
- 239000010703 silicon Substances 0.000 description 20
- 229910052757 nitrogen Inorganic materials 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 239000012788 optical film Substances 0.000 description 3
- 239000003507 refrigerant Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 241000656145 Thyrsites atun Species 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002831 nitrogen free-radicals Chemical class 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 1
- 241001602688 Pama Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- -1 nitrogen nitride Chemical class 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3211—Nitridation of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Definitions
- the present invention relates to a semiconductor device having a capacitor formed by using a plasma process, a method of manufacturing the same, a semiconductor manufacturing device capable of performing a plasma process used when forming the capacitor, and a computer recording device.
- Media related a semiconductor device having a capacitor formed by using a plasma process, a method of manufacturing the same, a semiconductor manufacturing device capable of performing a plasma process used when forming the capacitor, and a computer recording device.
- a DRAM as a semiconductor device has a structure in which a memory cell has a MOS transistor and a capacitor for storing a charge for storage.
- MOS transistor MOS transistor
- capacitor for storing a charge for storage.
- reduction in the size of transistors and capacitors in the semiconductor devices has been required.
- the capacitance of a capacitor is proportional to its area and inversely proportional to its thickness, there is naturally a limit in reducing its thickness.
- Insulator Semiconductor structure is often used.
- polysilicon is used for the semiconductor layer (lower electrode) of the MIS structure.
- titanium nitride may be used in a peripheral circuit of a logic device instead of the lower electrode made of a polysilicon material.
- the surface of titanium nitride as the lower electrode of the capacitor is oxidized when heat-treated as in the case of polysilicon. As a result, TiO is formed and the conductive resistance increases.
- Another problem is that the apparent thickness of the insulating film constituting the capacitor increases and the capacitance decreases.
- Japanese Patent Publication No. 2001-274148 discloses a method of forming a silicon nitride film on a silicon oxide film by plasma processing.
- Patent Document 1 Japanese Patent Publication No. 2001-274148
- the present invention has been made in view of the above situation, and has as its object to provide a semiconductor device capable of suppressing a decrease in the capacitance of a capacitor without increasing the film thickness, a method of manufacturing the same, and a manufacturing apparatus thereof. And It also aims to suppress leakage current in capacitors.
- a first aspect of the present invention is a semiconductor device having a capacitor, wherein the capacitor includes a lower electrode, an upper electrode, the lower electrode, and the upper electrode. And a surface of the lower electrode on the side of the insulating layer is nitrided.
- a second aspect of the present invention is a method of manufacturing a semiconductor device, comprising: forming a lower electrode for a capacitor on a semiconductor substrate; nitriding a surface of the lower electrode; Forming an insulating film on the electrode; and forming an upper electrode on the insulating film.
- a third aspect of the present invention relates to an apparatus used in a manufacturing process of a capacitor having an upper electrode, a lower electrode, and an insulating film formed between these electrodes.
- a processing container for accommodating a semiconductor substrate; a gas supply unit for supplying a gas according to a process into the processing container; and a microwave supply unit for supplying a microwave for exciting plasma in the processing container. . Then, after loading the semiconductor substrate on which the lower electrode is formed into the processing container so as to form a nitride film on the surface of the lower electrode, the gas supply unit supplies nitrogen gas to the processing container.
- the surface is nitrided, thereby improving the oxidation resistance during a heat treatment in a later step.
- the capacitance of the capacitor is large, the effect when the present invention is applied to the DRAM capacitor is more remarkable.
- the surface of the titanium nitride Nitriding to form a nitrogen-rich layer improves the oxidation resistance during the heat treatment in a later step, as in the case of the lower electrode made of polysilicon.
- a step of forming a lower electrode for a capacitor on a semiconductor substrate, a step of nitriding a surface of the lower electrode, a step of forming an insulating film on the lower electrode, and a step of forming an upper electrode on the insulating film Is performed, for example, in a semiconductor manufacturing apparatus.
- Each of these steps is executed by the computer controlling the semiconductor manufacturing apparatus based on the software of the computer recording medium.
- FIG. 1 is an explanatory view of a cross section showing a structure of a capacitor according to a first embodiment of the present invention.
- FIG. 2 is a flowchart illustrating an example of a method for manufacturing a semiconductor device of the present invention.
- FIG. 3 is a cross-sectional view illustrating a structure of a plasma processing apparatus according to the present invention.
- FIG. 4 is a graph showing the operation and effect of the capacitor according to the first embodiment.
- FIG. 5 is an explanatory diagram of a cross section showing a structure of a capacitor according to a second example of the present invention.
- FIG. 6 is a process chart showing a part of the manufacturing process of the capacitor according to the second embodiment.
- FIG. 6 (A) shows a state of depositing titanium nitride
- FIG. 6 (B) shows a nitrogen nitride by plasma nitriding.
- FIG. 4 shows a state in which a layer is formed.
- FIG. 7 is a graph showing the operation and effect of the capacitor according to the second embodiment.
- FIG. 8 is a graph showing the operation and effect of the capacitor according to the second embodiment.
- FIG. 9 is a graph showing the pressure dependency of the film thickness during the plasma nitriding treatment.
- Each of the multiple memory cells that make up the DRAM has a structure that includes one MOS transistor, one capacitor, and an element isolation region.
- a MOS transistor is composed of, for example, a source electrode and a drain electrode, a gate insulating film and a gate electrode, which are N-type doped on a P-type silicon substrate.
- the drain electrode is connected to a bit line.
- the gate electrode is connected to a word line.
- a protective oxide film is formed around the gate electrode.
- FIG. 1A shows the structure of the capacitor 10 according to the first embodiment of the present invention.
- the capacitor 10 includes an interlayer insulating film 17 formed on a silicon substrate 11, a lower electrode 12 formed on the interlayer insulating film 17, an insulating film 14 formed on the lower electrode 12, and an insulating film 14. And an upper electrode layer 16 formed thereon.
- the upper electrode layer 16 is a metal layer such as TiN, and the lower electrode 12 also has a polysilicon force.
- the lower electrode 12 has a nitride layer 18 on the side in contact with the insulating film 14.
- the capacitor 10 is electrically connected to the source 15 of the MOS transistor and the polysilicon 19.
- a contact hole is opened in the interlayer insulating film 17 by etching, and polysilicon is deposited by a CVD method or the like to form the lower electrode 12 (Step Sl).
- a nitride layer 18 (polysilicon nitride film) is formed on the surface of the lower electrode 12 by plasma nitriding (step S2).
- the insulating film 14 is formed on the nitride film 18 (Step S3).
- further upper electrode layer 16 is formed (Step S4).
- Step S4 necessary etching is performed to form a concavo-convex shape in order to increase the surface area, and the capacitor 10 is formed.
- FIG. 3 schematically shows a configuration of a semiconductor manufacturing apparatus (plasma processing apparatus) 20 used for the plasma nitriding processing of the present invention.
- the semiconductor manufacturing apparatus 20 has a processing vessel 21 provided with a substrate holding table 22 for holding a silicon wafer W as a substrate to be processed.
- a heater 22a is provided inside the substrate holder 22, and the silicon wafer W can be heated to a desired temperature by supplying power from a power supply 22b.
- the gas (gas) in the processing vessel 21 is exhausted from the exhaust ports 21A and 21B via an exhaust pump 21C.
- a gas baffle plate (partition plate) 211 that also has an aluminum force is arranged around the substrate holding table 22.
- a quartz cover 212 is provided on the upper surface of the gas baffle plate 211.
- An opening is provided above the processing container 21 so as to correspond to the silicon wafer W on the substrate holder 22. This opening is closed by a dielectric plate 23 that also generates quartz or Al 2 O force.
- a planar antenna 24 is disposed above the dielectric plate 23 (outside the processing container 21).
- the planar antenna 24 has a plurality of slots 24a for transmitting electromagnetic waves supplied from the waveguide.
- a wavelength shortening plate 25 and a waveguide 28 are arranged.
- a cooling plate 26 is arranged outside the processing vessel 21 so as to cover the upper part of the wavelength shortening plate 25. Inside the cooling plate 26, a refrigerant passage 26a through which the refrigerant flows is provided.
- a gas supply port 27 for introducing a gas during plasma nitriding is provided on the inner side wall of the processing container 21.
- an argon gas supply source 41 and a nitrogen gas supply source 42 are prepared as processing gas supply sources, and valves 41a and 42a, mass flow controllers 41b and 42b for adjusting flow rates, and valves 41c and 42c are provided. It is connected to the gas supply port 27 via. Further, inside the inner wall of the processing container 21, a refrigerant channel 21a is formed so as to surround the entire container.
- the semiconductor manufacturing apparatus 20 is provided with an electromagnetic wave generator (magnetron) 29 for generating electromagnetic waves of several GHz for exciting plasma.
- the microwave generated by the electromagnetic wave generator 29 propagates through the waveguide 28 and is introduced into the processing vessel 21.
- the semiconductor manufacturing apparatus 20 is controlled by a control device 51.
- the control device 51 has a central processing unit 52, a support circuit 53, and a recording medium 54 containing the related control software.
- the control device 51 controls, for example, the supply and stop of the gas from the gas supply port 27, the flow rate adjustment, the temperature adjustment of the heater 22a, the exhaust of the exhaust pump 21C, and the electromagnetic wave generator 29, and the like. The necessary control in each process in which the plasma processing is performed is performed.
- the central processing unit 52 of the control device 51 a processor of a general-purpose computer can be used.
- the storage medium 54 various types of storage media such as a RAM, a ROM, a flexible disk, and a hard disk can be used.
- the support circuit 53 is connected to the central processing unit 52 to support the processor in various ways.
- the main part of the semiconductor manufacturing equipment 20 is configured as described above! RU
- the wafer W having the lower electrode 12 formed on the silicon substrate 11 is set on the substrate holder 22. After that, the air inside the processing vessel 21 is exhausted through the exhaust ports 21A and 21B. The inside of the processing container 21 is set to a predetermined processing pressure. An inert gas such as an argon gas and a nitrogen gas is supplied from the gas supply port 27.
- the microwave having a frequency of several GHz generated by the electromagnetic wave generator 29 is supplied to the processing container 21 through the waveguide 28.
- the microwave is introduced into the processing vessel 21 via the planar antenna 24 and the dielectric plate 23.
- the microwave excites the plasma to generate nitrogen radicals.
- the high-density plasma generated by the microwave excitation in the processing vessel 21 generates a nitride layer 18 on the surface of the lower electrode 12.
- an insulating film 14 is formed on the lower electrode 12.
- the insulating film 14 is made of, for example, a silicon oxide film.
- the upper electrode layer 16 is formed on the insulating film 14, and the capacitor 10 is formed.
- heat treatment is performed in the step of forming the insulating film 14 or the step of forming the upper electrode 16, since the nitride layer 18 is formed on the lower electrode 12, the upper surface of the lower electrode 12 is effectively oxidized. Be suppressed.
- the upper electrode 16 can be made of polysilicon instead of a metal material such as titanium nitride or aluminum.
- a metal material such as titanium nitride or aluminum.
- the No. 1 force No. 3 is the silicon substrate subjected to the plasma nitriding treatment based on the present invention.
- a mixed gas of argon gas and nitrogen gas was used as the processing gas.
- the flow rate ratio was 1000Z40 (sccm) in each case.
- the plasma output during the plasma processing was 3500 W, the processing pressure was 67 Pa, and the processing temperature was 400 ° C.
- No. 1 power No. 3 pama f3 ⁇ 4 force S was different during plasma treatment, No. 1 pike 30 hectares, No. 2 pike 120 heaps, and ⁇ . 3 were 300 seconds. No.
- FIG. 4 shows data of a silicon substrate treated with a high-speed thermal nitride film as a comparative example.
- the processing time was 180 seconds.
- seven samples were prepared for each of No. 1 force and No. 4 samples. Samples No. 1 to No. 4 above were subjected to thermal oxidation treatment between 600 ° C and 900 ° C after the above nitriding treatment.
- FIG. 4 shows the effect on the nitride film in the experiment shown in Table 1.
- the vertical axis represents the amount of increase in optical film thickness due to oxidation of the nitride film, and the unit is angstrom.
- the horizontal axis shows the processing temperature of the high-speed thermal oxidation processing, and the unit is Celsius.
- Each point in the figure represents the amount of film increase due to thermal oxidation of the nitride film at the thermal oxidation treatment temperature.
- the plasma-nitrided sample had a relatively small increase in optical film thickness compared to the high-speed thermal nitridation, and the effect of thermal oxidation was relatively small. Is small.
- the longer the plasma nitridation time the smaller the increase in optical film thickness.
- the longer the plasma nitridation time, the thicker the nitride film, and the thicker the nitrided film by the plasma nitridation treatment the less the effect of the thermal oxidation treatment, and the better the oxidation resistance.
- the capacitor 100 has a lower electrode layer 112 made of titanium nitride, in which a via hole is opened by etching on an interlayer insulating film 117 formed on an interlayer insulating film 111, a noria metal 32 and a via metal 119 are embedded,
- the insulating film 14 formed on the lower electrode layer 112 and the upper electrode 16 formed on the insulating film 14 are formed by CVD.
- the upper electrode 16 is a metal layer such as TiN.
- a nitrogen-rich layer 118 is formed on a surface in contact with the insulating film.
- a via hole is opened by etching on the interlayer insulating film 117 formed by the CVD method or the like on the interlayer insulating film 111, and the via metal 32 and the via metal 119 are buried.
- a lower electrode 112 is formed by depositing titanium nitride thereon. Thereafter, a nitrogen-rich layer 118 is formed on the surface of the lower electrode 112 by plasma nitriding (see FIGS. 6A and 6B).
- a part of the manufacturing process of the capacitor 100 according to the present embodiment is performed by the plasma processing apparatus 20 shown in FIG.
- the wafer W having the lower electrode 112 formed on the silicon substrate 11 is set on the substrate holder 22 of the plasma processing apparatus 20.
- the air inside the processing vessel 21 is exhausted through the exhaust ports 21A and 21B.
- the inside of the processing container 21 is set to a predetermined processing pressure. Inert gas and nitrogen gas are supplied from the gas supply port 27.
- the microwave having a frequency of several GHz generated by the electromagnetic wave generator is supplied to the processing container 21 through the waveguide 28.
- the microwave is introduced into the processing vessel 21 via the planar antenna 24 and the dielectric plate 23.
- the plasma is excited by the microwaves to generate nitrogen radicals.
- the high-density plasma generated by the microwave excitation in the processing vessel 21 here forms an additional nitride layer 118 on the surface of the lower electrode 112. under Since the part electrode 112 is made of titanium nitride, nitrogen is distributed throughout the part electrode 112.
- the nitrogen-rich layer 118 is formed by doping nitrogen by plasma nitriding. For this reason, the nitrogen-rich layer 118 is a layer having a higher nitrogen content in the lower electrode 112 than in other regions.
- the insulating film 14 is formed on the lower electrode 112.
- This insulating film 14 is made of, for example, a silicon oxide film.
- an upper electrode 16 is formed on the insulating film 14, and a capacitor 100 is formed.
- heat treatment is performed in the step of forming the insulating film 14 or the step of forming the upper electrode 16, the nitrogen-rich layer 118 is formed on the lower electrode 112. Is suppressed.
- the upper electrode 16 may be made of polysilicon instead of a metal material such as titanium nitride or aluminum.
- a silicon oxynitride film, a silicon oxynitride film, a silicon oxidized tantalum, a silicon oxidized aluminum, or the like can be used in addition to the silicon oxidized film.
- FIG. 7 shows the relationship between the processing time of the plasma nitriding treatment of the lower electrode 112 and the sheet resistance.
- the gas pressure was measured separately for 01: 1: (133 &), 100 mT (13.3 Pa), and 500 mT (13.3 X 5 Pa).
- the lower the gas pressure of nitrogen the lower the sheet resistance.
- the higher the gas pressure the more efficiently the nitrogen-rich layer 118 can be formed.
- a sample was prepared by plasma nitriding to form a nitrogen-rich layer.
- Two types of samples according to the present invention were prepared, one with a plasma nitridation time of 120 seconds (mouth in FIG. 8) and one with a plasma nitridation time of 30 seconds ((in FIG. 8).
- a substrate with only a titanium nitride film ( ⁇ in Fig. 8) without plasma nitridation was also used.
- FIG. 8 shows the measurement results.
- the vertical axis represents the sheet resistance of the titanium nitride film (lower electrode 112).
- the horizontal axis shows the reference value (TiN as depo) before the plasma oxidation treatment and the oxide film thickness when the plasma oxidation treatment was performed on the silicon substrate finished with hydrofluoric acid. Angstrom is indicated. The larger the oxide film thickness, the longer the plasma oxidation treatment time.
- FIG. 9 shows the film thickness when the lower electrode of the Si is subjected to the plasma nitriding treatment by changing the pressure at the time of the plasma treatment in the capacitor having the irregular surface of the lower electrode.
- Open means that the unevenness of the lower electrode surface is sparse
- Dense means that the unevenness of the lower electrode surface is dense, and indicates the film thickness of the bottom in the recess.
- the uniformity of the film thickness was dependent on the pressure during the plasma nitriding treatment. According to the verification by the inventors, the pressure was 1 Torr (133 Pa)-5 Torr. (5 X 133 Pa), more preferably around 3 Torr (3 X 133 Pa).
- a thin-film capacitor can be manufactured without lowering the capacity, which is useful for manufacturing a semiconductor device, for example, a DRAM.
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04788006A EP1670060A1 (en) | 2003-09-26 | 2004-09-22 | Semiconductor device, semiconductor device manufacturing method, semiconductor device manufacturing apparatus, and computer recording medium |
JP2005514196A JPWO2005031869A1 (ja) | 2003-09-26 | 2004-09-22 | 半導体装置,半導体装置の製造方法,半導体製造装置及びコンピュータ記録媒体 |
US11/388,990 US7524774B2 (en) | 2003-09-26 | 2006-03-27 | Manufacturing method of semiconductor device, semiconductor manufacturing apparatus, plasma nitridation method, computer recording medium, and program |
Applications Claiming Priority (2)
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JP2003334479 | 2003-09-26 |
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WO2005031869A1 true WO2005031869A1 (ja) | 2005-04-07 |
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PCT/JP2004/013823 WO2005031869A1 (ja) | 2003-09-26 | 2004-09-22 | 半導体装置,半導体装置の製造方法,半導体製造装置及びコンピュータ記録媒体 |
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EP (1) | EP1670060A1 (ja) |
JP (2) | JPWO2005031869A1 (ja) |
KR (1) | KR20060058723A (ja) |
CN (1) | CN1820370A (ja) |
TW (1) | TWI256703B (ja) |
WO (1) | WO2005031869A1 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007005696A (ja) * | 2005-06-27 | 2007-01-11 | Tokyo Electron Ltd | プラズマ窒化処理方法および半導体装置の製造方法 |
JP2007067366A (ja) * | 2005-08-05 | 2007-03-15 | Elpida Memory Inc | 半導体記憶装置の製造方法 |
US7524774B2 (en) | 2003-09-26 | 2009-04-28 | Tokyo Electron Limited | Manufacturing method of semiconductor device, semiconductor manufacturing apparatus, plasma nitridation method, computer recording medium, and program |
JP2010135812A (ja) * | 2010-01-13 | 2010-06-17 | Tokyo Electron Ltd | 半導体装置の製造方法 |
JP2013503489A (ja) * | 2009-08-26 | 2013-01-31 | クアルコム,インコーポレイテッド | 磁気ランダムアクセスメモリを製造するシステムおよび方法 |
Families Citing this family (1)
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WO2019133509A2 (en) * | 2017-12-29 | 2019-07-04 | Applied Materials, Inc. | Method of reducing leakage current of storage capacitors for display applications |
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JP2003124348A (ja) * | 2001-10-17 | 2003-04-25 | Elpida Memory Inc | 半導体装置及びその製造方法 |
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JP3597334B2 (ja) * | 1996-12-17 | 2004-12-08 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
JP2000353780A (ja) * | 1999-06-11 | 2000-12-19 | Sony Corp | 容量素子の製造方法及び容量素子 |
KR100338110B1 (ko) * | 1999-11-09 | 2002-05-24 | 박종섭 | 반도체 소자의 캐패시터 제조방법 |
TW557514B (en) * | 2001-08-02 | 2003-10-11 | Tokyo Electron Ltd | Method for processing a substrate and material for electronic devices |
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2004
- 2004-09-22 WO PCT/JP2004/013823 patent/WO2005031869A1/ja active Application Filing
- 2004-09-22 CN CNA2004800197160A patent/CN1820370A/zh active Pending
- 2004-09-22 JP JP2005514196A patent/JPWO2005031869A1/ja active Pending
- 2004-09-22 EP EP04788006A patent/EP1670060A1/en not_active Withdrawn
- 2004-09-22 KR KR1020067005870A patent/KR20060058723A/ko active Search and Examination
- 2004-09-24 TW TW093129060A patent/TWI256703B/zh not_active IP Right Cessation
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2011
- 2011-05-17 JP JP2011110612A patent/JP2011155312A/ja active Pending
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JP2000208744A (ja) * | 1999-01-12 | 2000-07-28 | Lucent Technol Inc | 五酸化タンタル層を用いた集積回路用コンデンサを製造するための方法 |
JP2001257327A (ja) * | 2000-03-10 | 2001-09-21 | Nec Corp | 半導体装置およびその製造方法 |
JP2003092361A (ja) * | 2001-06-29 | 2003-03-28 | Hynix Semiconductor Inc | 酸化タンタルコンデンサーの形成方法 |
JP2003124348A (ja) * | 2001-10-17 | 2003-04-25 | Elpida Memory Inc | 半導体装置及びその製造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7524774B2 (en) | 2003-09-26 | 2009-04-28 | Tokyo Electron Limited | Manufacturing method of semiconductor device, semiconductor manufacturing apparatus, plasma nitridation method, computer recording medium, and program |
JP2007005696A (ja) * | 2005-06-27 | 2007-01-11 | Tokyo Electron Ltd | プラズマ窒化処理方法および半導体装置の製造方法 |
JP4522916B2 (ja) * | 2005-06-27 | 2010-08-11 | 東京エレクトロン株式会社 | プラズマ窒化処理方法、制御プログラム、コンピュータ記憶媒体およびプラズマ処理装置 |
JP2007067366A (ja) * | 2005-08-05 | 2007-03-15 | Elpida Memory Inc | 半導体記憶装置の製造方法 |
JP2013503489A (ja) * | 2009-08-26 | 2013-01-31 | クアルコム,インコーポレイテッド | 磁気ランダムアクセスメモリを製造するシステムおよび方法 |
JP2014170964A (ja) * | 2009-08-26 | 2014-09-18 | Qualcomm Inc | 磁気ランダムアクセスメモリを製造するシステムおよび方法 |
JP2010135812A (ja) * | 2010-01-13 | 2010-06-17 | Tokyo Electron Ltd | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
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JPWO2005031869A1 (ja) | 2006-12-07 |
EP1670060A1 (en) | 2006-06-14 |
CN1820370A (zh) | 2006-08-16 |
JP2011155312A (ja) | 2011-08-11 |
KR20060058723A (ko) | 2006-05-30 |
TW200525702A (en) | 2005-08-01 |
TWI256703B (en) | 2006-06-11 |
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