WO2019133509A2 - Method of reducing leakage current of storage capacitors for display applications - Google Patents
Method of reducing leakage current of storage capacitors for display applications Download PDFInfo
- Publication number
- WO2019133509A2 WO2019133509A2 PCT/US2018/067223 US2018067223W WO2019133509A2 WO 2019133509 A2 WO2019133509 A2 WO 2019133509A2 US 2018067223 W US2018067223 W US 2018067223W WO 2019133509 A2 WO2019133509 A2 WO 2019133509A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal electrode
- nitride
- degrees celsius
- substrate
- dielectric layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000003990 capacitor Substances 0.000 title claims abstract description 33
- 238000003860 storage Methods 0.000 title description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- 239000002184 metal Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000007789 gas Substances 0.000 claims description 37
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 239000004408 titanium dioxide Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000009826 distribution Methods 0.000 description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000002243 precursor Substances 0.000 description 6
- 238000000429 assembly Methods 0.000 description 5
- 230000000712 assembly Effects 0.000 description 5
- 238000010926 purge Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005485 electric heating Methods 0.000 description 2
- SRLSISLWUNZOOB-UHFFFAOYSA-N ethyl(methyl)azanide;zirconium(4+) Chemical compound [Zr+4].CC[N-]C.CC[N-]C.CC[N-]C.CC[N-]C SRLSISLWUNZOOB-UHFFFAOYSA-N 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000012809 cooling fluid Substances 0.000 description 1
- STHAQIJXOMGURG-UHFFFAOYSA-N cyclopenta-1,3-diene;dimethylazanide;zirconium(4+) Chemical compound [Zr+4].C[N-]C.C[N-]C.C[N-]C.C=1C=C[CH-]C=1 STHAQIJXOMGURG-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 125000002147 dimethylamino group Chemical group [H]C([H])([H])N(*)C([H])([H])[H] 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002831 nitrogen free-radicals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
Definitions
- Embodiments of the present disclosure generally relate to a method for forming a layer stack including a dielectric layer having a high dielectric constant (high K) value for display devices. More particularly, embodiments of the disclosure relate to a method for forming a metal-insulator-metal (MIM) capacitor used in thin-film transistor (TFT) circuits.
- MIM metal-insulator-metal
- Display devices have been widely used for a wide range of electronic applications, such as TVs, monitors, mobile phones, MP3 players, e-book readers, personal digital assistants (PDAs) and the like.
- a pixel circuit in the backplane of a display panel utilizes TFTs and capacitors to control the color or brightness of each pixel of the display screen.
- the capacitors hold the electrical charge to maintain the gate voltage of the driving TFT, so that the color or brightness is maintained between two consequent frame refreshes.
- the storage capacitor in the TFT circuit usually is a MIM structure including a layer of dielectric material disposed between two metal electrodes. The capacitance is determined by the area of the capacitor and dielectric constant of the dielectric material.
- Embodiments of the present disclosure generally relate to a method for forming a metal-insulator-metal (MIM) capacitor for display applications.
- a capacitor includes a first metal electrode and a nitride disposed on the first metal electrode.
- the nitride is formed at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius.
- the capacitor further comprises a high K dielectric layer disposed on the nitride and a second metal electrode disposed on the high K dielectric layer.
- a method in another embodiment, includes forming a first metal electrode on a substrate and exposing the first metal electrode to a nitrogen containing plasma in a processing chamber. A portion of the first metal electrode is converted to a nitride having work function greater than 4.33 eV. The nitride is formed at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius. The method further includes forming a high K dielectric layer on the nitride in the processing chamber, and forming a second metal electrode on the high K dielectric layer.
- a method in another embodiment, includes forming a first metal electrode on a substrate and exposing the first metal electrode to a nitrogen containing plasma in a processing chamber.
- the substrate is maintained at a temperature ranging from about 50 degrees Celsius to about 180 degrees Celsius, and a portion of the first metal electrode is converted to a nitride.
- the method further includes forming a high K dielectric layer on the nitride in the processing chamber, and forming a second metal electrode on the high K dielectric layer.
- Figure 1 is a cross-sectional view of a processing chamber that may be used to treat a metal layer in accordance with one embodiment of the present disclosure.
- Figure 2 is a cross-sectional view of a processing chamber that may be used to treat a metal layer in accordance with one embodiment of the present disclosure.
- Figure 3 is a flow diagram of a method for forming a MIM capacitor in accordance with one embodiment of the present disclosure.
- Figures 4A - 4D illustrate schematic cross-sectional views of the MIM capacitor during different stages of the method of Figure 3.
- Embodiments of the present disclosure generally relate to a method for forming a metal-insulator-metal (MIM) capacitor for display applications.
- the method includes forming a metal electrode over a substrate, and exposing the metal electrode to a nitrogen containing plasma in a processing chamber.
- the substrate is maintained at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius as the metal electrode is exposed to the nitrogen containing plasma, which converts a surface of the metal electrode to a nitride.
- the method further includes forming a high K dielectric layer on the nitride surface of the metal electrode in the same processing chamber. With the plasma treating of the metal electrode, leakage current of the MIM capacitor is reduced and the breakdown field of the MIM capacitor is improved.
- the terms“over,”“under,”“between,” and“on” as used herein refer to a relative position of one layer with respect to other layers.
- one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
- one layer disposed between layers may be directly in contact with the two layers or may have one or more intervening layers.
- a first layer“on” a second layer is in contact with the second layer.
- the relative position of one layer with respect to other layers is provided assuming operations are performed relative to a substrate without consideration of the absolute orientation of the substrate.
- FIG. 1 is a schematic cross-section view of one embodiment of a chemical vapor deposition (CVD) processing chamber 100 that may be used to perform the embodiments discussed herein.
- a metal electrode may be treated with a nitrogen containing plasma or an oxygen containing plasma.
- a high K dielectric layer such as a Zr0 2 layer, may be deposited on the treated metal electrode.
- CVD processing chamber such as plasma enhanced CVD (PECVD) processing chamber, is available from Applied Materials, Inc., located in Santa Clara, CA. It is contemplated that other deposition chambers, including those from other manufacturers, may be utilized to practice the present disclosure.
- PECVD plasma enhanced CVD
- the chamber 100 generally includes one or more walls 142, a bottom 104 and a lid 1 12 which bound a process volume 106.
- a gas distribution plate 1 10 and substrate support assembly 130 are disposed within the process volume 106.
- the process volume 106 is accessed through a slit valve opening 108 formed through a wall 142 such that a substrate 102 may be transferred into and out of the chamber 100.
- the substrate support assembly 130 includes a substrate receiving surface 132 for supporting the substrate 102.
- a stem 134 couples the substrate support assembly 130 to a lift system 136 which raises and lowers the substrate support assembly 130 between substrate transfer and processing positions.
- a shadow frame 133 may be optionally placed over periphery of the substrate 102 during processing to prevent deposition on the edge of the substrate 102.
- Lift pins 138 are moveably disposed through the substrate support assembly 130 and are adapted to space the substrate 102 from the substrate receiving surface 132.
- the substrate support assembly 130 may also include heating and/or cooling elements 139 utilized to maintain the substrate support assembly 130 at a predetermined temperature, such as about 200 degrees Celsius or less, for example between about 20 degrees Celsius and about 200 degrees Celsius, or between about 50 degrees Celsius and about 180 degrees Celsius. In one embodiment, the substrate support assembly 130 is maintained between about 100 degrees Celsius and about 150 degrees Celsius during processing.
- a predetermined temperature such as about 200 degrees Celsius or less, for example between about 20 degrees Celsius and about 200 degrees Celsius, or between about 50 degrees Celsius and about 180 degrees Celsius.
- the substrate support assembly 130 is maintained between about 100 degrees Celsius and about 150 degrees Celsius during processing.
- the substrate support assembly 130 may also include grounding straps 131 to provide an RF return path around the periphery of the substrate support assembly 130.
- the gas distribution plate 1 10 is coupled at its periphery to the lid 1 12 or wall 142 of the chamber 100 by a suspension 1 14.
- the gas distribution plate 1 10 is also coupled to the lid 1 12 by one or more center supports 1 16 to help prevent sag and/or to control the straightness/curvature of the gas distribution plate 1 10. It is contemplated that the one or more center supports 1 16 maybe utilized.
- the gas distribution plate 1 10 may have different configurations with different dimensions.
- the gas distribution plate 1 10 has a downstream surface 150.
- a plurality of apertures 1 1 1 are formed through the gas distribution plate 1 10.
- the downstream surface 150 faces an upper surface 1 18 of the substrate 102 disposed on the substrate support assembly 130.
- the apertures 1 1 1 may have different shapes, number, densities, dimensions, and distributions across the gas distribution plate 1 10. In one embodiment, a diameter of the apertures 1 1 1 may be selected between about 0.01 inch and about 1 inch.
- a gas source 120 is coupled to the lid 1 12 to provide one or more gases through the lid 1 12 and then through the apertures 1 1 1 formed in the gas distribution plate 1 10 to the process volume 106.
- the gas source 120 may be a nitrogen containing gas source.
- a vacuum pump 109 is coupled to the chamber 100 to maintain the gas in the process volume 106 at a predetermined pressure.
- An RF power source 122 is coupled to the lid 1 12 and/or to the gas distribution plate 1 10 to provide a RF power that creates an electric field between the gas distribution plate 1 10 and the substrate support assembly 130 so that a plasma may be generated from the one or more gases, such as a nitrogen containing gas, between the gas distribution plate 1 10 and the substrate support assembly 130.
- the RF power may be applied at various RF frequencies. For example, RF power may be applied at a frequency between about 0.3 MHz and about 200 MHz. In one embodiment the RF power is provided at a frequency of 13.56 MHz.
- a remote plasma source 124 such as an inductively coupled remote plasma source, may also be coupled between the gas source 120 and the gas distribution plate 1 10. Between processing substrates, a cleaning gas may be energized in the remote plasma source 124 to remotely provide plasma utilized to clean chamber components. The cleaning gas entering the process volume 106 may be further excited by the RF power provided to the gas distribution plate 1 10 by the power source 122. Suitable cleaning gases include, but are not limited to, NF 3 , F 2 , and SF 6 .
- the substrate 102 that may be processed in the chamber 100 may have a surface area of 10,000 cm 2 or more, such as 25,000 cm 2 or more, for example about 55,000 cm 2 or more. It is understood that after processing the substrate may be cut to form smaller other devices.
- FIG. 2 is a schematic cross sectional view of an atomic layer deposition (ALD) chamber 200 that may be used to practice embodiments discussed herein.
- a metal electrode may be treated with a nitrogen containing plasma or an oxygen containing plasma within the chamber 200. Additionally or alternatively, a high K dielectric layer, such as a Zr0 2 layer, may be deposited on the treated metal electrode.
- the ALD chamber 200 is a plasma enhanced ALD (PE-ALD) chamber.
- the chamber 200 generally includes a chamber body 202, a lid assembly 204, a substrate support assembly 206, and a process kit 250.
- the lid assembly 204 is disposed on the chamber body 202, and the substrate support assembly 206 is at least partially disposed within the chamber body 202.
- the chamber body 202 includes a slit valve opening 208 formed in a sidewall thereof to provide access to the interior of the processing chamber 200.
- the chamber body 202 includes one or more apertures that are in fluid communication with a vacuum system (e.g., a vacuum pump). The apertures provide an egress for gases within the chamber 200.
- the lid assembly 204 includes one or more differential pump and purge assemblies 220.
- the differential pump and purge assemblies 220 are mounted to the lid assembly 204 with bellows 222.
- the bellows 222 allow the pump and purge assemblies 220 to move vertically with respect to the lid assembly 204 while still maintaining a seal against gas leaks.
- the lid assembly 204 includes a RF cathode 210 that can generate a plasma of reactive species within the chamber 200 and/or within the process kit 250.
- the RF cathode 210 may be heated by electric heating elements (not shown), and cooled by circulation of cooling fluids. Any power source capable of activating the gases into reactive species and maintaining the plasma of reactive species may be used.
- RF or microwave (MW) based power discharge techniques may be used.
- the activation may also be generated by a thermally based technique, a gas breakdown technique, a high intensity light source (e.g., UV energy), or exposure to an x-ray source.
- the substrate support assembly 206 can be at least partially disposed within the chamber body 202.
- the substrate support assembly 206 includes a substrate support member or susceptor 230 to support the substrate 102 for processing within the chamber body.
- the susceptor 230 is coupled to a substrate lift mechanism (not shown) through a shaft 224 or shafts 224 which extend through one or more openings 226 formed in a bottom surface of the chamber body 202.
- the substrate lift mechanism is flexibly sealed to the chamber body 202 by a bellows 228 that prevents vacuum leakage from around the shafts 224.
- the substrate lift mechanism allows the susceptor 230 to be moved vertically within the chamber 200 between a lower robot entry position, as shown, and processing, process kit transfer, and substrate transfer positions. In some embodiments, the substrate lift mechanism moves between fewer positions than those described.
- the susceptor 230 includes one or more bores 234 through the susceptor 230 to accommodate one or more lift pins 236.
- Each lift pin 236 is mounted so that the lift pin 236 may slide freely within a bore 234.
- the support assembly 206 is movable such that the upper surface of the lift pins 236 can be located above the substrate support surface 238 of the susceptor 230 when the support assembly 206 is in a lower position.
- the upper surface of the lift pins 236 is located below or substantially planar with the upper substrate support surface 238 of the susceptor 230 when the support assembly 206 is in a raised position.
- the lift pins 236 push against a lower surface of the substrate 102, lifting the substrate off the susceptor 230.
- the susceptor 230 may raise the substrate 102 off of the lift pins 236.
- the substrate 102 may be secured to the susceptor 230 using a vacuum chuck (not shown), an electrostatic chuck (not shown), or a mechanical clamp (not shown).
- the temperature of the susceptor 230 may be controlled (by, e.g., a process controller) during processing in the ALD chamber 200 to influence temperature of the substrate 102 and the process kit 250 to improve performance of processing.
- the susceptor 230 may be heated by, for example, electric heating elements (not shown) within the susceptor 230.
- the temperature of the susceptor 230 may be determined by pyrometers (not shown) in the chamber 200.
- the susceptor 230 includes process kit insulation buttons 237 that may include one or more seals 239.
- the process kit insulation buttons 237 may be used to carry the process kit 250 on the susceptor 230.
- the one or more seals 239 in the process kit insulation buttons 237 are compressed when the susceptor lifts the process kit 250 into the processing position.
- FIG 3 is a flow diagram of a method 300 for forming a MIM capacitor in accordance with one embodiment of the present disclosure.
- Figures 4A - 4D illustrate schematic cross-sectional views of the MIM capacitor during different stages of the method 300 of Figure 3.
- the method 300 starts at operation 302 by forming a first metal electrode 402 on a substrate 400, as shown in Figure 4A.
- the substrate 400 may be the substrate 102 shown in Figure 1 and Figure 2.
- the substrate 400 may have different combinations of films, structures or layers previously formed thereon to facilitate forming different device structures or different film stacks on the substrate 400.
- the substrate 400 may be any one of glass substrate, plastic substrate, polymer substrate, roll-to-roll substrate, or other suitable transparent substrate suitable for forming a thin film transistor thereon for display applications.
- the first metal electrode 402 may be fabricated from any suitable metal, such as titanium (Ti) or molybdenum (Mo).
- the first metal electrode 402 is a multi-layer stack including two or more metal layers, such as a first Ti layer, an aluminum (Al) layer disposed on the first Ti layer, and a second Ti layer disposed on the Al layer.
- the first metal electrode 402 may be formed on the substrate 400 by any suitable method.
- the first metal electrode 402 is deposited on the substrate 400 by a physical vapor deposition (PVD) process. As shown in Figure 4A, the first metal electrode 402 has a thickness ti ranging from about 500 Angstroms to about 5000 Angstroms.
- the first metal electrode 402 is exposed to a nitrogen containing plasma, as shown in Figure 4B.
- the reactive species, such as nitrogen radicals, in the nitrogen containing plasma modify the surface of the metal electrode 402 and convert the surface of the metal electrode 402 to a nitride 404.
- the nitride 404 is titanium nitride or molybdenum nitride.
- the metal electrode 402 includes a native oxide (not shown) formed thereon, and the reactive species in the nitrogen containing plasma convert the native oxide surface to an oxynitride.
- the nitride 404 is titanium oxynitride.
- the substrate 400 including the first metal electrode 402 formed thereon is placed into a processing chamber, such as the chamber 100 shown in Figure 1 or the chamber 200 shown in Figure 2.
- the nitrogen containing plasma is formed by introducing a gas into the processing chamber and exciting the gas.
- the gas may be a nitrogen containing gas, such as ammonia (NH 3 ).
- the gas is oxygen free.
- the gas does not contain oxygen because any oxidation of the first metal electrode 402 can lead to decreased performance of the capacitor.
- the nitrogen containing plasma may be capacitively coupled, inductively coupled, or microwave induced.
- the substrate 400 is maintained at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius during the exposure to the nitrogen containing plasma.
- any temperature greater than 200 degrees Celsius can damage the substrate 400.
- the temperature of the substrate is maintained at from about 50 degrees Celsius to about 180 degrees Celsius, such as from about 100 degrees Celsius to about 150 degrees Celsius.
- the nitride 404 is formed at a temperature from about 20 degrees Celsius to about 200 degrees Celsius, such as from about 50 degrees Celsius to about 180 degrees Celsius, for example from about 100 degrees Celsius to about 150 degrees Celsius.
- the first metal electrode 402 is exposed to the nitrogen containing plasma for a duration ranging from about 30 seconds to about 10 minutes, such as from about 1 minute to about 5 minutes.
- the nitride 404 has a thickness t 2 ranging from about 10 Angstroms to about 50 Angstroms.
- the remaining first metal electrode 402 has a thickness t 3 ranging from about 450 Angstroms to about 4990 Angstroms. Because the nitride 404 is converted from a portion of the first metal electrode 402, the sum of thicknesses t 2 and t 3 is equal to the thickness t-i, as shown in Figure 4B. In some embodiments, the sum of the thicknesses t 2 and t 3 is different from the thickness t-i.
- the work function is increased because the work function of the nitride 404 is greater than the work function of the first metal electrode 402.
- the first metal work electrode 402 is fabricated from Ti having work function of 4.33 eV
- the nitride 404 is titanium nitride having work function greater than 4.33 eV, such as 4.75 eV.
- a high K dielectric layer 406 is formed on the nitride 404, as shown in Figure 4C.
- the high K dielectric layer 406 is fabricated from any suitable dielectric material having a K value of 20 or higher, such as Zr0 2 , aluminum oxide (Al 2 0 3 ), titanium dioxide (Ti0 2 ) or hafnium dioxide (Hf0 2 ).
- the high K dielectric layer 406 is a multi-layer stack including at least one layer of high K dielectric material.
- the high K dielectric layer 406 includes a Zr0 2 layer and a silicon nitride (SiN) layer.
- the high K dielectric layer 406 includes a layer of high K dielectric material sandwiched between two dielectric layers.
- the high K dielectric layer 406 formed on the nitride 404 has a K value ranging from about 20 to about 50.
- the high K dielectric layer 406 has a thickness ranging from about 250 Angstroms to about 900 Angstroms.
- the high K dielectric layer 406 is deposited in the same chamber as the chamber in which the first metal electrode 402 is exposed to the nitrogen containing plasma or the oxygen containing plasma.
- the chamber is a PE-ALD chamber, such as the chamber 200 shown in Figure 2.
- precursors utilized for depositing the high K dielectric layer 406 include a zirconium containing precursor and an oxygen containing precursor.
- Suitable zirconium containing precursor includes zirconium-organometallic precursors, such as tetrakis(ethylmethylamino)zirconium (TEMAZ), tris(dimethylamino)cyclopentadienyl zirconium (C 5 H5)Zr[N(CH 3 ) 2 ]3, or the like.
- Suitable oxygen containing precursor includes H 2 0, 0 2 , 0 3 , H 2 0 2 , C0 2, N0 2 , N 2 0, or the like.
- the chamber is a PECVD chamber, such as the chamber 100 shown in Figure 1.
- a second metal electrode 408 is formed on the high K dielectric layer 406, as shown in Figure 4D.
- the second metal electrode 408 may or may not be fabricated from the same material as the first metal electrode 402.
- the second metal electrode 408 may be deposited by the same deposition process as the first metal electrode 402.
- a post metallization annealing process may be performed following forming the second metal electrode 408.
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Abstract
Embodiments of the present disclosure generally relate to a method for forming a metal-insulator-metal (MIM) capacitor for display applications. The method includes forming a metal electrode over a substrate, and exposing the metal electrode to a nitrogen containing plasma in a processing chamber. The substrate is maintained at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius as the metal electrode is exposed to the nitrogen containing plasma, which converts a surface of the metal electrode to a nitride. The method further includes forming a high K dielectric layer on the nitride surface of the metal electrode in the same processing chamber. With the plasma treating of the metal electrode, leakage current of the MIM capacitor is reduced and the breakdown field of the MIM capacitor is improved.
Description
METHOD OF REDUCING LEAKAGE CURRENT OF STORAGE CAPACITORS
FOR DISPLAY APPLICATIONS
BACKGROUND
Field
[0001] Embodiments of the present disclosure generally relate to a method for forming a layer stack including a dielectric layer having a high dielectric constant (high K) value for display devices. More particularly, embodiments of the disclosure relate to a method for forming a metal-insulator-metal (MIM) capacitor used in thin-film transistor (TFT) circuits.
Description of the Related Art
[0002] Display devices have been widely used for a wide range of electronic applications, such as TVs, monitors, mobile phones, MP3 players, e-book readers, personal digital assistants (PDAs) and the like. In some devices, a pixel circuit in the backplane of a display panel utilizes TFTs and capacitors to control the color or brightness of each pixel of the display screen. The capacitors hold the electrical charge to maintain the gate voltage of the driving TFT, so that the color or brightness is maintained between two consequent frame refreshes. The storage capacitor in the TFT circuit usually is a MIM structure including a layer of dielectric material disposed between two metal electrodes. The capacitance is determined by the area of the capacitor and dielectric constant of the dielectric material.
[0003] Conventionally, silicon nitride, which has a dielectric constant of about 7, has been used as the dielectric material. As the resolution of the display increases, the area of each pixel keeps shrinking. Therefore, there is very limited area for the storage capacitor. To achieve the same capacitance, a high K material, such as zirconium dioxide (Zr02), is utilized as the dielectric material. However, Zr02 has lower electron energy band gap compared to silicon nitride. When the Zr02 is integrated with the bottom and the top electrodes, the capacitor
leakage current is high and the breakdown field is low, which makes the display device less stable and less reliable.
[0004] Therefore, there is a need for a method for forming a MIM capacitor for manufacturing display devices that is stable and reliable.
SUMMARY
[0005] Embodiments of the present disclosure generally relate to a method for forming a metal-insulator-metal (MIM) capacitor for display applications. In one embodiment, a capacitor includes a first metal electrode and a nitride disposed on the first metal electrode. The nitride is formed at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius. The capacitor further comprises a high K dielectric layer disposed on the nitride and a second metal electrode disposed on the high K dielectric layer.
[0006] In another embodiment, a method includes forming a first metal electrode on a substrate and exposing the first metal electrode to a nitrogen containing plasma in a processing chamber. A portion of the first metal electrode is converted to a nitride having work function greater than 4.33 eV. The nitride is formed at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius. The method further includes forming a high K dielectric layer on the nitride in the processing chamber, and forming a second metal electrode on the high K dielectric layer.
[0007] In another embodiment, a method includes forming a first metal electrode on a substrate and exposing the first metal electrode to a nitrogen containing plasma in a processing chamber. The substrate is maintained at a temperature ranging from about 50 degrees Celsius to about 180 degrees Celsius, and a portion of the first metal electrode is converted to a nitride. The method further includes forming a high K dielectric layer on the nitride in the processing chamber, and forming a second metal electrode on the high K dielectric layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] So that the manner in which the above recited features of the disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.
[0009] Figure 1 is a cross-sectional view of a processing chamber that may be used to treat a metal layer in accordance with one embodiment of the present disclosure.
[0010] Figure 2 is a cross-sectional view of a processing chamber that may be used to treat a metal layer in accordance with one embodiment of the present disclosure.
[0011] Figure 3 is a flow diagram of a method for forming a MIM capacitor in accordance with one embodiment of the present disclosure.
[0012] Figures 4A - 4D illustrate schematic cross-sectional views of the MIM capacitor during different stages of the method of Figure 3.
[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
DETAILED DESCRIPTION
[0014] Embodiments of the present disclosure generally relate to a method for forming a metal-insulator-metal (MIM) capacitor for display applications. The method includes forming a metal electrode over a substrate, and exposing the metal electrode to a nitrogen containing plasma in a processing chamber. The
substrate is maintained at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius as the metal electrode is exposed to the nitrogen containing plasma, which converts a surface of the metal electrode to a nitride. The method further includes forming a high K dielectric layer on the nitride surface of the metal electrode in the same processing chamber. With the plasma treating of the metal electrode, leakage current of the MIM capacitor is reduced and the breakdown field of the MIM capacitor is improved.
[0015] The terms“over,”“under,”“between,” and“on” as used herein refer to a relative position of one layer with respect to other layers. As such, for example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer“on” a second layer is in contact with the second layer. Additionally, the relative position of one layer with respect to other layers is provided assuming operations are performed relative to a substrate without consideration of the absolute orientation of the substrate.
[0016] Figure 1 is a schematic cross-section view of one embodiment of a chemical vapor deposition (CVD) processing chamber 100 that may be used to perform the embodiments discussed herein. Within the chamber 100, a metal electrode may be treated with a nitrogen containing plasma or an oxygen containing plasma. Additionally or alternatively, a high K dielectric layer, such as a Zr02 layer, may be deposited on the treated metal electrode. One suitable CVD processing chamber, such as plasma enhanced CVD (PECVD) processing chamber, is available from Applied Materials, Inc., located in Santa Clara, CA. It is contemplated that other deposition chambers, including those from other manufacturers, may be utilized to practice the present disclosure.
[0017] The chamber 100 generally includes one or more walls 142, a bottom 104 and a lid 1 12 which bound a process volume 106. A gas distribution plate
1 10 and substrate support assembly 130 are disposed within the process volume 106. The process volume 106 is accessed through a slit valve opening 108 formed through a wall 142 such that a substrate 102 may be transferred into and out of the chamber 100.
[0018] The substrate support assembly 130 includes a substrate receiving surface 132 for supporting the substrate 102. A stem 134 couples the substrate support assembly 130 to a lift system 136 which raises and lowers the substrate support assembly 130 between substrate transfer and processing positions. A shadow frame 133 may be optionally placed over periphery of the substrate 102 during processing to prevent deposition on the edge of the substrate 102. Lift pins 138 are moveably disposed through the substrate support assembly 130 and are adapted to space the substrate 102 from the substrate receiving surface 132. The substrate support assembly 130 may also include heating and/or cooling elements 139 utilized to maintain the substrate support assembly 130 at a predetermined temperature, such as about 200 degrees Celsius or less, for example between about 20 degrees Celsius and about 200 degrees Celsius, or between about 50 degrees Celsius and about 180 degrees Celsius. In one embodiment, the substrate support assembly 130 is maintained between about 100 degrees Celsius and about 150 degrees Celsius during processing.
[0019] The substrate support assembly 130 may also include grounding straps 131 to provide an RF return path around the periphery of the substrate support assembly 130.
[0020] The gas distribution plate 1 10 is coupled at its periphery to the lid 1 12 or wall 142 of the chamber 100 by a suspension 1 14. The gas distribution plate 1 10 is also coupled to the lid 1 12 by one or more center supports 1 16 to help prevent sag and/or to control the straightness/curvature of the gas distribution plate 1 10. It is contemplated that the one or more center supports 1 16 maybe utilized. The gas distribution plate 1 10 may have different configurations with different dimensions. The gas distribution plate 1 10 has a downstream surface
150. A plurality of apertures 1 1 1 are formed through the gas distribution plate 1 10. The downstream surface 150 faces an upper surface 1 18 of the substrate 102 disposed on the substrate support assembly 130. The apertures 1 1 1 may have different shapes, number, densities, dimensions, and distributions across the gas distribution plate 1 10. In one embodiment, a diameter of the apertures 1 1 1 may be selected between about 0.01 inch and about 1 inch.
[0021] A gas source 120 is coupled to the lid 1 12 to provide one or more gases through the lid 1 12 and then through the apertures 1 1 1 formed in the gas distribution plate 1 10 to the process volume 106. The gas source 120 may be a nitrogen containing gas source. A vacuum pump 109 is coupled to the chamber 100 to maintain the gas in the process volume 106 at a predetermined pressure.
[0022] An RF power source 122 is coupled to the lid 1 12 and/or to the gas distribution plate 1 10 to provide a RF power that creates an electric field between the gas distribution plate 1 10 and the substrate support assembly 130 so that a plasma may be generated from the one or more gases, such as a nitrogen containing gas, between the gas distribution plate 1 10 and the substrate support assembly 130. The RF power may be applied at various RF frequencies. For example, RF power may be applied at a frequency between about 0.3 MHz and about 200 MHz. In one embodiment the RF power is provided at a frequency of 13.56 MHz.
[0023] A remote plasma source 124, such as an inductively coupled remote plasma source, may also be coupled between the gas source 120 and the gas distribution plate 1 10. Between processing substrates, a cleaning gas may be energized in the remote plasma source 124 to remotely provide plasma utilized to clean chamber components. The cleaning gas entering the process volume 106 may be further excited by the RF power provided to the gas distribution plate 1 10 by the power source 122. Suitable cleaning gases include, but are not limited to, NF3, F2, and SF6.
[0024] In one embodiment, the substrate 102 that may be processed in the chamber 100 may have a surface area of 10,000 cm2 or more, such as 25,000 cm2 or more, for example about 55,000 cm2 or more. It is understood that after processing the substrate may be cut to form smaller other devices.
[0025] Figure 2 is a schematic cross sectional view of an atomic layer deposition (ALD) chamber 200 that may be used to practice embodiments discussed herein. A metal electrode may be treated with a nitrogen containing plasma or an oxygen containing plasma within the chamber 200. Additionally or alternatively, a high K dielectric layer, such as a Zr02 layer, may be deposited on the treated metal electrode. In one embodiment, the ALD chamber 200 is a plasma enhanced ALD (PE-ALD) chamber. The chamber 200 generally includes a chamber body 202, a lid assembly 204, a substrate support assembly 206, and a process kit 250. The lid assembly 204 is disposed on the chamber body 202, and the substrate support assembly 206 is at least partially disposed within the chamber body 202. The chamber body 202 includes a slit valve opening 208 formed in a sidewall thereof to provide access to the interior of the processing chamber 200. In some embodiments, the chamber body 202 includes one or more apertures that are in fluid communication with a vacuum system (e.g., a vacuum pump). The apertures provide an egress for gases within the chamber 200. The lid assembly 204 includes one or more differential pump and purge assemblies 220. The differential pump and purge assemblies 220 are mounted to the lid assembly 204 with bellows 222. The bellows 222 allow the pump and purge assemblies 220 to move vertically with respect to the lid assembly 204 while still maintaining a seal against gas leaks. When the process kit 250 is raised into a processing position, a first seal 286 and a second seal 288 on the process kit 250 are brought into contact with the differential pump and purge assemblies 220. The differential pump and purge assemblies 220 are connected with a vacuum system (not shown) and maintained at a low pressure.
[0026] As shown in Figure 2, the lid assembly 204 includes a RF cathode 210 that can generate a plasma of reactive species within the chamber 200 and/or within the process kit 250. The RF cathode 210 may be heated by electric heating elements (not shown), and cooled by circulation of cooling fluids. Any power source capable of activating the gases into reactive species and maintaining the plasma of reactive species may be used. For example, RF or microwave (MW) based power discharge techniques may be used. The activation may also be generated by a thermally based technique, a gas breakdown technique, a high intensity light source (e.g., UV energy), or exposure to an x-ray source.
[0027] The substrate support assembly 206 can be at least partially disposed within the chamber body 202. The substrate support assembly 206 includes a substrate support member or susceptor 230 to support the substrate 102 for processing within the chamber body. The susceptor 230 is coupled to a substrate lift mechanism (not shown) through a shaft 224 or shafts 224 which extend through one or more openings 226 formed in a bottom surface of the chamber body 202. The substrate lift mechanism is flexibly sealed to the chamber body 202 by a bellows 228 that prevents vacuum leakage from around the shafts 224. The substrate lift mechanism allows the susceptor 230 to be moved vertically within the chamber 200 between a lower robot entry position, as shown, and processing, process kit transfer, and substrate transfer positions. In some embodiments, the substrate lift mechanism moves between fewer positions than those described.
[0028] As shown in Figure 2, the susceptor 230 includes one or more bores 234 through the susceptor 230 to accommodate one or more lift pins 236. Each lift pin 236 is mounted so that the lift pin 236 may slide freely within a bore 234. The support assembly 206 is movable such that the upper surface of the lift pins 236 can be located above the substrate support surface 238 of the susceptor 230 when the support assembly 206 is in a lower position. Conversely, the upper
surface of the lift pins 236 is located below or substantially planar with the upper substrate support surface 238 of the susceptor 230 when the support assembly 206 is in a raised position. When contacting the chamber body 202, the lift pins 236 push against a lower surface of the substrate 102, lifting the substrate off the susceptor 230. Conversely, the susceptor 230 may raise the substrate 102 off of the lift pins 236.
[0029] In some embodiments, the substrate 102 may be secured to the susceptor 230 using a vacuum chuck (not shown), an electrostatic chuck (not shown), or a mechanical clamp (not shown). The temperature of the susceptor 230 may be controlled (by, e.g., a process controller) during processing in the ALD chamber 200 to influence temperature of the substrate 102 and the process kit 250 to improve performance of processing. The susceptor 230 may be heated by, for example, electric heating elements (not shown) within the susceptor 230. The temperature of the susceptor 230 may be determined by pyrometers (not shown) in the chamber 200.
[0030] In some embodiments, the susceptor 230 includes process kit insulation buttons 237 that may include one or more seals 239. The process kit insulation buttons 237 may be used to carry the process kit 250 on the susceptor 230. The one or more seals 239 in the process kit insulation buttons 237 are compressed when the susceptor lifts the process kit 250 into the processing position.
[0031] Figure 3 is a flow diagram of a method 300 for forming a MIM capacitor in accordance with one embodiment of the present disclosure. Figures 4A - 4D illustrate schematic cross-sectional views of the MIM capacitor during different stages of the method 300 of Figure 3. The method 300 starts at operation 302 by forming a first metal electrode 402 on a substrate 400, as shown in Figure 4A. The substrate 400 may be the substrate 102 shown in Figure 1 and Figure 2. The substrate 400 may have different combinations of films, structures or layers previously formed thereon to facilitate forming different device structures or
different film stacks on the substrate 400. The substrate 400 may be any one of glass substrate, plastic substrate, polymer substrate, roll-to-roll substrate, or other suitable transparent substrate suitable for forming a thin film transistor thereon for display applications. The first metal electrode 402 may be fabricated from any suitable metal, such as titanium (Ti) or molybdenum (Mo). In some embodiments, the first metal electrode 402 is a multi-layer stack including two or more metal layers, such as a first Ti layer, an aluminum (Al) layer disposed on the first Ti layer, and a second Ti layer disposed on the Al layer. The first metal electrode 402 may be formed on the substrate 400 by any suitable method. In one embodiment, the first metal electrode 402 is deposited on the substrate 400 by a physical vapor deposition (PVD) process. As shown in Figure 4A, the first metal electrode 402 has a thickness ti ranging from about 500 Angstroms to about 5000 Angstroms.
[0032] At operation 304, the first metal electrode 402 is exposed to a nitrogen containing plasma, as shown in Figure 4B. The reactive species, such as nitrogen radicals, in the nitrogen containing plasma modify the surface of the metal electrode 402 and convert the surface of the metal electrode 402 to a nitride 404. In one embodiment, the nitride 404 is titanium nitride or molybdenum nitride. In another embodiment, the metal electrode 402 includes a native oxide (not shown) formed thereon, and the reactive species in the nitrogen containing plasma convert the native oxide surface to an oxynitride. For example, the nitride 404 is titanium oxynitride.
[0033] The substrate 400 including the first metal electrode 402 formed thereon is placed into a processing chamber, such as the chamber 100 shown in Figure 1 or the chamber 200 shown in Figure 2. In one embodiment, the nitrogen containing plasma is formed by introducing a gas into the processing chamber and exciting the gas. The gas may be a nitrogen containing gas, such as ammonia (NH3). The gas is oxygen free. The gas does not contain oxygen because any oxidation of the first metal electrode 402 can lead to decreased
performance of the capacitor. The nitrogen containing plasma may be capacitively coupled, inductively coupled, or microwave induced. The substrate 400 is maintained at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius during the exposure to the nitrogen containing plasma. Because the substrate 400 is fabricated from glass or polymer, any temperature greater than 200 degrees Celsius can damage the substrate 400. In one embodiment, the temperature of the substrate is maintained at from about 50 degrees Celsius to about 180 degrees Celsius, such as from about 100 degrees Celsius to about 150 degrees Celsius. In other words, the nitride 404 is formed at a temperature from about 20 degrees Celsius to about 200 degrees Celsius, such as from about 50 degrees Celsius to about 180 degrees Celsius, for example from about 100 degrees Celsius to about 150 degrees Celsius. The first metal electrode 402 is exposed to the nitrogen containing plasma for a duration ranging from about 30 seconds to about 10 minutes, such as from about 1 minute to about 5 minutes.
[0034] The nitride 404 has a thickness t2 ranging from about 10 Angstroms to about 50 Angstroms. The remaining first metal electrode 402 has a thickness t3 ranging from about 450 Angstroms to about 4990 Angstroms. Because the nitride 404 is converted from a portion of the first metal electrode 402, the sum of thicknesses t2 and t3 is equal to the thickness t-i, as shown in Figure 4B. In some embodiments, the sum of the thicknesses t2 and t3 is different from the thickness t-i. By converting a portion of the first metal electrode 402 to the nitride 404, the work function is increased because the work function of the nitride 404 is greater than the work function of the first metal electrode 402. For example, the first metal work electrode 402 is fabricated from Ti having work function of 4.33 eV, and the nitride 404 is titanium nitride having work function greater than 4.33 eV, such as 4.75 eV.
[0035] Next, at operation 306, a high K dielectric layer 406 is formed on the nitride 404, as shown in Figure 4C. The high K dielectric layer 406 is fabricated
from any suitable dielectric material having a K value of 20 or higher, such as Zr02, aluminum oxide (Al203), titanium dioxide (Ti02) or hafnium dioxide (Hf02). In some embodiments, the high K dielectric layer 406 is a multi-layer stack including at least one layer of high K dielectric material. In one embodiment, the high K dielectric layer 406 includes a Zr02 layer and a silicon nitride (SiN) layer. In another embodiment, the high K dielectric layer 406 includes a layer of high K dielectric material sandwiched between two dielectric layers. The high K dielectric layer 406 formed on the nitride 404 has a K value ranging from about 20 to about 50. The high K dielectric layer 406 has a thickness ranging from about 250 Angstroms to about 900 Angstroms. In one embodiment, the high K dielectric layer 406 is deposited in the same chamber as the chamber in which the first metal electrode 402 is exposed to the nitrogen containing plasma or the oxygen containing plasma. In one embodiment, the chamber is a PE-ALD chamber, such as the chamber 200 shown in Figure 2. In one embodiment, precursors utilized for depositing the high K dielectric layer 406 include a zirconium containing precursor and an oxygen containing precursor. Suitable zirconium containing precursor includes zirconium-organometallic precursors, such as tetrakis(ethylmethylamino)zirconium (TEMAZ), tris(dimethylamino)cyclopentadienyl zirconium (C5H5)Zr[N(CH3)2]3, or the like. Suitable oxygen containing precursor includes H20, 02, 03, H202, C02, N02, N20, or the like. In another embodiment, the chamber is a PECVD chamber, such as the chamber 100 shown in Figure 1.
[0036] At operation 308, a second metal electrode 408 is formed on the high K dielectric layer 406, as shown in Figure 4D. The second metal electrode 408 may or may not be fabricated from the same material as the first metal electrode 402. The second metal electrode 408 may be deposited by the same deposition process as the first metal electrode 402. A post metallization annealing process may be performed following forming the second metal electrode 408.
[0037] By treating the first metal electrode of a MIM capacitor with a nitrogen containing plasma, leakage current of the MIM capacitor is reduced and the breakdown field of the MIM capacitor is improved. Furthermore, the K value of the high K dielectric layer is not affected by the plasma treating of the first metal electrode.
[0038] While the foregoing is directed to embodiments of the disclosure, other and further embodiments may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims
1. A capacitor, comprising:
a first metal electrode;
a nitride disposed on the first metal electrode, wherein the nitride is formed at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius;
a high K dielectric layer disposed on the nitride; and
a second metal electrode disposed on the high K dielectric layer.
2. The capacitor of claim 1 , wherein the first metal electrode comprises titanium and the nitride comprises titanium nitride.
3. The capacitor of claim 1 , wherein the first metal electrode comprises molybdenum and the nitride comprises molybdenum nitride.
4. The capacitor of claim 1 , wherein the high K dielectric layer comprises zirconium dioxide, hafnium dioxide, titanium dioxide, or aluminum oxide.
5. The capacitor of claim 1 , wherein the second metal electrode comprises a same material as the first metal electrode.
6. The capacitor of claim 1 , wherein the second metal electrode comprises a different material than the first metal electrode.
7. A method, comprising:
forming a first metal electrode on a substrate;
exposing the first metal electrode to a nitrogen containing plasma in a processing chamber, wherein a portion of the first metal electrode is converted to
a nitride having work function greater than 4.33 eV, wherein the nitride is formed at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius;
forming a high K dielectric layer on the nitride in the processing chamber; and
forming a second metal electrode on the high K dielectric layer.
8. The method of claim 7, wherein the processing chamber is a plasma enhanced atomic layer deposition chamber.
9. The method of claim 7, wherein the processing chamber is a plasma enhanced chemical vapor deposition chamber.
10. The method of claim 7, wherein the nitrogen containing plasma is formed by exciting a nitrogen containing gas, and the nitrogen containing gas comprises ammonia.
1 1. The method of claim 7, wherein the substrate is maintained at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius during the exposing the first metal electrode to the nitrogen containing plasma.
12. A method, comprising:
forming a first metal electrode on a substrate;
exposing the first metal electrode to a nitrogen containing plasma in a processing chamber, wherein the substrate is maintained at a temperature ranging from about 50 degrees Celsius to about 180 degrees Celsius, and wherein a portion of the first metal electrode is converted to a nitride;
forming a high K dielectric layer on the nitride in the processing chamber; and
forming a second metal electrode on the high K dielectric layer.
13. The method of claim 12, wherein the processing chamber is a plasma enhanced atomic layer deposition chamber.
14. The method of claim 12, wherein the high K dielectric layer comprises zirconium dioxide, hafnium dioxide, or aluminum oxide.
15. The method of claim 12, wherein the temperature ranges from about 100 degrees Celsius to about 150 degrees Celsius.
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KR1020207019229A KR102430400B1 (en) | 2017-12-29 | 2018-12-21 | How to Reduce Leakage Current of Storage Capacitors for Display Applications |
CN202410171868.1A CN118119268A (en) | 2017-12-29 | 2018-12-21 | Method for reducing leakage current of storage capacitor for display application |
KR1020227026759A KR102641942B1 (en) | 2017-12-29 | 2018-12-21 | Method of reducing leakage current of storage capacitors for display applications |
CN201880078075.8A CN111566833B (en) | 2017-12-29 | 2018-12-21 | Method for reducing leakage current of storage capacitor for display application |
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EP0862203A1 (en) * | 1997-01-31 | 1998-09-02 | Texas Instruments Incorporated | Method for fabricating a semiconductor memory capacitor |
GB2358284B (en) * | 1999-07-02 | 2004-07-14 | Hyundai Electronics Ind | Method of manufacturing capacitor for semiconductor memory device |
US20020168847A1 (en) * | 2001-05-09 | 2002-11-14 | Applied Materials, Inc. | Methods of forming a nitridated surface on a metallic layer and products produced thereby |
US7129128B2 (en) | 2001-08-29 | 2006-10-31 | Micron Technology, Inc. | Method of improved high K dielectric-polysilicon interface for CMOS devices |
US6717193B2 (en) * | 2001-10-09 | 2004-04-06 | Koninklijke Philips Electronics N.V. | Metal-insulator-metal (MIM) capacitor structure and methods of fabricating same |
US6753618B2 (en) * | 2002-03-11 | 2004-06-22 | Micron Technology, Inc. | MIM capacitor with metal nitride electrode materials and method of formation |
KR100538806B1 (en) * | 2003-02-21 | 2005-12-26 | 주식회사 하이닉스반도체 | SEMICONDUCTOR DEVICE WITH EPITAXIAL C49-TiSi2 LAYER AND METHOD FOR FABRICATING THE SAME |
KR100532434B1 (en) * | 2003-05-09 | 2005-11-30 | 삼성전자주식회사 | Methods for manufacturing capacitor of semiconductor memory device |
CN1820370A (en) * | 2003-09-26 | 2006-08-16 | 东京毅力科创株式会社 | Manufacturing method of semiconductor device, semiconductor manufacturing apparatus, computer recording medium |
KR100655074B1 (en) * | 2004-11-11 | 2006-12-11 | 삼성전자주식회사 | Storage capacitor and Method for manufacturing the same |
KR100695887B1 (en) * | 2004-12-09 | 2007-03-20 | 삼성전자주식회사 | Method for forming a titanium nitride layer and method for forming a lower electrode of a MIM capacitor using the titanium nitride layer |
KR20070034248A (en) * | 2005-09-23 | 2007-03-28 | 삼성전자주식회사 | MIM type capacitors and manufacturing method thereof |
KR20110044489A (en) * | 2009-10-23 | 2011-04-29 | 삼성전자주식회사 | Semiconductor construction including dielectric layer, capacitor using the same and method of forming the semiconductor construction |
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US9449927B2 (en) | 2012-11-29 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Seal ring structure with metal-insulator-metal capacitor |
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