CN111566833A - Method for reducing leakage current of storage capacitor for display application - Google Patents

Method for reducing leakage current of storage capacitor for display application Download PDF

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Publication number
CN111566833A
CN111566833A CN201880078075.8A CN201880078075A CN111566833A CN 111566833 A CN111566833 A CN 111566833A CN 201880078075 A CN201880078075 A CN 201880078075A CN 111566833 A CN111566833 A CN 111566833A
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metal electrode
nitride
degrees celsius
substrate
dielectric layer
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CN111566833B (en
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翟羽佳
芮祥新
赵来
崔寿永
杰瑞安·杰瑞·陈
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Applied Materials Inc
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Applied Materials Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

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Abstract

Embodiments of the present disclosure generally relate to a method of forming a metal-insulator-metal (MIM) capacitor for display applications. The method comprises the following steps: forming a metal electrode over a substrate; and exposing the metal electrode to a nitrogen-containing plasma in a processing chamber. Maintaining the substrate at a temperature in a range of about 20 degrees Celsius to about 200 degrees Celsius while exposing the metal electrode to the nitrogen-containing plasma, which converts a surface of the metal electrode to a nitride. The method also includes forming a high-K dielectric layer on the nitride surface of the metal electrode in the same processing chamber. By plasma treating the metal electrode, leakage current of the MIM capacitor is reduced and breakdown field of the MIM capacitor is improved.

Description

Method for reducing leakage current of storage capacitor for display application
Background
FIELD
Embodiments of the present disclosure generally relate to a method of forming a layer stack including a dielectric layer having a high dielectric constant (high-K) value for a display device. In particular, embodiments of the present disclosure relate to a method for forming a metal-insulator-metal (MIM) capacitor for use in a Thin Film Transistor (TFT) circuit.
Description of the related Art
Display devices have been widely used in a wide range of electronic applications such as TVs, monitors, mobile phones, MP3 players, electronic book readers, Personal Digital Assistants (PDAs), and the like. In some devices, pixel circuitry in the backplane of the display panel utilizes TFTs and capacitors to control the color or brightness of each pixel of the display screen. The capacitor holds a charge to maintain the gate voltage of the driving TFT so that the color or brightness is maintained between two subsequent frame refreshes. The storage capacitor in a TFT circuit is typically a MIM structure comprising one layer of dielectric material arranged between two metal electrodes. The capacitance is determined by the area of the capacitor and the dielectric constant of the dielectric material.
Conventionally, silicon nitride having a dielectric constant of about 7 has been used as a dielectric material. As the resolution of the display increases, the area of each pixel is continually reduced. Thus, the face of the storage capacitorThe product is very limited. To obtain the same capacitance, for example zirconium dioxide (ZrO)2) Such as high K materials, are used as dielectric materials. However, compared to silicon nitride, ZrO2Has a lower electronic energy band gap. When ZrO2When integrated with the bottom and top electrodes, the capacitor leakage current is high and the breakdown field is low, which makes the display device less stable and less reliable.
What is needed, therefore, is a method of forming a MIM capacitor for use in manufacturing a stable and reliable display device.
Disclosure of Invention
Embodiments of the present disclosure generally relate to a method of forming a metal-insulator-metal (MIM) capacitor for display applications. In one embodiment, a capacitor includes a first metal electrode and a nitride disposed on the first metal electrode. The nitride is formed at a temperature in a range of about 20 degrees celsius to about 200 degrees celsius. The capacitor also includes a high-K dielectric layer disposed on the nitride and a second metal electrode disposed on the high-K dielectric layer.
In another embodiment, a method comprises: forming a first metal electrode on a substrate; and exposing the first metal electrode to a nitrogen-containing plasma in the processing chamber. A portion of the first metal electrode is converted to a nitride having a work function greater than 4.33 eV. The nitride is formed at a temperature in a range of about 20 degrees celsius to about 200 degrees celsius. The method further comprises the following steps: forming a high-K dielectric layer on the nitride in the processing chamber; and forming a second metal electrode on the high-K dielectric layer.
In another embodiment, a method comprises: forming a first metal electrode on a substrate; and exposing the first metal electrode to a nitrogen-containing plasma in the processing chamber. The substrate is maintained at a temperature in a range of about 50 degrees celsius to about 180 degrees celsius and a portion of the first metal electrode is converted to a nitride. The method further comprises the following steps: forming a high-K dielectric layer on the nitride in the processing chamber; and forming a second metal electrode on the high-K dielectric layer.
Drawings
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.
Fig. 1 is a cross-sectional view of a process chamber that may be used to process a metal layer according to one embodiment of the present disclosure.
Fig. 2 is a cross-sectional view of a process chamber that may be used to process a metal layer according to one embodiment of the present disclosure.
Fig. 3 is a flow chart of a method for forming a MIM capacitor according to one embodiment of the present disclosure.
Fig. 4A-4D illustrate schematic cross-sectional views of a MIM capacitor during different stages of the method of fig. 3.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
Detailed Description
Embodiments of the present disclosure generally relate to a method of forming a metal-insulator-metal (MIM) capacitor for display applications. The method comprises the following steps: forming a metal electrode over a substrate; and exposing the metal electrode to a nitrogen-containing plasma in a processing chamber. Maintaining the substrate at a temperature in a range of about 20 degrees Celsius to about 200 degrees Celsius while exposing the metal electrode to the nitrogen-containing plasma, which converts a surface of the metal electrode to a nitride. The method also includes forming a high-K dielectric layer on the nitride surface of the metal electrode in the same processing chamber. By plasma treating the metal electrode, leakage current of the MIM capacitor is reduced and breakdown field of the MIM capacitor is improved.
As used herein, the terms "above … …," "below … …," "between … …," and "above … …" refer to the relative position of one layer with respect to the other layers. Thus, for example, one layer disposed above or below another layer may be directly in contact with the other layer, or may have one or more intervening layers. Further, one layer disposed between layers may be in direct contact with both layers, or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in contact with the second layer. Additionally, the relative position of one layer with respect to the other layers is provided assuming that the operation is performed with respect to the substrate without regard to the absolute orientation of the substrate.
Fig. 1 is a schematic cross-sectional view of one embodiment of a Chemical Vapor Deposition (CVD) processing chamber 100 that may be used to perform the embodiments discussed herein. Within the chamber 100, the metal electrode may be treated with a nitrogen-containing plasma or an oxygen-containing plasma. Additionally or alternatively, a high-K dielectric layer, such as ZrO, may be deposited on the treated metal electrode2And (3) a layer. One suitable CVD processing chamber, such as a plasma enhanced CVD (pecvd) processing chamber, is available from Applied Materials, inc. It is contemplated that the present disclosure may be practiced with other deposition chambers, including those from other manufacturers.
The chamber 100 generally includes one or more walls 142, a bottom 104, and a lid 112 that define a process volume 106. A gas distribution plate 110 and a substrate support assembly 130 are disposed within the process volume 106. The process volume 106 is accessed through a slit valve opening 108 formed through the wall 142 so that the substrate 102 may be transferred into and out of the chamber 100.
The substrate support assembly 130 includes a substrate receiving surface 132 for supporting the substrate 102. The rods 134 couple the substrate support assembly 130 to a lift system 136 that raises and lowers the substrate support assembly 130 between substrate transfer and processing positions. A shadow frame 133 may optionally be placed over the perimeter of the substrate 102 during processing to prevent deposition from occurring on the edges of the substrate 102. The lift pins 138 are movably disposed through the substrate support assembly 130 and are adapted to space the substrate 102 from the substrate receiving surface 132. The substrate support assembly 130 may also include heating and/or cooling elements 139 for maintaining the substrate support assembly 130 at a predetermined temperature, such as about 200 degrees celsius or less, for example between about 20 degrees celsius to about 200 degrees celsius, or between about 50 degrees celsius to about 180 degrees celsius. In one embodiment, the substrate support assembly 130 is maintained at between about 100 degrees celsius and about 150 degrees celsius during processing.
The substrate support assembly 130 may also include a ground strap 131 to provide an RF return path around the perimeter of the substrate support assembly 130.
The gas distribution plate 110 is coupled at its periphery to the lid 112 or wall 142 of the chamber 100 by a suspension 114. The gas distribution plate 110 may also be coupled to the lid 112 by one or more central supports 116 to help prevent sagging and/or control the straightness/curvature of the gas distribution plate 110. It is contemplated that one or more center supports 116 may be utilized. The gas distribution plate 110 may have different configurations with different dimensions. The gas distribution plate 110 has a downstream surface 150. A plurality of holes 111 are formed through the gas distribution plate 110. The downstream surface 150 faces the upper surface 118 of the substrate 102 disposed on the substrate support assembly 130. The apertures 111 may have different shapes, numbers, densities, sizes, and distributions across the gas distribution plate 110. In one embodiment, the diameter of the bore 111 may be selected to be between about 0.01 inches and about 1 inch.
A gas source 120 is coupled to the lid 112 to pass one or more gases through the lid 112 and then through the holes 111 formed in the gas distribution plate 110 to the process volume 106. The gas source 120 may be a nitrogen-containing gas source. A vacuum pump 109 is coupled to the chamber 100 to maintain the gas in the process volume 106 at a predetermined pressure.
An RF power source 122 is coupled to the lid 112 and/or the gas distribution plate 110 to provide RF power that forms an electric field between the gas distribution plate 110 and the substrate support assembly 130 such that a plasma may be generated between the gas distribution plate 110 and the substrate support assembly 130 from one or more gases, such as a nitrogen-containing gas. RF power may be applied at various RF frequencies. For example, the RF power may be applied at a frequency between about 0.3MHz and about 200 MHz. In one embodiment, the RF power is provided at a frequency of 13.56 MHz.
A remote plasma source 124, such as an inductively coupled remote plasma source, may also be coupled between the gas source 120 and the gas distribution plate 110. Between steps of processing the substrate, a cleaning gas may be energized in the remote plasma source 124 to remotely provide a plasma for cleaning chamber components. The cleaning gases entering the process volume 106 may be further excited by the RF power provided to the gas distribution plate 110 by the power source 122. Suitable cleaning gases include, but are not limited to, NF3、F2And SF6。
In one embodiment, the substrate 102 that may be processed in the chamber 100 may have a thickness of 10,000cm2Or larger, such as 25,000cm2Or greater, e.g. about 55,000cm2Or a larger surface area. It is understood that after processing, the substrate may be cut to form smaller other devices.
FIG. 2 is a schematic cross-sectional view of an Atomic Layer Deposition (ALD) chamber 200 that may be used to practice embodiments discussed herein. The metal electrode may be treated with a nitrogen-containing plasma or an oxygen-containing plasma within the chamber 200. Additionally or alternatively, a high-K dielectric layer, such as ZrO, may be deposited on the treated metal electrode2And (3) a layer. In one embodiment, the ALD chamber 200 is a plasma-enhanced ALD (PE-ALD) chamber. The chamber 200 generally includes a chamber body 202, a lid assembly 204, a substrate support assembly 206, and a process kit 250. The lid assembly 204 is disposed on the chamber body 202, and the substrate support assembly 206 is at least partially disposed within the chamber body 202. The chamber body 202 includes a slit valve opening 208 formed in a sidewall of the chamber body 202 to provide access to the interior of the processing chamber. In some embodiments, the chamber body 202 includes one or more apertures in fluid communication with a vacuum system (e.g., a vacuum pump). The holes provide an outlet for the gas within the chamber 200. The lid assembly 204 includes one or more differential pumps and a purge assembly 220. The differential pump and purge assembly 220 is mounted to the cap assembly 204 with bellows 222. The bellows 222 allows the pump and purge assembly 220 to be vertically oriented with respect to the lid assembly 204Move while still maintaining a seal to prevent gas leakage. When the process kit 250 is raised to the processing position, the first and second seals 286, 288 on the process kit 250 are in contact with the differential pump and purge assembly 220. The differential pump and purge assembly 220 is connected to a vacuum system (not shown) and maintained at a low pressure.
As shown in fig. 2, the lid assembly 204 includes an RF cathode 210 that can generate a plasma of active species within the chamber 200 and/or within the process kit 250. The RF cathode 210 may be heated by an electrical heating element (not shown) and cooled by circulation of a cooling fluid. Any power source capable of activating a gas into a reactive species and maintaining a plasma of the reactive species may be used. For example, RF or Microwave (MW) based power discharge techniques may be used. Activation may also be generated by heat-based techniques, gas decomposition techniques, high intensity light sources (e.g., UV energy), or exposure to an x-ray source.
The substrate support assembly 206 may be at least partially disposed within the chamber body 202. The substrate support assembly 206 includes a substrate support member or pedestal 230 to support the substrate 102 for processing within the chamber body. The pedestal 230 is coupled to a substrate lift mechanism (not shown) by a shaft 224 or shafts 224 extending through one or more openings 226 formed in the bottom surface of the chamber body 202. The substrate lift mechanism is flexibly sealed to the chamber body 202 by bellows 228 to prevent vacuum leakage around the shaft 224. The substrate lift mechanism allows the pedestal 230 to move vertically within the chamber 200 between the lower robot entry position shown and the processing, process kit transfer, and substrate transfer positions. In some embodiments, the substrate lift mechanism moves between fewer positions than described.
As shown in fig. 2, the base 230 includes one or more apertures 230 through the base 234 to receive one or more lift pins 236. Each lifter 236 is mounted such that the lifter 236 is free to slide within the aperture 234. The support assembly 206 may be movable such that the upper surface of the lift pins 236 may be positioned above the substrate support surface 238 of the pedestal 230 when the support assembly 206 is in the lower position. Conversely, when the support assembly 206 is in the raised position, the upper surface of the lift pins 236 are below or substantially flush with the upper substrate support surface 238 of the pedestal 230. When contacting the chamber body 202, the lift pins 236 push against the lower surface of the substrate 102, thereby lifting the substrate off of the pedestal 230. Conversely, the pedestal 230 may lift the substrate 102 from the lift pins 236.
In some embodiments, the substrate 102 may be secured to the pedestal 230 using a vacuum chuck (not shown), an electrostatic chuck (not shown), or a mechanical clamp (not shown). The temperature of the pedestal 230 may be controlled during processing in the ALD chamber 200 (through, for example, process processing) to affect the temperature of the substrate 102 and the process kit 250 to improve the performance of the process. The susceptor 230 may be heated, for example, by an electrical heating element (not shown) within the susceptor 230. The temperature of the susceptor 230 may be determined by a pyrometer (not shown) in the chamber 200.
In some embodiments, the base 230 includes a process kit insulating button 237, which may include one or more seals 239. Process kit insulation button 237 may be used to carry process kit 250 on base 230. When the pedestal lifts the process kit 250 into the processing position, one or more seals 239 in the process kit isolation button 237 are compressed.
Fig. 3 is a flow chart of a method 300 for forming a MIM capacitor according to one embodiment of the present disclosure. Fig. 4A-4D illustrate schematic cross-sectional views of a MIM capacitor during different stages of the method 300 of fig. 3. The method 300 begins at operation 302 by forming a first metal electrode 402 on a substrate 400, as shown in fig. 4A. The substrate 400 may be the substrate 102 shown in fig. 1 and 2. Substrate 400 may have different combinations of films, structures, or layers previously formed thereon to facilitate the formation of different device structures or different film stacks on substrate 400. The substrate 400 may be any of a glass substrate, a plastic substrate, a polymer substrate, a roll-to-roll substrate, or other suitable transparent substrate suitable for forming thin film transistors thereon for display applications. The first metal electrode 402 may be made of any suitable metal, such as titanium (Ti) or molybdenum (Mo). In some embodiments, the first metal electrode 402 is a multilayer stack comprising two or more metal layers, the gold beingThe sub-layers are such as a first Ti layer, an aluminum (Al) layer disposed on the first Ti layer, and a second Ti layer disposed on the Al layer. The first metal electrode 402 may be formed on the substrate 400 by any suitable method. In one embodiment, the first metal electrode 402 is deposited on the substrate 400 by a Physical Vapor Deposition (PVD) process. As shown in FIG. 4A, the first metal electrode 402 has a thickness t in the range of about 500 angstroms to about 5000 angstroms1。
At operation 304, the first metal electrode 402 is exposed to a nitrogen-containing plasma, as shown in FIG. 4B. Active species such as nitrogen radicals in the nitrogen-containing plasma modify the surface of the metal electrode 402 and convert the surface of the metal electrode 402 to nitride 404. In one embodiment, nitride 404 is titanium nitride or molybdenum nitride. In another embodiment, the metal electrode 402 includes a native oxide (not shown) formed thereon, and the active species in the nitrogen-containing plasma converts the native oxide surface to an oxynitride. For example, nitride 404 is titanium oxynitride.
The substrate 400 including the first metal electrode 402 formed thereon is placed in a processing chamber, such as the chamber 100 shown in fig. 1 or the chamber 200 shown in fig. 2. In one embodiment, a nitrogen-containing plasma is formed by introducing a gas into a process chamber and exciting the gas. The gas may be a nitrogen-containing gas, such as ammonia (NH)3). The gas is oxygen-free. The gas does not contain oxygen because any oxidation of the first metal electrode 402 may result in a degradation of the capacitor performance. The nitrogen-containing plasma may be capacitively coupled, inductively coupled, or microwave induced. The substrate 400 is maintained at a temperature in a range from about 20 degrees celsius to about 200 degrees celsius during the exposure to the nitrogen-containing plasma. Since the substrate 400 is made of glass or polymer, any temperature higher than 200 degrees celsius may damage the substrate 400. In one embodiment, the temperature of the substrate is maintained at about 50 degrees celsius to about 180 degrees celsius, such as about 100 degrees celsius to about 150 degrees celsius. In other words, nitride 404 is formed at a temperature from about 20 degrees celsius to about 200 degrees celsius, such as from about 50 degrees celsius to about 180 degrees celsius, for example from about 100 degrees celsius to about 150 degrees celsius. Exposing the first metal electrode 402For a duration of from about 30 seconds to about 10 minutes, such as from about 1 minute to about 5 minutes, in the nitrogen-containing plasma.
Nitride 404 has a thickness t ranging from about 10 angstroms to about 50 angstroms2. The remaining first metal electrode 402 has a thickness t in the range of about 450 angstroms to about 4990 angstroms3. Since the nitride 404 is converted from a portion of the first metal electrode 402, the thickness t2And t3Is equal to the thickness t1As shown in fig. 4B. In some embodiments, the thickness t2And t3Is different from the thickness t1. By converting a portion of the first metal electrode 402 to nitride 404, the work function is increased because the work function of the nitride 404 is greater than the work function of the first metal electrode 402. For example, the first metallic work electrode 402 is made of Ti with a work function of 4.33eV, and the nitride 404 is titanium nitride with a work function greater than 4.33eV, such as 4.75 eV.
Next, at operation 306, a high-K dielectric layer 406 is formed over the nitride 404, as shown in fig. 4C. high-K dielectric layer 406 is made of any suitable dielectric material having a K value of 20 or higher, such as ZrO2Alumina (Al)2O3) Titanium dioxide (TiO)2) Or hafnium oxide (HfO)2). In some embodiments, the high-K dielectric layer 406 is a multi-layer stack including at least one layer of a high-K dielectric material. In one embodiment, high-K dielectric layer 406 comprises ZrO2A layer and a silicon nitride (SiN) layer. In another embodiment, the high-K dielectric layer 406 includes a layer of high-K dielectric material sandwiched between two dielectric layers. The high-K dielectric layer 406 formed on the nitride 404 has a K value ranging from about 20 to about 50. high-K dielectric layer 406 has a thickness ranging from about 250 angstroms to about 900 angstroms. In one embodiment, the high-K dielectric layer 406 is deposited in the same chamber as the first metal electrode 402 is exposed to the nitrogen-containing plasma or the oxygen-containing plasma. In one embodiment, the chamber is a PE-ALD chamber, such as the chamber 200 shown in FIG. 2. In one embodiment, the precursors used to deposit high-K dielectric layer 406 include a zirconium-containing precursor and an oxygen-containing precursor. Suitable zirconium-containing precursors include zirconium organylMetal precursors, such as tetrakis (ethylmethylamino) zirconium (TEMAZ), tris (dimethylamino) cyclopentadienyl zirconium (C)5H5)Zr[N(CH3)2]3Or the like. Suitable oxygen-containing precursors include H2O、O2、O3、H2O2、CO2、NO2、N2O, and the like. In another embodiment, the chamber is a PECVD chamber, such as the chamber 100 shown in figure 1.
At operation 308, a second metal electrode 408 is formed on the high-K dielectric layer 406, as shown in fig. 4D. The second metal electrode 408 may or may not be made of the same material as the first metal electrode 402. The second metal electrode 408 may be deposited by the same deposition process as the first metal electrode 402. A post metallization annealing process may be performed after forming the second metal electrode 408.
By treating the first metal electrode of the MIM capacitor with a nitrogen containing plasma, the leakage current of the MIM capacitor is reduced and the breakdown field of the MIM capacitor is improved. In addition, the K value of the high-K dielectric layer is not affected by the plasma treatment of the first metal electrode.
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (15)

1. A capacitor, comprising:
a first metal electrode;
a nitride disposed on the first metal electrode, wherein the nitride is formed at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius;
a high-K dielectric layer disposed on the nitride; and
a second metal electrode disposed on the high-K dielectric layer.
2. The capacitor of claim 1, wherein the first metal electrode comprises titanium and the nitride comprises titanium nitride.
3. The capacitor of claim 1, wherein the first metal electrode comprises molybdenum, and the nitride comprises molybdenum nitride.
4. The capacitor of claim 1 wherein the high-K dielectric layer comprises zirconium dioxide, hafnium dioxide, titanium dioxide, or aluminum oxide.
5. The capacitor of claim 1, wherein the second metal electrode comprises the same material as the first metal electrode.
6. The capacitor of claim 1, wherein the second metal electrode comprises a different material than the first metal electrode.
7. A method, comprising:
forming a first metal electrode on a substrate;
exposing the first metal electrode to a nitrogen-containing plasma in a processing chamber, wherein a portion of the first metal electrode is converted to a nitride having a work function greater than 4.33eV, wherein the nitride is formed at a temperature ranging from about 20 degrees Celsius to about 200 degrees Celsius;
forming a high-K dielectric layer on the nitride in the processing chamber; and
and forming a second metal electrode on the high-K dielectric layer.
8. The method of claim 7, wherein the processing chamber is a plasma enhanced atomic layer deposition chamber.
9. The method of claim 7, wherein the processing chamber is a plasma enhanced chemical vapor deposition chamber.
10. The method of claim 7, wherein the nitrogen-containing plasma is formed by energizing a nitrogen-containing gas, and the nitrogen-containing gas comprises ammonia.
11. The method of claim 7, wherein the substrate is maintained at a temperature in a range of about 20 degrees Celsius to about 200 degrees Celsius during the exposing of the first metal electrode to the nitrogen-containing plasma.
12. A method, comprising:
forming a first metal electrode on a substrate;
exposing the first metal electrode to a nitrogen-containing plasma in a processing chamber, wherein the substrate is maintained at a temperature in a range of about 50 degrees Celsius to about 180 degrees Celsius, and wherein a portion of the first metal electrode is converted to a nitride;
forming a high-K dielectric layer on the nitride in the processing chamber; and
and forming a second metal electrode on the high-K dielectric layer.
13. The method of claim 12, wherein the processing chamber is a plasma enhanced atomic layer deposition chamber.
14. The method of claim 12, wherein the high-K dielectric layer comprises zirconium dioxide, hafnium dioxide, or aluminum oxide.
15. The method of claim 12, wherein the temperature is in a range of about 100 degrees celsius to about 150 degrees celsius.
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