WO2005027348A1 - Multiplexing of digital signals at multiple supply voltages in an integrated circuit - Google Patents

Multiplexing of digital signals at multiple supply voltages in an integrated circuit Download PDF

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Publication number
WO2005027348A1
WO2005027348A1 PCT/US2004/027499 US2004027499W WO2005027348A1 WO 2005027348 A1 WO2005027348 A1 WO 2005027348A1 US 2004027499 W US2004027499 W US 2004027499W WO 2005027348 A1 WO2005027348 A1 WO 2005027348A1
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WO
WIPO (PCT)
Prior art keywords
voltage
terminal
digital signal
signal line
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/027499
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English (en)
French (fr)
Inventor
Christopher K. Chun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
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Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to KR1020067004544A priority Critical patent/KR101102257B1/ko
Priority to JP2006525363A priority patent/JP4675897B2/ja
Publication of WO2005027348A1 publication Critical patent/WO2005027348A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H03K17/005—Switching arrangements with several input- or output terminals with several inputs only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

Definitions

  • This invention relates to generally to integrated circuits (ICs), and more particularly, emphasis on the following aspects of the invention. BACKGROUND OF THE INVENTION
  • a semiconductor die In integrated circuit (IC) manufacturing, a semiconductor die is provided with terminals, commonly referred to as pads, for communicating with a user or other circuits in an application.
  • the die may be housed in a package having user accessible terminals for mounting on a substrate or a printed circuit board.
  • Various methods are used to couple the die pads to the terminals of the package, such as for example, wirebonds or solder balls.
  • complex integrated circuit designs incorporate more functions on a single integrated circuit die than can easily be coupled to the user accessible terminals, or pins, on the integrated circuit package housing the die.
  • the various signals on the integrated circuit die can be multiplexed to the user accessible terminals using simple digital multiplexers.
  • many ICs today include digital circuits requiring more than one supply voltage.
  • a digital signal from one part of the IC may be from a circuit operating from one supply voltage level (for example 1.0 volt), and a digital signal from another part of the IC may be from a circuit operating at another supply voltage level (for example 1.6 volts). Because of the difference in supply voltage levels, a simple digital multiplexer may not be able to reliably multiplex these signals. Therefore, there is a need for a multiplexing circuit in an IC that can multiplex digital signals that are provided at different supply voltage levels.
  • FIG. 1 illustrates, in block diagram form, an integrated circuit die having a multiple voltage multiplexer in accordance with the present invention.
  • FIG. 2 illustrates, in block diagram form, the multiplexer of FIG. 1 in more detail.
  • FIG. 3 illustrates, in schematic diagram form, a level shifter of the multiplexer of FIG. 2.
  • FIG. 4 illustrates, in schematic diagram form, an analog multiplexer circuit of the multiplexer of FIG. 2.
  • FIG. 5 illustrates, in block diagram form, a wireless device including the integrated circuit of FIG. 1.
  • the present invention provides a multiplexer circuit that can multiplex digital signals provided at different supply voltage levels.
  • the multiplexer circuit includes an analog multiplexer for receiving the digital signals, a level shifter coupled to the output of the analog multiplexer, and a supply voltage multiplexer for providing one of various supply voltages used on the IC corresponding to the signals being multiplexed.
  • a control circuit is used to control the input selection of the analog multiplexer as well as the supply voltage multiplexer for providing the correct supply voltage to the level shifter. This provides the ability to multiplex digital signals of differing voltage levels onto a single pad on the IC.
  • FIG. 1 illustrates, in block diagram form, an integrated circuit die 10 having a multiple voltage multiplexer 30 in accordance with the present invention.
  • integrated circuit die 10 includes- a digital signal processor (DSP) core 12, an application processor (AP) core 14, and a plurality of pads.
  • DSP core 12 and AP core 14 operate independently of each other.
  • DSP core 12 and AP core 14 may operate at one or more supply voltage levels (1.6, 1.4, 1.2, and 1.0 volts).
  • the plurality of pads are arranged around a perimeter of IC 10, and are user accessible terminals for providing electrical connections for the various signals and supply voltages communicated to and from IC 10.
  • the plurality of pads include a representative input/output (I/O) pad 16, and representative power supply pads 18, 20, 22, 24, and 26.
  • I/O input/output
  • Power supply pad 18 receives a power supply voltage labeled "VPAD”, power supply pad 20 is coupled to ground and labeled "VSS1", power supply pad 22 is coupled to receive a power supply voltage labeled "VDD1”, power supply pad 24 is coupled to receive a power supply voltage labeled "VDD2”, and power supply pad 26 is coupled to ground and labeled "VSS2".
  • DSP core 12 may operate at 1.6 volts, 1.4 volts, 1.2 volts, and 1.0 volt depending on the operating mode.
  • AP core 14 may operate at 1.6 volts, 1.4 volts, 1.2 volts, and 1.0 volt depending on the operating mode.
  • DSP core 12 and AP core 14 may operate at different supply voltage levels at the same time.
  • Integrated circuit 10 may include many more signals than there are external pins available on a package.
  • IC 10 may include 500 or more signals to be multiplexed to only 300 pins.
  • FIG. 1 illustrates only one simple example of multiple signals being multiplexed to one pin in accordance with the present invention.
  • DSP core 12 includes a plurality of signal lines 15 for conducting a plurality of digital signals at a supply voltage level of 1.2 volts.
  • AP core 14 includes a plurality of signal lines 17 for conducting a plurality of digital signals at a supply voltage level of 1.4 volts.
  • a digital signal is a "rail-to-rail” signal. That is, if the digital signal is provided from a circuit operating with a supply voltage of, for example, 1.4 volts, then a logic "one” is a 1.4 volt signal and a logic "zero” is a zero volt signal.
  • the pluralities of signal lines 15 and 17 are coupled to input and output terminals, as the case may be, of multiple voltage multiplexer 30. Multiplexer 30 selectively controls which one of the pluralities of signals 15 and 17 communicates via I/O pad 16, and performs a voltage translation from the internal voltage, such as for example, 1.2 or 1.4 volts, to 2.5 volts. The operation of multiplexer circuit 30 will be described in more detail below.
  • integrated circuit die 10 may include additional circuitry (not shown).
  • IC 10 is a baseband integrated circuit for wireless devices.
  • the additional circuitry may include, for example, one or more memories, display control circuits, timers, debug and test circuits, analog circuits, etc.
  • IC 10 may include circuitry other than a DSP core and an AP core. Or, the IC may have only one core.
  • the IC may be, for example, an application specific integrated circuit (ASIC) having circuit portions that operate at one supply voltage level and circuit portions that operate at another supply voltage level.
  • ASIC application specific integrated circuit
  • the IC may include different memory types that require different voltage levels. FIG.
  • Multiple voltage multiplexer 30 includes analog multiplexers 32, 34, and 36, level shifters 38, 40, and 42, register 39, output buffer 44, input buffer 46, and pad 16.
  • Each of analog multiplexers 32, 34, and 36, input buffer 46, output buffer 44, and a portion of level shifters 38, 40, and 42 are supplied by power supply voltage VPAD.
  • An output path includes analog multiplexer 32, level shifter 40 and output buffer 44.
  • Analog multiplexer 32 receives digital output signals labeled "SOI" and "S02". Signals SOI and S02 may be from DSP core 12 or from AP core 14, or from another circuit (not shown) of IC 10.
  • SOI is from a circuit operating at supply voltage VCC1
  • S02 is from a circuit operating at supply voltage VCC2.
  • digital signals SOI and S02 may be from circuits supplied with the same supply voltage or from circuits supplied by different supply voltages.
  • a control terminal of analog multiplexer 32 receives a multiplexer select signal labeled "MUX SEL".
  • the MUX SEL signal determines which of digital signals SOI and S02 are coupled to the output of analog multiplexer 32.
  • the output terminal of analog multiplexer 32 is coupled to an input of level shifter 40.
  • the MUX SEL signal is provided to the control terminal of multiplexer 34 for setting the voltage level of portions of level shifters 40 and 42 (see FIG. 3), where the voltage level corresponds to the supply voltage level of the selected digital signal SOI or S02, that is, supply voltage VCC1 or supply voltage VCC2.
  • a programmable register 39 is used to provide a control signal labeled "MUX CONTROL" to control the multiplexers and level shifters.
  • Signal MUX SEL depends on signal MUX CONTROL. That is, the logic level of the MUX SEL signal is determined by the MUX CONTROL signal.
  • level shifter 38 is optionally provided because the MUX CONTROL signal may originate from a circuit having a different supply voltage than VPAD.
  • Programmable register 39 may include one or more bits, each bit for selecting from one or more voltage levels.
  • the voltage level of level shifters 40 and 42 is set by selecting one of VDD1 or VDD2 via analog multiplexer 34. For example, if signal SOI is selected at multiplexer 32, then supply voltage VDD1 will be provided to level shifter 40. Likewise, if signal S02 is selected at multiplexer 32, then supply voltage VDD2 will be provided to level shifter 40.
  • Level shifter 38 is similar to level shifters 40 and 42, and will be discussed below in more detail in the discussion of FIG. 3.
  • analog multiplexer 32 The operation of analog multiplexer 32 will be discussed below in more detail in the discussion of FIG. 4. Still referring to FIG. 2, the level shifted digital signal from level shifter 40 is provided to an input of buffer circuit 44, and in response, a buffered digital signal at the VPAD power supply voltage is provided to pad 16 when output enable signal OE is asserted.
  • an input path of multiplexer 30 includes input buffer 46, level shifter 42, and analog multiplexer 36. Note that in the illustrated embodiment, analog multiplexer 36 performs a de-multiplexing function. A digital input signal is received at pad 16 at the pad voltage level VPAD. The digital input signal is provided to an input of input buffer circuit 46.
  • a buffered input signal is provided at the output of buffer 46 to an input of level shifter 42 when input enable signal IE is asserted.
  • Input enable signal IE and output enable signal OE are provided by control circuitry that is not shown.
  • Control signal MUX SEL which is derived from control signal MUX CONTROL, as discussed above, selects an output of multiplexer 36, either SI1 or SI2. Also, the MUX SEL signal selects the corresponding supply voltage, either VDD1 or VDD2, via multiplexer 34.
  • a level shifted digital signal at the proper voltage level is then provided to internal circuits of IC 10 via analog de-multiplexer 36. Note that the multiplexers 32 and 34 of FIG. 2 each have two inputs and de-multiplexer 36 had two outputs.
  • FIG. 3 illustrates, in schematic diagram form, one embodiment of level shifter 40 of the multiplexer of FIG. 2. Note that level shifters 38 and 42 are similar to level shifter 40.
  • Level shifter 40 includes inverter 50, P-channel transistors 52 and 54, and N-channel transistors 56 and 58. Inverter 50 receives either VDDl or VDD2 as a supply voltage as determined by control MUX SEL. The particular supply voltage corresponds to the voltage level of a digital signal being provided from the output of multiplexer 32.
  • Transistors 52, 54, 56, and 58 form an amplifier.
  • the amplifier is coupled to the power supply voltage VPAD.
  • An output of the amplifier is coupled to input buffer 44 (see FIG. 2).
  • level shifter 40 Using level shifter 40, a signal at voltage level VDDl or VDD2 is translated, or level shifted to voltage level VPAD.
  • VDDl and VDD2 are at a lower voltage potential than VPAD, however, in other embodiments, VDDl and VDDl may be at a higher voltage potential.
  • inverter 50 provides a logic low voltage to the gate of N-channel transistor 56.
  • N-channel transistor 56 is substantially non-conductive or "OFF".
  • the gate of N- transistor 58 is supplied with the logic high voltage from multiplexer 32 at VCC1 and N-channel transistor 58 is conductive or "ON”.
  • the gate of P- channel transistor 52 is pulled low through transistor 58, causing P-channel transistor 52 to be ON, thus pulling the output of the amplifier up to a logic high equal to about voltage VPAD.
  • N-channel transistor 56 is "ON” and N-channel transistor 58 is "OFF”.
  • the gate of P-channel transistor 54 is pulled low through transistor 56, causing P- channel transistor 54 to be ON.
  • Level shifter 40 as illustrated in FIG. 3, is just one example of a level shifter that can be used with multiplexer circuit 30. In other embodiments, a different type of level shifter may be used for translating a digital signal from one voltage level to another voltage level.
  • FIG. 4 illustrates, in schematic diagram form, one embodiment of analog multiplexer circuit 32 of multiplexer 30 of FIG. 2. Analog multiplexers 34 and 36 are similar to analog multiplexer 32. Analog multiplexer 32 includes inverters 64, 66, and 68, and transmission gates 60 and 62.
  • Transmission gates 60 and 62 each comprise parallel-connected N-channel and P-channel transistors.
  • Each of the inverters is a conventional CMOS (complementary metal oxide semiconductor) inverter supplied by power supply voltage VPAD.
  • CMOS complementary metal oxide semiconductor
  • MUX SEL signal is a logic high voltage
  • transmission gate 60 is conductive and transmission gate 62 is substantially non-conductive.
  • Digital signal SOI is communicated to the input of level shifter 40.
  • transmission gate 60 is substantially non-conductive and transmission gate 62 is conductive.
  • Digital signal S02 is communicated to the input of level shifter 40.
  • the use of transmission gates 60 and 62 allow digital signals SOI and S02 to be transmitted without a threshold voltage drop.
  • FIG. 5 illustrates, in block diagram form, a wireless device 72 including integrated circuit 10.
  • Wireless device 72 includes an RF (radio frequency) IC 76, a power management IC 74 in addition to integrated circuit 10.
  • wireless device 72 is a cellular telephone.
  • wireless device 72 may be any type of 2-way radio, such as for example, a walkie-talkie, 2-way pager, PDA (personal digital assistant), or personal computer, or any device for providing voice and/or data transmitting and/or receiving functions.
  • the present invention as described herein, provides the ability to multiplex digital signals of differing voltage levels onto a single pad of an IC.

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  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Analogue/Digital Conversion (AREA)
PCT/US2004/027499 2003-09-05 2004-08-24 Multiplexing of digital signals at multiple supply voltages in an integrated circuit Ceased WO2005027348A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020067004544A KR101102257B1 (ko) 2003-09-05 2004-08-24 집적 회로에서 다중 공급 전압들로의 디지털 신호들의 멀티플렉싱 장치 및 멀티플렉싱 방법
JP2006525363A JP4675897B2 (ja) 2003-09-05 2004-08-24 集積回路内の複数の供給電圧でのデジタル信号の多重化

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/656,051 US6856173B1 (en) 2003-09-05 2003-09-05 Multiplexing of digital signals at multiple supply voltages in an integrated circuit
US10/656,051 2003-09-05

Publications (1)

Publication Number Publication Date
WO2005027348A1 true WO2005027348A1 (en) 2005-03-24

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US (1) US6856173B1 (enExample)
JP (1) JP4675897B2 (enExample)
KR (1) KR101102257B1 (enExample)
CN (1) CN100574106C (enExample)
TW (1) TWI344688B (enExample)
WO (1) WO2005027348A1 (enExample)

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JP2007504752A (ja) 2007-03-01
CN100574106C (zh) 2009-12-23
US6856173B1 (en) 2005-02-15
KR101102257B1 (ko) 2012-01-03
CN1846354A (zh) 2006-10-11
TW200516754A (en) 2005-05-16
JP4675897B2 (ja) 2011-04-27
KR20060079848A (ko) 2006-07-06
US20050052204A1 (en) 2005-03-10

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