WO2005027200A3 - Verfahren und vorrichtung zum kontaktieren von halbleiterchips auf einem metallischen substrat - Google Patents

Verfahren und vorrichtung zum kontaktieren von halbleiterchips auf einem metallischen substrat Download PDF

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Publication number
WO2005027200A3
WO2005027200A3 PCT/DE2004/001900 DE2004001900W WO2005027200A3 WO 2005027200 A3 WO2005027200 A3 WO 2005027200A3 DE 2004001900 W DE2004001900 W DE 2004001900W WO 2005027200 A3 WO2005027200 A3 WO 2005027200A3
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WO
WIPO (PCT)
Prior art keywords
contacting
substrate
semiconductor chips
chip
contacted
Prior art date
Application number
PCT/DE2004/001900
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English (en)
French (fr)
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WO2005027200A8 (de
WO2005027200A2 (de
Inventor
Martin Michalk
Manfred Michalk
Sabine Nieland
Original Assignee
Assa Abloy Identification Tech
Martin Michalk
Manfred Michalk
Sabine Nieland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Assa Abloy Identification Tech, Martin Michalk, Manfred Michalk, Sabine Nieland filed Critical Assa Abloy Identification Tech
Priority to US10/570,256 priority Critical patent/US7727861B2/en
Priority to AU2004273128A priority patent/AU2004273128A1/en
Priority to CA002539463A priority patent/CA2539463A1/en
Priority to EP04762724A priority patent/EP1661157A2/de
Publication of WO2005027200A2 publication Critical patent/WO2005027200A2/de
Publication of WO2005027200A3 publication Critical patent/WO2005027200A3/de
Publication of WO2005027200A8 publication Critical patent/WO2005027200A8/de

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren und eine Vorrichtung anzugeben, die es ermöglichen, die Produktivität des Chipbondens und der mit dem Chipbonden verbundenen vor- und nachgelagerten Arbeitsschritte zu erhöhen. Erfindungsgemäss gelingt die Lösung der Aufgabe durch ein Verfahren zum Kontaktieren von Halbleiterchips (3) auf einem metallischen Substrat (16), wobei sich mindestens auf einer Substratseite ein Ätzresist (27) befindet und auf der Kontaktierseite (30) Halbleiterchips (3) mittels Flip-Chip-Bond-Verfahren kontaktiert werden, wobei auf der Kontaktierseite (30) des Substrates (16) ein Kontaktierbereich (7) erzeugt wird, auf dem ein Halbleiterchip (3) mit zwei Kontakthügeln (6) so kontaktiert wird, dass beidseitig einer den Kontaktierbereich teilenden Strukturlinie (35) oder eines Strukturgrabens (13) je ein Kontakthügel (6) kontaktiert ist, dass nach dem Kontaktieren ein Underfilling des Chips (3) erfolgt und danach ein elektrisch isolierender Durchbruch im Kontaktierbereich (7) erzeugt wird und ein Trennen eines den Halbleiterchip (3) tragenden Moduls aus dem Substrat (16) erfolgt.
PCT/DE2004/001900 2003-09-06 2004-08-28 Verfahren und vorrichtung zum kontaktieren von halbleiterchips auf einem metallischen substrat WO2005027200A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US10/570,256 US7727861B2 (en) 2003-09-06 2004-08-28 Method and device for contacting semiconductor chips
AU2004273128A AU2004273128A1 (en) 2003-09-06 2004-08-28 Method and device for contacting semiconductor chips
CA002539463A CA2539463A1 (en) 2003-09-06 2004-08-28 Method and device for contacting vo semiconductor chips on a metallic substrate
EP04762724A EP1661157A2 (de) 2003-09-06 2004-08-28 Verfahren und vorrichtung zum kontaktieren von halbleiterchips auf einem metallischen substrat

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DE10341186A DE10341186A1 (de) 2003-09-06 2003-09-06 Verfahren und Vorrichtung zum Kontaktieren von Halbleiterchips
DE10341186.0 2003-09-06

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WO2005027200A2 WO2005027200A2 (de) 2005-03-24
WO2005027200A3 true WO2005027200A3 (de) 2006-03-16
WO2005027200A8 WO2005027200A8 (de) 2006-06-01

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EP (1) EP1661157A2 (de)
AU (1) AU2004273128A1 (de)
CA (1) CA2539463A1 (de)
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WO (1) WO2005027200A2 (de)

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JP4353853B2 (ja) * 2004-05-20 2009-10-28 三洋電機株式会社 回路装置の製造方法および板状体
DE102005007643A1 (de) * 2005-02-19 2006-08-31 Assa Abloy Identification Technology Group Ab Verfahren und Anordnung zum Kontaktieren von Halbleiterchips auf einem metallischen Substrat
EP1968109A3 (de) * 2007-03-08 2012-08-01 Nissan Motor Co., Ltd. Halbleiterbauelement und Verfahren zu seiner Herstellung
DE102014201635B3 (de) * 2014-01-30 2015-05-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Anordnung von elektronischen Bauelementen und elektronische Schaltanordnung
US9165832B1 (en) * 2014-06-30 2015-10-20 Applied Materials, Inc. Method of die singulation using laser ablation and induction of internal defects with a laser
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US20070163992A1 (en) 2007-07-19
WO2005027200A8 (de) 2006-06-01
WO2005027200A2 (de) 2005-03-24
DE10341186A1 (de) 2005-03-31
EP1661157A2 (de) 2006-05-31
AU2004273128A1 (en) 2005-03-24
CA2539463A1 (en) 2005-03-24
US7727861B2 (en) 2010-06-01

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