WO2005015629A1 - Verfahren zur herstellung eines kontaktes und elektronische bauelement, umfassend derartige kontakte - Google Patents
Verfahren zur herstellung eines kontaktes und elektronische bauelement, umfassend derartige kontakte Download PDFInfo
- Publication number
- WO2005015629A1 WO2005015629A1 PCT/DE2004/001294 DE2004001294W WO2005015629A1 WO 2005015629 A1 WO2005015629 A1 WO 2005015629A1 DE 2004001294 W DE2004001294 W DE 2004001294W WO 2005015629 A1 WO2005015629 A1 WO 2005015629A1
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- WIPO (PCT)
- Prior art keywords
- layer
- silicide
- metal
- passivation
- contact
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 113
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 109
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 32
- 229910052711 selenium Inorganic materials 0.000 claims abstract description 15
- 229910052717 sulfur Inorganic materials 0.000 claims abstract description 9
- 229910052714 tellurium Inorganic materials 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 128
- 239000002184 metal Substances 0.000 claims description 128
- 238000002161 passivation Methods 0.000 claims description 94
- 239000004065 semiconductor Substances 0.000 claims description 89
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 63
- 229910052710 silicon Inorganic materials 0.000 claims description 63
- 239000010703 silicon Substances 0.000 claims description 62
- 230000015572 biosynthetic process Effects 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 26
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 claims description 24
- 229910052798 chalcogen Inorganic materials 0.000 claims description 16
- 150000001787 chalcogens Chemical class 0.000 claims description 16
- 239000011669 selenium Substances 0.000 claims description 15
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000012212 insulator Substances 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 8
- 229910017052 cobalt Inorganic materials 0.000 claims description 8
- 239000010941 cobalt Substances 0.000 claims description 8
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 8
- 239000011593 sulfur Substances 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 229910006585 β-FeSi Inorganic materials 0.000 claims description 3
- 229910052748 manganese Inorganic materials 0.000 claims description 2
- 229910019974 CrSi Inorganic materials 0.000 claims 1
- 229910017028 MnSi Inorganic materials 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 230000007704 transition Effects 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 201
- 206010010144 Completed suicide Diseases 0.000 description 18
- 238000002513 implantation Methods 0.000 description 16
- 229910008310 Si—Ge Inorganic materials 0.000 description 12
- 229910052732 germanium Inorganic materials 0.000 description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 238000000137 annealing Methods 0.000 description 6
- 229910005883 NiSi Inorganic materials 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 229910019001 CoSi Inorganic materials 0.000 description 4
- 229910005742 Ge—C Inorganic materials 0.000 description 4
- 229910008484 TiSi Inorganic materials 0.000 description 4
- 238000005204 segregation Methods 0.000 description 4
- 238000005496 tempering Methods 0.000 description 4
- 238000007669 thermal treatment Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- 229910018540 Si C Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000002156 adsorbate Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052805 deuterium Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910005329 FeSi 2 Inorganic materials 0.000 description 1
- 229910005881 NiSi 2 Inorganic materials 0.000 description 1
- 241000120020 Tela Species 0.000 description 1
- 229910008812 WSi Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 germanid Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011572 manganese Substances 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28537—Deposition of Schottky electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66984—Devices using spin polarized carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention relates to a method for producing a contact and electronic components, comprising such contacts.
- Ohmic metal-semiconductor contacts with a small contact resistance are used in microelectronics e.g. B. by means of metal-silicon compounds, so-called suicides, such as TiSi 2 , CoSi 2 , NiSi and so on, realized on highly doped silicon.
- Doping depths of at least 50 to 100 nanometers or even more are required for the configuration of these highly doped regions in semiconductor substrates.
- the doping elements used during the ion implantation e.g. B. arsenic or boron are distributed in the semiconductor in a certain width.
- a subsequent thermal treatment leads to the activation of the doping elements and to the diffusion of these doping elements in the semiconductor.
- Schottky contacts Metal semiconductor contacts with diode behavior, so-called Schottky contacts, are of great interest for many applications. These show a non-linear characteristic curve that depends on the Schottky barrier.
- Ohmic and Schottky contacts are passivated by a temperature treatment in a hydrogen or deuterium atmosphere in order to reduce the density of the unsaturated bonds at the contact interface and thus to improve the electrical or optical properties.
- a disadvantage of the contacts produced according to the prior art is that these passivation effects only show up to approximately 300 ° C. However, this does not make it possible to process silicon components industrially, that is to say for series production.
- a further disadvantage is that the passivation effects known from the prior art have only been shown with UHV deposition and only with a few, pure metals. These processes are also not suitable for industrial use and are therefore unsuitable for the series production of metal-semiconductor contacts.
- the object of the invention is therefore to provide a method for producing ohmic contacts and Schottky contacts with an adjustable barrier height between a first layer and a layer adjacent to the first layer.
- the method for producing the contact provides that passivation elements are first introduced or applied in or on the first or the adjacent layer.
- a semiconductor layer or an insulator can be selected as the adjacent layer.
- a silicide, a germanide or a pure metal can be selected as the first layer.
- the passivation elements are then enriched at at least one interface of the first layer with the adjacent layer by means of a temperature treatment.
- the temperature treatment can simultaneously lead to silicide formation or germanide formation as the first layer and self-adjusting to the enrichment of the passivation elements the interface to the adjacent layer.
- the interface (s) between the first layer and the adjacent layer is passivated by enrichment of the passivation elements and for the production of the
- the work function at the interface is modified or reduced.
- the passivation elements sit at the ends of free bonds and fill up the structures at the interface between the first layer and the adjacent layer.
- a semiconductor layer e.g. B. silicon or a dielectric selected.
- the adjacent layer can have a substrate, that is to say a supporting function for the first layer.
- a metal silicide or a semiconductor silicon is selected as the silicide.
- the passivation of at least one interface of the first layer to the adjacent layer permits a wide variety of further processing options to produce such a contact, since, in contrast to the prior art, suicides and germanides are also used in addition to pure metals . Compared to passivated metal-semiconductor contacts with pure metals as contacts, the suicides / germanides are advantageously characterized by a much higher thermal stability and thus also by subsequently better processability.
- the method of sequential deposition of the passivation element and the metal known from the prior art is not comparable to the method according to the invention. Rather, the method according to the invention provides for the self-adjusting, ie locally limited, enrichment of the passivation elements at the interface (s). This is the prerequisite for electronic components with atomically sharp ohmic contacts on adjacent layers, such as semiconductors made of silicon and dielectrics, which have not been achieved in the prior art.
- the passivation elements are either deposited or implanted and enriched by a subsequent temperature treatment at the suicide interface with the adjacent layer.
- Deposition layer or to bring directly into the adjacent layer as a substrate close to the surface.
- the passivation elements can be applied or introduced both in an adjacent layer and in the metallic and / or silicon-containing parts, in the case of a germanide to be formed, in the parts containing germanium, and then the temperature treatment for the purpose of enrichment and possibly silicide or germanide formation he follows.
- the passivation element is actively enriched at the interface (s) of the first layer with the adjacent layer.
- the layer structure can either be annealed or oxidized in an inert atmosphere at appropriate temperatures.
- the passivation elements are enriched by means of thermally induced segregation from the semiconductor layer or by diffusion of the passivation element from the first layer to the interface with the adjacent layer.
- the solubility of the passivation element in the layers is small enough.
- the enrichment of a previously deposited or implanted passivation element can - as mentioned - also be brought about during the thermally induced formation of the first layer, that is to say during the formation of silicide or germanide.
- the prerequisite for this is that the solubility of the passivation element in the first layer is sufficiently low.
- the passivation elements from the silicide or germanide front to the adjacent layer that is e.g. B. pushed to a semiconductor layer made of silicon or a dielectric.
- the temperature treatment is then used in addition to the passivation of the interfaces at the same time to form the first layer.
- Chalcogenes such as selenium, sulfur or tellurium are chosen in particular as passivation elements.
- Chalcogens such as sulfur or selenium show particularly strong segregation effects in silicon and silicides / germanides, so that the interface between the the first and the adjacent layer is thermally enriched with sulfur or selenium or tellurium.
- the passivation element is advantageously divided into corresponding parts of the device with a dose of 10 12 to 10 16 cm 2
- Layer structure in the silicide or germanide or in their constituents before formation or in the metal as a respective first layer and / or optionally also introduced into the adjacent layer.
- a dose which corresponds to an enrichment of approximately one monolayer of the passivation element.
- the work function of a silicide or the Schottky barrier can also be reduced with a smaller concentration.
- the passivation of the interface can also be carried out using hydrogen or deuterium or generally with ions of group 1 of the periodic table. The introduction of those necessary for passivation
- Passivation elements can thus, as mentioned, take place before or after the generation of the suicide or germanid. This advantageously has the effect that a person skilled in the art can adapt the sequence of the process steps to the material system.
- strained silicon or germanium which reacts with a metal to form a germanide, or a le- Alloy of Si-Ge, Si-C, Si-Ge-C can be used because these layers will be of increasing importance in the future.
- an adjacent layer not a pure silicon substrate, but rather the particularly thin silicon cover layer of a SOI substrate as a substrate, which can already be produced in series, or else an SOI substrate with strained silicon, Si-Ge, Si-Ge Select C or Germanium as the top layer.
- the metal silicide or metal germanide is formed by depositing a metal on the silicon or germanium substrate and subsequent annealing or by additional selective deposition, usually selective epitaxy of silicon (or Si-Ge), prior to the metal deposition in the contact area and subsequent temperature treatment.
- silicide z. B. Ru 2 Si 3 or ß-FeSi 2 into consideration.
- the band discontinuities can be changed.
- semiconductor Suicides by doping with suitable materials, such as. B. manganese, cobalt, iron, and so on obtained magnetic properties, and the interface with the silicon substrate was passivated according to the invention, it is possible to implement so-called spin transistors with magnetic source and drain contacts and a gate.
- Polarized electrons can be injected from the magnetic source contact (magnetic semiconducting silicide) in the channel area consisting of silicon and by means of the field effect, the so-called Rashba effect (Rashba EI, Fiz. Tverd. Tela (Leningrad) (1960), Sov. Phys Solid State 2, 1109ff.)
- the spin direction can be rotated.
- the spin rotation causes a change in the resistance level when the polarized electron enters the magnetic drain region, which can be read out as a transistor signal.
- no semiconductor layer is selected as the adjacent layer, but a dielectric whose interface (s) with the silicide or germanide or with a metal is or are passivated as the first layer.
- a dielectric whose interface (s) with the silicide or germanide or with a metal is or are passivated as the first layer.
- Metal silicide insulator junctions are particularly advantageously used as gate contacts in future MOSFETs. puts.
- the (two-layer) silicided poly-silicon gate contacts on the gate dielectric which are common in today's silicon technology are replaced by a metal contact, e.g. B. from a metallic silicide to further reduce the gate capacity.
- Si0 2 or SiO x N y or an oxide with greater permeability can be selected, such as B. HfOx, ZrO x , LaAlO x .
- the metal content of a metal silicide or germanium is advantageously selected from the group of cobalt, nickel, titanium, platinum, tungsten and / or molybdenum.
- the metal silicide or the metal germanide is then advantageously produced by annealing after a suitable metal layer has been deposited or applied to the adjacent silicon- or germanium-containing layer.
- a semiconductor silicide as the first layer and a semiconductor layer as the adjacent layer
- a metal silicide / metal germanide as the first layer and a semiconductor layer or an insulator as the adjacent layer
- the method can be carried out using a mask.
- the Si0 2 mask used for the self-adjusting formation of the metal silicide or MetalIgermanids according to the prior art at the same time as an implantation mask for the passivation element.
- the advantages achieved by the method thus relate to the production of ohmic contacts or Schottky contacts with adjustable barrier height and metal silicide or metal germanide insulator transitions with adjustable work function. Materials are used that are already processed in series in microelectronics. It can be used to set ohmic contacts and negative Schottky barriers. Negative Schottky barriers can be used particularly advantageously for ultra-fast components, since this allows ballistic injection of electrons into an adjacent layer, for example into a semiconductor, to be implemented (Guo, J. and Lundstrom, MS (2002). IEEE Trans. Electron Devices 49 , 1897ff.).
- An electronic component thus comprises at least one passivated contact produced in this way.
- the contacts according to the invention are special for the production of so-called metal gates for future MOSFETs suitable, in which the work function of a gate dielectric is adjusted in particular by means of sulfur, selenium or tellurium.
- ultra-flat metal silicide semiconductor contacts for Schottky barrier MOSFETs can also be produced.
- the ultra-flat contacts make it possible to reduce or even eliminate the Schottky barrier at the metal silicide-semiconductor junction so that negative Schottky barriers are formed.
- This makes it possible to scale the SB-MOSFETs, in particular on silicon on insulator (SOI) substrates, even in a multi-gate arrangement up to gate lengths ⁇ 10 nanometers.
- spin transistors can be realized, which enable spin transport from the semiconductor silicide into a semiconductor layer as an adjacent layer using the so-called Rashba effect.
- Fig. 2 Formation of a passivated contact between a metal silicide as a first layer and a semiconductor layer as an adjacent layer after deposition of a metal layer (not shown) on a semiconductor layer 21 and first annealing to form the metal silicide 25. Then implantation in the metal silicide and / or in the semiconductor layer with passivation elements. Annealing again to enrich the passivation elements at the interfaces 26a, 26b of the metal silicide 25 to the semiconductor layer 21.
- a passivation element as layer 46 on the surface of a semiconductor layer 41 and subsequent deposition of a metal layer 44.
- the silicide layer 45 is only formed after the passivation element has been deposited and the enrichment takes place during the silicide formation by snow plow effect.
- the passivation elements are not built into the silicide.
- Layer for forming a gate dielectric Implantation of a passivation element (arrows) in the metal silicide 55. Subsequently, a temperature treatment is carried out to enrich the passivation element at the interface, which leads to a modification of the work function of the gate contact.
- Layer 59 is a base layer and consists, for. B. from silicon or from a SOI structure substrate.
- a metal silicide 65 as the first layer on a dielectric 67 as the adjacent layer.
- the components of the metal silicide are first deposited, that is to say a metal 64 is applied to a polysilicon 68 as components.
- the passivation element is preferably implanted in the polysilicon or introduced during the deposition.
- the suicide 65 is formed and the passivation element is enriched at the interface 66a to the dielectric 67 by means of temperature treatment (FIG. 6b)).
- SB Schottky barrier
- the passivation of the interfaces 76a and 76b takes place by implanting the passivation elements in the source and drain regions of the silicon layer 71 as the first layer and optionally also in the gate material 80 (for example polysilicon) (FIG. 7a)).
- a mask 2 for. B. from Si0 2 on a silicon-containing semiconductor substrate 1, in particular made of pure silicon, applied ( Figure la)). With the aid of the implantation mask 2, the establishment of contact is laterally limited.
- selenium or sulfur or tellurium as chalcogen in the semiconductor layer 1 near its surface that is z. B. up to a few 100 nanometers deep. This process is indicated by arrows ( Figure lb)).
- the dose is chosen so that sufficient passivation can be achieved after a temperature treatment. Typically, a dose of 10 13 -10 15 cm “2 is implanted for this purpose.
- a temperature treatment is optionally carried out.
- the metal silicide-semiconductor contact is produced.
- the metallic portion 4 of the suicide selected from the group of z. B. cobalt, nickel, titanium, platinum, tungsten or molybdenum, as a thin layer of z. B. 5 to 50 nanometers deposited.
- an additional titanium protective layer of e.g. B. deposited 10 nanometers before a two-stage tempering for silicide formation is carried out (not shown). After the first annealing at approx. 550 ° C, unreacted metal layers are selectively etched off.
- the second tempering takes place in a temperature range of 700 to 900 ° C z. B. for 30 seconds. Since silicide formation occurs in the area previously implanted with the chalcogen outside the mask 2, the chalcogen is preferably enriched at the interfaces 6a, b of the metal silicide 5 to the semiconductor layer 1, and thus an efficient passivation is achieved. Through the simultaneous use of a Si0 2 mask as an implantation mask and for silicide formation, the passivated interfaces are also formed in a self-adjusting manner, since the silicide formation and the passage through the mask are limited to identical areas.
- the result is an ohmic contact or a Schottky contact with a small, with particularly efficient passivation by means of high enrichment of the passivation element at the interface 6a, b, even with a negative Schottky barrier.
- Figure 2 To form a passivated contact between a metal silicide 25 as the first layer and a semiconductor layer 21 as the adjacent layer is again a mask 22, z. B. from Si0 2 on a semiconductor substrate 21, in particular made of silicon as a semiconductor, applied ( Figure 2a). With the help of the implantation mask 22 from z. B. Si0 2 , the contact production is laterally limited.
- the metal silicide 25 is first produced on the semiconductor layer 21.
- a metal is applied to the structure of FIG. 2a and, according to the prior art, is converted into a silicide 25 by temperature treatment in the area not covered by the mask 22.
- the metal silicide semiconductor contact consists of z. B. TiSi 2 , CoSi 2 , NiSi, NiSi 2 , PtSi, WSi 2 or from another metal silicide 25 to a further semiconductor layer 21.
- the metal silicide 25 has, as is known from the first embodiment, horizontally and vertically to the Silicon semiconductor layer 21 extending interfaces 26a, 26b. The metal silicide 25 is thus also arranged in or on the silicon layer 21.
- a chalcogen e.g. B. sulfur or selenium or tellurium either directly implanted in the metal silicide 25 and / or in the silicon semiconductor layer 21 near its interface ( Figure 2b).
- the dose is chosen so that sufficient passivation is achieved after tempering. For example, 7xl0 14 Se + cm "2 in the sili- zium 21 or implanted near the interfaces and then at temperatures of z. B. 700-1000 ° C annealed.
- the interfaces 26a and 26b are enriched with the passivation element. This will make the Schottky barrier of suicide 25 at the interface
- a mask 32 for. B. of Si0 2 , applied to the semiconductor substrate 31, in particular made of silicon as a semiconductor ( Figure 3a). With the help of the implant mask 32 from z. B. Si0 2 , the contact production is laterally limited.
- a metal 34 selected from the group of e.g. B. cobalt, nickel, titanium, platinum, tungsten or molybdenum, as a thin metal layer 34 of z. B. 5 to 50 nanometers deposited (Fig. 3a)).
- the implantation then takes place, again represented by arrows, directly into the metal layer 34 and / or near the interfaces between the metal layer 34 and the adjacent layer 31 (FIG. 3b).
- the passivation elements accumulate at the interfaces 36a, 36b by segregation from the adjacent layer 31 and / or diffusion out of the metal silicide 35, and thus produce the desired contact (FIG. 3c).
- Selective etching can be used to remove unreacted metal layers.
- Semiconductor layer 41 as an adjacent layer is again a mask 42, z. B. of Si0 2 , applied to a semiconductor substrate 41, in particular on silicon as a semiconductor ( Figure 4a)).
- a mask 42, z. B. of Si0 2 applied to a semiconductor substrate 41, in particular on silicon as a semiconductor ( Figure 4a)).
- the contact production is laterally limited.
- a passivation layer 46 e.g. B. a monolayer of a chalcogen, deposited (Fig. 4b)).
- a metal 44 is then deposited on this layer 46. (Fig. 4c)).
- the metal can be selected from the group of z. B. cobalt, nickel, titanium, platinum, tungsten or molybdenum, as a thin layer 44 of z. B. 5 to 50 nanometers are deposited on the passivation layer 46.
- the chalcogen is enriched at the interfaces 46a, 46b of the metal silicide to the semiconductor layer 41 and thus an efficient passivation is achieved.
- the resulting layer structure is treated thermally in such a way that a passivated silicide contact arises as a result of silicide formation (FIG. 4d)). This means that temperature treatment is used both for the silicidation and thus for the production of the metal silicide-semiconductor contact and for the passivation of the interfaces 46a, 46b.
- semiconductor layers with a substrate function are thus specified as adjacent layers.
- a metal or a metal silicide as the first layer is used as the gate contact, and the work function can be set by means of a chalcogen at the interface with a dielectric 57 as the adjacent layer.
- the chalcogen can be implanted in the previously generated silicide or in the metal contact and by an annealing on the
- Interface between metal silicide 55 and dielectric 57 can be enriched, which results in a change in the work function ( Figure 5).
- the contact here consists of the passivated interface (not shown) between the metal silicide 55 or the metal as the first layer and the dielectric 57 as the adjacent layer.
- This layer structure is arranged on a support layer 59.
- a dielectric 67 is first successively, then an amorphous or a polysilicon or alternatively a poly -Si-Ge layer 68 and then a metal 64 then deposited (Fig. 6a)).
- the passivation elements can be deposited with the poly gate material 68 or also implanted in this (not shown).
- Layers 68 and 64 have the silicon and metallic components of the suicide 65 to be formed.
- a thermal treatment takes place, which leads to the conversion of both layers 68 and 64, to the formation of the metal silicide 65 and to the passivation of the interface 66a to the dielectric 67 (FIG. 6b)).
- the suicides CoSi 2 , TiSi 2 and NiSi are particularly suitable.
- the ternary suicides TiSi x Ge y and NiSi x Ge y are particularly suitable.
- selenium can be implanted in the polysilicon 68 and, by thermal treatment, an enrichment of the selenium at the interface 66a between the metal silicide 65 as the first layer and Dielectric 67 can be achieved as an adjacent layer and thus the work function of the metal silicide 65 to the dielectric 67 can be set.
- the layer thickness of the polysilicon 68 and of the metal 64 are selected such that the polysilicon is completely or almost completely silicided.
- Layer 69 is a base layer and consists, for. B. made of silicon.
- FIG. 7 Seventh embodiment (FIG. 7):
- FIG. 7 shows the manufacture of a Schottky barrier MOSFET with negative Schottky barriers of the source and drain contacts through passivation.
- the source and drain contacts 75a, b are produced by silicidation and passivation according to one of the methods described in exemplary embodiments 1 to 4 (FIG. 7b)).
- the component structure of FIG. 7a) consists of a dielectric 77 as the adjacent layer, which is arranged on the semiconductor layer made of silicon 71 as the first layer.
- the gate contact 80, the insulation spacers 81a and 81b and the dielectric 77 are, as mentioned, arranged on a silicon on insulator or on a SiGe substrate 71, 79 (FIG. 7a)).
- the finished component structure has metal silicides 75a, b as first layer with the function of Schottky source and drain.
- the interfaces between the source and drain 76a, b to the MOSFET channel 71 as an adjacent layer are enriched by a temperature treatment with a passivation element.
- the passivation can e.g. B. by implantation of the passivation elements in the later source and drain regions of the silicon layer 71 and optionally also in the gate material 80, for. B. in polysilicon.
- a metal is then deposited (not shown) and the metal silicide 75a, b as source and drain, and optionally also the gate silicide on polysilicon, is formed in a self-adjusting manner by means of a temperature treatment.
- the unreacted metal on the spacers 81a and 81b - depending on the design also on the gate 80 - is removed by wet chemical means.
- the passivation elements accumulate at the interfaces 76a, b during the thermal treatment and reduce the Schottky barrier of the suicide 75a, b.
- the gate 80 can alternatively also be produced as a metal or metal silicide gate contact according to one of the methods described above (see FIGS. 5 and 6).
- the silicon layer 71 of an SOI substrate with a thickness of approximately ⁇ 30 nanometers so small as the starting layer structure that full-depleted MOSFETs can be formed. If can be. If the gate length is chosen to be extremely small, that is to say less than about 30 nanometers, and the passivation of the CoSi 2 or NiSi source / drain contacts 75a, 75b, for. B. with selenium on the source and drain side of the contact in the channel direction 76a, 76b lead to a negative Schottky barrier, ballistic transport of charge carriers is advantageously possible, as was shown by means of simulation calculations by Lundström.
- FIG. 7 Schottky barrier mosfet with strained silicon or with Si-Ge layer or Si-Ge-C layer 71:
- strained silicon or Si can also be used particularly advantageously -Ge, Si-Ge-C 71 on Si0 2 79 can be used for the production of Schottky barriers Mosfets.
- the silicidation and passivation takes place as in embodiment 6 or in the preceding examples.
- a metal gate according to exemplary embodiments 5 and 6 can also be used in order to be able to adjust the work function to the dielectric 77.
- Si0 2 or any high-K oxide can be used as dielectric 77.
- the semiconducting suicides for example Ru 2 Si 3 , jß-FeSi 2
- the passband discontinuities of the silicide / silicon Contact can be changed. This can advantageously influence the electrical transport from the silicide to the silicon.
- the component shown in Fig. 7 b represents a
- cobalt disilicide semiconductor contacts produced according to the invention are temperature stable.
- multi-gate MOSFETs FinFETs, omega-gates
- gate dielectric Si0 2 , Si 3 N, high k material
- gate contact (poly-Si, poly-SiGe, metal, silicide)
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Abstract
Description
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EP04738743.6A EP1649505B1 (de) | 2003-07-25 | 2004-06-19 | Verfahren zur herstellung eines kontaktes |
JP2006520656A JP4999457B2 (ja) | 2003-07-25 | 2004-06-19 | 接点の製作方法とその接点を持つ電子部品 |
US10/565,990 US7528058B2 (en) | 2003-07-25 | 2004-06-19 | Method for producing a contact and electronic component comprising said type of contact |
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DE10334353.9 | 2003-07-25 | ||
DE10334353A DE10334353A1 (de) | 2003-07-25 | 2003-07-25 | Verfahren zur Herstellung eines Kontaktes und elektronisches Bauelement, umfassend derartige Kontakte |
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US (1) | US7528058B2 (de) |
EP (1) | EP1649505B1 (de) |
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Cited By (2)
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JP2008131051A (ja) * | 2006-11-20 | 2008-06-05 | Qimonda Ag | 半導体装置の製造方法 |
CN102136428A (zh) * | 2011-01-25 | 2011-07-27 | 北京大学 | 一种锗基肖特基n型场效应晶体管的制备方法 |
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US6903433B1 (en) | 2000-01-19 | 2005-06-07 | Adrena, Inc. | Chemical sensor using chemically induced electron-hole production at a schottky barrier |
US7274082B2 (en) * | 2000-01-19 | 2007-09-25 | Adrena, Inc. | Chemical sensor using chemically induced electron-hole production at a schottky barrier |
BE1015721A3 (nl) * | 2003-10-17 | 2005-07-05 | Imec Inter Uni Micro Electr | Werkwijze voor het reduceren van de contactweerstand van de aansluitgebieden van een halfgeleiderinrichting. |
US6972470B2 (en) * | 2004-03-30 | 2005-12-06 | Texas Instruments Incorporated | Dual metal Schottky diode |
JP4940682B2 (ja) * | 2005-09-09 | 2012-05-30 | 富士通セミコンダクター株式会社 | 電界効果トランジスタおよびその製造方法 |
US7250666B2 (en) * | 2005-11-15 | 2007-07-31 | International Business Machines Corporation | Schottky barrier diode and method of forming a Schottky barrier diode |
DE102007024986A1 (de) | 2007-05-28 | 2008-12-04 | Forschungszentrum Jülich GmbH | Temperaturstabile TCO-Schicht, Verfahren zur Herstellung und Anwendung |
CN101981703A (zh) * | 2008-02-15 | 2011-02-23 | 新加坡科技研究局 | 具有化合价修正吸附物区域的光电探测器及其制备方法 |
US8164086B2 (en) * | 2008-09-17 | 2012-04-24 | The Provost, Fellows and Scholars of the Colege of the Holy and Undivided Trinity of Queen Elizabeth Near Dublin | Phase-controlled field effect transistor device and method for manufacturing thereof |
JP5367340B2 (ja) | 2008-10-30 | 2013-12-11 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
DE102010004230A1 (de) | 2009-01-23 | 2010-10-14 | Qimonda Ag | Integrierter Schaltkreis mit Kontaktstrukturen für P- und N-Dotierte Gebiete und Verfahren zu dessen Herstellung |
JP5550511B2 (ja) * | 2010-09-29 | 2014-07-16 | 株式会社東芝 | 半導体装置の製造方法 |
ITTO20110995A1 (it) * | 2011-10-31 | 2013-05-01 | St Microelectronics Srl | Dispositivo micro-elettro-meccanico dotato di regioni conduttive sepolte e relativo procedimento di fabbricazione |
US20140065799A1 (en) * | 2012-09-03 | 2014-03-06 | Intermolecular, Inc. | Methods and Systems for Low Resistance Contact Formation |
KR20140134068A (ko) * | 2013-05-13 | 2014-11-21 | 에스케이하이닉스 주식회사 | 스핀 트랜지스터 및 이 스핀 트랜지스터를 포함하는 반도체 장치, 메모리 장치, 마이크로프로세서, 프로세서, 시스템, 데이터 저장 시스템 및 메모리 시스템 |
US20150118833A1 (en) * | 2013-10-24 | 2015-04-30 | Applied Materials, Inc. | Method of making source/drain contacts by sputtering a doped target |
KR102634054B1 (ko) | 2018-08-06 | 2024-02-06 | 삼성전자주식회사 | 일렉트라이드 전극을 포함하는 트랜지스터 |
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EP1649505B1 (de) | 2014-01-15 |
EP1649505A1 (de) | 2006-04-26 |
DE10334353A1 (de) | 2005-02-17 |
JP4999457B2 (ja) | 2012-08-15 |
US7528058B2 (en) | 2009-05-05 |
US20060275968A1 (en) | 2006-12-07 |
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