WO2005013281A2 - Nonvolatile memory and method of making same - Google Patents

Nonvolatile memory and method of making same Download PDF

Info

Publication number
WO2005013281A2
WO2005013281A2 PCT/US2004/022436 US2004022436W WO2005013281A2 WO 2005013281 A2 WO2005013281 A2 WO 2005013281A2 US 2004022436 W US2004022436 W US 2004022436W WO 2005013281 A2 WO2005013281 A2 WO 2005013281A2
Authority
WO
WIPO (PCT)
Prior art keywords
control gate
voltage
transistor
applying
charge storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/022436
Other languages
English (en)
French (fr)
Other versions
WO2005013281A3 (en
Inventor
Erwin J. Prinz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to JP2006521870A priority Critical patent/JP2007500938A/ja
Publication of WO2005013281A2 publication Critical patent/WO2005013281A2/en
Publication of WO2005013281A3 publication Critical patent/WO2005013281A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/687—Floating-gate IGFETs having more than two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/06—Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals

Definitions

  • the present disclosure relates, in general to memory devices, and more particularly, to a nonvolatile memory device and method of making the same.
  • non- volatile memory single-transistor bi-cells having a dielectric with embedded silicon nanocrystals can be charged with electrons using hot carrier injection (HCI injection), HCI injection with reverse well/source bias, or Fowler-Nordheim (FN) tunneling.
  • HCI injection hot carrier injection
  • FN Fowler-Nordheim
  • the nanocrystals can be discharged with Fowler-Nordheim tunneling through either a top or a bottom dielectric with respect to the nanocrystals.
  • the array architecture considerations of either FN tunneling program/erase or HCI program / FN erase for single- transistor bitcells are also understood.
  • While vertical FN programming is a very low current operation, it results in a long programming time (e.g., on the order of 1-10 msec) and an inefficient bitcell with either two transistors per bitcell or two parallel conductors in a bitline direction.
  • HCI prograrrjrning results in an efficient bitcell and fast programming (e.g., on the order of 1-10 ⁇ sec) at the expense of high programming current (e.g., on the order of 100- 200 ⁇ A).
  • source-side injection in a split-gate bitcell in combination with an oxide-nitride-oxide (ONO) storage layer can be used with either hot hole erase or with erase through the thin top oxide of a SONOS device.
  • hot hole erase results in oxide degradation leading to read disturb
  • thin top oxide erase of an ONO layer results in susceptibility to read disturb for erase times on the order of between 100 msec to 1 sec.
  • Figure 1 is a cross-sectional view of a nonvolatile memory device having a split gate with nanoclusters embedded within a dielectric layer for charge storage according to one embodiment of the present disclosure
  • Figure 2 is a cross-sectional view of a nonvolatile memory device having a split gate with nanoclusters embedded within a dielectric layer and disposed under polysilicon spacers according to another embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a nonvolatile memory device according to another embodiment of the present disclosure.
  • Figure 4 is a cross-sectional view of a nonvolatile memory device including a shallow implant according to another embodiment of the present disclosure.
  • Figure 1 is a cross-sectional view of a nonvolatile memory device 10 having a split gate with nanoclusters embedded within a dielectric layer for charge storage according to one embodiment of the present disclosure.
  • Memory device 10 includes a substrate having a bitcell well 12 of a first conductivity type overlying a deep well 14 of a second conductivity type, opposite the first conductivity type.
  • the first conductivity type includes p-type and the second conductivity type includes n-type dopant.
  • Memory device 10 also includes a select gate transistor 15, the select gate transistor including gate dielectric 16 and gate electrode 18.
  • Memory device 10 further includes a control gate transistor 21, the control gate transistor including at least a first dielectric 22, a layer of nanoclusters 24, a second dielectric 26, and a gate electrode 28.
  • the structure of first dielectric 22, layer of nanoclusters 24, and second dielectric 26 form a charge storage structure, the nanoclusters being used for charge storage.
  • the first dielectric 22 includes a top oxide/nanocluster surface and forms an F/N tunneling dielectric.
  • the second dielectric 26 includes a bottom oxide/nanocluster surface and forms the bottom dielectric.
  • the nanoclusters comprise silicon nanocrystals.
  • the select gate transistor 15 is separated from the control gate transistor 21 by a narrow dielectric 20.
  • Narrow dielectric 20 has a dimension on the order of less than 200 angstroms ( ⁇ 20nm) between the select gate and control gate transistors.
  • Narrow dielectric 20 can include, for example, a narrow oxide sidewall dielectric.
  • Memory device 10 also includes source/drain regions 30 and 32. The various layers and doped regions, as discussed herein, of memory device 10 can be fabricated, respectively, using techniques known in the art.
  • the memory device 10 includes a split gate device in which a layer of nanoclusters is embedded between first and second dielectric layers, wherein the split gate device is utilized for non-volatile charge storage. That is, the split gate device has a control gate transistor with nanoclusters embedded between a bottom and top dielectric, and a select gate transistor with a gate dielectric.
  • the first and second dielectric layers include dielectrics having a thickness on the order of 35-70A.
  • the transistors of the split gate device are separated by a narrow dielectric area, such that source side injection is possible.
  • Table 1 Examples of source side injection with biases as applied to the 1-bit storage cell of memory device 10 are provided in Table 1 and Table 2. That is, Table 1 provides various bitcell operating voltages for carrying out an erase operation performed with Fowler- Nordheim tunneling through the top dielectric 26 of the 1-bit storage cell of memory device 10. In addition, Table 2 provides various bitcell operating voltages for carrying out an erase operation performed with Fowler-Nordheim tunneling through the bottom dielectric 22 of the 1-bit storage cell of memory device 10. Read current flows in the opposite direction to the write current.
  • bitcell operating voltages are as follows.
  • Bitcell well 12 of memory device 10 includes a p-type well at a bitcell well voltage, Npw.
  • Select gate 18 includes a polysilicon select gate, wherein a select gate voltage, Nsg, is applied to the same.
  • Control gate 28 includes a polysilicon control gate, wherein a control gate voltage, Ncg, is applied to the same.
  • Source and drain regions (30, 32) are at respective source/drain voltages, Nsource Ndrain.
  • Ndd represents a positive supply voltage
  • b/c Nt represents the bitcell threshold voltage
  • float represents neither coupled to a voltage or ground.
  • Table 1 Bitcell operating voltages for erase through top oxide for 1-bit storage.
  • Table 2 Bitcell operating voltages for erase through bottom oxide for 1-bit storage.
  • Figure 2 is a cross-sectional view of a nonvolatile memory device 40 having a split gate with nanoclusters embedded within a dielectric layer and disposed under polysilicon spacers according to another embodiment of the present disclosure.
  • the device 40 is built with control gates 52 formed by poly spacers. Accordingly, two bits can be stored, one bit on either side of the select gate 44.
  • a write operation for the device 40 of Figure 2 has a low programming current on the order of approximately 1-10 ⁇ A and a fast programming time on the order of approximately 1-10 ⁇ sec.
  • the erase operation operates on a block of bitcells with low erase current and an erase time on the order of approximately 10-100 msec.
  • the select gate uses a thin gate oxide on the order of approximately 50-100 A oxide, wherein the thin gate oxide is similar to a low voltage transistor oxide.
  • the select gate 44 includes a high voltage oxide with a thickness on the order of approximately 70-90 A. Such a high voltage oxide is similar to an input/output transistor (I/O) oxide.
  • the 90 A-thick oxide is necessary if the bitcell well 12 is biased at +6V or -6N to enable splitting the erase voltages between the bitcell well 12 and a corresponding control gate.
  • the device 40 includes a nanocluster-based memory device having select gate transistor 58; a thin film storage stack consisting of a bottom oxide 46 having a thickness on the order of 50-70 A, a layer of nanoclusters 48 on the order of 20- 25% surface coverage, and a top oxide 50 of a high temperature oxide (HTO) having a thickness on the order of approximately 50 A; and sidewall spacer control gates 52 on both sides of the select gate 44, over the thin film storage (TFS) stack.
  • Top oxide 50 includes HTO since HTO is a deposited oxide and minimizes the number of electron or hole trap sites in the deposited oxide, as compared with a large number of electron or hole trap sites in a low temperature oxide (e.g., TEOS).
  • a low temperature oxide e.g., TEOS
  • the thin film storage stack includes top oxide 50, nanoclusters 48, and bottom oxide 46 in the region disposed below a respective gate electrode 52.
  • memory device 40 is configured for source-side injection prograrnming and for Fowler-Nordheim tunneling erase through the top oxide 50.
  • the various layers and doped regions, as discussed herein, of memory device 40 can be fabricated, respectively, using techniques known in the art.
  • Examples of source side injection with biases as applied to the 2-bit storage cell of memory device 40 are provided in Table 3 and Table 4. That is, table 3 provides various bitcell operating voltages for carrying out an erase operation performed with Fowler- Nordheim tunneling through the top dielectric 50 of the 2-bit storage cell of memory device 40.
  • table 4 provides various bitcell operating voltages for carrying out an erase operation performed with Fowler-Nordheim tunneling through the bottom dielectric 46 of the 2-bit storage cell of memory device 40. Read current flows in the opposite direction to the write current.
  • bitcell operating voltages are as follows.
  • Bitcell well 12 of memory device 10 includes a p-type well at a bitcell well voltage, Npw.
  • Select gate 44 includes a polysilicon select gate, wherein a select gate voltage, Nsg, is applied to the same.
  • Control gates 52 include polysilicon control gates, wherein a first and second control gate voltage, Ncgl, Vcg2, is applied to the same, respectively.
  • Source and drain regions (30, 32) are at respective source/drain voltages, Vsource/Vdrain.
  • Vdd represents a positive supply voltage
  • b/c Vt represents the bitcell threshold voltage
  • Vo represent a programmed threshold voltage in which the nanocrystals are charged with one or more electrons
  • "float" represents neither coupled to a voltage or ground.
  • Table 4 Bitcell operating voltages for erase through bottom oxide for 2-bit storage.
  • FIG. 3 is a schematic diagram of a nonvolatile memory device 70 according to another embodiment of the present disclosure.
  • Memory device 70 includes an array of bit cells arranged in rows and columns, including bit cells according to the various embodiments disclosed herein, indicated by reference numerals 72, 74, 76, and 78, for example.
  • Memory device 70 further includes a row decoder 80, column decoder 82, sense amplifiers 84, and control circuit 88 for controlling row decoder 80 and column decoder 82.
  • Row decoder 80 receives address information via address input 90.
  • Column decoder 82 receives address information via address input 92.
  • Sense amplifiers receive signal information from column decoder 82 and output the amplified information or data out on data output 94.
  • Row decoder 80 decodes address information received on address input 90 and outputs information on appropriate word lines 96, 98.
  • Column decoder 82 decodes address information received on address input 92 and receives information via bit lines 100, 102, 104.
  • the bit cell 72 includes a memory device having a select gate transistor 112 and sidewall transistors 114, 116 disposed on opposite sides of gate transistor 112. Sidewall transistors 114 and 116 include dielectric nanocluster thin film storage memory stacks 118 and 120, respectively.
  • the dielectric nanocluster thin film storage memory stacks 118 and 120 comprise stacks similar to those of Figures 1, 2 or 4.
  • Bit cell 72 further includes source/drain regions 122 and 124 coupled to corresponding bit lines 102 and 104, respectively.
  • bit cell 72 includes a deep well region coupled to a voltage potential V WE L L , as indicated by reference numeral 126.
  • FIG 4 is a cross-sectional view of a nonvolatile memory device 130 including shallow implants (132, 134) according to another embodiment of the present disclosure.
  • shallow implants 132, 134
  • the threshold voltage Vt of a respective spacer device can be below zero volts (0 V), thereby alleviating the need for biasing the control gates during a read operation.
  • the memory device 40 is fabricated with a selectively lower channel doping under a respective spacer device using self-aligned counter doped implants of arsenic (As) or antimony (Sb).
  • the spacer devices have a channel region on the order of approximately 200-1000 angstroms, i.e., short channel device. Accordingly, the threshold voltage of the spacer devices is lowered without degradation of performance characteristics of the short channel spacer devices.
  • the terms "comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
PCT/US2004/022436 2003-07-31 2004-07-13 Nonvolatile memory and method of making same Ceased WO2005013281A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006521870A JP2007500938A (ja) 2003-07-31 2004-07-13 不揮発性メモリおよびその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/631,142 US6816414B1 (en) 2003-07-31 2003-07-31 Nonvolatile memory and method of making same
US10/631,142 2003-07-31

Publications (2)

Publication Number Publication Date
WO2005013281A2 true WO2005013281A2 (en) 2005-02-10
WO2005013281A3 WO2005013281A3 (en) 2005-05-19

Family

ID=33311102

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/022436 Ceased WO2005013281A2 (en) 2003-07-31 2004-07-13 Nonvolatile memory and method of making same

Country Status (6)

Country Link
US (1) US6816414B1 (enExample)
JP (1) JP2007500938A (enExample)
KR (1) KR101039244B1 (enExample)
CN (1) CN1816883A (enExample)
TW (1) TWI360818B (enExample)
WO (1) WO2005013281A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7957190B2 (en) 2008-05-30 2011-06-07 Freescale Semiconductor, Inc. Memory having P-type split gate memory cells and method of operation

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7192876B2 (en) 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
DE10326805B4 (de) * 2003-06-13 2007-02-15 Infineon Technologies Ag Herstellungsverfahren für nichtflüchtige Speicherzellen
US7098502B2 (en) * 2003-11-10 2006-08-29 Freescale Semiconductor, Inc. Transistor having three electrically isolated electrodes and method of formation
US7015535B2 (en) * 2004-05-04 2006-03-21 Oki Electric Industry Co., Ltd. Nonvolatile semiconductor memory device
US7324376B2 (en) * 2004-09-09 2008-01-29 Macronix International Co., Ltd. Method and apparatus for operating nonvolatile memory cells in a series arrangement
US7307888B2 (en) * 2004-09-09 2007-12-11 Macronix International Co., Ltd. Method and apparatus for operating nonvolatile memory in a parallel arrangement
US7327607B2 (en) * 2004-09-09 2008-02-05 Macronix International Co., Ltd. Method and apparatus for operating nonvolatile memory cells in a series arrangement
US7170785B2 (en) * 2004-09-09 2007-01-30 Macronix International Co., Ltd. Method and apparatus for operating a string of charge trapping memory cells
US7518179B2 (en) * 2004-10-08 2009-04-14 Freescale Semiconductor, Inc. Virtual ground memory array and method therefor
US7170128B2 (en) * 2004-12-02 2007-01-30 Atmel Corporation Multi-bit nanocrystal memory
KR100672998B1 (ko) * 2005-02-14 2007-01-24 삼성전자주식회사 불휘발성 메모리 소자, 그 구동 방법 및 형성 방법
US7619270B2 (en) * 2005-07-25 2009-11-17 Freescale Semiconductor, Inc. Electronic device including discontinuous storage elements
US7619275B2 (en) * 2005-07-25 2009-11-17 Freescale Semiconductor, Inc. Process for forming an electronic device including discontinuous storage elements
WO2007014115A1 (en) * 2005-07-25 2007-02-01 Freescale Semiconductor Electronic device including discontinuous storage elements
US7642594B2 (en) * 2005-07-25 2010-01-05 Freescale Semiconductor, Inc Electronic device including gate lines, bit lines, or a combination thereof
US7394686B2 (en) * 2005-07-25 2008-07-01 Freescale Semiconductor, Inc. Programmable structure including discontinuous storage elements and spacer control gates in a trench
US7262997B2 (en) 2005-07-25 2007-08-28 Freescale Semiconductor, Inc. Process for operating an electronic device including a memory array and conductive lines
US7112490B1 (en) * 2005-07-25 2006-09-26 Freescale Semiconductor, Inc. Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench
US7582929B2 (en) * 2005-07-25 2009-09-01 Freescale Semiconductor, Inc Electronic device including discontinuous storage elements
US7446372B2 (en) * 2005-09-01 2008-11-04 Micron Technology, Inc. DRAM tunneling access transistor
US7456465B2 (en) * 2005-09-30 2008-11-25 Freescale Semiconductor, Inc. Split gate memory cell and method therefor
TWI287868B (en) * 2005-11-17 2007-10-01 Ememory Technology Inc Single-poly non-volatile memory device
US20070158734A1 (en) * 2006-01-09 2007-07-12 Freescale Semiconductor, Inc. Electronic device with a multi-gated electrode structure and a process for forming the electronic device
US7341914B2 (en) * 2006-03-15 2008-03-11 Freescale Semiconductor, Inc. Method for forming a non-volatile memory and a peripheral device on a semiconductor substrate
US7700439B2 (en) * 2006-03-15 2010-04-20 Freescale Semiconductor, Inc. Silicided nonvolatile memory and method of making same
US7592224B2 (en) 2006-03-30 2009-09-22 Freescale Semiconductor, Inc Method of fabricating a storage device including decontinuous storage elements within and between trenches
US7656704B2 (en) * 2006-07-20 2010-02-02 Winbond Electronics Corp. Multi-level operation in nitride storage memory cell
US7483299B2 (en) * 2006-08-01 2009-01-27 Macronix International Co., Ltd. Devices and operation methods for reducing second bit effect in memory device
US7667260B2 (en) * 2006-08-09 2010-02-23 Micron Technology, Inc. Nanoscale floating gate and methods of formation
US7524719B2 (en) * 2006-08-31 2009-04-28 Freescale Semiconductor, Inc. Method of making self-aligned split gate memory cell
US7557008B2 (en) * 2007-01-23 2009-07-07 Freescale Semiconductor, Inc. Method of making a non-volatile memory device
US7572699B2 (en) * 2007-01-24 2009-08-11 Freescale Semiconductor, Inc Process of forming an electronic device including fins and discontinuous storage elements
US7838922B2 (en) * 2007-01-24 2010-11-23 Freescale Semiconductor, Inc. Electronic device including trenches and discontinuous storage elements
US7651916B2 (en) 2007-01-24 2010-01-26 Freescale Semiconductor, Inc Electronic device including trenches and discontinuous storage elements and processes of forming and using the same
US7932189B2 (en) * 2007-01-26 2011-04-26 Freescale Semiconductor, Inc. Process of forming an electronic device including a layer of discontinuous storage elements
US7416945B1 (en) * 2007-02-19 2008-08-26 Freescale Semiconductor, Inc. Method for forming a split gate memory device
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US7719039B2 (en) * 2007-09-28 2010-05-18 Freescale Semiconductor, Inc. Phase change memory structures including pillars
US7838363B2 (en) * 2007-10-31 2010-11-23 Freescale Semiconductor, Inc. Method of forming a split gate non-volatile memory cell
US20090251972A1 (en) * 2008-04-03 2009-10-08 Yue-Song He Nonvolatile memory arrays with charge trapping dielectric and with non-dielectric nanodots
US8372699B2 (en) * 2010-02-22 2013-02-12 Freescale Semiconductor, Inc. Method for forming a split-gate memory cell
US8536039B2 (en) * 2010-03-25 2013-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Nano-crystal gate structure for non-volatile memory
US8163615B1 (en) 2011-03-21 2012-04-24 Freescale Semiconductor, Inc. Split-gate non-volatile memory cell having improved overlap tolerance and method therefor
US20140167136A1 (en) * 2012-12-14 2014-06-19 Spansion Llc Charge Trapping Device with Improved Select Gate to Memory Gate Isoloation
US20140357072A1 (en) * 2013-05-31 2014-12-04 Jinmiao J. Shen Methods and structures for split gate memory
KR102345674B1 (ko) * 2015-04-06 2021-12-31 에스케이하이닉스 주식회사 불휘발성 메모리소자 및 그 제조방법과, 불휘발성 메모리 셀어레이
US10325663B1 (en) * 2017-12-29 2019-06-18 Macronix International Co., Ltd. Protecting memory cells from in-process charging effects
CN114335004B (zh) * 2022-03-11 2022-05-17 江苏游隼微电子有限公司 一种1.5t sonos器件及其制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0135239B1 (ko) * 1994-07-28 1998-04-22 김주용 플래쉬 이이피롬 셀 및 그 제조방법
JP3498116B2 (ja) * 1995-10-26 2004-02-16 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
US5740104A (en) * 1997-01-29 1998-04-14 Micron Technology, Inc. Multi-state flash memory cell and method for programming single electron differences
US5801401A (en) * 1997-01-29 1998-09-01 Micron Technology, Inc. Flash memory with microcrystalline silicon carbide film floating gate
US5824584A (en) 1997-06-16 1998-10-20 Motorola, Inc. Method of making and accessing split gate memory device
US5969383A (en) 1997-06-16 1999-10-19 Motorola, Inc. Split-gate memory device and method for accessing the same
KR100488583B1 (ko) * 1997-12-31 2005-12-08 삼성전자주식회사 듀얼비트게이트분리형플래쉬메모리소자및그의구동방법
US6255166B1 (en) 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
JP4058219B2 (ja) * 1999-09-17 2008-03-05 株式会社ルネサステクノロジ 半導体集積回路
JP3820917B2 (ja) * 2000-06-12 2006-09-13 ソニー株式会社 半導体記憶装置およびその動作方法
US6400610B1 (en) * 2000-07-05 2002-06-04 Motorola, Inc. Memory device including isolated storage elements that utilize hole conduction and method therefor
JP4147765B2 (ja) * 2001-06-01 2008-09-10 ソニー株式会社 不揮発性半導体メモリ装置およびその電荷注入方法
JP3622697B2 (ja) * 2001-07-23 2005-02-23 セイコーエプソン株式会社 不揮発性半導体記憶装置
TW546840B (en) * 2001-07-27 2003-08-11 Hitachi Ltd Non-volatile semiconductor memory device
JP2004040064A (ja) * 2002-07-01 2004-02-05 Yutaka Hayashi 不揮発性メモリとその製造方法
US6706599B1 (en) * 2003-03-20 2004-03-16 Motorola, Inc. Multi-bit non-volatile memory device and method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7957190B2 (en) 2008-05-30 2011-06-07 Freescale Semiconductor, Inc. Memory having P-type split gate memory cells and method of operation

Also Published As

Publication number Publication date
JP2007500938A (ja) 2007-01-18
TWI360818B (en) 2012-03-21
KR20060054400A (ko) 2006-05-22
TW200522079A (en) 2005-07-01
WO2005013281A3 (en) 2005-05-19
CN1816883A (zh) 2006-08-09
KR101039244B1 (ko) 2011-06-08
US6816414B1 (en) 2004-11-09

Similar Documents

Publication Publication Date Title
US6816414B1 (en) Nonvolatile memory and method of making same
JP4923321B2 (ja) 不揮発性半導体記憶装置の動作方法
US6949788B2 (en) Nonvolatile semiconductor memory device and method for operating the same
US7348237B2 (en) NOR flash memory cell with high storage density
US7071060B1 (en) EEPROM with split gate source side infection with sidewall spacers
US5379253A (en) High density EEPROM cell array with novel programming scheme and method of manufacture
CN101604706B (zh) 集成电路存储单元及非易失性存储单元
JP5712420B2 (ja) 不揮発性メモリセル、これを有するメモリアレイ、並びに、セル及びアレイの操作方法
US7211878B2 (en) Semiconductor nonvolatile memory, method of recording data in the semiconductor nonvolatile memory and method of reading data from the semiconductor nonvolatile memory
JPH1174389A (ja) スプリット・ゲート・メモリ装置
EP1103980B1 (en) 2-bit/cell type nonvolatile semiconductor memory
CN101179079A (zh) 密集阵列和电荷存储器件及其制造方法
JP2005005513A (ja) 不揮発性半導体メモリ装置およびその読み出し方法
US6801456B1 (en) Method for programming, erasing and reading a flash memory cell
JP4547749B2 (ja) 不揮発性半導体記憶装置
JP4572500B2 (ja) 不揮発性半導体メモリ装置およびその動作方法
US20090184359A1 (en) Split-gate non-volatile memory devices having nitride tunneling layers
JP2004134799A (ja) 単一ビット不揮発性メモリーセル、および、その書き込み方法および消去方法
US7184316B2 (en) Non-volatile memory cell array having common drain lines and method of operating the same
US7652320B2 (en) Non-volatile memory device having improved band-to-band tunneling induced hot electron injection efficiency and manufacturing method thereof
JP2004214506A (ja) 不揮発性半導体メモリ装置の動作方法
US20060226467A1 (en) P-channel charge trapping memory device with sub-gate
EP1870904B1 (en) Operating method of non-volatile memory device
US7061046B2 (en) Non-volatile semiconductor memory device
JPH065873A (ja) 不揮発性半導体記憶装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200480019272.0

Country of ref document: CN

AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2006521870

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1020067002156

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020067002156

Country of ref document: KR

122 Ep: pct application non-entry in european phase