WO2005008893A8 - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
WO2005008893A8
WO2005008893A8 PCT/JP2003/009030 JP0309030W WO2005008893A8 WO 2005008893 A8 WO2005008893 A8 WO 2005008893A8 JP 0309030 W JP0309030 W JP 0309030W WO 2005008893 A8 WO2005008893 A8 WO 2005008893A8
Authority
WO
WIPO (PCT)
Prior art keywords
memory block
terminals
integrated circuit
semiconductor integrated
data
Prior art date
Application number
PCT/JP2003/009030
Other languages
English (en)
French (fr)
Other versions
WO2005008893A1 (ja
Inventor
Masayuki Sato
Original Assignee
Innotech Corp
Masayuki Sato
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innotech Corp, Masayuki Sato filed Critical Innotech Corp
Priority to AU2003248073A priority Critical patent/AU2003248073A1/en
Priority to JP2005504364A priority patent/JP4334541B2/ja
Priority to PCT/JP2003/009030 priority patent/WO2005008893A1/ja
Publication of WO2005008893A1 publication Critical patent/WO2005008893A1/ja
Publication of WO2005008893A8 publication Critical patent/WO2005008893A8/ja

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

本半導体集積回路は、複数個のメモリブロック（１１）から構成されている。各メモリブロック（１１）は、四辺（１２ａ～１２ｄ）で囲まれ、各辺（１２ａ～１２ｄ）毎にアドレス入力端子（Ａ０～Ａ１１）およびデータ入出力端子（Ｄ０～Ｄ１１）が設けられている。隣接する２つのメモリブロック（１１）を第１および第２のメモリブロック（１１）とすると、第１のメモリブロック（１１）の辺（１２ａ）に設けられたアドレス入力端子（Ａ０～Ａ２）が、第２のメモリブロック（１１）の対向する辺のデータ入出力端子（Ｄ８～Ｄ６）にそれぞれ接続されている。第１のメモリブロック（１１）の辺（１２ａ）に設けられたデータ入出力端子（Ｄ０～Ｄ２）は、第２のメモリブロック（１１）の対向する辺のアドレス入力端子（Ａ８～Ａ６）にそれぞれ接続されている。各メモリブロック（１１）は、フレキシブルな可変論理セルを構成する。これらの可変論理セルによって所望の論理回路が形成される。
PCT/JP2003/009030 2003-07-16 2003-07-16 半導体集積回路 WO2005008893A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003248073A AU2003248073A1 (en) 2003-07-16 2003-07-16 Semiconductor integrated circuit
JP2005504364A JP4334541B2 (ja) 2003-07-16 2003-07-16 半導体集積回路
PCT/JP2003/009030 WO2005008893A1 (ja) 2003-07-16 2003-07-16 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/009030 WO2005008893A1 (ja) 2003-07-16 2003-07-16 半導体集積回路

Publications (2)

Publication Number Publication Date
WO2005008893A1 WO2005008893A1 (ja) 2005-01-27
WO2005008893A8 true WO2005008893A8 (ja) 2007-06-21

Family

ID=34074100

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2003/009030 WO2005008893A1 (ja) 2003-07-16 2003-07-16 半導体集積回路

Country Status (3)

Country Link
JP (1) JP4334541B2 (ja)
AU (1) AU2003248073A1 (ja)
WO (1) WO2005008893A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100883352B1 (ko) 2006-11-21 2009-02-11 한국전자통신연구원 원격대화에서 감정 및 의사의 표현 방법과 이를 위한 리얼이모티콘 시스템
US9379713B2 (en) * 2014-01-17 2016-06-28 Semiconductor Energy Laboratory Co., Ltd. Data processing device and driving method thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06276086A (ja) * 1993-03-18 1994-09-30 Fuji Xerox Co Ltd フィールドプログラマブルゲートアレイ
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
JP3471628B2 (ja) * 1998-05-12 2003-12-02 日本電信電話株式会社 書き換え可能な論理回路およびラッチ回路
JP3471623B2 (ja) * 1998-07-31 2003-12-02 日本電信電話株式会社 書き換え可能な論理回路
WO2000052753A1 (fr) * 1999-03-04 2000-09-08 Hitachi, Ltd. Circuit integre a semiconducteur, et procede de conception de circuits integres logiques comprenant ledit circuit
JP3517839B2 (ja) * 2000-11-29 2004-04-12 日本電信電話株式会社 プログラマブルセルアレイ回路
JP3665962B2 (ja) * 2000-12-20 2005-06-29 日本電信電話株式会社 プログラマブル論理セルアレイ回路及びその初期化方法
JP2003149300A (ja) * 2001-11-16 2003-05-21 Hitachi Ltd テスト方法および半導体装置
JP2003224468A (ja) * 2002-01-31 2003-08-08 Hitachi Ltd 半導体集積回路および製造方法並びにテスト方法

Also Published As

Publication number Publication date
WO2005008893A1 (ja) 2005-01-27
AU2003248073A8 (en) 2005-02-04
JPWO2005008893A1 (ja) 2006-09-07
JP4334541B2 (ja) 2009-09-30
AU2003248073A1 (en) 2005-02-04

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