WO2000052753A1 - Circuit integre a semiconducteur, et procede de conception de circuits integres logiques comprenant ledit circuit - Google Patents

Circuit integre a semiconducteur, et procede de conception de circuits integres logiques comprenant ledit circuit Download PDF

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Publication number
WO2000052753A1
WO2000052753A1 PCT/JP1999/001035 JP9901035W WO0052753A1 WO 2000052753 A1 WO2000052753 A1 WO 2000052753A1 JP 9901035 W JP9901035 W JP 9901035W WO 0052753 A1 WO0052753 A1 WO 0052753A1
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Prior art keywords
circuit
data
integrated circuit
signal
logic
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PCT/JP1999/001035
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English (en)
Japanese (ja)
Inventor
Masayuki Satoh
Takayuki Oshima
Isao Shimizu
Hideaki Takahashi
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Hitachi, Ltd.
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Publication date
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Priority to PCT/JP1999/001035 priority Critical patent/WO2000052753A1/fr
Publication of WO2000052753A1 publication Critical patent/WO2000052753A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Definitions

  • the present invention relates to a technology that is effective when used for designing a semiconductor integrated circuit and also for constructing a logic integrated circuit.
  • the design data described in the HDL is converted into a design data at the logic gate level by a program called a logic synthesis tool.
  • a logic synthesis tool is also provided by several EDA vendors.
  • the generated logic gate-level design data is again verified by test vectors.
  • the defect detection rate at this time is, for example, 95% or more. Failure due to verification If found, correct the design data at the logic gate level.
  • the layout and data at the element level are generated by a program called an automatic layout 'tool.
  • These automated layout tools are also provided by several EDA vendors.
  • the generated layout data is subjected to an actual load simulation by means of a test vector, including wiring delays, etc., and inappropriate parts are corrected and optimized.
  • a mask pattern data is generated by a network based on the generated layout data, and a mask is created based on the data.
  • a logic integrated circuit is formed on the semiconductor wafer by the previous process, and the wafer is cut into chips, sealed with a sealing material such as resin, and assembled into a package.
  • a sealing material such as resin
  • An object of the present invention is to provide a logic integrated circuit design method capable of greatly reducing the number of design steps and the development period.
  • Another object of the present invention is to provide a logic integrated circuit whose function can be easily changed as required.
  • Still another object of the present invention is to provide a logic integrated circuit capable of forming a normal function by substituting a defective part of a completed product even if the element has a defect.
  • a self-configuration circuit that is a semiconductor integrated circuit capable of configuring arbitrary logic
  • a design circuit at a functional level described in a language such as HDL is decoded by a control circuit, and the self-configuration is performed.
  • a logic integrated circuit having a desired logic function is configured.
  • the self-configuring circuit includes a memory circuit capable of reading and writing, a comparator circuit for comparing data written in the memory circuit with data read from the memory circuit, A variable address conversion circuit for converting the input address signal into a logic circuit having a desired logic function as an address signal to the memory circuit. Data is written to the memory circuit so that the read data of the logical circuit becomes an output signal expected for the input signal of the logic circuit.
  • the HDL language has a structure similar to that of an existing general programming language, and software that performs logic synthesis based on functional level design data written in the HDL language, that is, HDL description statements, and logic synthesis Since the software that converts design data into logic gate-level design data has already been developed, it generates a signal that determines the logical configuration of the self-configuring circuit based on the function-level design data. Such a control circuit can be fully realized using current technology.
  • the logic since the logic is configured using a self-configuring circuit having a memory circuit capable of reading and writing, the logic function can be changed by rewriting the memory circuit. Thus, it is possible to realize a logic integrated circuit whose functions can be easily changed according to the conditions.
  • the self-configuring circuit includes a comparison circuit that compares data written in the memory circuit with data read from the memory circuit, and a variable address conversion circuit.
  • the conversion address of the variable address conversion circuit can be constructed. If the memory circuit includes a defective part, the logic can be configured using only the normal area while avoiding the defective part. It can be avoided automatically and a normal function can be configured.
  • the control circuit that decodes the design data at the function level may be configured as a semiconductor integrated circuit different from the self-configured circuit, or may be configured as a self-configured circuit. It may be configured integrally on one semiconductor chip. When the control circuit for decoding the design data at the function level and the self-configuration circuit are integrated, a storage for storing the design data at the function level may be provided integrally.
  • a part of the memory circuit constituting the self-configuring circuit may be a storage region for storing the design data of the functional level.
  • the design data at the functional level described in the HDL language is about one tenth less than the design data at the logic gate level, so that It can be sufficiently stored in the memory circuit formed in the device.
  • the self-constituting circuit includes a memory circuit capable of reading and writing, and a memory written in the memory circuit.
  • a comparison circuit that compares data read from the memory circuit and an address conversion circuit that converts an address signal supplied to the memory circuit based on a comparison result in the comparison circuit
  • a comparison circuit that reads data from the memory circuit
  • a switch matrix circuit for switching the data stored in the storage circuit to an address signal input to the address conversion circuit. It is good to do. This makes it possible to configure a sequential circuit including a latch circuit such as a flip-flop.
  • the memory circuits that can be read and written in the self-configuration circuit include DRAM (dynamic random access memory) or SRAM (static random access memory).
  • a volatile memory e.g., memory
  • EEPROM electrically writable and erasable non-volatile storage device
  • FIG. 1 is a flowchart showing a procedure for developing a logic integrated circuit to which the present invention is applied.
  • FIG. 2 is a block diagram showing a first embodiment of a self-configuring circuit which enables the design method according to the present invention.
  • FIG. 3 is a block diagram showing a specific example of a variable address conversion circuit included in the self-configuration circuit of the first embodiment.
  • FIG. 4 is a logical configuration diagram showing a specific example of the comparison circuit included in the self-configuration circuit of the first embodiment.
  • FIG. 5 is a flowchart showing how to change the conversion address in the self-configuration circuit of the first embodiment.
  • FIG. 6 is an explanatory diagram showing an example of a logic gate circuit constituted by the self-configuration circuit of the first embodiment and its HDL description.
  • FIG. 7 is a block diagram illustrating an example of a system that configures a logic circuit having a desired logic function according to the HDL description using the self-configuration circuit according to the first embodiment.
  • FIG. 8 is a block diagram showing a second embodiment of the self-configuring circuit which enables the design method according to the present invention.
  • FIG. 9 is a circuit configuration diagram showing a specific example of a variable switch circuit included in the self-configuration circuit of the second embodiment.
  • FIG. 10 is a logical configuration diagram showing a specific example of a data storage circuit included in the self-configuration circuit of the second embodiment.
  • FIG. 11 is an explanatory diagram illustrating a flip-flop circuit as an example of a logic circuit including the self-configuration circuit according to the second embodiment and an HDL description thereof.
  • FIG. 12 is a flowchart illustrating an outline of a processing procedure in the control device when a desired logic circuit is configured using the self-configuration circuit according to the embodiment.
  • FIG. 13 is a block diagram showing a third embodiment of the self-configuring circuit which enables the design method according to the present invention.
  • FIG. 14 is a block diagram showing a fourth embodiment of the self-configuring circuit which enables the design method according to the present invention.
  • FIG. 15 is a flowchart showing a procedure for developing a conventional logic integrated circuit. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a flowchart showing a procedure for developing a logic integrated circuit to which the present invention is applied.
  • Step S describe the designed function in a language such as HDL (Step S 1).
  • step S3 the data is stored as a data file in a storage device such as a hard disk (step S3).
  • a storage device such as a hard disk
  • step S4 the operation of the design data described in the HDL is verified by a verification program called a test vector as to whether the operation is appropriate (step S4). If a defect is found by verification, the design data described in HDL is corrected. After that, the logic function described in the HDL is configured using a self-configuration circuit formed as a semiconductor integrated circuit (step S5). By the above procedure, a logic integrated circuit having a desired function is obtained, so that the development period is greatly reduced.
  • FIG. 2 shows a block diagram of a first embodiment of a self-constituting circuit that enables the design method according to the present invention according to the flowchart of FIG.
  • Each circuit block shown in FIG. 2 is formed on one semiconductor chip such as single crystal silicon by a known semiconductor manufacturing technique.
  • reference numeral 10 denotes a readable and writable memory circuit having substantially the same configuration as a known general-purpose DRAM (dynamic random access memory) or SRAM (static random access memory). It is.
  • a plurality of memory cells are arranged in a matrix, a plurality of read lines and a plurality of data lines are arranged in a lattice, and the memory cells in the same row correspond to each other.
  • the memory cells in the same column are connected to the corresponding memory array 11 and the corresponding memory cells in the memory array 11 by decoding the supplied address signal.
  • An address decoder 12 that sets one word line to the selected level, and a sense amplifier circuit 13 that amplifies the potential read from the memory cell connected to the selected word line to the data line
  • a write / read control circuit 14 for controlling the operation timing of the sense amplifier circuit 13 and the like based on the chip select signal CE and the write control signal WE.
  • the self-constituting circuit of this embodiment takes in a write data input from outside the chip and transfers it to the sense amplifier circuit 13 or read from the memory circuit 10.
  • An input / output & comparison circuit 20 that outputs data to the outside of the chip, compares read data with data input from outside the chip, and inputs / outputs an address signal input from outside the chip.
  • the variable address conversion circuit 30 converts the data according to the comparison result in the power & comparison circuit 20 and supplies the converted address to the address / decoder 12.
  • 41 is an address input terminal to which an address signal from the outside of the chip is input
  • 42 is a data input / output terminal to output read data from the memory circuit to the outside or to input write data from the outside.
  • FIG. 3 is a block diagram showing a specific example of the variable address conversion circuit 30 included in the self-configuration circuit of the embodiment shown in FIG.
  • the variable address circuit 30 has substantially the same circuit configuration as the memory circuit 10 of FIG.
  • variable address circuit 30 includes a plurality of memory cells arranged in a matrix, a plurality of word lines and a plurality of data lines arranged in a lattice, and the memory cells in the same row
  • the memory cells in the same column connected to the corresponding power supply line and the memory array 31 connected to the corresponding data line and the memory cell supplied to the input terminal 41 from the outside.
  • An address decoder 32 that decodes a dress signal to set one corresponding read line in the memory array 31 to a selected level, and a decode line from a memory cell connected to the selected read line.
  • a write control circuit for controlling the operation timing of the sense amplifier circuit 33 based on the comparison result signal CM from the input / output & comparison circuit 20. Composed of 3 4 etc. To have.
  • the address decoder 32 includes a decoding circuit and an incrementer or an arithmetic unit that increments the decoded address based on the comparison result signal CM.
  • the increment value may be stored in the memory 31 to reduce the storage capacity of the memory 31.
  • FIG. 4 shows a specific example of the input / output & comparison circuit 20 included in the self-configuration circuit of the first embodiment.
  • the input / output & comparison circuit 20 is connected to the signal line 51 connected to the output terminal of the sense amplifier circuit 13 and the data input / output terminal 42.
  • the switch means 21 provided between the read signal line 52 and the read / write control circuit 14 and controlled by the comparison instruction signal CC, and the read signal from the sense amplifier circuit 33
  • a NAND gate circuit 22 which receives the comparison instruction signal CC supplied from the write / read control circuit 14 as an input signal, an output signal of the NAND gate circuit 22 and the data input / output terminal 4 2 It is composed of an exclusive OR gate circuit 23 that receives signals and an OR gate circuit 24 that receives output signals of a plurality of exclusive OR gate circuits 23 as inputs.
  • a comparison circuit comprising the switch means 21, NAND gate circuit 22, and exclusive OR gate circuit 23 is provided for each data input / output terminal 42, and the exclusive OR gate of each comparison circuit is provided.
  • the output signal of the circuit 23 is input to the OR gate circuit 24, and the output signal of the OR gate circuit 24 is supplied to the variable address circuit 30 as a comparison result signal CM.
  • an input buffer and an output buffer commonly connected to the data input / output terminal 42 may be provided on the signal line 52 side.
  • variable address translation circuit 30 stores each address in the memory array 31 in each address of the memory array 31 by initial setting processing or the like. The corresponding address is stored.
  • the address decoder 32 of the variable address circuit 30 decodes the address signal and sets the corresponding read line in the memory array 31 to the selection level.
  • the previously stored address data is output, that is, the address conversion is performed (step S11).
  • the read address data is amplified by the sense amplifier 33 and supplied to the address decoder 12 of the memory circuit 10.
  • a dress The decoder 12 decodes the supplied address to set the corresponding word line in the memory array 11 to the selected level, and at that time, the data input from the outside via the input / output & comparison circuit 20. Write to the selected memory cell (step S12).
  • step S13 reading of the write data is performed from the memory array 11 (step S13).
  • the read data is amplified by the sense amplifier 13 and supplied to the input / output & comparison circuit 20.
  • the write data input at the time of data writing is input to the data input / output terminal 41.
  • the input / output & comparison circuit 20 compares the data read from the memory array 11 with the write data input to the data input / output terminal 41, and indicates a comparison result indicating a match or mismatch.
  • the signal CM is output to the write control circuit 34 of the variable address conversion circuit 30.
  • the write control circuit 34 checks the comparison result signal CM to determine whether or not the writing has been normally performed (step S14). If the write control circuit 34 determines that the write has failed, it sends a signal to the address decoder 32 to operate the internal increment and increment the input address signal (step S15). Then, the incremented address is supplied to the address decoder 12 to be decoded, and the next read line in the memory array 11 is set to the selected level. Then, the process returns to step S12, and data input from the outside via the input / output & comparison circuit 20 is written to the selected memory cell connected to the word line.
  • the write data is read from the memory array 11 again, and the input / output and comparison circuit 20 compares the read data with the data externally input to the data input / output terminal 42. Then, when they match, the write control circuit 34 outputs a write end signal WF to the outside, and the data write operation for one address ends (step S16). Upon receiving the write end signal WF, the external control circuit generates the next address signal and outputs the address signal to the address input terminal. 4 Enter in 1. In response, the write control flow of FIG. 5 is started again from step S1, and the write processing for the next address is executed.
  • the data to be written is read and written after the data is written, and if there is an error, the address is updated and the data is written to the next address position.
  • the address is automatically skipped and data is written to the next address. Therefore, in the self-configuration circuit of this embodiment, not only all the memory cells in the memory array 11 need not be normal, but also it is necessary to test the memory array in advance for any defective bits. It has the advantage that there is no.
  • the output signal line of the sense amplifier 33 of the variable address conversion circuit 30 in FIG. It is configured to be able to supply not only to the address decoder 12 of the memory circuit 10 but also to the input / output & comparison circuit 20. Then, in the same manner as described above, the normality / abnormality of the write data to the memory array 31 is determined, and if abnormal, the address is skipped. As a result, regarding the memory array 31 as well, not only all the memory cells need not be normal, but also it is not necessary to test the memory array for a defective bit in advance.
  • FIG. 6 shows an example of a logic gate circuit constituted by the self-configuration circuit of the first embodiment and an HDL description thereof.
  • FIG. 7 shows an example of a system that configures a logic circuit having a desired logic function according to the HDL description using the self-configuration circuit of the first embodiment.
  • 100 is the self-configuration circuit of the above embodiment
  • 200 is a storage device (file) storing design data described in HDL as shown in FIG. 6,
  • 300 is the storage device (file). Decodes the HDL description stored in the file and forms a signal to configure the corresponding logic function in the self-configuration circuit 100
  • This is a control device that outputs data.
  • the control device 300 can be configured using, for example, a general-purpose microphone computer.
  • the control device 300 decodes the HDL description and recognizes that the configuration target is a NAND gate circuit. For example, the control device 300 uses the truth table of Table 1 below as an address signal to be supplied to the self-configuration circuit 100. A combination "0, 0", “1, 0", “0, 1,...,” 1, 1 "of the indicated input signals In0, In1 is generated.
  • the generated address signal is applied to the address input terminal 41 (see FIG. 2) of the self-configuration circuit 100.
  • the control device 300 generates a data corresponding to the output Out 0 of the truth table as a write data corresponding to each of the above addresses, and sends the write data to the self-configuration circuit 100.
  • data is written to the memory circuit 10 according to the procedure described with reference to the flowchart of FIG.
  • the input address signal may be two bits. Therefore, the address' decoder 32 shown in FIG. 3 is divided into, for example, two bits, so that one read line in the memory array 31 can be selected with only two bits. Good.
  • FIG. 8 is a block diagram showing a second embodiment of the self-configuring circuit which enables the design method according to the present invention.
  • This embodiment is obtained by adding a data storage 60 and a switch matrix 70 as a variable switch circuit to the self-configuration circuit of the first embodiment shown in FIG.
  • the data storage 60 is the data input from the data input / output terminal 42 or the data read from the memory circuit 10. This circuit is provided between the input / output & comparison circuit 20 and the data input / output terminal 42.
  • the switch matrix 70 is a circuit for supplying the data held in the data storage 60 to the variable address conversion circuit 30 in place of the input address signal.
  • the address input terminal 41 And the variable address conversion circuit 30 is a circuit for supplying the data held in the data storage 60 to the variable address conversion circuit 30 in place of the input address signal.
  • the memory circuit 10, the input / output & comparison circuit 20, and the variable address conversion circuit 30 other than the data storage 60 and the switch matrix 70 have exactly the same configuration as that of the first embodiment.
  • FIG. 9 is a circuit configuration diagram showing a specific example of the switch matrix 70 included in the self-configuration circuit (FIG. 8) of the second embodiment.
  • the switch matrix 70 has a plurality of signal lines 71 on which address signals input to the address input terminals 41 and the output of the data storage 60 are provided.
  • the signal lines 72 on which signals are carried are arranged in a grid pattern so as to cross each other, and a switching circuit 73 is arranged at each intersection of the signal lines 71 and 72.
  • a RAM 74 for storing control information of each switch circuit 73 is provided.
  • the switching circuit 73 switches the address signal or data storage input from the address input terminal 41.
  • switch elements SW 1 and SW 2 which are a pair of MOS FETs that are turned on and off complementarily to select and output the 60 output signal.
  • the gate terminals of the switch elements SW 1 and SW 2 are connected to the RAM terminals.
  • FIG. 10 is a logical configuration diagram showing a specific example of the data storage circuit 60 included in the self-configuration circuit (FIG. 8) of the second embodiment.
  • the data storage circuit 60 includes a flip-flop FF provided for each two data lines of the memory array 11 in the memory circuit 10. 1, FF2, FFn, and AND gates G1, G2,... Gn for forming a latch clock for each flip-flop.
  • each flip-flop F Fi one signal (d i) of a pair of data lines is input to a data input terminal D.
  • the other signal (A i) of the pair of data lines is input to the AND gate G i together with the system clock signal CLK.
  • the output signal of the AND gate G i is input to the clock terminal ck of the corresponding flip-flop FF i, and the input signal to the data terminal D is synchronized with the falling or rising of the signal to the clock terminal ck. It is configured to be taken in the flip-flop FFi.
  • the signal Ai when the signal A i is at the low level, the output of the AND gate G i is fixed at the low level, so that even when the system clock CLK changes, the corresponding flip-flop FF i is latched. No action is taken. That is, in this embodiment, the signal Ai is used as a signal (hereinafter, referred to as an active bit) for controlling whether or not data is taken into the flip-flop FFi.
  • the self-configuration circuit in FIG. 8 uses the data storage 60 having the above-described operating characteristics to select data read from the memory circuit 10 according to a certain input state. Then, by supplying this to the variable address conversion circuit 30 via the switch matrix 70, the next input state can be controlled by the previous output data. That is, by this, the order A circuit can be configured.
  • FIG. 11 shows an example of a flip-flop circuit as an example of a logic circuit constituted by the self-configuration circuit of the second embodiment shown in FIG. 8 and its HDL description. ing.
  • each output terminal of two NAND gate circuits G11 and G12 is connected to one input terminal of the other NAND gate circuit.
  • the truth table representing the output signal states corresponding to the input signals of the two NAND gate circuits G 11 and G 12 constituting the flip-flop circuit is as shown in Table 2 below.
  • Al and A2 are the above-mentioned active bits stored in the memory circuit 10 corresponding to the input. Only when this active bit is "1", the output value of the flip-flop is the truth of the corresponding NAND gate. Outputs value data.
  • a flip-flop circuit as shown in FIG. 11 When a flip-flop circuit as shown in FIG. 11 is configured using the self-configuration circuit of FIG. 8, first, four input signals InO, Inl, In2, In3 Can be input from the address input terminal 41 through the switch matrix 70. Input to the variable address conversion circuit 30 and the output data d 1, A 1, d 2, and A 2 of the truth table in Table 2 corresponding to the combination of those input signals are input from the data input / output terminal 42 I do. As a result, the output data of the truth table d 1, A 1, d 2 and A 2 are written. As in the first embodiment, when writing is completed, reading is performed to determine whether or not writing has been performed normally, and in the case of a writing error, the address is updated and writing is performed at another address.
  • a state is set for a predetermined flip-flop (for example, FF1, FF2) in the storage 60.
  • FF1, FF2 a predetermined flip-flop
  • the input signals In 2 and In 3 are fixed to “0”, respectively, and attention is paid to the NAND gate circuit Gl 1, and the input signals In 0 and In 1 are flip-flop FF Set to "0, 0", “1, 0", "0, 1” or "1, 1" according to the data you want to keep at 1 and input from the address input terminal 41.
  • the input signals Ino and Inl are fixed at “0", respectively, and the input signals In2 and In3 are held in the flip-flop FF2 while focusing on the NAND gate circuit G12.
  • the N AND gate circuit G "1" is read out as the active bit A2 corresponding to 2. Therefore, the clock CLK is supplied to the flip-flop FF2 through the AND gate G2 of the data storage 60.
  • the flip-flop consisting of two NAND gates as shown in Fig. 11 has its output ⁇ ut 0, 0 because its output signal is fed back to one input terminal of the other NAND gate. ut 1 cannot be "0" at the same time. Therefore, when setting the states of the flip-flops FF1 and FF2 of the data storage 60, it is necessary to take care that neither of the holding states becomes "0".
  • the control information RAM 74 in the switch matrix circuit 70 is surrounded by a dotted line in FIG. 9 (A). Rewrite the storage data of the memory cells corresponding to the switches CSW31 and CSW22, and switch those switches from the address input terminal 41 to the output terminal of the data storage 60. As a result, the input signals I n1 and I n2 of the flip-flop in FIG. 11 are not permitted to be input, and the outputs Out 0 and Out 1 of the NAND gates Gll and G12 are input instead.
  • a signal (address) is supplied to the variable address conversion circuit 30 at the next stage. In other words, this forms a flip-flop feedback loop.
  • a system that configures a logic circuit having a desired logic function according to the HDL description using the self-configuration circuit of the second embodiment of FIG. 8 uses the self-configuration circuit of the first embodiment shown in FIG.
  • the system shown in Figure 7 It may be the same as In other words, the control device 300, which is configured separately from the self-configuration circuit, decodes the HDL description read from the file in which the HDL-described design data is stored, and assigns the corresponding logic function to the self-configuration circuit 1. Form and output a signal to be configured in 0 0.
  • the control device 300 decodes the HDL description and recognizes that the configuration target is a flip-flop circuit. For example, the control device 300 uses the truth of Table 2 below as an address signal to be supplied to the self-configuration circuit 100. Combination of input signals InO, In1, In2, In3 shown in the value table
  • the generated address signal is applied to the address input terminal 41 of the self-configuration circuit 100.
  • the controller 300 writes the active bits and the data A 1 and A 2 corresponding to the data d 1 and d 2 of the truth table and the data corresponding to the above-mentioned addresses. It is generated as data and applied to the data input / output terminal 42 in parallel with the input of the address signal to the self-configuration circuit 100 in time.
  • FIG. 12 shows an outline of a control procedure of the control device 300 constituting a desired logic circuit.
  • the control device 300 first decodes the HDL description (step S21), and extracts a combinational circuit and a sequential circuit constituting a logic circuit from the HDL description (step S22). Next, a truth table for the extracted combinational circuit or sequential circuit, that is, a truth value database is generated (step S23). Then, using the generated truth value data, the data writing to the memory circuit 10 of the self-configuration circuit 100 and the setting of the variable address conversion circuit 30 are performed according to the flowchart of FIG. (Step S24).
  • control device 300 decodes the HDL description and, when judging that the extracted logic circuit is a sequential circuit, extracts circuit connection information of the focused sequential circuit (step S25) .
  • control information to be stored in the control information RAM 74 of the switch matrix circuit 70 is generated and written using the extracted circuit connection information (step S26).
  • FIG. 13 shows a third embodiment of a self-configuring circuit which enables the design method according to the present invention.
  • a plurality of self-configuration circuits 100 as shown in FIG. 8 are arranged in a matrix on one semiconductor chip, and a horizontal wiring is provided between the self-configuration circuits.
  • a region 110 and a vertical wiring region 120 are provided, and a switcher for selectively connecting a signal line is provided at an intersection of the horizontal wiring region 110 and the vertical wiring region 120.
  • a trick circuit 130 is provided.
  • the address input terminal of each self-configuration A switch matrix circuit 140 for selectively coupling to the signal lines of the wiring area 120 and the data input / output terminals of each self-constituting circuit 100 are connected to the signal lines of the horizontal wiring area 110.
  • a switch matrix circuit 150 for selective coupling to the circuit.
  • FIG. 14 shows a fourth embodiment of the self-configuration circuit which enables the design method according to the present invention.
  • an HDL storage that stores design data of an HDL description as shown in FIG. 7 together with a self-configuration circuit 100 ′ shown in FIGS. 2, 8 and 13.
  • an HDL controller 300 ′ that decodes the HDL description and forms and outputs a signal for configuring the corresponding logical function using the self-configuration circuit 100.
  • the HDL controller 300 ′ that decodes the HDL sentence has a configuration similar to, for example, a CPU of a micro-program control method, that is, a memory (microphone) that stores a microprogram that describes a procedure for processing each HDL language. And a control circuit for controlling the read sequence of the memory, a decoder circuit for decoding the read microphone command and forming a control signal, and the like. Since the HDL language is not enormous and its grammar is relatively simple, it is possible to implement it on a single semiconductor chip using current semiconductor integrated circuit technology.
  • FIG. 14 shows that the memory circuit 10 mainly including the memory array and the variable address conversion circuit 30 are arranged in one memory space.
  • the memory array 11 forming the memory circuit 10 and the memory array 31 forming the variable address conversion circuit 30 may be arranged in separate areas in the same memory array.
  • a Dress '' Decor Dashes 12, 32, a comparison circuit 14, a storage device 60, a switch matrix 70, etc. are collectively shown as an addressing circuit. Since the storage 60 described in the embodiment of FIG. 8 is also a kind of memory, this is also based on the same idea as above, and the memory array 11 and the variable address
  • the conversion circuit 30 and the memory array 31 may be arranged in a separate area in one memory array.
  • the HDL storage that stores the design data of the HDL description can also be configured to be arranged in a separate area in one memory array together with the memory array 11 that constitutes the memory circuit 10. It is.
  • the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof.
  • the logical gate circuit to be configured is not limited to the NAND gate, but may be a NOR gate, an AND gate, an OR gate, or the like.
  • the flip-flop circuit to be configured is not limited to the one including only two NAND gates as shown in FIG. 11, but may be an RS flip-flop having a reset terminal and a reset terminal.
  • the invention made by the present inventor has been mainly described by taking, as an example, a method of designing a logic integrated circuit, which is a field of application as a background, but the present invention is not limited thereto.
  • it can be used for the development of a semiconductor integrated circuit in which a logic circuit and an analog circuit are mixed on one semiconductor chip.

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Abstract

Lors de l'utilisation d'un circuit intégré à semiconducteur auto-constitutif pouvant constituer une logique arbitraire, une unité ou un circuit de commande interprète les données de conception du niveau de fonction décrit dans un langage, par exemple HDL, et un signal permettant de déterminer la structure logique du circuit auto-constitutif provenant de l'unité de commande est introduit dans le circuit auto-constitutif de manière à constituer un circuit intégré logique doté d'une fonction logique voulue.
PCT/JP1999/001035 1999-03-04 1999-03-04 Circuit integre a semiconducteur, et procede de conception de circuits integres logiques comprenant ledit circuit WO2000052753A1 (fr)

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PCT/JP1999/001035 WO2000052753A1 (fr) 1999-03-04 1999-03-04 Circuit integre a semiconducteur, et procede de conception de circuits integres logiques comprenant ledit circuit

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PCT/JP1999/001035 WO2000052753A1 (fr) 1999-03-04 1999-03-04 Circuit integre a semiconducteur, et procede de conception de circuits integres logiques comprenant ledit circuit

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WO2000052753A1 true WO2000052753A1 (fr) 2000-09-08

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005008893A1 (fr) * 2003-07-16 2005-01-27 Innotech Corporation Circuit integre semiconducteur
WO2009001426A1 (fr) * 2007-06-25 2008-12-31 Taiyo Yuden Co., Ltd. Dispositif semi-conducteur

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPH07152794A (ja) * 1993-11-29 1995-06-16 Nec Corp 論理シミュレータ
JPH08115357A (ja) * 1994-10-19 1996-05-07 Fujitsu Ltd ネットリストのハードウェア言語への変換方法及び装置
JPH09237283A (ja) * 1996-02-29 1997-09-09 Ricoh Co Ltd Ｌｓｉ機能設計支援装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07152794A (ja) * 1993-11-29 1995-06-16 Nec Corp 論理シミュレータ
JPH08115357A (ja) * 1994-10-19 1996-05-07 Fujitsu Ltd ネットリストのハードウェア言語への変換方法及び装置
JPH09237283A (ja) * 1996-02-29 1997-09-09 Ricoh Co Ltd Ｌｓｉ機能設計支援装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005008893A1 (fr) * 2003-07-16 2005-01-27 Innotech Corporation Circuit integre semiconducteur
WO2009001426A1 (fr) * 2007-06-25 2008-12-31 Taiyo Yuden Co., Ltd. Dispositif semi-conducteur
US8050132B2 (en) 2007-06-25 2011-11-01 Taiyo Yuden Co., Ltd. Semiconductor device
JP5081240B2 (ja) * 2007-06-25 2012-11-28 太陽誘電株式会社 半導体装置

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