WO2005004237A1 - Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant - Google Patents
Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant Download PDFInfo
- Publication number
- WO2005004237A1 WO2005004237A1 PCT/EP2004/051314 EP2004051314W WO2005004237A1 WO 2005004237 A1 WO2005004237 A1 WO 2005004237A1 EP 2004051314 W EP2004051314 W EP 2004051314W WO 2005004237 A1 WO2005004237 A1 WO 2005004237A1
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- WIPO (PCT)
- Prior art keywords
- components
- component
- pads
- support
- heterogeneous
- Prior art date
Links
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Classifications
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Definitions
- the present invention relates to a process for interconnecting active and passive components, in two or three dimensions, and the resulting heterogeneous components having a small thickness.
- active and passive components in two or three dimensions, and the resulting heterogeneous components having a small thickness.
- passive components and in particular the capacitors
- the capacitors deposited on the substrate glass, alumina, silicon
- the disadvantage of these deposited capacitors comes from their very low permittivity. this range from 4 to a few tens, while the permittivities of ceramic capacitors reach several thousand. These latter capacitors based on barium titanate are very stable and very reliable.
- the present invention overcomes the aforementioned drawbacks by proposing an active and passive component interconnection method, particularly applicable to the interconnection of chip-type active components and ceramic capacitors, making it possible to produce heterogeneous components with two or three dimensions of small thickness.
- the process is based on a simultaneous thinning of the active and passive components embedded in a polymer layer by heterogeneous surfacing, that is to say non-selectively applied to both the passive and active components and to the polymer layer. the applicant having shown that, surprisingly, this process does not significantly affect the performance of passive components, including ceramic capacitors.
- the invention proposes a method of interconnecting active and passive components, provided with pads for their interconnection, characterized in that i comprises: positioning and fixing on a plane support of at least one active component and a passive component, the pads being in contact with the support, the deposition of a polymer layer on the entire support and said components, the removal of the support, the redistribution of the pads between the components and / or to the periphery by means of metal conductors arranged according to a predetermined pattern, making it possible to obtain a reconstituted heterogeneous structure, - the heterogeneous thinning of said structure by non-selective surfacing of the polymer layer and at least one passive component.
- FIG. 1 an embodiment of the method according to the invention
- FIGS. 2A, 2B and 2C exemplary embodiments of the steps of the method according to claim 1
- FIGS. 3A and 3B are exemplary embodiments of the prior thinning step on ceramic capacitors
- - Figure 4 the diagram of a resistance to which the method according to the invention can be applied
- - Figure 5 the method according to the invention applied to the three-dimensional interconnection
- FIG. 6, a diagram illustrating steps of the method described in FIG. 5
- FIG. 7, a diagram showing in a sectional view a thinned 3D heterogeneous component obtained by the process described starting from FIG.
- FIG. 1 describes an embodiment of the method for interconnecting passive and active components according to the invention, in particular for producing very thin three-dimensional heterogeneous components.
- heterogeneous component is meant an electronic component comprising both one or more active and passive components connected together to form an electronic circuit to provide a given electronic function.
- the active component comprises any component commonly called "chip” and implementing semiconductor technology, for example diode, transistor, or integrated circuit.
- Passive component is understood to mean the other components, whether they are conventional components of resistance, capacitor or surface-mounted inductance type, or the electromechanical components etched in silicon and known by the name of MEMS (abbreviation for Anglo-Saxon expression “Micro ElectroMechnical Systems”).
- MEMS Micro ElectroMechnical Systems
- the method according to the invention overcomes this disadvantage.
- the method described in the example of FIG. 1 notably comprises prior thinning of the passive components (step 10, optional), positioning and fixing on a plane support of at least one active component and one passive component (step 11).
- the first step of the method according to the invention consists in positioning and fixing on a plane support the components provided with pads for their interconnection and intended to be connected to one another.
- FIGS. 1 The first step of the method according to the invention, identified in FIG. 1, consists in positioning and fixing on a plane support the components provided with pads for their interconnection and intended to be connected to one another.
- FIG. 2A and 2B illustrate, according to an example, the realization of the steps of the method described in FIG. 1.
- the figures show the connection of an active component, identified 21, with a first passive component, for example a 20, and a second passive component, in this example a ceramic capacitor, identified 22.
- a passive MEMS-type component denoted 27.
- These components are The pads of the components, marked respectively 211 for the active component and 221 for the ceramic capacitor, are in contact with the support.
- a large number of components arranged in the form of substantially identical patterns can be positioned and fixed on the support 23.
- the process is then applied collectively to the entire support and the reconstituted structure (or reconstituted wafer) obtained at the end of the process will be cut to obtain as many individual heterogeneous components.
- the support 23 is an adhesive sheet that can be peeled off without special treatment, such as for example a polyvinyl chloride sheet of the type used in the manufacture of silicon washers or "wafer" according to the English expression, and commonly called drum skin.
- the positioning of the components, very precise, is achieved for example by an optical control camera with referenced reference pads.
- an adhesive sheet as a support makes it possible to avoid the adhesive gluing of the components, which is more complicated to implement because the drop of glue must be extremely well calibrated and very thin to avoid touching the pads, and more limited in the possibilities of application because the pads must necessarily be at the periphery of the component.
- an adhesive sheet can be removed without special treatment, by peeling, while that a bonding of the support requires a heat treatment to polymerize the glue and acid chemical treatment to remove it.
- the ceramic capacitor 22 has undergone a prior thinning step described by means of FIG. 3A. This optional step makes it possible to thin the ceramic capacitor in two faces facing each other and to further reduce the thickness thereof.
- the ceramic capacitor (30) conventionally comprises a zone of interspersed even and odd planar electrodes, marked respectively 31 and 32, two ceramic filling zones 33 and 34 located on either side of the electrode zone. which are not electrically functional, and two terminal pins marked (generally in silver-palladium or nickel-gold) to which are connected for example respectively the even and odd electrodes 31 32.
- the ceramic capacitor is thinned according to one of its faces, for example by polishing. According to a first variant shown in FIG. 3A, the capacitor is thinned along a face parallel to the electrodes.
- the capacitor is for example glued on a support 36 by means of an adhesive material that can be easily peeled, for example wax 37 or a tacky film such as that described above.
- the polishing can be carried out in zones 33 and 34 which are not electrically functional.
- FIG. 3A shows the thinned capacitor in the ceramic zone 33 along the section plane marked C.
- the applicant has shown that it is possible to thin in the zone of electrodes.
- the capacitive value will decrease as the electrode levels are removed.
- An optical check can be performed to verify that thinning is not performed across the plane of the electrodes.
- the very low price of the ceramic capacitors (10 to 100 times lower than the capacitors deposited) makes it possible to sort the components once thinned and to keep only the good ones, by non-destructive and instantaneous ceramic capacitor reliability test techniques. known to those skilled in the art.
- the thinned capacitors are then detached and can be transferred to the support 23 (FIG. 2A), the thinned face facing the support so that the sections 351 termination pads (Figure 3A) provide the function of pads 221 of the passive component.
- FIG. 3B illustrates the case of prior thinning of a ceramic capacitor with attached electrode.
- the ceramic capacitors have termination pads 35 made of a material incompatible with the metallization that will be applied during the redistribution step of the pads (step 15 described below), and which is fixed by the chip metallization technology. Thus, it may be necessary to carry out the thinned capacitors with non-oxidizable metals or alloys (gold or gold-palladium, for example).
- electrodes 39 in the form of a ribbon or wire are glued to the termination pads 35 by means of conductive glue (for example silver) or by brazing. After thinning (section C), the non-oxidizable electrodes 39 have sections 391 which can provide the function of pads 221 of the passive component (FIG. 2A).
- the capacitor can be thinned along one of its faces perpendicular to the plane of the electrodes, which reduces the capacitive value but makes it possible to keep the positioning symmetry of the electrodes relative to the faces which are parallel thereto.
- the external metallizations 35 of the electrodes extending on the four adjacent faces, the capacitor may be glued to the adhesive support 23 by the ends of the metallizations 35 with the electrodes parallel or perpendicular to the plane of the support.
- FIG. 4 represents the diagram of a commercial passive component, of resistor type, to which the method can be applied.
- the resistor 40 comprises an inert substrate 41, for example alumina, whose thickness is of the order of a millimeter, a resistive layer 42 (of the order of one micron) and conductive pads 43 generally formed of layers of conductive material which encase the lateral faces of the component, on both sides of the active layer.
- the very thin active layer 42 is positioned near a face. Prior thinning of the component is possible on the opposite side to that carrying the active layer.
- the component is then positioned and fixed on the substrate with the face carrying the active layer facing the substrate. During the interconnection process according to the invention, the component is positioned on the support 23 (FIG.
- step 16 of the method, described in FIG. below
- the zones 431 of the pads 43 in contact with the support 23 form the pads 221 of the component (FIG. 2A).
- the method is applied in the same way to an inductance-type component, the active layer then being an inductive layer.
- the next step, labeled 12, consists of depositing on the assembly of components and the support a polymer layer (marked 24 in FIGS. 2A, 2B), for example epoxy resin.
- the rectification of the polymer layer is an optional step of the interconnection method according to the invention, particularly advantageous in the case where the method is applied collectively to a reconstituted washer.
- the grinding indicated A in FIG. 2A, consists of a lapping followed optionally by polishing.
- the applicant has shown that it is possible, if the thickness of the components so requires, and in particular passive components, to carry out a heterogeneous thinning, that is to say non-selective, resulting in a cut in the thickness of the structure through the different materials that form the diversity of components and the layer.
- the support 24 (step 14) is then removed to proceed with the redistribution of the pads (step 15).
- the support being formed of an adhesive sheet
- the removal is carried out by a simple peeling of the sheet.
- the redistribution of the pads is intended to connect together the components of the same pattern and / or to make connections to the periphery of the pattern for a subsequent three-dimensional interconnection.
- Figure 2B illustrates an advantageous embodiment of this step.
- a layer 25 of a layer is deposited over the entire surface.
- the pattern corresponding to the pattern of the pads 221 is etched in the polymer layer by illumination through a mask.
- a metal layer is then deposited, and again the metal layer is etched by a similar technique in a predetermined pattern of connections to form the metal conductors 26 connecting the component to another component and / or to the periphery.
- several layers of metal may be deposited on each other.
- the choice of the metal must be compatible with the material of which the pads 221 of the passive and active components are constituted.
- the metal is a tricouche-type alloy conventionally used and having layers of titanium-tungsten, nickel and gold. At the end of this step, a reconstituted heterogeneous structure is obtained.
- the section marked B in FIG. 2B is made through the polymer forming the layer 24, the material forming the passive component, for example the ceramic for a capacitor as described in FIG. 2B, or the alumina in the case a resistor and optionally the silicon forming the support of the active component.
- the cut is made by honing followed by non-selective polishing of the surface of the structure. Lapping and polishing are advantageously done by mechanical abrasion, a process that is widely used in the semiconductor field and is inexpensive.
- a thinned heterogeneous structure which can be cut (step 17) is then obtained to form ultra-thin heterogeneous elementary components.
- the components thus obtained are two-dimensional. They can be used as such to make two-dimensional micro-boxes, or, as described below, for three-dimensional stacking.
- MEMS is another particularly interesting case of passive component to which the interconnection method according to the invention can be applied.
- MEMS are electromechanical components etched in silicon and having sensor, actuator, switch, etc. Highly sensitive to moisture and external stresses, they are necessarily arranged in a cavity protected by a cover, for example plastic.
- FIG. 2C illustrates the interconnection of a MEMS 27 and a chip 21 with the method according to the invention.
- the MEMS 27 comprises, protected by a cover 270, a sensitive portion 271 etched in a substrate 272 generally of silicon.
- the substrate is positioned and adhered to the support 23 (not shown in FIG. 2C).
- the sensitive portion is located on the substrate 272 on the opposite side to that in contact with the support, in fact, it must not receive glue or resin and stay out of stress.
- the interface 273 has two faces equipped with metal contacts 275 and 276 respectively on the face vis-à-vis the support 23 on which the interface is bonded and on the opposite face, the contacts being interconnected.
- the contacts 276 are connected to metal pads 274 of the substrate 272, in contact with the sensitive surface 271, by connection wires 277.
- the cap 270 which can be made of organic material ( epoxy resin) or inorganic (silicon, glass, ceramic such as alumina, metal or metal alloys) is "glued" to the interface273. It is ensured that the thickness of the cover is sufficient so that after final thinning it can always maintain its integrity and constitute a protective cavity for the MEMS.
- the support is then removed to proceed with the redistribution of the pads.
- the redistribution of the pads is made according to the method described above.
- the perimeter of the hood is usually connected with nothing. If for electrical reasons of shielding for example it had to be connected to a mass electrical, it is enough to metallize its periphery (metallization 278) if this one is insulating or to do nothing if this one is conductive; the periphery 278 will then be connected to pads 279 of the interface 273.
- two metallization layers 261 and 262 are provided, deposited on two layers of insulating material 251, 252 which make it possible to connect the hood to the mass through its periphery 278.
- the thinning (cut B) is in the thickness of the hood.
- the interconnection method as described above applies to the production of three-dimensional thinned heterogeneous components.
- the method implemented for the production of 3D components includes steps of the method described in French Patent Application No. 90 154 73 filed on 11/12/1990 in the name of the applicant. The steps are briefly recalled in FIG. 5 and FIG. 6 illustrates, in one example, the various steps.
- the embodiment (50) of the thinned heterogeneous elementary components (denoted 60 in FIG. 6) is made by the interconnection method according to the invention as described previously and illustrated in FIG. 1. A sectional view of an example of Heterogeneous elementary component thinned thus produced is shown in Figure 2B.
- the elementary components include connections 601 (FIG. 6) oriented towards the periphery of the component.
- the components are then stacked and glued (step 51) on a substrate 61.
- the components 60 are either identical components or components having different electrical functions.
- the substrate 61 is for example an adhesive sheet of the type of that described above.
- the first component 62 bonded to the substrate is an interconnection component, for example a printed circuit substrate, for the subsequent connection of the 3D component, and comprising pads 621 positioned on the substrate side face connected to studs 622 positioned on the face vis-à-vis.
- the elementary components 60 are therefore stacked on this first interconnection component and bonded, for example by means of an epoxy adhesive 63.
- the assembly formed of the stack of the elementary components 60 and the interconnection component 62 is embedded (step 52, FIG. 5) with a polymer material 64 (for example an epoxy resin) to form a parallelepiped shaped block.
- the faces of this block are then metallized to form the connections (step 54).
- the method used is a collective process. On a single substrate 61, the individual heterogeneous components are stacked and glued together as described above.
- the coating material is applied to the entire support and the resulting structure is cut (step 53) so as to reveal the sections of all the conductors (601, 622) arriving at the periphery for each of the levels consisting of the elementary components 60 and the interconnection component 62.
- the faces of this block are then metallized in 4 or 5 faces (step 54), short-circuiting the set of drivers
- FIG. 7 is a sectional view of an exemplary embodiment of a three-dimensional thinned heterogeneous component obtained by the method as described in FIG. 5.
- the thinned three-dimensional heterogeneous component comprises the component of FIG. interconnection 62 with the pads 621 for the connection with the substrate on which it will be reported to be interconnected with others and, stacked thereon, the thinned heterogeneous elementary components 60,5 between which layers of glue are arranged 63.
- the metallization layer 71 short-circuiting the conductors leading to the periphery of each level is deposited on the 4 or 5 faces of the three-dimensional component, making it possible, after etching, to form an interconnection network between the assembly.
- different levels In the example of Figure 7 are shown active components 21 and passive 20, 22 of the capacitor type and connection wires respectively.
- the advantage of such connection son 20 may be the interconnection of the different levels through the use of a conductive layer 63, such as an anisotropic glue ACF type (for "Anisotropic Conductive Film” according to the English-5 expression Saxon), in liquid or film form, which is conductive in the direction in which pressure is exerted.
- ACF type for "Anisotropic Conductive Film” according to the English-5 expression Saxon
- FIG. 8 illustrates by a diagram another example of implementation of the interconnection method according to the invention for producing three-dimensional thinned heterogeneous components.
- the process substantially involves the steps of the process described in FIG. 1. Only in this example, more than one active component is stacked on top of each other prior to deposition of the polymer layer (step 12 FIG. 1).
- This implementation of the method according to the invention is particularly advantageous in the case where the active components have sufficiently small thicknesses to be able to be stacked with a total height of the stack which remains lower than the height of the passive component.
- the active components will not be affected, however it will proceed to a non-selective surfacing of the polymer layer and passive components, to reduce the thickness of the component heterogeneous thus formed.
- the method described here comprises positioning and fixing on a plane support of at least one passive component 80 and at least one first active component 81, the pads of the components (respectively 801, 811) being in contact with the support.
- the flat support is for example an adhesive sheet as described above.
- the method also comprises stacking and gluing the first active component 81 with a second active component 82, the pads 821 of the second component being on the opposite side to that on the other. contact with the first component.
- a second active component On this second component, one or more other active components 83 may also be stacked, the pads 831 of each other component being on the face opposite to that in contact with the lower component.
- the number of active components that can be stacked depends on their thickness relative to that of the passive component 80.
- the connection of the active components is done in the following manner.
- one or more pads adapters 84 are positioned and fixed on the plane support (not shown) in the same way as the passive component 80 and the first active component 81.
- the adapters can be of the same type as those described.
- Each adapter has two faces with metal contacts interconnected, denoted respectively 841 on the face in contact with the support and 842 on the other face, vis-à-vis.
- the adapters 84 may be formed of a metal grid.
- the metal grid coated in a resin consists for example of ferro-nickel alloy, copper. It is nickel-plated and gilded so that it can receive wire cabling.
- the method comprises the formation of connections by means of wires 822 between the pads 821 of the second component 82 and the contacts 842 of the adapter, as well as, where appropriate, the formation of connections by connector wires 832 between the pads of each other component 83 and 842 contacts of the adapter or the lower component pads, here the pads 821 of the second component 82.
- the subsequent steps of the method are similar to those described in the example of Figure 1 and include the deposition of a layer of polymer 85 on the assembly of the support and components, the removal of the support, then the redistribution of the pads between the components and / or to the periphery by means of metal conductors 86 to obtain a reconstituted heterogeneous 3D structure.
- This structure is then subjected to heterogeneous thinning by non-selective surfacing of a polymer layer and passive components (section noted E in FIG. 8).
- the active components are not thinned during the heterogeneous thinning step, these components being in any case assumed sufficiently thin in themselves.
- the redistribution of the studs in this example is made in the same way as that described from FIG. 2B with the deposition of a photo-etchable insulating layer (87, FIG. 8), the etching of the layer in a pattern corresponding to the positioning of the pads. (801, 811, 841), depositing a metal layer, then etching the metal layer according to the desired pattern of metal conductors.
- the passive components may undergo a prior thinning step.
- the method can be applied collectively by fixing a large number of components arranged in the form of identical patterns on the same support. The reconstituted structure obtained at the end of the process will then be cut to obtain as many individual heterogeneous components.
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- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
- Semiconductor Integrated Circuits (AREA)
- Physical Or Chemical Processes And Apparatus (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04766105A EP1642336A1 (fr) | 2003-07-01 | 2004-06-30 | Procede d interconnexion de composants actif et passif et co mposant heterogene a faible epaisseur en resultant |
US10/562,685 US7635639B2 (en) | 2003-07-01 | 2004-06-30 | Method for the interconnection of active and passive components and resulting thin heterogeneous component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0307977 | 2003-07-01 | ||
FR0307977A FR2857157B1 (fr) | 2003-07-01 | 2003-07-01 | Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005004237A1 true WO2005004237A1 (fr) | 2005-01-13 |
Family
ID=33522652
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2004/051314 WO2005004237A1 (fr) | 2003-07-01 | 2004-06-30 | Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant |
Country Status (4)
Country | Link |
---|---|
US (1) | US7635639B2 (fr) |
EP (1) | EP1642336A1 (fr) |
FR (1) | FR2857157B1 (fr) |
WO (1) | WO2005004237A1 (fr) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2884049B1 (fr) * | 2005-04-01 | 2007-06-22 | 3D Plus Sa Sa | Module electronique de faible epaisseur comprenant un empilement de boitiers electroniques a billes de connexion |
FR2894070B1 (fr) * | 2005-11-30 | 2008-04-11 | 3D Plus Sa Sa | Module electronique 3d |
FR2895568B1 (fr) * | 2005-12-23 | 2008-02-08 | 3D Plus Sa Sa | Procede de fabrication collective de modules electroniques 3d |
AT503191B1 (de) * | 2006-02-02 | 2008-07-15 | Austria Tech & System Tech | Leiterplattenelement mit wenigstens einem eingebetteten bauelement sowie verfahren zum einbetten zumindest eines bauelements in einem leiterplattenelement |
US8420505B2 (en) * | 2006-03-25 | 2013-04-16 | International Rectifier Corporation | Process for manufacture of thin wafer |
FR2905198B1 (fr) * | 2006-08-22 | 2008-10-17 | 3D Plus Sa Sa | Procede de fabrication collective de modules electroniques 3d |
FR2911995B1 (fr) * | 2007-01-30 | 2009-03-06 | 3D Plus Sa Sa | Procede d'interconnexion de tranches electroniques |
FR2917236B1 (fr) | 2007-06-07 | 2009-10-23 | Commissariat Energie Atomique | Procede de realisation de via dans un substrat reconstitue. |
FR2917234B1 (fr) | 2007-06-07 | 2009-11-06 | Commissariat Energie Atomique | Dispositif multi composants integres dans une matrice semi-conductrice. |
FR2923081B1 (fr) * | 2007-10-26 | 2009-12-11 | 3D Plus | Procede d'interconnexion verticale de modules electroniques 3d par des vias. |
FR2934082B1 (fr) * | 2008-07-21 | 2011-05-27 | Commissariat Energie Atomique | Dispositif multi composants integres dans une matrice |
FR2940521B1 (fr) | 2008-12-19 | 2011-11-11 | 3D Plus | Procede de fabrication collective de modules electroniques pour montage en surface |
FR2943176B1 (fr) | 2009-03-10 | 2011-08-05 | 3D Plus | Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee |
FR2947948B1 (fr) | 2009-07-09 | 2012-03-09 | Commissariat Energie Atomique | Plaquette poignee presentant des fenetres de visualisation |
FR2985367A1 (fr) * | 2011-12-29 | 2013-07-05 | 3D Plus | Procede de fabrication collective de modules electroniques 3d ne comportant que des pcbs valides |
US11213690B2 (en) | 2012-06-15 | 2022-01-04 | Medtronic, Inc. | Wafer level packages of high voltage units for implantable medical devices |
US8824161B2 (en) | 2012-06-15 | 2014-09-02 | Medtronic, Inc. | Integrated circuit packaging for implantable medical devices |
FR3048123B1 (fr) | 2016-02-19 | 2018-11-16 | 3D Plus | Procede d'interconnexion chip on chip miniaturisee d'un module electronique 3d |
FR3053158B1 (fr) | 2016-06-22 | 2018-11-16 | 3D Plus | Procede de fabrication collective de modules electroniques 3d configures pour fonctionner a plus d'1 ghz |
CN112928077A (zh) * | 2021-01-20 | 2021-06-08 | 上海先方半导体有限公司 | 一种多芯片异质集成封装单元及其制造方法、堆叠结构 |
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US3235939A (en) * | 1962-09-06 | 1966-02-22 | Aerovox Corp | Process for manufacturing multilayer ceramic capacitors |
US5324687A (en) * | 1992-10-16 | 1994-06-28 | General Electric Company | Method for thinning of integrated circuit chips for lightweight packaged electronic systems |
EP0611129A2 (fr) * | 1993-02-08 | 1994-08-17 | General Electric Company | Substrat intégré pour modules à circuits intégrés |
EP1137066A2 (fr) * | 2000-03-24 | 2001-09-26 | Shinko Electric Industries Co. Ltd. | Dispositif semi-conducteur et méthode de fabrication associée |
WO2002015266A2 (fr) * | 2000-08-16 | 2002-02-21 | Intel Corporation | Couche formee directement sur un boitier a puce encapsule |
FR2818804A1 (fr) * | 2000-12-21 | 2002-06-28 | Thomson Csf | Procede de realisation d'un module multi-composants enterres et module obtenu par ce procede |
US20020175400A1 (en) * | 2001-05-26 | 2002-11-28 | Gerber Mark A. | Semiconductor device and method of formation |
US20030045030A1 (en) * | 2001-08-31 | 2003-03-06 | Hitachi, Ltd. | Method of manufacturing a semiconductor device |
Family Cites Families (17)
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FR2591801B1 (fr) * | 1985-12-17 | 1988-10-14 | Inf Milit Spatiale Aeronaut | Boitier d'encapsulation d'un circuit electronique |
US5847448A (en) * | 1990-12-11 | 1998-12-08 | Thomson-Csf | Method and device for interconnecting integrated circuits in three dimensions |
FR2674680B1 (fr) * | 1991-03-26 | 1993-12-03 | Thomson Csf | Procede de realisation de connexions coaxiales pour composant electronique, et boitier de composant comportant de telles connexions. |
FR2688629A1 (fr) * | 1992-03-10 | 1993-09-17 | Thomson Csf | Procede et dispositif d'encapsulation en trois dimensions de pastilles semi-conductrices. |
FR2688630B1 (fr) * | 1992-03-13 | 2001-08-10 | Thomson Csf | Procede et dispositif d'interconnexion en trois dimensions de boitiers de composants electroniques. |
FR2691836B1 (fr) * | 1992-05-27 | 1997-04-30 | Ela Medical Sa | Procede de fabrication d'un dispositif a semi-conducteurs comportant au moins une puce et dispositif correspondant. |
FR2696871B1 (fr) * | 1992-10-13 | 1994-11-18 | Thomson Csf | Procédé d'interconnexion 3D de boîtiers de composants électroniques, et composants 3D en résultant. |
FR2709020B1 (fr) * | 1993-08-13 | 1995-09-08 | Thomson Csf | Procédé d'interconnexion de pastilles semi-conductrices en trois dimensions, et composant en résultant. |
FR2719967B1 (fr) * | 1994-05-10 | 1996-06-07 | Thomson Csf | Interconnexion en trois dimensions de boîtiers de composants électroniques utilisant des circuits imprimés. |
US6441495B1 (en) * | 1997-10-06 | 2002-08-27 | Rohm Co., Ltd. | Semiconductor device of stacked chips |
US6066513A (en) * | 1998-10-02 | 2000-05-23 | International Business Machines Corporation | Process for precise multichip integration and product thereof |
US6110806A (en) * | 1999-03-26 | 2000-08-29 | International Business Machines Corporation | Process for precision alignment of chips for mounting on a substrate |
FR2802706B1 (fr) * | 1999-12-15 | 2002-03-01 | 3D Plus Sa | Procede et dispositif d'interconnexion en trois dimensions de composants electroniques |
FR2805082B1 (fr) * | 2000-02-11 | 2003-01-31 | 3D Plus Sa | Procede d'interconnexion en trois dimensions et dispositif electronique obtenu par ce procede |
TW569424B (en) * | 2000-03-17 | 2004-01-01 | Matsushita Electric Ind Co Ltd | Module with embedded electric elements and the manufacturing method thereof |
JP3839323B2 (ja) * | 2001-04-06 | 2006-11-01 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6787884B2 (en) * | 2002-05-30 | 2004-09-07 | Matsushita Electric Industrial Co., Ltd. | Circuit component, circuit component package, circuit component built-in module, circuit component package production and circuit component built-in module production |
-
2003
- 2003-07-01 FR FR0307977A patent/FR2857157B1/fr not_active Expired - Lifetime
-
2004
- 2004-06-30 EP EP04766105A patent/EP1642336A1/fr not_active Withdrawn
- 2004-06-30 US US10/562,685 patent/US7635639B2/en not_active Expired - Lifetime
- 2004-06-30 WO PCT/EP2004/051314 patent/WO2005004237A1/fr active Application Filing
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3235939A (en) * | 1962-09-06 | 1966-02-22 | Aerovox Corp | Process for manufacturing multilayer ceramic capacitors |
US5324687A (en) * | 1992-10-16 | 1994-06-28 | General Electric Company | Method for thinning of integrated circuit chips for lightweight packaged electronic systems |
EP0611129A2 (fr) * | 1993-02-08 | 1994-08-17 | General Electric Company | Substrat intégré pour modules à circuits intégrés |
EP1137066A2 (fr) * | 2000-03-24 | 2001-09-26 | Shinko Electric Industries Co. Ltd. | Dispositif semi-conducteur et méthode de fabrication associée |
WO2002015266A2 (fr) * | 2000-08-16 | 2002-02-21 | Intel Corporation | Couche formee directement sur un boitier a puce encapsule |
FR2818804A1 (fr) * | 2000-12-21 | 2002-06-28 | Thomson Csf | Procede de realisation d'un module multi-composants enterres et module obtenu par ce procede |
US20020175400A1 (en) * | 2001-05-26 | 2002-11-28 | Gerber Mark A. | Semiconductor device and method of formation |
US20030045030A1 (en) * | 2001-08-31 | 2003-03-06 | Hitachi, Ltd. | Method of manufacturing a semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
FR2857157A1 (fr) | 2005-01-07 |
US7635639B2 (en) | 2009-12-22 |
EP1642336A1 (fr) | 2006-04-05 |
US20070117369A1 (en) | 2007-05-24 |
FR2857157B1 (fr) | 2005-09-23 |
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